JP5686696B2 - amplifier - Google Patents

Description

  The present invention relates to an amplifier that controls a bias current in accordance with the level of an output noise voltage.

  In conventional amplifiers for low frequency sensor applications that handle minute signals, there is a concern about the influence of flicker noise dominant in the low frequency region. A low-noise amplifier is generally used as a sensor amplifier. In order to satisfy a desired output noise characteristic with this amplifier, a desired gain is set, and the amplifier is set so as to satisfy the output noise characteristic at the gain. The transistor size and bias current value of the differential input circuit and the output circuit are determined (see, for example, Patent Document 1).

JP 2008-141302 A

  In a general amplifier, the bias currents of the differential input circuit and the output circuit are fixed, and there is a problem that the output noise voltage varies depending on the gain setting.

  An object of the present invention is to provide an amplifier capable of suppressing an output noise voltage to be low by controlling a bias current.

In order to achieve the above object, the invention according to claim 1 is directed to a differential input circuit that amplifies a difference between a normal input voltage and an inverted input voltage, and an output signal of the differential input circuit is amplified to an output terminal. In an amplifier having an output circuit for outputting, and a bias circuit for outputting a bias voltage to the current source of the differential input circuit and the current source of the output circuit, both the normal input voltage and the inverted input voltage are set to the ground voltage. When the output noise voltage appearing at the output terminal is detected, and the level of the output noise voltage is higher than the reference voltage, the bias circuit is set to increase the current of each current source according to the difference. When the level of the output noise voltage is lower than the reference voltage, the bias circuit is set so as to reduce the current of each current source according to the difference.
According to a second aspect of the present invention, in the amplifier according to the first aspect, a switch that switches a normal input terminal and an inverting input terminal of the differential input circuit to one of a signal input side and a ground side, and the positive switch by the switch. A sample hold circuit that samples and holds an output noise voltage appearing at the output terminal when both the inverted input voltage and the inverted input voltage are switched to the ground side, and the output noise voltage and the reference voltage held by the sample hold circuit When the held voltage is larger than the reference voltage, the bias circuit is set to increase the current of each current source according to the difference, and the held voltage is set higher than the reference voltage. And a noise comparison circuit that sets the bias circuit so as to reduce the current of each current source according to the difference. Characterized in that was.

  According to the present invention, since the bias current of the differential input circuit and the output circuit can be set according to the level of the output noise voltage, the output noise voltage can be suppressed when the output noise voltage is higher than the reference voltage. Is low, there is an advantage that current consumption can be suppressed.

It is a circuit diagram of the amplifier of the Example of this invention.

  FIG. 1 shows a circuit of an amplifier according to one embodiment of the present invention. A differential input circuit 1 includes differentially connected PMOS transistors MP1 and MP2, a current source PMOS transistor MP3, and current mirror connected NMOS transistors MN1 and MN2 as active loads. A switch SW1 is connected to the normal input terminal 1a to which the gate of the transistor MP1 is connected, and a switch SW2 is connected to the inverting input terminal 1b to which the gate of the transistor MP2 is connected. The switch SW1 is switched as shown to input the normal input voltage VIN + to the gate of the transistor MP1, and the switch SW2 is switched as shown to input the inverted input voltage VIN− to the gate of the transistor MP2. However, the switches SW1 and SW2 are switched to the opposite side of the figure to connect the gates of the transistors M1 and MP2 to the ground GND.

  Reference numeral 2 denotes an output circuit, which includes an output NMOS transistor MN3, a current source PMOS transistor MP4, and a resistor Rc1 and a capacitor Cc1 that form a phase compensation circuit connected between the drain and gate of the transistor MN3. .

  3 is a sample and hold circuit that samples and holds the output voltage VOUT of the output terminal 2a of the output circuit 2, and 4 is a noise comparison that compares the voltage Vh held by the sample and hold circuit 1 with the reference voltage Vr and outputs a bias control signal Vb. A circuit 5 is a bias circuit for controlling the gate voltages of the transistors MP3 and MP4 according to the bias control signal Vb.

ここで、
Ｋ：素子特有の係数
Ｉ_Ｄ：ドレイン電流
ａ：０．５〜２の間の値をとる定数
ｆ：周波数
μ：チャネルの平均電子移動度
Ｃox：単位面積当たりのゲート酸化膜容量
Ｗ：ゲート幅
Ｌ：ゲート長
である。 In general, flicker noise in a MOS transistor in an amplifier is considered to be mainly caused by traps related to contamination and crystal defects, and can be expressed by the following equation (1).

here,
K: device specific coefficient _ID : drain current a: constant between 0.5 and 2 f: frequency μ: average electron mobility of channel Cox: gate oxide film capacitance per unit area W: gate width L: The gate length.

Next, when Expression (1) is expressed using the transfer conductance gm, the following Expression (2) is obtained.

ここで、
ｉ_ｄはＭＯＳトランジスタのドレイン電流
ｖ_inはゲート入力電圧
である。 Further, the transfer conductance gm is expressed by Expression (3).

here,
i _d is the drain current v _in of the MOS transistor is a gate input voltage.

  From equation (2), it can be seen that the noise of the MOS transistor alone can be reduced by increasing gm. From the equation (3), it is understood that the drain current should be increased in order to increase the gm. In the amplifier, the noise voltage generated in the input stage is transmitted to the next stage and amplified and output. Therefore, the output noise voltage is increased or decreased by increasing or decreasing the drain current of the MOS transistor of the differential input circuit used in the input stage. Can be controlled.

  As an operation example of the amplifier of FIG. 1, the gates of the differential input transistors MP1 and MP2 are connected to the ground GND by switching the switches SW1 and SW2 at an arbitrary time, and the output noise voltage at that time is sampled and held by the sample and hold circuit 3 The hold voltage Vh is compared with the reference voltage Vr by the noise comparison circuit 4, and the difference voltage is fed back to the bias circuit 5 as the bias control voltage Vb.

  As a result, when the hold voltage Vh is larger than the reference voltage Vr, the bias circuit 5 controls to reduce the gate voltages of the transistors MP3 and MP4, whereby the bias currents of the differential input circuit 1 and the output circuit 2 are reduced. The noise voltage to be output is reduced. On the other hand, when the hold voltage Vh is smaller than the reference voltage Vr, the bias circuit 5 controls to increase the gate voltages of the transistors MP3 and MP4, thereby reducing the bias currents of the differential input circuit 1 and the output circuit 2. In addition, current consumption is suppressed.

  As described above, the output noise voltage can be suppressed by setting the bias voltages of the transistors MP3 and MP4 before actual use of the amplifier and operating the transistors at the bias voltage during actual use.

  1: differential input circuit, 2: output circuit, 3: sample hold circuit, 4: noise comparison circuit, 5: bias circuit.

Claims (2)

A differential input circuit that amplifies the difference between the normal input voltage and the inverted input voltage; an output circuit that amplifies an output signal of the differential input circuit and outputs the output signal to an output terminal; a current source of the differential input circuit; In an amplifier having a bias circuit that outputs a bias voltage to a current source of an output circuit,
An output noise voltage that appears at the output terminal when both the normal input voltage and the inverted input voltage are set to a ground voltage is detected. The bias circuit is set to increase the current of each current source, and when the level of the output noise voltage is lower than the reference voltage, the bias circuit is configured to decrease the current of each current source according to the difference. An amplifier characterized by being set. The amplifier of claim 1, wherein
A switch for switching the normal input terminal and the inverted input terminal of the differential input circuit to one of a signal input side and a ground side;
A sample-and-hold circuit that samples and holds an output noise voltage that appears at the output terminal when both the normal input voltage and the inverted input voltage are switched to the ground side by the switch;
The output noise voltage held by the sample and hold circuit is compared with a reference voltage. When the held voltage is larger than the reference voltage, the bias of the current source is increased according to the difference. When the circuit is set and the held voltage is smaller than the reference voltage, a noise comparison circuit that sets the bias circuit to reduce the current of each current source according to the difference, and
An amplifier comprising:

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