JP5685923B2 - Method for connecting transistor arrays - Google Patents

Description

The present invention drives each pixel of a unit display device used when manufacturing a large display device.
The present invention relates to a transistor array and a method for connecting such transistor arrays.

Until now, a method of tiling a plurality of unit display devices has been proposed as one of methods for manufacturing a large display device. With regard to a technique for manufacturing a large display device by tiling, for example, Patent Document 1 (Japanese Patent Laid-Open No. 10-96911) discloses a first and second substrate having an inner light shielding portion and an edge light shielding portion. In the manufacturing method of the liquid crystal display device including, the step of dividing the light shielding portion of the edge into a first region and a second region, the step of dividing the first region of the light shielding portion of the edge on the first substrate, Removing the first region of the light shielding portion at the edge and leaving the second region of the light shielding portion at the edge; and interconnecting the second region of the light shielding portion at the edge of the first substrate and the second substrate; A manufacturing method of a liquid crystal display device characterized by having
Japanese Patent Laid-Open No. 10-96911

  By the way, an electrode (leading electrode) to which a signal for driving each pixel of the unit display panel is input has a configuration drawn from two sides of the rectangular display area of the display panel. When a large display device is manufactured by tiling using a unit display panel, a display device using a maximum of four unit display panels (Patent Document 1) when trying to lay out the lead electrode portion and the display area so as not to overlap. Only the display device shown in FIG. 9 and the like can be manufactured, which has been a bottleneck in manufacturing a large display device. That is, the configuration in which the lead-out electrode portions in the conventional unit display panel are drawn out from the two sides of the display area is a factor that hinders the increase in the size of the display device, which is a problem.

  It is noted that some conventional unit display panels have a structure in which the lead-out electrode portion is drawn out to the back side of the unit display panel. However, it is very costly to manufacture such a structure. Therefore, it has been a problem in manufacturing a large display device.

The present invention is for solving the above-described problems, and the invention according to claim 1 is provided with a base material having a rectangular main surface and a stacking direction of the base material with respect to the main surface. A data line routing electrode and a scan line routing electrode, a data line conduction unit electrically connected to the data line routing electrode, a scan line conduction unit electrically connected to the scan line routing electrode, and the data line conduction unit have a, a plurality comprises display area pixel electrode predetermined voltage is held by a circuit including a transistor which is driven by a signal from the scan line conductive portion, wherein when viewed in the stacking direction, at least the data line lead-out electrode or the one of the scan lines lead electrodes, overlap the display area, the data line lead electrodes及The scan line routing electrode is arranged so as to extend to one side of the substrate, and the data line routing electrode and the scan line routing electrode extend between two sides adjacent to the side of the substrate. A tiling electrode for connecting two or more transistor arrays provided on the substrate, and connecting the tiling electrodes of the connected transistor arrays; and one tiling electrode. And a step of cutting the portion.

In the invention, in the method of connecting the transistor array according to claim 1, and a connecting portion and the data line lead-out electrode and the data line conductive portion are electrically connected, the scan line lead-out electrodes and scan lines according to claim 2 The connection part which electrically connects with the conduction | electrical_connection part is distribute | arranged to the periphery of the said base material, It is characterized by the above-mentioned.

According to a third aspect of the present invention, there is provided the connection method of the transistor array coupling method according to the first or second aspect , wherein the data line routing electrode and the data line conduction portion are electrically connected as viewed from the stacking direction. In addition, a connection portion where the scan line routing electrode and the scan line conduction portion are electrically connected is covered with the pixel electrode.

According to a fourth aspect of the present invention, in the transistor array coupling method according to any one of the first to third aspects, the data line routing electrode extending to one side of the substrate and the An ESD ring is disposed around the scan line routing electrode.

According to a fifth aspect of the present invention, in the method for connecting transistor arrays according to any one of the first to fourth aspects, a signal is supplied to the data line routing electrode and the scan line routing electrode on the substrate. A driver IC is provided for supplying power.

  According to the transistor array of the present invention, it becomes possible to manufacture a unit display panel in which electrodes are drawn out from only one side of the rectangular display area, so that the number of unit display panels for tiling is limited. Therefore, a larger display device can be easily manufactured.

  Further, according to the transistor array of the present invention, the unit display panel can be manufactured at a low cost, so that a large display device manufactured by tiling the unit display panel can be manufactured at a low cost.

  In addition, according to the transistor array coupling method of the present invention, unit display panels can be simply coupled, so that a larger display device can be manufactured without increasing the cost.

It is a perspective view of the base material 10 used in order to comprise the transistor array 1 which concerns on embodiment of this invention. 1 is a perspective view of a transistor array 1 according to an embodiment of the present invention. It is a figure explaining the structure of one pixel 310 of the transistor array 1 which concerns on embodiment of this invention. It is a figure which shows the equivalent circuit of the transistor array 1 which concerns on embodiment of this invention. 1 is an exploded perspective view of a unit display panel 500 configured by a transistor array 1 according to an embodiment of the present invention. 1 is a perspective view of a unit display panel 500 configured by a transistor array 1 according to an embodiment of the present invention. It is a disassembled perspective view of the laminated structure outline of the transistor array 1 which concerns on other embodiment of this invention. It is a perspective view of the base material 10 used in order to comprise the transistor array 1 which concerns on other embodiment of this invention. It is a figure explaining the connection method of the transistor array 1 which concerns on other embodiment of this invention. It is a schematic diagram which shows the example of a layout of the display panel 500 at the time of manufacturing a tiling display. It is a schematic diagram which shows the example of a layout of the display panel 500 at the time of manufacturing a tiling display. 4 is a diagram schematically showing a configuration example of a display panel 500. FIG. It is a perspective view of the transistor array 1 which concerns on other embodiment of this invention. It is a figure explaining that diode D1, D2 of the ESD ring 600 can be comprised by transistor Tr1, Tr2.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view of a base material 10 used for constituting a transistor array 1 according to an embodiment of the present invention, and FIG. 2 is a perspective view of the transistor array 1 according to an embodiment of the present invention. FIG. 2 shows the transistor array 1 formed by laminating a predetermined material on the base material 10 shown in FIG. The transistor array 1 is for performing display control of a display area 300 having pixels 310 arranged in an 8 × 8 matrix. The number of pixels 310 constituting the display area 300 is not limited to 8 × 8, and may be arbitrary. Further, the number of pixels 310 constituting the display area 300 is smaller than the actual one for convenience of illustration.

  FIG. 5 is an exploded perspective view of the unit display panel 500 including the transistor array 1 according to the embodiment of the present invention. The display layer 400 and the transparent electrode layer are formed on the transistor array 1 built on the substrate 10. A state in which 450 is sequentially laminated is shown. FIG. 6 is a perspective view of a unit display panel 500 including the transistor array 1 according to the embodiment of the present invention.

  In the present embodiment, a transistor array 1 that drives a display panel as a unit for configuring a large display device by tiling will be described as an example. As the unit display panel as described above, for example, electronic paper is assumed, and the substrate 10 will be described based on the case where a flexible material is used. However, the transistor array 1 of the present invention is applied. Possible display panels are not limited to electronic paper, but can be applied to other display elements.

  As a material used for the base material 10, for example, a material mainly composed of polyimide and excellent in flexibility, insulation, and heat resistance can be used. The substrate 10 is not limited to this, and examples of the base material 10 include polyethylene naphthalate, polyethylene terephthalate, polyether sulfone, polycarbonate, polyether imide, polyether ether ketone, polyether ketone, polyphenylene sulfide, liquid crystal polymer, epoxy resin, and silicone resin. Finol resin and the like can be used. In the present invention, any of these insulating materials can be suitably used. In addition, the insulating material used for the base material 10 may be only one type, or may be two or more types.

As shown in FIG. 1, the main surface of the substrate 10 is formed in a rectangular shape, and a data line routing electrode 100 for supplying a signal to the data line of the active matrix transistor array 1 and the transistor array 1 A scan line routing electrode 200 for supplying a signal to the scan line is provided on the main surface. Also, a driver IC conduction electrode 30 used for supplying a drive signal to the driver IC 50 that generates a signal to be supplied to the data line routing electrode 100 and the scan line routing electrode 200 is also formed on the main surface. Yes.

  In the present embodiment, both the data line driver IC 50 and the scan line driver IC 50 are arranged on the side DA side of the rectangular ABCD of the substrate 10. Further, the data line routing electrode 100 and the scan line routing electrode 200 connected to the driver IC 50 are also integrated on the side DA side.

  The data line routing electrode 100 aggregated on the side DA side is routed to the side AB and electrically connected to a circuit formed in the vertical direction (stacking direction) of the main surface from the side AB through a through hole. Configured to do.

  Further, the scan line routing electrode 200 aggregated on the side DA side is routed to the side BC and is connected to a circuit formed in the vertical direction (stacking direction) of the main surface from the side BC via a through hole. Configured for electrical connection.

  In the embodiment shown in FIG. 1, the data line routing electrode 100 is routed to the periphery of the side AB of the substrate 10, and the scan line routing electrode 200 is routed to the periphery of the side BC of the substrate 10. However, it is not necessary to form each of these electrodes on the periphery of the base material 10 (that is, at the edge of the base material 10) from the initial stage of manufacture. For example, it is possible to prepare a base material having a margin, configure the transistor array 1 as in the present embodiment, and remove the margin by cutting with a laser or a cutting machine at the final stage of manufacture.

  In the present embodiment, the conductive material used for the electrical connection portion in the data line routing electrode 100, the scan line routing electrode 200, the driver IC conduction electrode 30, or the like or the electrical connection portion in the through hole or the like is a connection having desired conductivity. The electrode is not particularly limited as long as the electrode can be formed. Examples of such a conductive material include metal materials such as gold, copper, silver, aluminum, chromium, nickel, and tin, conductive polymer materials such as polyaniline and polyethylenedioxythiophene, and oxides such as ITO and IZO. Can be mentioned.

  As shown in FIG. 2, the data line routing electrode 100 is electrically connected to a circuit constituting the eight pixels 310 arranged in the side AB on the side AB. Similarly, the scan line routing electrode 200 is connected to the side BC on the side BC. The circuit is configured to be electrically connected to the circuits constituting the eight pixels 310 arranged in the BC.

  The pixel 310 indicated by P in FIG. 2 has a structure in which it is directly electrically connected to both the data line routing electrode 100 and the scan line routing electrode 200. Therefore, taking the pixel 310 indicated by P as an example, how the data line routing electrode 100 and the scan line routing electrode 200 are connected to the circuit constituting the pixel 310 in the stacking direction will be described.

In the present embodiment, the data line routing electrode 100 is electrically connected to a circuit constituting the eight pixels 310 arranged in the side AB, and the scan line routing electrode 200 is set in eight pixels in the side BC. 310 is directly connected to the data line, and the data line routing electrode 100 and the data line conduction unit 110 are electrically connected, and the scan line routing electrode 200 and the scan line conduction unit 210 are electrically connected. Although the connection portion is arranged on the periphery of the base material 10, such a layout is not an essential configuration.

  For example, in FIG. 2, the data line routing electrode 100 that is directly connected to the pixel 310 indicated by P may be configured to be connected to any of the eight pixels 310 arranged on the side BC side. . For this reason, as described above, the layout in which each of the connection portions is arranged on the periphery of the base material 10 is not an essential component.

  FIG. 3 is a diagram illustrating the structure of one pixel 310 of the transistor array 1 according to the embodiment of the present invention. 3A is a view of a conductor portion and a semiconductor portion constituting the pixel 310 shown in FIG. 3P as viewed from the stacking direction, and FIG. 3B shows a cross section taken along line XX ′ in FIG. 3C shows a cross section taken along line YY ′ in FIG. 3A, and FIG. 3D shows a cross section taken along line ZZ ′ in FIG.

  FIG. 4 is a diagram showing an equivalent circuit of the transistor array 1 according to the embodiment of the present invention. As shown in FIG. 3, the circuit constituting one pixel 310 of the transistor array 1 is provided so as to correspond to the lattice points of the data line and the scan line, and the circuit of one pixel 310 is a field effect transistor Tr. And a series connection of two capacitors Cs and Cp connected in parallel. In this circuit, the source electrode of the transistor Tr is connected to the data line, and the gate electrode is connected to the scan line. Further, the drain electrode of the transistor Tr is connected to the upper electrode 331 side constituting the capacitor Cs and the pixel electrode 330 side constituting the capacitor Cp. Here, the capacitor Cs is for accumulating a signal supplied to the pixel 310 for a relatively long time, and the capacitor Cp is a transparent electrode layer 450 facing the pixel electrode 330 through the display layer 400. It is the capacity that occurs between. Vcom in FIG. 4 indicates the potential of the transparent electrode layer 450 and is common to all the pixels 310. In the above circuit, Vcom is electrically connected to the lower electrode 332 of the capacitor Cs and the transparent electrode layer 450 side of the capacitor Cp.

  As shown in FIG. 3B, the data line routing electrode 100 arranged on the base material 10 is connected to the data line conducting portion 110 via the electrical connecting portion Th. The data line conducting part 110 is a conducting part corresponding to the data line in the equivalent circuit of FIG. As shown in FIG. 3A, in each pixel 310, the source electrode 322 is drawn from the data line conducting portion 110. The data line conducting portion 110 is conducted to the circuit of the adjacent pixel 310 arranged in the vertical direction as viewed in FIG.

  As shown in FIG. 3C, the scan line routing electrode 200 disposed on the base material 10 is connected to the scan line conducting part 210 via the electrical connection part Th. The scan line conducting unit 210 is a conducting unit corresponding to the scan line in the equivalent circuit of FIG. As shown in FIG. 3A, in each pixel 310, the gate electrode 323 is drawn from the scan line conducting portion 210. The scan line conducting portion 210 is conducted to the circuit of the adjacent pixel 310 arranged in the horizontal direction as seen in FIG.

  As shown in FIG. 3D, the source electrode 322 extracted from the data line conduction unit 110, the gate electrode 323 extracted from the scan line conduction unit 210, and a layer at the same level as the source electrode 322 are provided. A transistor Tr is configured by the drain electrode 321, the semiconductor layer 324, and the gate insulating layer 342.

  The upper electrode 331 of the capacitor Cs is connected to one end of the source electrode 322 constituting the transistor Tr as described above. As shown in FIG. 3D, the upper electrode 331 is further connected to the pixel electrode 330 through the electrical connection portion Th. The pixel electrode 330 is provided so as to cover the entire pixel 310 when viewed from the stacking direction.

  In this embodiment, when viewed from the stacking direction of the pixel electrode 330, the data line routing electrode 100 shown in FIG. 3B and the electrical connection portion Th of the data line conducting portion 110 and the scan line shown in FIG. One feature is that the lead electrode 200 and the electrical connection portion Th of the scan line conduction portion 210 overlap each other. Signals for display on the unit display panel 500 are carried on the above two electrical connection portions, and voltage fluctuations due to these signals tend to cause interference in the peripheral configuration. Since the pixel electrode 330 is covered, the pixel electrode 330 functions as a shield, so that the effect of suppressing the interference can be expected.

  In the present specification and claims, the first configuration is covered by the second configuration when viewed from the stacking direction when the projection by the first configuration is performed when the projection is performed in the stacking direction. It is included in the projection with two configurations.

  In a layer at the same level as the layer where the gate electrode 323 is formed, a lower electrode 332 is provided so as to face the upper electrode 331, and a capacitor Cs is formed by these facing electrodes. Further, the lower electrode 332 is provided with a connection electrode 335 so as to be electrically connected to the lower electrode 332 constituting the pixel 310 adjacent in the horizontal direction. A series of lower electrodes 332 that are adjacent to each other in the horizontal direction are connected via the connection electrode 335, and are electrically connected to the transparent electrode layer 450 constituting the uppermost surface portion of the display panel 500 via a transfer gate (not shown). Connected. A capacitor Cp is formed by the pixel electrode 330 and the transparent electrode layer 450 facing the pixel electrode 330.

  In the transistor array 1 as described above, an interlayer insulating layer 341, a gate insulating layer 342, and a sealing layer 343 are provided as insulating layers at each layer level. Here, a semiconductor material used for the semiconductor layer 324 and an insulating material used for the interlayer insulating layer 341, the gate insulating layer 342, the sealing layer 343, and the like are described.

  The semiconductor layer 324 used in the present invention is not particularly limited as long as it exhibits desired transistor characteristics depending on the use of the transistor array 1 and the like. As such a semiconductor layer 324, for example, an organic transistor using an organic semiconductor material, an amorphous silicon transistor using a silicon material, a polysilicon transistor, an InGaZnO transistor using a semiconductor oxide material, a ZnO transistor, or the like can be used. Can be mentioned. In the present invention, any of these semiconductor layers 324 can be suitably used, but in the present invention, an organic transistor is preferably used. This is because by using an organic transistor as the semiconductor layer 324, the transistor array 1 of the present invention can be manufactured more simply.

The organic transistor used in the present invention is not particularly limited as long as an organic semiconductor layer made of an organic semiconductor material is used and functions as a transistor. Examples of the organic semiconductor material used for such an organic transistor include a π-electron conjugated aromatic compound, a chain compound, an organic pigment, and an organic silicon compound. More specifically, low molecular organic semiconductor materials such as pentacene, and polypyrroles such as polypyrrole, poly (N-substituted pyrrole), poly (3-substituted pyrrole), and poly (3,4-disubstituted pyrrole). , Polythiophene, poly (3-substituted thiophene), poly (3,4-disubstituted thiophene), polythiophenes such as polybenzothiophene, polyisothianaphthenes such as polyisothianaphthene, and polychess such as polychenylene vinylene Nylene vinylenes, poly (p-phenylene vinylenes) such as poly (p-phenylene vinylene), polyanilines such as polyaniline and poly (N-substituted aniline), polyacetylenes such as polyacetylene, polyazulenes such as polydiacetylene and polyazulene High molecular organic semiconductor materials such as Of these, pentacene or polythiophenes can be preferably used in the present invention.

  Examples of the insulating material used for the interlayer insulating layer 341, the gate insulating layer 342, the sealing layer 343, and the like include silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, barium strontium titanate (BST), and zircon titanate. Insulating inorganic materials such as lead acid (PZT) and insulating organic materials such as acrylic resins, phenolic resins, fluorine resins, epoxy resins, cardo resins, vinyl resins, imide resins, and novolac resins An insulating organic material such as a material can be used.

  As shown in FIG. 5, the display layer 400 and the transparent electrode layer 450 are sequentially stacked on the upper surface portion of the transistor array 1 configured as described above. Here, the display layer 400 can be appropriately selected according to the display method of electronic paper. As a display method of electronic paper, known ones can be applied, for example, electrophoresis method, twist ball method, powder movement method (electronic powder fluid method, charged toner type method), liquid crystal display method, thermal method. (Coloring method, light scattering method), electrodeposition method, movable film method, electrochromic method, electrowetting method, magnetophoresis method and the like.

  The material of the transparent electrode layer 450 is not particularly limited as long as it is a conductive material capable of forming a transparent electrode. For example, indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide, Conductive oxides such as zinc oxide, indium oxide, and aluminum zinc oxide (AZO) can be used.

  When the display layer 400 and the transparent electrode layer 450 are stacked on the transistor array 1, each transfer gate (not shown) and the transparent electrode layer 450 are electrically connected by a conduction portion (not shown) and two drivers are provided. IC50 is mounted. Of these, the driver IC 50 for the data line is electrically connected to the data line routing electrode 100 and the driver IC conduction electrode 30, and the driver IC 50 for the scan line is electrically connected to the scan line routing electrode 200 and the driver IC conduction electrode 30. Thus, the display panel 500 is completed. Such a display panel 500 has a configuration in which a lead-out electrode is drawn out from only one side of the display area 300, and is used as a unit display panel 500 for manufacturing a large display device by tiling a plurality of the display panels. Is done.

  Here, again, the configuration peculiar to the transistor array 1 according to the present embodiment will be organized. When the display panel 500 is configured by the transistor array 1 of the present invention, the configuration in which the routing electrode is led out from only one side of the display area 300 is that the data line routing electrode 100 and the scan line routing electrode 200 are arranged in the stacking direction. This is because it overlaps with the display area 300 as viewed from the viewpoint.

Here, in the embodiment described with reference to FIGS. 1 to 6, the data line routing electrode 100 and the scan line routing electrode 200 both overlap the display area 300 as viewed from the stacking direction, so that only one side of the routing electrode is provided. However, the present invention is not limited to such a case, and can be realized by superimposing one of the data line routing electrode 100 and the scan line routing electrode 200 on the display area 300. Such a case will be described with reference to FIG. FIG. 7 is an exploded perspective view schematically showing a stacked structure of a transistor array 1 according to another embodiment of the present invention.

  In FIG. 7, a region corresponding to the one-dot chain line indicates a region that becomes the display area 300 after the transistor array 1 is formed on the base material 10. Considering the rectangular ABCD formed by the display area 300 as a reference, the scan line routing electrode 200 is concentrated on the side AB side on the base material 10 used in the transistor array 1 according to another embodiment. Yes.

  In a range surrounded by a dotted line on the interlayer insulating layer 341, a configuration S such as the gate electrode 323 that conducts with the scan line is arranged, and each configuration S includes a through-hole conducting portion on the side AB side. Conducted through (not shown).

  In addition, in a range surrounded by a dotted line on the gate insulating layer 342, a configuration D such as the source electrode 322 that is electrically connected to the data line is arranged, and each configuration D is electrically connected to the data line routing electrode 100. .

  In general, the transistor array 1 having the stacked structure as described above can be manufactured. In the case of such a transistor array 1, the display area 300 overlaps with the scan line leading electrode as viewed from the stacking direction. Only 200. As described above, the transistor array 1 according to the present invention can be realized by configuring so that either the data line routing electrode 100 or the scan line routing electrode 200 overlaps the display area 300.

  In addition, in the present specification and claims, the first configuration and the second configuration are superimposed when viewed from the stacking direction, when the projection is performed in the stacking direction, It shows that the projection according to the second configuration overlaps.

  According to the transistor array 1 of the present invention as described above, the unit display panel 500 in which the data line lead electrode 100 and the scan line lead electrode 200 are drawn from only one side of the rectangular display area 300 can be manufactured. Therefore, the number of unit display panels 500 on which tiling is performed is not limited, and a larger display device can be easily manufactured.

  Further, the transistor array 1 of the present invention has a simple structure in which either one of the data line routing electrode 100 or the scan line routing electrode 200 is configured to overlap the display area 300, so that the unit display panel 500 can be manufactured at low cost, and a large-sized display device manufactured by tiling it can be manufactured at low cost.

  Returning to the embodiment shown in FIGS. In the present embodiment, the data line routing electrode 100 and the scan line routing electrode 200 are arranged so as to extend to one side of the substrate 10 (side DA in FIG. 1). Thus, the number of unit display panels 500 to be performed is not limited, and an effect that a larger display device can be easily manufactured can be obtained.

  Further, in the present embodiment, the connection part where the data line routing electrode 100 and the data line conduction part 110 are electrically connected and the connection part where the scan line routing electrode 200 and the scan line conduction part 210 are electrically connected are the base material 10. It is characterized by being arranged in the periphery (side AB and side BC vicinity of FIG. 1), and it can be said that the effect similar to the above is enjoyed also by such a feature point.

  Next, another embodiment of the present invention will be described. FIG. 8 is a perspective view of a base material 10 used for constituting a transistor array 1 according to another embodiment of the present invention, which corresponds to FIG. 1 in the previous embodiment. In the present embodiment, for tiling that conducts between two sides (side AB and side CD) adjacent to one side (DA) of the substrate 10 on which the data line routing electrode 100 and the scan line routing electrode 200 extend. It differs from the previous embodiment in that the electrode 70 is provided on the substrate 10.

  The tiling electrode 70 is a plurality of linear electrodes that conduct from the side AB to the side CD. The number of filament electrodes provided as the tiling electrode 70 is not particularly limited. Further, all of the filament electrodes constituting the tiling electrode 70 are electrically connected to the driver IC conductive electrode 30. Since the method of manufacturing the transistor array 1 and the display panel 500 based on the base material 10 configured as described above is the same as that of the previous embodiment, the description thereof is omitted.

  Next, a method for manufacturing a large display device by connecting the transistor array 1 (or the display panel 500) according to this embodiment will be described. FIG. 9 is a diagram for explaining a connection method of the transistor array 1 according to another embodiment of the present invention. In FIG. 9, a case where two of the display panel 500 and the display panel 500 'manufactured based on the base material 10 shown in FIG. 8 are connected will be described as an example.

When two display panels or transistor arrays are connected to each other, as shown in FIG. 9, the display panel 500 is arranged so that the line electrodes of the tiling electrodes 70 provided on the two base materials are coincident with each other. The display panel 500 ′ is disposed. Next, tiling on the display panel 500 is performed by the connecting flexible printed circuit board 550 (the dotted line portion in the drawing is a conductive portion) provided with the line electrodes in the tiling electrode 70 and the same arrangement of line electrodes. The line electrode of the electrode for use 70 and the line electrode of the electrode for tiling 70 on the display panel 500 ′ are made conductive. Next, the portions indicated by FIG. 9 × (cross mark) on the tiling electrode 70 and the driver IC conduction electrode 30 are cut by a laser or the like. As a result, the filament electrode of the tiling electrode 70 is electrically connected to an appropriate driver IC 50, and therefore, the tiling electrode 70 can be used as a conductive portion for driving the driver IC 50.

  According to the connecting method of the transistor array 1 according to the present invention as described above, one kind of common standard transistor array 1 provided with the tiling electrode 70 is provided, and these are connected to provide unnecessary tiling. Since a large display device can be configured simply by cutting the electrode 70, the manufacturing cost of a tiling display (display device) can be reduced.

  In addition, according to the connection method of the transistor array 1 of the present invention, the unit display panels 500 can be easily connected, so that a larger display device can be manufactured without increasing the cost.

Here, a layout example when a large display device (tiling display) is configured using the unit display panel 500 manufactured based on the present invention will be described. When viewed from the stacking direction of the display panel 500, the display panel 500 is generally configured by a display unit 510 including the display area 300 and a wiring unit 520 provided with a driver IC, the routing electrode 100, and the like. When a tiling display is manufactured using such a unit display panel 500, a layout as shown in FIG. 10 is taken to constitute a display without providing any overlapping portion between the unit display panels 500. It becomes possible. According to the layout example shown in FIG. 10, it is possible to provide an unlimited number of display panels 500 without overlapping each other.

  In the example of FIG. 10, when the tiling display is manufactured, the unit display panels 500 are laid out so as not to overlap each other. However, the present invention is not limited to this, and the unit display panels 500 may be laid out so as to overlap each other. It is. FIG. 11A is a schematic view of the layout of the overlapping portion viewed from the stacking direction, and FIG. 11B is a schematic view of the layout viewed from the cross-sectional direction. In this embodiment, since the unit display panel 500 can be manufactured thinly, it is possible to manufacture a tiling display in which joints are not conspicuous even if the unit display panel 500 is laid out so as to have an overlapping portion as shown in FIG. it can.

  10 and 11, a method for manufacturing a display by laying out a plurality of unit display panels 500 has been described. However, a single unit display panel 500 may be used as a display. When the display is configured only by the unit display panel 500, the flexible display unit 510 other than the wiring unit 520 provided with a driver IC or the like can be a display that can be rolled, for example.

  Next, another embodiment of the present invention will be described. FIG. 12 is a diagram schematically illustrating a configuration example of the display panel 500, and is a diagram illustrating a cross-sectional structure of the display panel 500. In the embodiment described so far, as shown in FIG. 12A, one display layer 400 is stacked on one transistor array 1, and one transparent electrode 450 is further stacked thereon to form a display panel 500. I was trying to compose. On the other hand, as another embodiment, a display panel 500 as shown in FIG. 12B can be configured. That is, in configuring the display panel 500, one display layer 400 may be stacked on the two tiling transistor arrays 1, 1 ′, and one transparent electrode 450 may be further stacked thereon. Good. Furthermore, not limited to the example of FIG. 12B, the display panel 500 may be configured by stacking a combination of an arbitrary number of display layers and transparent electrodes on an arbitrary number of tiled transistor arrays. it can.

  Next, another embodiment of the present invention will be described. FIG. 13 is a perspective view of a transistor array 1 according to another embodiment of the present invention. The present embodiment is different from the embodiments described so far in that an ESD ring 600 is arranged around the data line routing electrode 100 and the scan line routing electrode 200 extending to one side of the substrate 10. It is characterized by that.

  As shown in the balloon of FIG. 13, the ESD ring 600 electrically surrounds the periphery of the data line routing electrode 100, the scan line routing electrode 200, and the transfer gate, and the data line routing electrode 100 (or the scan line routing electrode). 200, or a transfer gate), diodes D1 and D2 are connected.

  As shown in FIG. 14, the diodes D1 and D2 can be configured by short-circuiting one of the source and drain electrodes of the gate electrodes of the transistors Tr1 and Tr2 similar to the transistors described in the previous embodiment. A laminated structure for this purpose can be realized by applying the structure described in FIG.

ESD is an abbreviation for Electro Static Discharge, and the ESD ring 600 as described above is provided around the data line routing electrode 100 and the scan line routing electrode 200 and the transfer gate, whereby the data line routing electrode 100 and the scan line routing are provided. Static electricity generated in the electrode 200, the transfer gate, and the base material 10 can be released to the ESD ring 600 side via the diodes D1 and D2. According to the embodiment in which the ESD ring 600 is provided as described above, the ESD ring 600 is also arranged on one side of the base material 10, like the data line routing electrode 100 and the scan line routing electrode 200. Seamless tiling using the remaining three sides is performed, and a large display device can be configured.

  As described above, according to the transistor array of the present invention, it is possible to manufacture a unit display panel in which the lead-out electrode is drawn out from only one side of the rectangular display area. There is no limitation, and a larger display device can be easily manufactured.

  Further, according to the transistor array of the present invention, the unit display panel can be manufactured at a low cost, so that a large display device manufactured by tiling the unit display panel can be manufactured at a low cost.

In addition, according to the transistor array coupling method of the present invention, unit display panels can be simply coupled, so that a larger display device can be manufactured without increasing the cost.
(Example)
A PEN film substrate was used as the substrate 10, and Al (film thickness 150 nm) and then Cr (film thickness 20 nm) were sputter-deposited thereon and laminated on the entire surface of the substrate. Subsequently, the Al / Cr laminated thin film was patterned by a photolithography process and an etching process to form a data line routing electrode 100 and a scan line routing electrode 200.

  Next, ultraviolet photosensitive acrylic resin was spin-coated on the lead-out electrode, exposure through a photomask and an alkali development process were performed, and through holes were patterned. Subsequently, it was heat-cured in an oven at 150 ° C. to form an interlayer insulating layer 341 (film thickness: 3 μm).

  Subsequently, Al (thickness: 150 nm) is sputter-deposited on the interlayer insulating layer 341, and then the Al thin film is patterned by a photolithography process and an etching process to form the scan line conductive portion 210, the gate electrode 323, and the Cs lower electrode 332. Formed. In this step, the scan line routing electrode 200 and the scan line conducting part 210 are conducted.

  Next, an ultraviolet photosensitive acrylic resin was spin-coated on the surface on which the gate electrode 323 was formed, exposure through a photomask and an alkali development process were performed, and patterning of the through hole of the data line conduction portion 110 was performed. Subsequently, it was cured by heating in an oven at 150 ° C. to form a gate insulating layer 342 (film thickness 1 μm).

Next, a positive photoresist is applied onto the gate insulating layer 342 by spin coating, and after exposure and development processes using a photomask, the data line conducting portion 110, the source electrode 322 and the drain electrode 321, and the Cs upper electrode 331. The photoresist in the formation area was removed. Next, Au (film thickness 50 nm) was sputter-deposited to form an Au thin film on the entire surface of the photoresist. Next, the photoresist and the Au thin film on the photoresist were removed in an ultrasonic bath while being immersed in acetone, and the data line conducting portion 110, the source electrode 322, the drain electrode 321, and the Cs upper electrode 331 were formed. In this step, the data line routing electrode 100 and the data line conducting portion 110 are conducted.

Next, an organic semiconductor solution in which a thiophene polymer is dissolved in a monochlorobenzene solution at a solid concentration of 1 wt% is prepared, and an organic semiconductor layer having a thickness of 50 nm is formed on the entire surface on which the source / drain electrodes are formed by spin coating. Formed. Next, an ultraviolet photosensitive acrylic resin was spin-coated on the organic semiconductor layer, exposure through a photomask and an alkali development process were performed, and the acrylic resin was patterned on the transistor channel region. Next, the resin was heated and cured in an oven at 150 ° C. to form an acrylic resin on the transistor channel region.

  Next, vacuum ultraviolet rays (wavelength: 172 nm, illuminance: 3 mW / cm 2) were irradiated for 60 seconds in the atmosphere, and the organic semiconductor in a region other than that covered with the acrylic resin was removed by ashing, and the semiconductor was patterned. Thereby, the semiconductor layer 324 was obtained.

  Next, ultraviolet photosensitive acrylic resin was spin-coated, exposure through a photomask and an alkali development process were performed, and patterning of the through hole of the pixel electrode 330 conduction portion (electric connection portion Th) was performed. Subsequently, it was cured by heating in an oven at 150 ° C. to form a sealing layer (film thickness: 10 μm).

  Next, the carbon paste was subjected to pattern printing by screen printing so as to cover the data line conduction part 110 and the scan line conduction part 210, thereby forming a pixel electrode (film thickness: 5 μm). In this step, the pixel electrode 330 and the Cs upper electrode 331 are made conductive.

  Next, the data line routing electrode 100 and the scan line routing electrode 200 are cut by a cutting machine except for one side extending outside the display area to form a transistor array 1 having three sides as a frame. did. As a result of the cutting, the frame on the three sides was about 100 μm wide.

  Subsequently, four pieces of the transistor array 1 having a display area of 100 mm × 100 mm produced in the above process were bonded to an electronic paper sheet of a twist ball type having a size of 200 mm × 200 mm using an adhesive material. At this time, the base material of the transistor array 1 which is a separate body was bonded and fixed at about 50 μm to produce a display panel 500 (tiling display).

  A predetermined signal was sent from the produced display panel 500 data line routing electrode 100 and scan line routing electrode 200 to display a pattern on the electronic paper sheet. As a result, the non-responsive area of the electronic paper sheet in the gap between the separate transistor arrays 1 was about 200 μm wide, and a tiling display with reduced joints between the transistor arrays 1 could be produced. Further, in the same process as the transistor manufacturing process described above, an ESD ring is formed by disposing a diode on one side where the data line routing electrode 100 and the scan line routing electrode 200 extend outside the display area, We were able to contribute to the framing of the three sides.

DESCRIPTION OF SYMBOLS 1 ... Transistor array 10 ... Base material 30 ... Driver IC conduction electrode 50 ... Driver IC
70 ... Tiling electrode 100 ... Data line routing electrode 110 ... Data line conducting portion 200 ... Scan line routing electrode 210 ... Scan line conducting portion 300 ... Display area 310 ... Pixel 321 ... Drain electrode 322 ... Source electrode 323 ... Gate electrode 324 ... Semiconductor layer 330 ... Pixel electrode 331 ... Upper electrode 332 ... Lower electrode 341 ... Interlayer insulating layer 342 ... Gate insulating layer 343 ... Sealing layer 400 ... Display layer 450 ... Transparent electrode layer 500 ... Display panel 510 ... Display unit 520 ... Wiring unit 550 ... Connection Flexible printed circuit board 600 ... ESD ring Th ... electrical connection

Claims (5)

A base material having a rectangular main surface;
A data line routing electrode and a scan line routing electrode arranged in the stacking direction with respect to the main surface of the substrate;
A data line conducting portion electrically connected to the data line routing electrode;
A scan line conducting portion electrically connected to the scan line routing electrode;
Have a, a plurality comprises display area pixel electrode predetermined voltage is held by a circuit including a transistor which is driven by a signal from the said scan line conductive section and the data line conductive section,
When viewed from the stacking direction, at least one of the data line routing electrode or the scan line routing electrode is overlapped with the display area ,
The data line routing electrode and the scan line routing electrode are arranged so as to extend to one side of the substrate,
Two or more transistor arrays each having a tiling electrode connected to one side of the substrate on which the data line routing electrode and the scan line routing electrode extend are connected to each other are connected to the substrate. And conducting the tiling electrodes between the connected transistor arrays; and
And a step of cutting off a part of the tiling electrode. The connection part where the data line routing electrode and the data line conduction part are electrically connected and the connection part where the scan line routing electrode and the scan line conduction part are electrically connected are arranged on the periphery of the base material. The method of connecting transistor arrays according to claim 1 . When viewed from the stacking direction, the pixel electrode covers a connection portion where the data line routing electrode and the data line conduction portion are electrically connected and a connection portion where the scan line routing electrode and the scan line conduction portion are electrically connected. The transistor array connection method according to claim 1, wherein the transistor array is connected . 4. The ESD ring according to claim 1 , wherein an ESD ring is disposed around the data line routing electrode and the scan line routing electrode extending to one side of the base material. 5. The connection method of the transistor array of description. 5. The transistor array according to claim 1 , wherein a driver IC that supplies a signal to the data line routing electrode and the scan line routing electrode is disposed on the substrate . 6. Consolidation method .

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