JP5110325B2 - Light emitting device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a light emitting device and a method for manufacturing the same, and more particularly to a light emitting device including a display panel in which a plurality of display pixels each having a self light emitting element are arranged on a substrate, and a method for manufacturing the same.

  In recent years, as a next-generation display device following a liquid crystal display (LCD), a display device including a light-emitting element type display panel in which a plurality of display pixels each having a self-light-emitting element is two-dimensionally arranged has been widespread. For example, a display panel (organic EL display panel) in which organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”) are two-dimensionally arranged is known as a display device for electronic devices such as mobile phones and portable music players. Yes.

  As is well known, an organic EL element has an element structure in which, for example, an anode (anode) electrode, an organic EL layer (light emitting functional layer), and a cathode (cathode) electrode are sequentially laminated on one side of a glass substrate or the like. Have. Then, by applying a voltage between the anode electrode and the cathode electrode so as to exceed the emission threshold value in the organic EL layer, based on the energy generated when the holes and electrons injected in the organic EL layer recombine. Light (excitation light) is emitted. The organic EL layer generally has a configuration in which a carrier transport layer such as a hole transport layer or an electron transport layer, and a light emitting layer are sequentially laminated.

  Here, in order to prevent the organic EL layer from being deteriorated by moisture in the organic EL display panel, for example, Patent Document 1 includes a glass substrate or the like so as to face the element substrate on which the organic EL element is formed. A sealing structure in which a sealing substrate is sealed with an adhesive to block outside air is disclosed.

JP 2000-0608048 A

  In the organic EL display panel as described above, generally, an organic EL element is arranged on a substrate to form a display area, and the organic EL element is driven to emit light in a peripheral area surrounding the display area on the substrate. Various wirings for supplying signals and power supply voltages are provided. For this reason, a space for wiring must be provided outside the display area, which increases the size of the peripheral area of the display panel, and restricts the product design and size. In addition, when the size of the peripheral area (frame) of the display panel is large, the number of panel substrates cut out from one mother glass is reduced at the time of manufacturing the display panel, resulting in an increase in product cost. Had.

  In view of the above-described problems, an object of the present invention is to provide a light emitting device having a panel structure capable of narrowing the frame of a display panel and a manufacturing method thereof.

The light-emitting device according to the first aspect of the present invention includes a display region in which a plurality of display pixels are arranged, and a peripheral portion in which ends of a plurality of signal lines connected to each of the display pixels are exposed. One substrate, a plurality of connection pads arranged to correspond to end portions of the signal lines, a control circuit for supplying a control signal for driving the display pixels to the signal lines, and the plurality of connections A second substrate having a plurality of connection wirings for individually connecting a pad and the control circuit; joining the first substrate to the second substrate; and end portions of the plurality of signal lines And a bonding member that electrically connects the plurality of connection pads individually, and the control circuit is covered with a planarization film formed on a surface of the second substrate, and the connection pads and the that the connection wiring is provided on the planarization layer And butterflies.

According to a second aspect of the present invention, in the light emitting device according to the first aspect, the control circuit is disposed inside a region of the second substrate that is bonded to the first substrate. To do.
According to a third aspect of the present invention, in the light emitting device according to the first or second aspect, a separation distance between the first substrate and the second substrate is a separation between the plurality of connection pads on the second substrate. It is characterized by being set smaller than the distance.
According to a fourth aspect of the present invention, in the light emitting device according to any one of the first to third aspects, the plurality of signal lines are applied with at least a plurality of selection signals for setting the display pixels in a selected state. And a plurality of data lines to which display data for driving the display pixels in a display state is supplied.
According to a fifth aspect of the present invention, in the light emitting device according to any one of the first to fourth aspects, the light emitting device is arranged outside a region bonded to the first substrate, and is electrically connected to the outside of the second substrate. A plurality of external connection pads for connection and a plurality of external connection wirings for individually connecting the plurality of external connection pads and the control circuit are provided on the second substrate. .
According to a sixth aspect of the present invention, in the light emitting device according to any one of the first to third aspects,
The plurality of signal lines include a plurality of scan lines to which a selection signal for setting the display pixel in a selected state is applied and a plurality of data to which display data for driving the display pixel in the display state is supplied. And a plurality of power supply voltage lines to which a power supply voltage supplied to the display pixel is applied,
The second substrate has a quadrilateral shape;
A plurality of external connection pads arranged on the first side of the second substrate outside the region bonded to the first substrate and electrically connected to the outside of the second substrate; A plurality of external connection wirings for individually connecting the external connection pads and the control circuit are provided on the second substrate,
The connection pads corresponding to the scan lines are arranged on the second side of the second substrate,
The connection pads corresponding to the data lines are arranged on the third side of the second substrate,
The connection pads corresponding to the power supply voltage line are arranged on a fourth side of the second substrate .
According to a seventh aspect of the present invention, in the light emitting device according to any one of the first to sixth aspects, the joining member is an anisotropic conductive adhesive.
The control circuit may be disposed outside the region of the second substrate where the first substrate is bonded.
The control circuit is preferably an integrated circuit formed into a thin film.
The display pixel may include a pixel driving circuit corresponding to an active matrix driving method and a light emitting element.
The light emitting element may be an organic electroluminescence element.

According to an eighth aspect of the present invention, there is provided a method for manufacturing a light emitting device, wherein a plurality of display pixels are arranged in a display region, and ends of a plurality of signal lines connected to each of the display pixels are exposed on an outer periphery of the display region. A control circuit for supplying a control signal for driving the display pixel to the signal line, a step of forming a first substrate to be formed, a plurality of connection pads arranged to correspond to the end portions of the signal line Bonding the first substrate and the second substrate using a single bonding member, forming a second substrate individually connected by a plurality of connection wirings, and seen containing a step of connecting a plurality of the end portion and the plurality of connection pads of the signal lines electrically individually, the step of forming the second substrate, the control on the surface of the second substrate A step of mounting a circuit, and the first circuit so as to cover the control circuit. Forming a planarizing film on the substrate, forming an opening through which the connection terminal of the control circuit is exposed in the planarizing film, and on the control circuit and the planarizing film through the opening Forming the connection wiring for connecting the connection pads formed on the substrate .

According to a ninth aspect of the present invention, in the method for manufacturing a light emitting device according to the eighth aspect, the step of forming the second substrate is performed in an area of the second substrate where the first substrate is bonded. Further, the control circuit is mounted.
The joining member may be an anisotropic conductive adhesive.
According to a tenth aspect of the present invention, in the method for manufacturing a light emitting device according to the eighth or ninth aspect , the first substrate and the second substrate when the first substrate and the second substrate are bonded together. The distance between the substrates is set to be smaller than the distance between the plurality of connection pads on the second substrate.

  According to the light emitting device and the manufacturing method thereof according to the present invention, the display panel can be narrowed, so that the degree of freedom in the product design and size of the display panel can be improved and the product cost can be reduced. Can do.

1 is a schematic configuration diagram illustrating a first embodiment of a light emitting device according to the present invention. It is a schematic plan view which shows an example of the pixel array substrate applied to the light-emitting device concerning this embodiment. It is a schematic plan view which shows an example of the opposing board | substrate applied to the light-emitting device which concerns on this embodiment. FIG. 3 is an equivalent circuit diagram illustrating a circuit configuration example of display pixels that are two-dimensionally arranged on the display panel according to the embodiment. It is a schematic block diagram of the light-emitting device which concerns on a comparison object. It is a schematic plan view which shows an example of the pixel array board | substrate applied to the light-emitting device which concerns on a comparison object. It is a schematic block diagram of the opposing board | substrate applied to the light-emitting device which concerns on 2nd Embodiment. It is a schematic block diagram of the opposing board | substrate applied to the light-emitting device which concerns on 3rd Embodiment. It is a schematic block diagram which shows the light-emitting device which concerns on 4th Embodiment. It is a schematic plan view which shows an example of the opposing board | substrate applied to the light-emitting device which concerns on this embodiment. It is a schematic block diagram which shows the light-emitting device which concerns on 5th Embodiment. It is a schematic plan view which shows an example of the opposing board | substrate applied to the light-emitting device which concerns on this embodiment.

Hereinafter, a light emitting device and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments.
<First Embodiment>
(Light emitting device)
First, a display panel (organic EL display panel) and display pixels applied to the light-emitting device according to the present invention will be described.

  FIG. 1 is a schematic configuration diagram showing a first embodiment of a light emitting device according to the present invention. 1A is a schematic side view of the light-emitting device according to the present embodiment, and FIG. 1B is a schematic plan view viewed from the field of view of the light-emitting device according to the present embodiment. (c) is a schematic sectional drawing which shows the cross section along the IA-IA line in the top view shown in FIG.1 (b). In this specification, “I” is used as a symbol corresponding to the Roman numeral “1” shown in FIG.

  FIG. 2 is a schematic plan view showing an example of a pixel array substrate applied to the light emitting device according to this embodiment. Here, FIG. 2 shows the pixel array substrate applied to the light emitting device according to the present embodiment as viewed from the side of the bonding surface with the counter substrate (that is, along the line IIB-IIB shown in FIG. 1A). It is a schematic plan view). In this specification, “II” is used for convenience for the symbol corresponding to the Roman numeral “2” shown in FIG. In the plan view shown in FIG. 2, for convenience of explanation, only the relationship between each wiring layer provided on the insulating substrate, the display region, and the peripheral portion is shown, and a light emitting element ( The display of an organic EL element) and a pixel driving circuit (see FIG. 4 described later) for driving the light emitting element to emit light is omitted.

  FIG. 3 is a schematic plan view showing an example of a counter substrate applied to the light emitting device according to this embodiment. Here, FIG. 3A shows the counter substrate applied to the light emitting device according to the present embodiment as viewed from the side of the bonding surface with the pixel array substrate (that is, IIIC-IIIC shown in FIG. 1A). FIG. 3B is a schematic cross-sectional view showing a cross section taken along line IIID-IIID in the plan view shown in FIG. 3A. In this specification, “III” is used as a symbol corresponding to the Roman numeral “3” shown in FIG. In FIGS. 2 and 3A, hatching is shown for the sake of convenience in order to clarify the region where the adhesive for bonding the pixel array substrate and the counter substrate is provided.

  The light emitting device according to this embodiment includes a pixel array substrate (first substrate) 10 and a counter substrate (second substrate) 20 as shown in FIGS. Yes. The pixel array substrate 10 and the counter substrate 20 are bonded together so as to face each other via a sealing material BND such as an anisotropic conductive adhesive (or a sealing material with an anisotropic conductive connector; a bonding member). The opposing surfaces are spaced apart from each other at a predetermined interval. Here, as shown in FIG. 1B, the pixel array substrate 10 and the counter substrate 20 are parallel flat plates each having a rectangular planar shape, and the counter substrate 20 is more than the pixel array substrate 10. It is set to be large. In particular, in the present embodiment, as shown in FIG. 1B, the positions of the end surfaces of the pixel array substrate 10 and the counter substrate 20 on the left side and the upper and lower sides of the pixel array substrate 10 and the counter substrate 20 are aligned. The end surface of the pixel array substrate 10 protrudes from the position of the end surface on the right side of the pixel array substrate 10 and is joined to the counter substrate 20 at the peripheral edge of each side of the pixel array substrate 10.

  As shown in FIGS. 1C and 2, the pixel array substrate 10 is made of an insulating substrate 11 such as glass, and is bonded to the counter substrate 20 (hereinafter referred to as “one side” for convenience). In addition, a display area 12 is provided. In addition, a peripheral portion where the sealing material BND is provided is set on the outer periphery of the display region 12. In the display area 12, for example, a plurality of display pixels PIX having light emitting elements such as organic EL elements are two-dimensionally arranged in a matrix, and control signals and display data for driving the light emitting elements of the display pixels PIX to emit light, Signal lines for supplying a power supply voltage and the like are arranged in the row direction and the column direction of the display region 12 corresponding to the arrangement of the display pixels PIX.

  Specifically, scanning lines Ls and power supply voltage lines La are arranged in the vertical direction (row direction) in FIG. 2, and data lines Ld are arranged in the horizontal direction (column direction) in the drawing. At each intersection of the scanning line Ls (or power supply voltage line La) and the data line Ld, a display pixel PIX including a light emitting element such as an organic EL element is provided. As will be described later, a selection signal for setting the display pixel PIX in each row to a selected state is applied to the scanning line Ls. Further, as will be described later, a power supply voltage (for example, an anode voltage) Vdd for causing the light emitting elements of the display pixels PIX in each row to emit light is applied to the power supply voltage line La. As will be described later, display data (for example, gradation voltage) for causing the light emitting elements of the display pixels PIX in each column to emit light with a desired luminance is applied to the data line Ld. The details of the display pixel PIX and the relationship between the display pixel PIX and each signal line will be described in detail later.

  On the other hand, at the peripheral edge set on the outer periphery of the display region 12, the end portions on one end side of each of the signal lines (scanning line Ls, power supply voltage line La, and data line Ld) are exposed, and the seal material BND and the part are exposed. By overlapping, the counter substrate 20 side is electrically connected through the sealing material BND. Specifically, as shown in FIG. 2, the edge of the scanning line Ls of each row is provided to extend at the peripheral edge above the insulating substrate 11. In addition, at the lower peripheral portion of the insulating substrate 11, end portions of the power supply voltage lines La of the respective rows are provided so as to extend. Further, the end of the data line Ld of each column is provided to extend to the left peripheral edge of the insulating substrate 11. Here, the scanning lines Ls, the power supply voltage lines La, and the data lines Ld are arranged with a predetermined pitch. Note that the end of each signal line may be provided with a connection pad wider than the width of each signal line. In this case, the connection pads are preferably staggered in even rows (or even columns) and odd rows (or odd columns) so that adjacent connection pads do not short-circuit.

  In addition, the sealing material BND interposed between the peripheral edge of the pixel array substrate 10 and the counter substrate 20 is connected to each signal line (scanning line) in a binder (adhesive solvent) for bonding and fixing the substrates together. Ls, power supply voltage line La, data line Ld), and commercially available fillers (conductive particles) for electrically connecting the connection pads on the counter substrate 20 side, which will be described later, are uniformly dispersed. An adhesive can be applied. Here, the sealing material BND is irradiated with a paste type that can be printed on the insulating substrate 11, a liquid type that can be applied, a thin film type, a type that solidifies the binder by heat and pressure, or ultraviolet rays. From the solidification method such as the type to be solidified, an appropriate one can be selected according to the manufacturing process. Specifically, as the sealing material BND, fine particles such as nickel or gold-plated nickel, or gold-plated acrylic or polystyrene resin or the like are dispersed in a binder such as an epoxy or synthetic rubber resin. An anisotropic conductive paste can be used. For example, “Dotite” series by Fujikura Kasei Co., Ltd., “ThreeBond 3373” by ThreeBond Co., Ltd., etc. can be applied well.

  As shown in FIGS. 3A and 3B, the counter substrate 20 is made of an insulating substrate 21 such as glass and is bonded to the pixel array substrate 10 (hereinafter referred to as “one side” for convenience). ), Pixel array connection pads 22s, 22a, 22d, routing wirings (connection wirings) 23s, 23a, 23d, routing wirings (external connection wirings) 25, external circuit connection pads (external connection pads) 24, and a thin film Integrated circuit (control circuit; hereinafter referred to as “film-forming IC”) 26. Thinning is performed using techniques such as wafer polishing and peeling. The thickness of the integrated circuit is preferably about 50 μm or less, and is preferably a separation distance (gap between substrates) G between the bonded pixel array substrate 10 and the counter substrate 20.

  The lead-out wirings 23s, 23a, 23d, and 25 are thin film wirings. As shown in FIGS. 3A and 3B, the pixel array connection pads 22s, 22a, 22d, and the like are formed on one end side formed by the thin film wirings. An external circuit connection pad 24 is connected, and the other end side is connected to a plurality of bump electrodes of the filmed IC 26, and a plurality of connection pads formed by the thin film wiring are connected. As shown in FIG. 3A, the pixel array connection pads 22 s, 22 a, and 22 d are regions (to which the insulating substrate 11 of the pixel array substrate 10 is bonded in the insulating substrate 21 constituting the counter substrate 20). (Hereinafter referred to as “joining region”), which is arranged in a region where the sealing material BND is interposed when joining to the pixel array substrate 10.

  Here, the pixel array connection pads 22s, 22a, and 22d are respectively end portions of the scanning line Ls, the power supply voltage line La, and the data line Ld that are arranged so that one end side extends to the peripheral portion of the pixel array substrate 10 described above. And have a predetermined pitch and are arranged at positions corresponding to each other so as to be electrically connected individually via the conductive filler in the sealing material BND. In addition, as shown in FIG. 3A, the lead wirings 23 s, 23 a, and 23 d that connect the pixel array connection pads 22 s, 22 a, and 22 d and the film forming IC 26 are pixels on the insulating substrate 21 that constitutes the counter substrate 20. Arranged inside the bonding region of the array substrate 10 (insulating substrate 11).

  Further, as shown in FIG. 3A, the external circuit connection pad 24 is a region other than the bonding region of the pixel array substrate 10 (insulating substrate 11) in the insulating substrate 21 constituting the counter substrate 20, The pixel array connection pads 22s, 22a, and 22d are arranged on the peripheral edge where they are not arranged. Here, the external circuit connection pads 24 are arranged with a predetermined pitch so as to be electrically connected individually to a control circuit, a power supply circuit, etc. (all of which are not shown) provided outside the light emitting device. Has been. The external circuit connection pad 24 is connected to each wiring of the flexible wiring board connected to an external circuit (not shown).

  Further, as shown in FIGS. 3A and 3B, the film-forming IC 26 is disposed inside the bonding region of the pixel array substrate 10 in the insulating substrate 21 constituting the counter substrate 20. The film-forming IC 26 generates various signals, drive voltages, and the like based on control signals, power supply voltages, and the like that are applied via the external circuit connection pads 24 and the routing wirings 25, and leads the routing wirings 23s, 23a, 23d, the pixel array connection pads 22s, 22a, and 22d, and the sealing circuit BND, and the function of a driver circuit that applies to the scanning line Ls, the power supply voltage line La, and the data line Ld disposed on the pixel array substrate 10. ing. In the film IC 26, the electrode pad of the film IC is attached to the predetermined wiring pattern formed on the lower surface of the insulating substrate 21 with an anisotropic conductive adhesive, and the film IC 26 is formed on the surface opposite to the insulating substrate 21. Electrode terminals connected to the lead wirings 23s, 23a, 23d, and 25 are provided, or the filmed IC 26 is attached to an insulating substrate with an ultraviolet curing or thermosetting adhesive, and the electrode pads and pixels of the filmed IC 26 The array connection pads 22s, 22a, and 22d and the externalized color connection pads 24 may be connected by patterning by a vapor deposition method using a metal mask, wire bonding, or the like.

  In the light emitting device according to the present embodiment, the separation distance (inter-substrate gap) G between the bonded pixel array substrate 10 and the counter substrate 20 is equal to each other between adjacent pads in the pixel array connection pads 22s, 22a, and 22d. It is set to be smaller than the separation distance (inter-terminal space) S.

  Specifically, the inter-substrate gap G between the pixel array substrate 10 and the counter substrate 20 is set to, for example, 5 μm or less, while the inter-terminal space S between the adjacent pixel array connection pads 22s, 22a, and 22d is, for example, It is set to 120 μm or less longer than 5 μm. In this case, the film-formed IC 26 is formed to have a thickness of 5 μm or less.

  According to this, the pixel array substrate 10 and the counter substrate 20 are satisfactorily made by using the sealing material BND including the conductive filler having a particle size larger than the inter-substrate gap G and smaller than the inter-terminal space S. Can be joined. That is, according to the sealing material BND including the conductive filler satisfying such conditions, the electrical connection between the pixel array substrate 10 and the counter substrate 20 is prevented while preventing the pixel array connection pads 22s, 22a, and 22d from being short-circuited. Connection and a desired inter-substrate gap G can be realized satisfactorily. At this time, by setting the thickness of the film forming IC 26 provided on the counter substrate 20 to be smaller (thinner) than the inter-substrate gap G, the film forming IC 26 is placed inside the bonding area of the pixel array substrate 10 in the counter substrate 20. It can be implemented well.

(Display pixel)
Next, specific examples of display pixels applicable to the light emitting device according to this embodiment will be described.
FIG. 4 is an equivalent circuit diagram showing a circuit configuration example of display pixels that are two-dimensionally arranged on the display panel according to the present embodiment. FIG. 4A is a circuit configuration example of a display pixel having a pixel driving circuit composed of two transistors and one capacitor, and FIG. 4B is composed of three transistors and one capacitor. 3 is a circuit configuration example of a display pixel having a pixel driving circuit.

  As shown in FIGS. 4A and 4B, the display pixel PIX includes a pixel drive circuit DC and an organic EL element (light emitting element) OEL. The pixel drive circuit DC has a circuit configuration including a plurality of transistors (for example, amorphous silicon thin film transistors TFT). The organic EL element OEL emits light when a light emission drive current controlled by the pixel drive circuit DC is supplied to the anode terminal.

(Configuration example 1)
Specifically, the pixel drive circuit DC illustrated in FIG. 4A includes transistors Tr11 and Tr12 and a capacitor Cs. The transistor Tr11 has a gate terminal connected to a scanning line Ls arranged in the row direction of the display region 12 (corresponding to the vertical direction in FIG. 2), and a drain terminal in the column direction of the display region 12 (FIG. 2 corresponds to the data line Ld disposed in the horizontal direction of the drawing), and the source terminal is connected to the contact N11. The transistor Tr12 has a gate terminal connected to the contact N11, a drain terminal connected to the power supply voltage line La arranged in the row direction (corresponding to the vertical direction in FIG. 2), and a source terminal connected to the contact N12. Has been. The capacitor Cs is connected between the gate terminal (contact N11) and the source terminal (contact N12) of the transistor Tr12.

  The organic EL element OEL has an anode terminal (anode electrode) connected to the contact N12 of the pixel drive circuit DC and a cathode terminal (cathode electrode), for example, a predetermined low potential power supply (reference voltage Vss; for example, ground potential Vgnd). Connected directly or indirectly.

  As shown in FIG. 2, the scanning line Ls and the data line Ld are formed so that one end of each of them extends to the peripheral edge of the insulating substrate 11. As shown in FIGS. 1 and 3, at the peripheral edge, the seal material BND, the pixel array connection pads 22s and 22d provided on the counter substrate 20 side, and the lead wirings 23s and 23d are opposed to each other. The substrate 20 is connected to a film forming IC 26 disposed inside the bonding region of the pixel array substrate 10.

  Here, the film forming IC 26 in this configuration example has a function of, for example, a scanning driver, and applies a selection signal (selection voltage) Vsel to the scanning line Ls of each row at a predetermined timing. Thereby, the display pixels PIX in each row arranged on the pixel array substrate 10 are sequentially set to the selected state. The film forming IC 26 also has a function as a data driver, for example, and applies a gradation signal (gradation voltage) Vdata corresponding to display data to the data line Ld of each column at a predetermined timing. Thereby, the display data is written at a timing synchronized with the selection state of the display pixel PIX in each row.

  Similarly to the scanning line Ls and the data line Ld, the power supply voltage line La is also formed so that one end thereof extends to the peripheral edge of the insulating substrate 11 as shown in FIG. . As shown in FIG. 1 and FIG. 3, the power supply voltage line La is connected to the peripheral portion via the sealing material BND, the pixel array connection pad 22a provided on the counter substrate 20 side, and the lead wiring 23a. The sealing material BND, the pixel array connection pad 22a, the pixel array connection pad 22a and a part of the external circuit connection pads 24 directly without being connected to the film forming IC 26. It is connected to the part of the external circuit connection pads 24 via a lead wiring to be connected. The external circuit connection pad 24 to which the power supply voltage line La is connected is directly or indirectly connected to, for example, a predetermined high potential power supply.

  Here, a predetermined voltage is applied to the power supply voltage line La to flow a light emission driving current corresponding to the display data to the anode terminal (anode electrode) of the organic EL element OEL provided in each display pixel PIX. The This voltage is set to a constant high voltage (power supply voltage Vdd) having a higher potential than the cathode terminal (reference voltage Vss applied to the cathode electrode (for example, ground potential Vgnd)) of the organic EL element OEL.

(Display pixel drive control)
The drive control operation in the display pixel PIX having the circuit configuration as shown in FIG. 4A first uses the scan driver function of the film forming IC 26 provided on the counter substrate 20 side in a predetermined selection period. The film-forming IC 26 scans through the routing wiring 23s, the pixel array connection pad 22s, and the sealing material BND by a control signal such as a clock signal and a start signal supplied from some external circuit connection pads 24 to the film-forming IC 26. A selection voltage Vsel of a selection level (on level; for example, high level) is applied to the line Ls. As a result, the transistor Tr11 is turned on and the display pixel PIX is set to the selected state.

  In synchronization with this timing, digital gradation display data and clock signals supplied from a part of the external circuit connection pads 24 to the film forming IC 26 using the data driver function of the film forming IC 26 provided on the counter substrate 20 side. The film-forming IC 26 applies a gradation voltage Vdata having a voltage value corresponding to the display data to the data line Ld through the lead wiring 23d, the pixel array connection pad 22d, and the seal material BND in response to a control signal such as . As a result, a potential corresponding to the gradation voltage Vdata is applied to the contact N11 (that is, the gate terminal of the transistor Tr12) via the transistor Tr11, so that the transistor Tr12 is turned on in a conductive state corresponding to the potential.

  Accordingly, the reference voltage Vss (ground potential Vgnd) on the low potential side is applied to the low potential side reference voltage Vss (ground potential Vgnd) from the power supply voltage line La to which the high potential side power supply voltage Vdd is applied via the transistor Tr12 and the organic EL element OEL. Since the light emission driving current having the current value flows, the organic EL element OEL emits light with a luminance gradation corresponding to the gradation voltage Vdata (that is, display data). At this time, charges are accumulated (charged) in the capacitor Cs between the gate and the source of the transistor Tr12 based on the gradation voltage Vdata applied to the contact N11. Here, the light emitted from the organic EL element OEL of the display pixel PIX is emitted to the visual field side (lower side of the drawing of FIG. 1A) through the insulating substrate 11 constituting the pixel array substrate 10. That is, the light emitting device according to this embodiment has a bottom emission type light emitting structure.

  Next, in the non-selection period after the end of the selection period, the transistor Tr11 is turned off by applying a non-selection level (off level; for example, low level) selection voltage Vsel from the film forming IC 26 to the scanning line Ls. Thus, the display pixel PIX is set to a non-selected state. As a result, the data line Ld and the pixel drive circuit DC are electrically disconnected. At this time, the charge accumulated in the capacitor Cs is held, so that a voltage corresponding to the gradation voltage Vdata (that is, a potential difference between the gate and the source) is maintained at the gate terminal of the transistor Tr12.

  Accordingly, similarly to the light emission operation in the selected state, a light emission drive current flows from the power supply voltage line La (power supply voltage Vdd) to the organic EL element OEL via the transistor Tr12, and light emission continues at the same luminance for a predetermined period. This light emitting operation state is controlled so as to continue, for example, for one frame period until the next gradation voltage Vdata is applied (written). Then, such a drive control operation is performed on all the display pixels PIX two-dimensionally arranged on the pixel array substrate 10, for example, for each row, thereby executing an image display operation for displaying desired image information. be able to.

  In the display pixel PIX shown in FIG. 4A, the film forming IC 26 adjusts (designates) the voltage value of the gradation voltage Vdata to be written to each display pixel PIX according to the display data, and the pixel driving circuit DC. Thus, the circuit configuration of the voltage designation type gradation control method in which the current value of the light emission driving current flowing through the organic EL element OEL is controlled to perform the light emission operation at a desired luminance gradation is shown. The present invention is not limited to this, and the current value written to each display pixel PIX is adjusted (designated) according to the display data by the film forming IC 26, and is caused to flow to the organic EL element OEL by the pixel driving circuit DC. It may have a circuit configuration of a current designation type gradation control system in which the light emission driving current is controlled to emit light at a desired luminance gradation. In the following configuration example 2, a display pixel PIX having a pixel driving circuit DC corresponding to a current designation type gradation control method will be described.

(Configuration example 2)
Specifically, the pixel drive circuit DC illustrated in FIG. 4B includes transistors Tr21, Tr22, Tr23, and a capacitor Cs. The transistor Tr21 has a gate terminal connected to the scanning line Ls, a drain terminal connected to the power supply voltage line La, and a source terminal connected to the contact N21. The transistor Tr22 has a gate terminal connected to the scanning line Ls, a source terminal connected to the data line Ld, and a drain terminal connected to the contact N22. The transistor Tr23 has a gate terminal connected to the contact N21, a drain terminal connected to the power supply voltage line La, and a source terminal connected to the contact N22. The capacitor Cs is connected between the gate terminal (contact N21) and the source terminal (contact N22) of the transistor Tr23.

  The organic EL element OEL has an anode terminal (anode electrode) connected to the contact N22 of the pixel drive circuit DC, and a cathode terminal (cathode electrode) directly to a predetermined low potential reference voltage Vss (for example, ground potential Vgnd). Or indirectly connected.

  The scan line Ls, the data line Ld, and the power supply voltage line La are formed so that one end of each extends to the peripheral edge of the insulating substrate 11, as in the above-described configuration example 1. In FIG. 5, the pixel array connection pad 22s and the lead wiring 23s, the pixel array connection pad 22d and the lead wiring 23d, the pixel array connection pad 22a and the lead wiring 23a provided on the counter substrate 20 side are connected to each other through the sealing material BND. Has been.

  Then, the film forming IC 26 applies a selection voltage Vsel to the scanning line Ls at a predetermined timing, and a gradation signal (gradation voltage Vdata or gradation) corresponding to display data is applied to the data line Ld. Current Idata). On the other hand, the power supply voltage line La is connected to the external circuit connection pad 24 via the film forming IC 26 provided on the counter substrate 20 side or directly. As will be described later, a predetermined low level or high level power supply voltage Vsc is applied to the power supply voltage line La in accordance with the operating state of the display pixel PIX.

  The reference voltage Vss applied to the cathode terminal (cathode electrode) of the organic EL element OEL is a constant voltage (for example, the ground potential Vgnd), and the power supply voltage Vsc applied to the power supply voltage line La is equal to the reference voltage Vss. Set based on. That is, in the writing operation period in which the gradation voltage Vdata or the gradation current Idata corresponding to the display data is supplied to the display pixel PIX (pixel driving circuit DC), the power supply voltage Vsc set to the low level is equal to or lower than the reference voltage Vss. In the light emission operation period in which the light emission drive current is supplied to the organic EL element (light emitting element) OEL and the light emission operation is performed at the luminance gradation according to the display data, the power supply voltage Vsc set to the high level is the reference. The potential is set sufficiently higher than the voltage Vss.

(Display pixel drive control)
The drive control operation in the display pixel PIX having the circuit configuration as shown in FIG. 4B is a write operation (write operation) for holding a voltage component corresponding to display data within a predetermined one processing cycle period. (Operation period) and a light emission operation (light emission operation period) for causing the organic EL element OEL to emit light at a luminance gradation according to display data.

  First, in the writing operation (writing operation period) to the display pixel PIX, the scan driver function of the film forming IC 26 is used, and a clock signal and a start signal supplied to the film forming IC 26 from some external circuit connection pads 24. The film forming IC 26 applies a selection voltage Vsel of a selection level (on level; for example, high level) to the scanning line Ls through the lead wiring 23s, the pixel array connection pad 22s, and the sealing material BND in response to a control signal such as To do. In this writing operation (writing operation period), for example, the power driver function of the film forming IC 26 is used, and the film is generated by a control signal such as a clock signal supplied from some external circuit connection pads 24 to the film forming IC 26. The integrated IC 26 applies a low-level power supply voltage Vsc to the power supply voltage line La through the routing wiring 23a, the pixel array connection pad 22a, and the sealing material BND, or a power supply circuit (not shown) outside the light emitting device. Is omitted) through some of the external circuit connection pads 24, a part of the external circuit connection pads 24 and the pixel array connection pads 22a that are directly connected, the pixel array connection pads 22a, and the sealing material BND. The low level power supply voltage Vsc is applied to the power supply voltage line La. In synchronism with this timing, the film driver IC 26 uses the data driver function of the film forming IC 26 to control the digital gradation display data supplied from some external circuit connection pads 24 to the film forming IC 26 and a control signal such as a clock signal. The integrated IC 26 supplies the gradation voltage Vdata or the gradation current Idata to the data line Ld via the routing wiring 23d, the pixel array connection pad 22d, and the sealing material BND, and a current having a current value corresponding to the display data. Shed.

  As a result, the display pixel PIX is set to the selected state, the transistors Tr21 and Tr22 are turned on, the low-level power supply voltage Vsc is applied to the gate terminal (contact N21) of the transistor Tr23, and the source terminal of the transistor Tr23 (Contact N22) is electrically connected to the data line Ld.

  Here, the gradation voltage Vdata or the gradation current Idata supplied to the data line Ld corresponds to the low-level power supply voltage Vsc according to the luminance gradation value included in the display data written to each display pixel PIX. Since the voltage is relatively negative, the write current Ia corresponding to the gradation voltage Vdata or the gradation current Idata flows from the power supply voltage line La to the data line Ld via the display pixel PIX. As a result, a voltage level lower than the low-level power supply voltage Vsc is applied to the source terminal (contact N22) of the transistor Tr23.

  Accordingly, a potential difference is generated between the contacts N21 and N22 (that is, between the gate and source of the transistor Tr23), so that the transistor Tr23 is turned on, and the transistor Tr23, the contact N22, the transistor Tr22, and the data line Ld are connected from the power supply voltage line La. Thus, a write current Ia corresponding to the gradation voltage Vdata or the gradation current Idata flows in the direction of the film forming IC 26.

  At this time, charges corresponding to the potential difference generated between the contacts N21 and N22 are accumulated in the capacitor Cs and held as a voltage component. Further, a power supply voltage Vsc having a voltage level equal to or lower than the reference voltage Vss (ground potential Vgnd) is applied to the power supply voltage line La, and the write current Ia is controlled to flow from the display pixel PIX in the direction of the data line Ld. Has been. As a result, the potential applied to the anode terminal (contact N22) of the organic EL element OEL is lower than the potential of the cathode terminal (reference voltage Vss), so that no current flows through the organic EL element OEL and the light emission operation is performed. No (non-light emitting operation).

  Next, in the light emission operation (light emission operation period) after the end of the writing operation, the film formation IC 26 uses the scanning driver function of the film formation IC 26, and the film formation IC 26 passes through the lead wiring 23s, the pixel array connection pad 22s, and the sealing material BND. A non-selection level (low level) selection voltage Vsel is applied to the scanning line Ls. In synchronization with this timing or at a predetermined timing, for example, using a power driver function of the film forming IC 26 or a power circuit outside the light emitting device (not shown), from some external circuit connection pads 24 In response to a control signal such as a clock signal supplied to the film forming IC 26, the film forming IC 26 supplies a high level power supply voltage Vsc to the power supply voltage line La via the lead-out wiring 23a, the pixel array connection pad 22a, and the sealing material BND. Apply.

  As a result, the transistors Tr21 and Tr22 are turned off, the application of the power supply voltage Vsc to the gate terminal (contact N21) of the transistor Tr23 is cut off, and the gradation voltage Vdata to the source terminal (contact N22) of the transistor Tr23 is cut off. Alternatively, the application of the voltage level due to the pull-in operation of the gradation current Idata is cut off. At this time, since the charge accumulated in the above-described write operation is held in the capacitor Cs, the transistor Tr23 maintains the on state. Further, since the power supply voltage Vsc higher than the reference voltage Vss (ground potential Vgnd) is applied to the power supply voltage line La, the potential applied to the anode terminal (contact N22) of the organic EL element OEL is the cathode terminal. Higher than the potential (ground potential).

  Therefore, since the light emission drive current Ib flows in the forward bias direction from the power supply voltage line La to the organic EL element OEL via the transistor Tr23 and the contact N22, the organic EL element OEL emits light. At this time, the voltage component held by the capacitor Cs corresponds to a potential difference in the case where the write current Ia corresponding to the gradation voltage Vdata or the gradation current Idata is caused to flow in the transistor Tr23. Therefore, the light emission drive that flows through the organic EL element OEL. The current Ib has a current value (Ib≈Ia) substantially equal to the write current Ia. Thereby, the organic EL element OEL emits light at a luminance gradation corresponding to the display data. Here, the light emitted from the organic EL element OEL of the display pixel PIX is emitted to the visual field side (lower side of the drawing of FIG. 1A) through the insulating substrate 11 constituting the pixel array substrate 10.

  In each of the above-described configuration examples, the circuit configuration including two or three transistors as the pixel driving circuit DC is shown, but the present invention is not limited to this embodiment, and two or more transistors are included. It may have another circuit configuration including a transistor. In addition, the case where the organic EL element OEL is applied as the light emitting element driven to emit light by the pixel driving circuit DC is shown, but the present invention is not limited to this, and any current-controlled light emitting element can be used. Other light emitting elements such as light emitting diodes may be used.

(Production method)
Next, a method for manufacturing the above-described light emitting device will be described. Here, a light emitting device having the display pixel PIX composed of the pixel driving circuit DC and the organic EL element OEL as described above will be described. In the following description, FIGS.

  In the method for manufacturing the light emitting device described above, first, the pixel array substrate 10 and the counter substrate 20 are individually manufactured. As shown in FIG. 2, the method for manufacturing the pixel array substrate 10 includes the pixel driving described above on one side of the insulating substrate 11 made of, for example, glass, quartz, or transparent resin (on the side of the bonding surface with the counter substrate 20). A plurality of display pixels PIX each including a transistor and a capacitor constituting the circuit DC, various wiring layers and interlayer insulating films, and an organic EL element OEL are two-dimensionally arranged to form a pixel array in the display region 12.

  Here, on the insulating substrate 11 on which at least the pixel array is formed, for example, an inorganic insulating film is coated to protect the surface of the display region 12 of the pixel array substrate 10. Also, the end of each signal line (scanning line Ls, power supply voltage line La, data line Ld) for applying the selection signal Vsel, gradation signals Vdata, Idata, power supply voltages Vdd, Vsc to the pixel drive circuit DC and the organic EL element OEL. As shown in FIG. 2, the portions are arranged with a predetermined pitch along each side of the peripheral portion of the insulating substrate 11, and are formed so that the upper surface thereof is exposed. The pixel array constituting the pixel array substrate 10 is regularly formed at a plurality of locations on one side of the mother glass, and then separated into each size of the substrate including each pixel array, thereby providing a plurality of pixel array substrates. 10 is cut out.

  On the other hand, as shown in FIG. 3, the manufacturing method of the counter substrate 20 is made of, for example, aluminum on one surface side of the insulating substrate 21 made of glass, quartz, transparent resin, or the like (bonding surface side with the pixel array substrate 10). After coating the conductive film, patterning is performed by photolithography to form pixel array connection pads 22s, 22a, and 22d so as to correspond to the signal lines arranged on the peripheral edge of the pixel array substrate 10 described above, External circuit connection pads 24 are formed in a region of the insulating substrate 21 other than the bonding region of the pixel array substrate 10 (insulating substrate 11). Here, the pitches of the pixel array connection pads 22s, 22a, and 22d are respectively the scanning lines Ls, power supply voltage lines La, and the like formed on the pixel array substrate 10 side along the peripheral edge of the bonding region of the pixel array substrate 10. The data lines Ld are arranged so as to correspond to each pitch. Further, the external circuit connection pads 24 are arranged at a predetermined pitch suitable for connection with an external circuit along a peripheral portion (a peripheral portion on the right side in FIG. 2) other than the bonding region of the pixel array substrate 10 in the insulating substrate 21. Arranged. The pixel array connection pads 22s, 22a, and 22d and the external circuit connection pads 24 are collectively formed by patterning a conductive film formed on the insulating substrate 21 using a sputtering method or a vapor deposition method, for example. Or formed by wire bonding.

  Next, the film forming IC 26 is sucked by a suction tool such as a stamp (not shown), and then the suction tool is moved together with the film forming IC 26 so that a predetermined area within the bonding area of the pixel array substrate 10 on one side of the insulating substrate 21 is obtained. The film-formed IC 26 is bonded and mounted at the position. Here, the ultraviolet curable resin is applied to the predetermined position, and after the film-forming IC 26 is placed, the ultraviolet curable resin is irradiated with ultraviolet rays through the insulating substrate 21 and cured to form the film-formed IC 26. To fix.

  Next, the pixel array connection pads 22s, 22a, 22d, and the external circuit connection pads 24 are formed, and the conductive surface is conductively formed on one surface side of the insulating substrate 21 on which the film-formed IC 26 is mounted using, for example, sputtering or vapor deposition. A film is formed. Next, by patterning this conductive film, as shown in FIGS. 3A and 3B, the connection terminals (not shown) of the film-forming IC 26 and the pixel array connection pads 22s, 22a, 22d, or A plurality of routing wires 23s, 23a, 23d, and 25 for individually connecting the external circuit connection pads 24 are formed. The pixel array connection pads 22s, 22a, and 22d, the external circuit connection pad 24, and the routing wirings 23s, 23a, 23d, and 25 are not limited to those formed in different manufacturing processes. That is, first, a film is formed on the insulating substrate 21 by using a sputtering method or a vapor deposition method with only the film-formed IC 26 mounted thereon, and the pixel is formed by patterning the conductive film. The array connection pads 22s, 22a, and 22d, the external circuit connection pad 24, and the routing wirings 23s, 23a, 23d, and 25 may be integrally formed in a lump. The pixel array connection pads 22s, 22a, 22d, the external circuit connection pads 24, the routing wirings 23s, 23a, 23d, 25, and the film-forming IC 26 provided on the counter substrate 20 are arranged at a plurality of locations on one side of the mother glass. Formed or mounted.

  Next, the pixel array substrate 10 and the counter substrate 20 are bonded to each other through a sealing material BND, and the pixel array (display pixel PIX) formed in the display region 12 is sealed. Specifically, for example, a paste-like sealing material BND is printed on the peripheral portion of the insulating substrate 11 on the pixel array substrate 10 side, and each signal line (scanning line Ls and power supply voltage line La is arranged on the peripheral portion. , The end of the data line Ld) and the insulating substrates 11 and 21 face each other so that the positions of the pixel array connection pads 22s, 22a, and 22d provided on the insulating substrate 21 on the counter substrate 20 side are aligned. Let them join.

  Next, for example, by applying heat and pressure to the sealing material BND, the binder of the sealing material BND is spread to spread the conductive filler on each signal line (scanning line Ls, power supply voltage line La, data line) on the pixel array substrate 10 side. Ld) and the pixel array connection pads 22s, 22a and 22d on the counter substrate 20 side are brought into contact with each other, and the binder is solidified to seal the pixel array substrate 10 and the counter substrate 20. Thereby, as shown in FIG. 1C, the pixel array in the display region 12 is sealed between the pixel array substrate 10 and the counter substrate 20, and the pixel array substrate 10 and the counter substrate 20 are sealed. It is electrically connected via the material BND.

  Thereafter, the mother glass constituting the plurality of insulating substrates 11 is cut for each individual insulating substrate 11, and the mother glass constituting the plurality of insulating substrates 21 is cut for each individual insulating substrate 11. One light emitting panel is obtained. Then, the pixel array substrate 10 and the counter substrate 20 cut out from the mother glass are subjected to a predetermined inspection using an inspection device such as a prober. Specifically, a probe needle is brought into contact with a plurality of external circuit connection pads 24 on the insulating substrate 21 and a predetermined signal or voltage is applied to appropriately output a signal from the film forming IC 26 to each display pixel PIX. Inspections such as operation characteristics and control functions of the film forming IC 26 and the display pixel PIX are performed.

(Verification of effects)
Next, functions and effects unique to the light emitting device and the manufacturing method thereof according to the present embodiment will be described in detail.
FIG. 5 is a schematic configuration diagram schematically showing a light emitting device according to the related art corresponding to the present embodiment in order to verify the operation effect of the light emitting device according to the present embodiment (hereinafter, FIG. 5). The light emitting device shown is referred to as “comparative object”). FIG. 5A is a schematic plan view seen from the field of view of the light emitting device according to the comparison target, and FIG. 5B is a schematic side view of the light emitting device according to the comparison target.

  FIG. 6 is a schematic plan view illustrating an example of a pixel array substrate applied to a light emitting device according to a comparison target. Here, FIG. 6 shows the pixel array substrate applied to the light emitting device according to the comparison target as viewed from the side of the bonding surface with the sealing substrate (that is, along the VIE-VIE line shown in FIG. 5B). It is a schematic plan view). In this specification, “VI” is used for convenience for the symbol corresponding to the Roman numeral “6” shown in FIG. Further, in the plan view shown in FIG. 6, for convenience of explanation, only the relationship between each wiring layer disposed on the insulating substrate, the display region, and the peripheral portion is shown, and a light emitting element ( The display of the organic EL element) and the pixel driving circuit (see FIG. 4 described above) is omitted. Further, in FIG. 6, hatching is shown for convenience in order to clarify a region where an adhesive for bonding the pixel array substrate and the sealing substrate is provided.

  As illustrated in FIGS. 5A, 5 </ b> B, and 6, the light emitting device according to the comparison target includes a pixel array substrate 110 and a sealing substrate 120. The pixel array substrate 110 and the sealing substrate 120 are bonded to each other with an insulating adhesive 130 therebetween. In the pixel array substrate 110, as shown in FIG. 6, a display region 112 in which a plurality of display pixels PIX are two-dimensionally arranged is set on one surface side of the insulating substrate 111 (the bonding surface side with the sealing substrate 120). ing. In the display area 112, scanning lines Ls and power supply voltage lines La are arranged in the vertical direction (row direction) in the drawing corresponding to a plurality of two-dimensionally arranged display pixels, and the data lines Ld are in the horizontal direction in the drawing. It is arranged in the (column direction).

  On the other hand, in the peripheral region on the outer periphery of the display region 112, a plurality of line lead pads 122s, 122a, 122d, a plurality of lead wirings 123s, 123a, 123d, 125, a plurality of external circuit connection pads 124, and a driver circuit 126 are provided. And are provided. The line lead-out pads 122s, 122a, and 122d are regularly arranged on the outer periphery of the display region 112, and are connected to the ends on one end side of the scanning line Ls, the power supply voltage line La, and the data line Ld, respectively. The lead-out wirings 123s, 123a, and 123d are disposed on the outer peripheral side of the line lead-out pads 122s, 122a, and 122d, and connect the line lead-out pads 122s, 122a, and 122d to the driver circuit 126.

  The external circuit connection pads 124 are arranged outside the display area 112 of the insulating substrate 111, for example, at the end of the right side of the insulating substrate 111. The lead wiring 125 connects the external circuit connection pad 124 and the driver circuit 126. The driver circuit 126 has an IC chip form, for example, and is disposed outside the display area 112 of the insulating substrate 111.

  The sealing substrate 120 is an insulating parallel plate such as glass, and is bonded so as to face at least the display region 112 of the pixel array substrate 110. 5 and 6, the sealing substrate 120 is bonded to the pixel array substrate 110 via an insulating adhesive 130, for example, at the outer periphery of the region where the line drawing pads 122s, 122a, and 122d are arranged. . That is, the area including the display area 112 of the pixel array substrate 110 and the area where the line drawing pads 122s, 122a, and 122d on the outer periphery thereof are arranged is sealed by the sealing substrate 120.

  As described above, in the light emitting device according to the comparison target (in the prior art), the line lead connected to each of the scanning line Ls, the power supply voltage line La, and the data line Ld on the outer periphery of the display region 112 of the pixel array substrate 110. The pads 122s, 122a, 122d are arranged, and the line lead-out pads 122s, 122a, 122d and the driver circuit 126 are connected by the lead wirings 123s, 123a, 123d arranged in the outer peripheral area. That is, since the scanning line Ls, the power supply voltage line La, and the data line Ld are arranged in the display area 112 of the pixel array substrate 110, the display wirings 123s, 123a, and 123d can be arranged on the pixel array substrate 110 by displaying. It had to be arranged on the outer periphery of the region 112.

  Therefore, an area (space) for disposing the wiring lines 123s, 123a, 123d must be provided in the peripheral area of the display area 112 of the pixel array substrate 110, and the size of the frame portion of the display panel increases. The problem was that the design and size were limited. In addition, since the outer size of the pixel array substrate 110 is increased by increasing the peripheral region of the display region 112, the number of the pixel array substrates 110 cut out from one mother glass is reduced when the display panel is manufactured. As a result, there was a problem of increasing the product cost. Further, in order to make the peripheral region of the display region 112 as narrow as possible, it is conceivable to reduce the wiring width by reducing the wiring width of the lead-out wirings 123s, 123a, 123d. The voltage drop due to the increase and the voltage variation due to the non-uniform wiring length become conspicuous, and there is a problem that the display characteristics are deteriorated, the manufacturing process is increased and complicated, and the manufacturing yield is deteriorated.

  On the other hand, in the light emitting device and the manufacturing method thereof according to the present embodiment, the lead wires 23s, 23a, 23d, and 25 are provided on the counter substrate 20 that is bonded to the pixel array substrate 10 via the sealing material BND. Since it has a configuration in which a film-forming IC 26 that is a circuit is provided, at least one of the lead wirings 23 s, 23 a, 23 d, and 25 of the counter substrate 20 in a plan view scans the display region 12 of the pixel array substrate 10. Since it may overlap with at least one of the line Ls, the power supply voltage line La, and the data line Ld, it is not necessary to provide a region for arranging the routing wiring on the outer periphery of the display region 12 of the pixel array substrate 10. That is, the size of the pixel array substrate 10 and the counter substrate 20 can be reduced as much as possible.

  Therefore, according to the light emitting device and the manufacturing method thereof according to the present embodiment, the size of the frame portion of the display panel can be reduced as much as possible, so that the degree of freedom can be improved without restricting the product design and size. it can. For this reason, since the pitch between wirings can be expanded as compared with the light emitting device according to the comparison object, it is possible to widen the wiring width and reduce the wiring resistance. Therefore, there is no need to make the routing wiring multilayer in the peripheral region or to narrow the pitch between the wirings, so that the manufacturing process can be simplified and the manufacturing yield can be improved. In particular, as shown in FIGS. 4A and 4B, each display pixel PIX is provided with a pixel driving circuit DC, and is arranged in the display region 12 when performing image display using an active matrix driving method. The number and type of signal lines to be increased. However, in the present embodiment, by arranging the routing wirings 23s, 23a, and 23d on the counter substrate 20 side, restrictions on the wiring pattern, the pitch between wirings, the wiring structure, and the like can be greatly relaxed. It is extremely effective in simplifying the process and improving the manufacturing yield. In addition, since the outer size of the pixel array substrate 10 and thus the outer size of the counter substrate 20 can be reduced, the number of pixel array substrates 10 cut out from one mother glass can be increased during the manufacture of the display panel. Product cost can be reduced.

  In addition, in the light emitting device and the manufacturing method thereof according to the present embodiment, a film-formed IC that becomes the lead wiring and the driver circuit is provided inside the bonding region of the pixel array substrate 10 in the counter substrate 20, thereby providing a wiring path ( The degree of freedom of the wiring pattern) can be improved, and the wiring length can be substantially shortened and substantially uniform as compared with the case of the light emitting device according to the comparison target. As a result, the wiring resistance can be reduced and the voltage drop can be suppressed, the voltage variation can be suppressed, and the display characteristics can be improved. In particular, when an organic EL element is used as a light emitting element provided in a display pixel, a current (light emission driving current) is required to perform a light emitting operation. Therefore, as shown in this embodiment, reducing the resistance of the power supply voltage line La, which is a power wiring, is extremely effective in improving display characteristics and saving power in the light emitting device.

  Further, in the light emitting device and the manufacturing method thereof according to the present embodiment, the distance between the signal lines arranged in the display area 12 of the pixel array substrate 10 and the pixel array connection pads 22 s arranged on the counter substrate 20. , 22a and 22d are set based on the separation distance (inter-substrate gap) G when the pixel array substrate 10 and the counter substrate 20 are joined.

  Therefore, when the probe inspection is performed on the pixel array substrate 10 and the counter substrate 20, the distance between adjacent signal lines and connection pads can be set relatively wide. There is no need to use a prober (inspection device) with positioning accuracy, and the probe needle and the signal line or the connection pad can be satisfactorily brought into contact with a simple and inexpensive inspection device, thereby suppressing the occurrence of inspection mistakes. Can do.

<Second Embodiment>
Next, a second embodiment of the light emitting device according to the present invention will be described. In the present embodiment, the configuration equivalent to that of the first embodiment described above is simplified or omitted with reference to FIGS. 1 to 4 as appropriate.
FIG. 7 is a schematic configuration diagram of a counter substrate applied to the light emitting device according to the second embodiment. Here, FIG. 7 shows a cross section taken along line IIID-IIID in the plan view shown in FIG.

  In the first embodiment described above, as shown in FIG. 3B, a configuration in which a film-formed IC 26 that is a driver circuit made thin is mounted on one surface side of the insulating substrate 21 of the counter substrate 20. Indicated. In this embodiment, as shown in FIG. 7, an integrated circuit 27 (hereinafter referred to as “general-purpose IC” for convenience) having the form of an existing and commercially available IC chip is provided on one side of the insulating substrate 21. It is mounted on. Further, a planarizing film 28 thicker than the thickness of the general-purpose IC 27 is provided on one surface side of the insulating substrate 21, and the general-purpose IC 27 is completely covered with the flattening film 28. Then, pixel array connection pads 22s, 22a, and 22d, external circuit connection pads 24, and routing wires 23s, 23a, 23d, and 25 as shown in FIG. 3 are provided on the upper surface of the planarizing film 28. The lead-out wirings 23 s, 23 a, and 23 d connect the general-purpose IC 27 to the pixel array connection pads 22 s, 22 a, and 22 d regularly arranged along the peripheral edge of the bonding region of the pixel array substrate 10 in the counter substrate 20. It is arranged like this. Here, the general-purpose IC 27 is completely covered (embedded) with the planarizing film 28. For example, only the connection terminals (not shown) arranged on the upper surface thereof are exposed from the planarizing film 28. An opening is formed, and is connected to the pixel array connection pads 22s, 22a, and 22d through the routing wirings 23s, 23a, and 23d in the opening.

  As is well known, a driver IC (general-purpose IC) having a form of an existing and commercially available IC chip is much thicker than the above-described film-formed IC 26. For example, in the above-described film-formed IC 26, generally While a thickness of 1 μm or less can be realized, the general-purpose IC has a thickness of 0.5 to 1 mm. When such a general-purpose IC 27 is mounted on the insulating substrate 21, the flatness of the surface of the insulating substrate 21 deteriorates. Therefore, when there are terminals on the general-purpose IC 27, the routing wirings 23 s, 23 a, and 23 d are connected to the general-purpose IC 27. It breaks at the level difference. Further, as in the first embodiment described above, the pitches of the pixel array connection pads 22s, 22a, and 22d are set to be short. For example, the shortest pitch among these pitches is sufficiently shorter than the thickness of the general-purpose IC 27. Since the diameter of the conductive particles in the sealing material BND is shorter than the thickness of the general-purpose IC 27 and the sealing material BND is bonded so as to maintain electrical connection, the sealing material BND becomes thinner than the general-purpose IC 27. Therefore, the pixel array substrate 10 and the counter substrate 20 cannot be directly bonded to each other through the substrate.

  Therefore, in the present embodiment, the planarization film 28 is formed on the insulating substrate 21 on which the general-purpose IC 27 is mounted, and the pixel array connection pads 22s, 22a, 22d and the routing wirings 23s, 23a are formed on the upper surface of the planarization film 28. , 23d, etc., can ensure surface flatness on the bonding surface side of the counter substrate 20, and further, the distance between the pixel array connection pad 22s and the scanning line Ls, the pixel array connection pad 22a, The distance between the power supply voltage line La and the distance between the pixel array connection pad 22d and the data line Ld can be set to be equal to or smaller than the diameter of the conductive particles in the sealing material BND. Therefore, even when the general-purpose IC 27 mounted on the insulating substrate 21 is thick, the pixel array substrate 10 and the counter substrate 20 can be satisfactorily bonded via the sealing material BND, and electrical connection between the substrates is achieved. Can be realized satisfactorily. In addition, by having such a configuration, a commercially available inexpensive driver IC (general-purpose IC) can be applied as a driver circuit mounted on the counter substrate 20, so that the product cost can be reduced. .

  In the present embodiment, the configuration in which the general-purpose IC 27 mounted on the insulating substrate 21 of the counter substrate 20 is covered with the planarization film 28 and embedded is described, but the present invention is not limited to this. Absent. For example, a circuit element such as a chip capacitor, an inductor, or a resistor may be formed or mounted on the insulating substrate 21 in addition to the general-purpose IC 27, and may be covered with a planarization film 28 and embedded. Good. According to this, even when the standardized general-purpose IC 27 is applied to the present embodiment, the signal and voltage characteristics can be adjusted and controlled on the counter substrate 20 side, so that the display characteristics can be improved. Can do.

<Third Embodiment>
Next, a third embodiment of the light emitting device according to the present invention will be described. In the present embodiment, the configuration equivalent to that of the first embodiment described above is simplified or omitted with reference to FIGS. 1 to 4 as appropriate.
FIG. 8 is a schematic configuration diagram of a counter substrate applied to the light emitting device according to the third embodiment. Here, FIG. 8 is a schematic plan view taken along the line IIC-IIC shown in FIG.

  In the first embodiment described above, as shown in FIG. 3A, one film-formed IC 26 is provided inside the bonding region of the pixel array substrate 10 in the insulating substrate 21 constituting the counter substrate 20. The installed configuration is shown. In the present embodiment, as shown in FIG. 8, a plurality of film-formed ICs 26 and 29 (or general-purpose ICs) are mounted inside the bonding region of the pixel array substrate 10 in the insulating substrate 21. Here, the film forming IC 26 has various driver functions for driving and controlling the display pixels PIX arranged on the pixel array substrate 10 as in the first embodiment. Further, the film forming IC 29 is, for example, a memory module, and displays various control data necessary for driving and controlling the display pixels PIX by the film forming IC 26 and display data including luminance gradation values of the organic EL element OEL. Save temporarily.

  With such a configuration, the counter substrate 20 can be enhanced in function, so that a control circuit, a memory circuit, and the like provided outside the light emitting device can be simplified. In the present embodiment, the film IC 26 has a driver function and the film IC 29 has a memory function. However, the present invention is not limited to this. That is, both the film forming ICs 26 and 29 have individual driver functions. For example, the film forming IC 26 may have a scan driver and data driver function, and the film forming IC 29 may have a power driver function. Further, the first film forming IC connected to the lead wiring 23s as the scanning driver and the second film forming IC connected to the lead wiring 23d as the data driver may be used. There may be. Further, instead of the film-forming ICs 26 and 29, a general-purpose IC as shown in the second embodiment may be mounted and covered with a planarizing film.

<Fourth Embodiment>
Next, a fourth embodiment of the light emitting device according to the present invention will be described. In the present embodiment, the configuration equivalent to that of the first embodiment described above is simplified or omitted with reference to FIGS. 1 to 4 as appropriate.

  FIG. 9 is a schematic configuration diagram illustrating a light emitting device according to the fourth embodiment. FIG. 9A is a schematic side view of the light emitting device according to this embodiment, and FIG. 9B is a schematic plan view of the light emitting device according to this embodiment as viewed from the field of view. FIG. 10 is a schematic plan view showing an example of a counter substrate applied to the light emitting device according to this embodiment. Here, FIG. 10 shows the counter substrate applied to the light emitting device according to the present embodiment as viewed from the side of the joint surface with the pixel array substrate (that is, along the XF-XF line shown in FIG. 9A). It is a schematic plan view). In this specification, “X” is used for convenience as a symbol corresponding to the Roman numeral “10” shown in FIG.

  In the first to third embodiments described above, as shown in FIG. 3A and FIG. 8, 1 in the junction region of the pixel array substrate 10 in the insulating substrate 21 constituting the counter substrate 20. Alternatively, a configuration in which a plurality of film-forming ICs 26 and 29 or a general-purpose IC 27 is arranged is shown. In this embodiment, as shown in FIGS. 9 and 10, a general-purpose IC 27 (or a film-formed IC) is arranged in a region other than the bonding region of the pixel array substrate 10 in the insulating substrate 21 of the counter substrate 20. Yes. That is, the pixel array connection pads 22s, 22a, and 22d arranged at the periphery of the bonding region of the pixel array substrate 10 (insulating substrate 11) in the insulating substrate 21 and the general-purpose IC 27 mounted outside the bonding region. Are connected via routing wires 23s, 23a, and 23d disposed in the junction region. The general-purpose IC 27 is connected to an external circuit connection pad 24 arranged at an end portion outside the bonding region of the insulating substrate 21 through the lead wiring 25.

  By having such a configuration, the general-purpose IC 27 is disposed in an arbitrary area outside the bonding area of the insulating substrate 21, so that an inexpensive and optimal general-purpose IC can be selected regardless of the thickness of the IC chip. Cost can be reduced. In addition, since the general-purpose IC 27 does not intervene in the junction region between the pixel array substrate 10 (insulating substrate 11) and the counter substrate 20 (insulating substrate 21), as shown in the first embodiment described above, the substrates are connected to each other. A light-emitting device having a simple bonding structure that is directly bonded can be realized.

  In the present embodiment, since the general-purpose IC 27 is disposed outside the bonding area of the pixel array substrate 10 in the counter substrate 20, the light emitted from the organic EL element OEL of the display pixel PIX constitutes the counter substrate 20. It is also possible to provide a light emitting device having a top emission type light emitting structure that is emitted through the insulating substrate 21. In this case, the upper side in FIG. 9A is set as the visual field side.

<Fifth Embodiment>
Next, a fifth embodiment of the light emitting device according to the present invention will be described. In the present embodiment, the configuration equivalent to that of the first embodiment described above is simplified or omitted with reference to FIGS. 1 to 4 as appropriate.

  FIG. 11 is a schematic configuration diagram illustrating a light emitting device according to the fifth embodiment. FIG. 11A is a schematic side view of the light emitting device according to this embodiment, and FIG. 11B is a schematic plan view showing an example of a pixel array substrate applied to the light emitting device according to this embodiment. is there. Here, FIG. 11B shows the pixel array substrate applied to the light emitting device according to the present embodiment as viewed from the side of the bonding surface with the counter substrate (that is, the XIG-XIG shown in FIG. 11A). It is a schematic plan view (as viewed along the line). In this specification, “XI” is used as a symbol corresponding to the Roman numeral “11” shown in FIG.

  FIG. 12 is a schematic plan view showing an example of a counter substrate applied to the light emitting device according to this embodiment. Here, FIG. 12 shows the counter substrate applied to the light emitting device according to the present embodiment as viewed from the side of the joint surface with the pixel array substrate (that is, along the XIIH-XIIH line shown in FIG. 11A). It is a schematic plan view). In this specification, “XII” is used as a symbol corresponding to the Roman numeral “12” shown in FIG.

  In the first to fourth embodiments described above, a light emitting device in which a pixel driving circuit DC is provided in each display pixel PIX that is two-dimensionally arranged on the pixel array substrate 10 and image display is performed by an active matrix driving method. The configuration of was explained. In the present embodiment, the light emitting device has a configuration corresponding to a case where image display is performed by a passive matrix driving method.

  Specifically, as shown in FIG. 11B, a plurality of scanning lines in the row direction (vertical direction in the drawing) corresponding to the plurality of display pixels PIX two-dimensionally arranged in the display region of the pixel array substrate 10. Ls is arranged, and a plurality of data lines Ld are arranged in the column direction (left-right direction in the drawing). For example, the scanning line Ls becomes an anode electrode of the organic EL element of each display pixel PIX, and the data line Ld becomes a cathode electrode of the organic EL element. At each intersection of the scanning line Ls and the data line Ld, an organic EL layer having a light emitting layer (not shown) is formed.

  As shown in FIG. 11B, for example, in the region on the left side of the display region 12, the scanning line Ls has an end portion on one end side extending to the peripheral portion above the insulating substrate 11 in the drawing. In the region on the right side of the display region 12 in the drawing, the end portion on one end side thereof is disposed so as to extend to the peripheral portion below the insulating substrate 11 in the drawing. As shown in FIG. 11B, the data line Ld is, for example, such that the end on one end side thereof extends to the peripheral edge on the left side of the insulating substrate 11 as shown in FIG. 11B. It is arranged. These scanning lines Ls and data lines Ld are provided on the counter substrate 20 via a sealing material BND provided on the peripheral edge of the insulating substrate 11, as shown in FIGS. The pixel array connection pads 22s and 22d are electrically connected. As shown in FIG. 12, the counter substrate 20 has a film-formed IC 26 (or a general-purpose IC) mounted inside the bonding region of the pixel array substrate 10. The pixel array connection pads 22s and 22d are connected to connection terminals (not shown) of the film forming IC 26 through individual lead wirings 23s and 23d, respectively.

  Thereby, also in this embodiment, the effect similar to the 1st thru | or 3rd embodiment mentioned above can be acquired. In particular, in the case of a light-emitting device that supports a passive matrix driving method, the types and number of signal lines provided in the display region 12 can be reduced as compared with an active matrix type. Accordingly, the degree of freedom with respect to the wiring pattern, the pitch between the wirings, the wiring structure, and the like of the routing wirings 23s, 23d, and 25 disposed on the counter substrate 20 can be improved, thereby simplifying the manufacturing process and improving the manufacturing yield. Can be planned.

  In the present embodiment, as shown in FIG. 11B, the display region 12 is divided into left and right regions, and an end portion on one end side extends to the peripheral portion above the drawing of the insulating substrate 11. A configuration is shown in which a group of scanning lines Ls to be performed and a group of scanning lines Ls having an end portion on one end side are provided at the peripheral edge below the drawing. In this case, no wiring layer is formed in the left side region DLa of the peripheral portion below the drawing and the right region DLb of the peripheral portion above the drawing. In addition, regions DPa and DPb in which the pixel array connection pads 22s are not formed also occur in the peripheral portion of the counter substrate 20 (insulating substrate 21) facing these regions DLa and DLb. When such a pixel array substrate 10 and the counter substrate 20 are bonded using the sealing material BND, a region where the scan line Ls and the pixel array connection pad 22s are bonded via a conductive filler, the scan line Ls, and the pixel In the regions DLa, DLb and DPa, DPb where the array connection pads 22s are not formed, there is a possibility that a difference or deviation occurs in the separation distance between substrates (inter-substrate gap G). Therefore, for example, in the insulating substrate 11 of the pixel array substrate 10, pseudo (dummy) wiring layers are formed in the regions DLa and DLb where the scanning lines Ls are not formed, and the insulating substrate 21 of the counter substrate 20 is formed. A pseudo (dummy) connection pad may be formed in the regions DPa and DPb where the pixel array connection pad 22s is not formed. As a result, the distance between the substrates (the gap between the substrates) can be made uniform, so that the pixel array substrate 10 and the counter substrate 20 can be evenly sealed to achieve a good sealing state. .

In the present embodiment, the case where the pixel array substrate corresponding to the passive matrix driving method is bonded to the counter substrate 20 according to the first embodiment has been described. However, the present invention is not limited to this. Instead, it may be bonded to the counter substrate according to the second to fourth embodiments.
The light emitting device in the present embodiment is a display panel, but is not limited thereto, and may be applied as an exposure device of a printing device.

10 pixel array substrate 11 insulating substrate 12 display area 20 counter substrate 21 insulating substrate 22s, 22a, 22d pixel array connection pad 23s, 23a, 23d, 25 lead-out wiring 24 external circuit connection pad 26, 29 film-formed IC
27 General-purpose IC
28 Flattening film BND Anisotropic conductive adhesive PIX Display pixel Ls Scan line La Power supply voltage line Ld Data line DC Pixel drive circuit OEL Organic EL element

Claims (10)

A first substrate having a display area in which a plurality of display pixels are arranged, and a peripheral edge portion at which ends of a plurality of signal lines connected to each of the display pixels are exposed;
A plurality of connection pads arranged to correspond to ends of the signal lines; a control circuit for supplying a control signal for driving the display pixels to the signal lines; the plurality of connection pads and the control circuit; A second substrate having a plurality of connection wirings that individually connect
A bonding member for bonding the first substrate and the second substrate and electrically connecting the ends of the plurality of signal lines and the plurality of connection pads individually;
Equipped with a,
The light emitting device , wherein the control circuit is covered with a planarization film formed on a surface of the second substrate, and the connection pads and the connection wiring are provided on the planarization film .   The light-emitting device according to claim 1, wherein the control circuit is disposed inside a region of the second substrate that is bonded to the first substrate.   The distance between the first substrate and the second substrate is set to be smaller than the distance between the plurality of connection pads on the second substrate. Light-emitting device.   The plurality of signal lines are supplied with at least a plurality of scanning lines to which a selection signal for setting the display pixel in a selected state is applied, and a plurality of display data for driving the display pixel in the display state. 4. The light emitting device according to claim 1, further comprising: a data line.   A plurality of external connection pads arranged outside a region bonded to the first substrate and electrically connected to the outside of the second substrate; the plurality of external connection pads; and the control circuit. 5. The light emitting device according to claim 1, wherein a plurality of external connection wirings that are individually connected are provided on the second substrate. The plurality of signal lines include a plurality of scan lines to which a selection signal for setting the display pixel in a selected state is applied and a plurality of data to which display data for driving the display pixel in the display state is supplied. And a plurality of power supply voltage lines to which a power supply voltage supplied to the display pixel is applied,
The second substrate has a quadrilateral shape;
A plurality of external connection pads arranged on the first side of the second substrate outside the region bonded to the first substrate and electrically connected to the outside of the second substrate; A plurality of external connection wirings for individually connecting the external connection pads and the control circuit are provided on the second substrate,
The connection pads corresponding to the scan lines are arranged on the second side of the second substrate,
The connection pads corresponding to the data lines are arranged on the third side of the second substrate,
4. The light emitting device according to claim 1, wherein the connection pads corresponding to the power supply voltage line are arranged on a fourth side of the second substrate. 5. The joining member, the light emitting device according to any one of claims 1 to 6, characterized in that the anisotropic conductive adhesive. Forming a first substrate in which a plurality of display pixels are arranged in a display area, and the ends of a plurality of signal lines connected to each of the display pixels are exposed on an outer periphery of the display area;
A plurality of connection pads arranged so as to correspond to the end portions of the signal lines and a control circuit for supplying a control signal for driving the display pixels to the signal lines are individually connected by a plurality of connection wirings. Forming a formed second substrate;
A step of bonding the first substrate and the second substrate using a single bonding member and electrically connecting the ends of the plurality of signal lines and the plurality of connection pads individually. When,
Only including,
The step of forming the second substrate includes the step of mounting the control circuit on the surface of the second substrate, and the step of forming a planarizing film on the second substrate so as to cover the control circuit. A step of forming an opening through which the connection terminal of the control circuit is exposed in the planarizing film, and connecting the control circuit and the connection pad formed on the planarizing film through the opening. And a step of forming the connection wiring . 9. The light emitting device according to claim 8 , wherein in the step of forming the second substrate, the control circuit is mounted inside a region of the second substrate to which the first substrate is bonded. Manufacturing method. The distance between the first substrate and the second substrate when the first substrate and the second substrate are bonded is greater than the distance between the plurality of connection pads on the second substrate. 10. The method of manufacturing a light emitting device according to claim 8, wherein the light emitting device is set to be smaller.

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