JP2008152291A - Electro-optical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize the device. <P>SOLUTION: The electrooptical device comprises a plurality of unit circuits which is disposed in correspondence to intersection sections for a plurality of scanning lines and a plurality of data lines in an operation region 12 of the substrate 10 and in which each includes an electrooptical element 60, at least one peripheral circuit 14 which has an active element and is formed around the operation region, and a sealing member 84 which has a mounting section 90 existing so as to overlap on the peripheral circuit 14 and seals the electrooptical element 60. The peripheral circuit 14 is any of a scanning line drive circuit for supplying a scanning signal to the unit circuit via a plurality of the scanning lines, an inspection circuit for inspecting the goodness/badness of the unit circuit, and a precharge circuit for outputting a precharge signal to the plurality of the data lines. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electro-optical device, a manufacturing method thereof, and an electronic apparatus.

  In an electro-optical device such as an electroluminescence panel, a region for forming a circuit is necessary, and since an element that is easily affected by oxygen or moisture is included, a region for providing a sealing member for sealing the element is provided. is required. Conventionally, an area for forming a circuit and a mounting area for a sealing member are necessary, so that the apparatus has been enlarged.

  An object of the present invention is to reduce the size of the apparatus.

(1) An electro-optical device according to the present invention includes a substrate and an operation region of the substrate corresponding to intersections of a plurality of scanning lines and a plurality of data lines, each including an electro-optical element. A plurality of unit circuits, an active element, at least one peripheral circuit formed around the operation region, and a mounting portion that is positioned so as to overlap the peripheral circuit, A sealing member that seals the electro-optic element, and the peripheral circuit supplies a scanning signal to the unit circuit via the plurality of scanning lines, and the unit circuit is good or bad Are either an inspection circuit for inspecting and a precharge circuit for outputting a precharge signal to the plurality of data lines.
According to the present invention, since the attachment portion of the sealing member and the peripheral circuit overlap, the apparatus can be reduced in size. Note that the overlap means that at least a part of the attachment portion and at least a part of the peripheral circuit overlap. Further, the substrate is not limited to a plate shape, and includes a substrate that can support other members even in other shapes.
(2) The electro-optical device may further include a spacer adjacent to the peripheral circuit, and the attachment portion may be located above both the peripheral circuit and the spacer.
(3) In this electro-optical device, the spacer may be formed of the same material as the wiring that electrically connects the electro-optical element and the peripheral circuit.
(4) In this electro-optical device, each of the electro-optical elements may include any one of a plurality of light-emitting color light-emitting layers.
(5) An electronic apparatus according to the present invention includes an electro-optical device.
(6) In the electro-optical device manufacturing method according to the present invention, a plurality of unit circuits each including an electro-optical element corresponding to the intersections of the plurality of scanning lines and the plurality of data lines in the operation region of the substrate. Forming at least one peripheral circuit having an active element around the operating region of the substrate; and a sealing member for sealing the electro-optical element, the attachment portion of which is the peripheral Mounting on the substrate so as to overlap with the circuit, the peripheral circuit supplying a scanning signal to the unit circuit via the plurality of scanning lines, the unit circuit of the unit circuit It is either an inspection circuit for inspecting pass / fail or a precharge circuit that outputs a precharge signal to the plurality of data lines.
According to the present invention, since the attachment portion of the sealing member and the peripheral circuit are overlapped, the device can be reduced in size. Note that the overlap means that at least a part of the attachment portion and at least a part of the peripheral circuit overlap. Further, the substrate is not limited to a plate shape, and includes a substrate that can support other members even in other shapes.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an electro-optical device according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating details of the electro-optical device. The electro-optical device 1 may be an electro-optical device such as a display device (for example, a display panel) or a storage device. An electro-optical device 1 shown in FIG. 1 is an organic EL (Electroluminescence) device (for example, an organic EL panel). A substrate (for example, a flexible substrate) 2 is attached to the electro-optical device 1 and is electrically connected thereto. An anisotropic conductive material such as an anisotropic conductive film or an anisotropic conductive paste may be used for the attachment and electrical connection. Electrical connection includes contact. This also applies to the following description. The substrate 2 is a wiring substrate on which wiring patterns and terminals (not shown) are formed. An integrated circuit chip (or semiconductor chip) 3 is mounted on the substrate 2. The integrated circuit chip 3 may have a power supply circuit, a control circuit, and the like. For the mounting, TAB (Tape Automated Bonding) or COF (Chip On Film) may be applied, and the package form may be TCP (Tape Carrier Package). The electro-optical device 1 having the substrate 2 on which the integrated circuit chip 3 is mounted can be referred to as an electronic module (for example, a display module such as a liquid crystal module or an EL module).

  The electro-optical device 1 has a substrate 10. The substrate 10 may be a rigid substrate (for example, a glass substrate or a silicon substrate) or a flexible substrate (for example, a film substrate). The board | substrate 10 may have a light transmittance and may have a light-shielding property. For example, in a bottom emission (or back emission) type display device (for example, an organic EL panel), a light transmissive substrate 10 may be used, and light may be extracted from the substrate 10 side. In the top emission type organic EL panel, a light-shielding substrate 10 may be used. In addition, the board | substrate 10 is not limited to a plate-shaped thing, Even if it is other shapes, the thing which can support another member is included.

  The substrate 10 includes an operation area (for example, a display area) 12. The substrate 10 may be provided with one or a plurality of peripheral circuits (for example, a scanning line driving circuit) 14. The peripheral circuit 14 may be formed around the operation region 12. A pair of peripheral circuits 14 may be formed so as to sandwich the operation region 12. Three or more peripheral circuits 14 may be formed so as to surround the operation region 12. The peripheral circuit 14 has an active element 88 (see FIG. 7). The active element 88 has an active function such as amplification, control, conversion, storage, and various processing of input signals. The active element 88 may be a transistor (for example, a MOS transistor). The active element 88 excludes passive elements such as resistors and capacitors, but the peripheral circuit 14 may include passive elements. The active element 88 may be formed of a polysilicon thin film, and may further include a metal wiring.

The peripheral circuit 14 may be a scanning line driving circuit for supplying a scanning signal to a unit circuit including the electro-optical element 60 via a plurality of scanning lines (for example, the wiring 54).
The peripheral circuit 14 is an inspection circuit for inspecting the quality of the unit circuit including the electro-optical element 60 or for inspecting whether the operation (for example, display operation) in the operation region 12 is normally performed. May be. The peripheral circuit 14 is used in advance as a part of a precharge signal (for example, a signal (voltage or current) to increase the operation speed (display speed) in the operation area 12 or to a plurality of data lines (for example, the wiring 52). It may be a precharge circuit for outputting a signal to be charged. Each of the pair of peripheral circuits 14 sandwiching the operation region 12 may be a scanning line driving circuit, and the other at least one peripheral circuit 14 may be a test circuit or a precharge circuit.

  A plurality of external terminals 20 may be formed on the substrate 10. The plurality of external terminals 20 may be arranged along one side of the substrate 10. The external terminal 20 is provided in the end region 18. The end region 18 is a region that is distinguished from the region on the operation region 12 side by a straight line L (see FIG. 2) that passes outside the operation region 12. The end region 18 is a part of the peripheral region of the substrate 10. The definition of the end region is the same in the following description. The operation region 12 may be a central region (region excluding the peripheral region) of the substrate 10.

  A plurality of or one side wiring (for example, cathode line) 22 may be formed on the substrate 10. The side wiring 22 may be provided in an end region 18 (for example, an end region in which the external terminal 20 is provided) 18. The side wiring 22 may be electrically connected to two or more external terminals 20. The side wiring 22 may have a first portion 24 extending from the external terminal 20 in the direction of the operation region 12. The side wiring 22 may have a second portion 26 that is bent from the first portion 24 and extends in the width direction of the operation region 12. The second portion 26 may be electrically connected to the conductive portion 74 (see FIG. 4).

  One or a plurality of common wirings (for example, common anode lines) 30, 32, and 34 may be formed on the substrate 10. The common wirings 30, 32, and 34 may be provided in an end region 18 (for example, an end region in which the side wiring 22 is provided or an end region in which the external terminal 20 is provided) 18. Each or any one of the common wires 30, 32, 34 may be electrically connected to two or more external terminals 20. Each or any one of the common wires 30, 32, 34 may have a first portion 36 that extends from the external terminal 20 in the direction of the operation region 12. Each or any one of the common wires 30, 32, 34 may have a second portion 38 that is bent from the first portion 36 and extends in the width direction of the operation region 12. The first portion 36 of any one of the common wires 30, 32, 34 (for example, the common wire 30) is outside the first portion 36 of the other one (for example, the common wire 32 or 34) (the substrate 10). It may be arranged at a position close to the end of. One of the common wires 30, 32, 34 (for example, the common wire 30 (specifically, the second portion 38)) is the other one (eg, the common wire 32 or 34 (specifically, the second portion thereof). 38)) may be arranged closer to the operating region 12.

  The common wirings 30, 32, and 34 may be electrically connected to a plurality of wirings 44, 46, and 48 (see FIG. 2). The number of common wirings 30, 32, and 34 (for example, 3) may be smaller than the number of wirings 44, 46, and 48 (for example, 3 × n (n = 2, 3, 4,...)). One group of wirings 44, 46, and 48 may be electrically connected to each of the common wirings 30, 32, and 34.

  The side wiring 22 (for example, the second portion 26) may be disposed at a position closer to the operation region 12 than the common wirings 30, 32, and 34 (for example, the respective second portions 38). Further, the side wiring 22 may be formed outside the common wirings 30, 32, 34 or so as to surround the common wirings 30, 32, 34. Specifically, the first portion 24 of the side wiring 22 may be formed on the outer side (position close to the end portion of the substrate 10) than the first portion 36 of each of the common wirings 30, 32, 34.

  The electro-optical device 1 (for example, the substrate 10) has a multilayer structure including a plurality of conductive patterns. FIG. 3A to FIG. 3C are diagrams showing conductive patterns of each layer in order from the bottom to the top. 4 is a cross-sectional view taken along line IV-IV in FIG.

  The side wiring 22 includes a laminated portion of two or more conductive patterns. For example, as shown in FIG. 4, a part of the conductive pattern 41 (see FIG. 3A), a part of the conductive pattern 42 thereon (see FIG. 3B), and a conductive pattern thereon. 43 (see FIG. 3C) and at least a part of the side wiring 22 is constituted by a laminated portion. By doing so, the side wiring 22 can be formed at least partially thick, and the electrical resistance can be reduced. This content can also be applied to at least one of the external terminal 20 and the common wirings 30, 32, and 34.

  5 is a cross-sectional view taken along the line VV in FIG. A plurality of wires (for example, anode wires) 44, 46, and 48 that are electrically connected to the common wires 30, 32, and 34 are formed on the substrate 10. Each of the wirings 44, 46, 48 is electrically connected to any one second portion 38 of the common wirings 30, 32, 34. In a matrix display device having pixels arranged in a matrix, the number of wirings 44, 46, and 48 may be the same as the number of columns of pixels. Each of the wirings 44, 46, and 48 may be formed by a part of each of two or more conductive patterns. For example, a part of the conductive pattern 41 (see FIG. 3A) and a part of the conductive pattern 42 on the conductive pattern 41 (see FIG. 3B) are electrically connected to each other, and the conductive pattern 42 (see FIG. 3B). )) And a part of the conductive pattern 43 thereon (see FIG. 3C) may be electrically connected to form the wirings 44, 46, and 48.

  Each of the common wirings 30, 32, and 34 is electrically connected to the wiring of any group among the wirings 44, 46, and 48, but is not electrically connected to the wirings of the remaining groups. For example, the first group wiring 44 is electrically connected to the common wiring 30, the second group wiring 46 is electrically connected to the common wiring 32, and the third group wiring 48 is electrically connected to the common wiring 34. It may be connected. In this case, the common wiring 30 is not electrically connected to the second and third group wirings 46 and 48, and the common wiring 32 is electrically connected to the first and third group wirings 44 and 48. The common wiring 34 is not electrically connected to the wirings 44 and 46 of the first and second groups.

  The wirings 44, 46, and 48 and the common wirings 30, 32, and 34 may be arranged so as to cross three-dimensionally. In that case, a contact part is provided between the parts which should be electrically connected among the overlapping parts, and an insulator is provided between the parts which are not electrically connected. For example, the first contact portion 50 that electrically connects the wirings 44, 46, 48 and the common wirings 30, 32, 34 may be formed by a part of the conductive pattern 42 shown in FIG. . In that case, the wirings 44, 46, and 44 are formed by both portions of the conductive patterns 41 and 43 (see FIGS. 3A and 3C) located in a layer different from the conductive pattern 42 (for example, adjacent upper and lower layers). 48 and the common wirings 30, 32, and 34 may be overlapped. In the present embodiment, the wirings 44, 46 and 48 are formed so as to pass under the common wirings 30, 32 and 34. The first contact portion 50 of each of the common wires 30, 32, and 34 and any one of the wires 44, 46, and 48 is located in the end region (for example, the end region provided with the external terminal 20) 18. .

The wirings 44, 46 and 48 may be arranged so as to intersect the side wiring 22 three-dimensionally. In that case, an insulator is provided between the overlapping portions. For example, the wirings 44, 46, and 48 are formed by both portions of the plurality of conductive patterns 41 and 43 (see FIGS. 3A and 3C) positioned in a plurality of stacked layers or a layer that jumps over one layer. In addition, overlapping portions of the side wirings 22 may be formed. In the present embodiment, wirings 44, 46 and 48 are formed so as to pass under the side wiring 22.
According to this, a capacitor can be formed by the wirings 44, 46, 48, the insulator and the side wiring 22, and a sudden voltage drop of the wirings 44, 46, 48 can be prevented.

  6 is a cross-sectional view taken along line VI-VI in FIG. A plurality of wirings (for example, data lines) 52 are formed on the substrate 10. The wiring 52 may be formed by a part of each of two or more conductive patterns. For example, a part of the conductive pattern 41 (see FIG. 3A) and a part of the conductive pattern 42 on the conductive pattern 41 (see FIG. 3B) are electrically connected to each other, and the conductive pattern 42 (see FIG. 3B). )) And a part of the conductive pattern 43 thereon (see FIG. 3C) may be electrically connected to form the wiring 52.

  The wiring 52 may be disposed so as to three-dimensionally intersect the side wiring 22 and the common wirings 30, 32, and 34. In that case, an insulator is provided between the overlapping portions. For example, the wiring 52 and the side wiring 22 are formed by both portions of the plurality of conductive patterns 41 and 43 (see FIG. 3A and FIG. 3C) positioned in a plurality of stacked layers or a layer that jumps over one layer. The overlapping portion and the overlapping portion of the wiring 52 and the common wirings 30, 32, and 34 may be formed. In the present embodiment, the wiring 52 is formed so as to pass under the side wiring 22 and the common wirings 30, 32, 34. The wiring 52 may be separated from the side wiring 22 (or the common wiring 30, 32, 34) so that no capacitor is formed between them or the influence of the capacitor may be reduced. By doing so, the capacitance impedance for the signal flowing through the wiring 52 can be reduced.

  A plurality of wirings (for example, scanning lines) 54 are formed on the substrate 10. The wiring 54 electrically connects the peripheral circuit (for example, the scanning line driving circuit) 14 and the electro-optical element 60. The peripheral circuit 14 may be electrically connected to each end of the wiring 54. The matrix region may be partitioned by the wiring 54 and the wirings 44, 46, 48, 52. The wiring 54 may be arranged so as to intersect with the wirings 44, 46, 48, 52 three-dimensionally. In that case, an insulator is provided between the overlapping portions. For example, the wiring 54 and the wirings 44 and 46 are formed by both portions of the plurality of conductive patterns 41 and 43 (see FIGS. 3A and 3C) positioned in a plurality of stacked layers or a layer that jumps over one layer. , 48, 52 may be formed. In the present embodiment, the wiring 54 is formed so as to pass under the wirings 44, 46, 48, 52.

  A plurality of electro-optic elements 60 are provided on the substrate 10. The region where the electro-optic element 60 is provided is the operation region 12. The electro-optical element 60 is provided corresponding to the intersection of a plurality of scanning lines (for example, the wiring 54) and a plurality of data lines (for example, the wiring 52). The plurality of electro-optical elements 60 include a plurality of light emitting layers 62 of a plurality of light emission colors (for example, red, green, and blue). Each electro-optical element 60 has a light emitting layer 62 of any one light emitting color. The material constituting the light emitting layer 62 may be either a polymer material, a low molecular material, or a material using both in combination. The light emitting layer 62 emits light when a current flows. The light emitting layer 62 may have different light emission efficiency depending on the light emission color. One group of wirings 44, 46, or 48 electrically connected to one common wiring 30, 32, or 34 corresponds to the light emitting layer 62 of the same emission color (specifically, electrically connected). ing).

  The electro-optical element 60 may include at least one of the first and second buffer layers 64 and 66. The first buffer layer 64 may be a hole injection layer that stabilizes hole injection into the light emitting layer 62 or may include a hole injection layer. The first buffer layer 64 may have a hole transport layer. The hole transport layer may be provided between the light emitting layer 62 and the hole injection layer. The second buffer layer 66 may be an electron injection layer that stabilizes electron injection into the light emitting layer 62 or may have an electron injection layer. The second buffer layer 66 may have an electron transport layer. The electron transport layer may be provided between the light emitting layer 62 and the electron injection layer. The adjacent light emitting layers 62 are partitioned (electrically insulated) by the banks 68.

  A plurality of first electrodes 70 are provided on the substrate 10. Each first electrode 70 is for supplying electric energy to one of the electro-optic elements 60. The first electrode 70 may be in contact with the electro-optic element 60 (for example, the first buffer layer 64 (for example, hole injection layer)). Each first electrode 70 is electrically connected to one of the wirings 44, 46, and 48. Each of the wirings 44, 46, and 48 may be electrically connected to a group of first electrodes 70.

  A plurality of or one second electrode 72 is provided on the substrate 10. The second electrode 72 is for supplying electric energy to the electro-optical element 60. The second electrode 72 may be in contact with the electro-optical element 60 (for example, the second buffer layer 66 (for example, the electron injection layer)). The second electrode 72 has a portion facing the first electrode 70. The second electrode 72 may be disposed above the first electrode 70.

  The second electrode 72 is electrically connected to the conductive portion 74. The conductive portion 74 may be provided so as not to face the first electrode 70. The second electrode 72 and the conductive portion 74 may be integrally formed. The conductive portion 74 is electrically connected to the side wiring 22 (for example, the second portion 26 thereof). The second contact portion 76 between the conductive portion 74 and the side wiring 22 is located in an end region (for example, an end region where the first contact portion 50 is provided or an end region where the external terminal 20 is provided) 18. You may do it. When the conductive portion 74 and the side wiring 22 are in contact with each other, the contact portion between them is the second contact portion 76. The second contact portion 76 may extend in the width direction of the operation region 12. For example, the second contact portion 76 may be formed so as to have a length equal to or longer than the distance between the first electrodes 70 located at both ends in the width direction of the operation region 12. Thus, by making the second contact portion 76 longer, the electrical resistance between the conductive portion 74 and the side wiring 22 can be reduced. As a result, the flow of electrons from the side wiring 22 to the second electrode 72 becomes smooth.

  A covering layer 80 is provided on the substrate 10 so as to cover the common wires 30, 32, and 34. The covering layer 80 may be formed of one or more layers. The covering layer 80 may be formed of an electrically insulating material. At least the surface of the coating layer 80 may be formed of an oxide or a nitride. The side wiring 22 (at least the second portion 26) is exposed from the coating layer 80.

  As shown in FIGS. 5 and 6, a spacer 82 is provided next to the common wires 30, 32, and 34 (for example, a position away from the operation region 12 or a position near the end of the substrate 10). The spacer 82 may be a dummy wiring formed of the same material as at least one of the common wirings 30, 32, 34, the side wiring 22, and the wirings 44, 46, 48, 52. The spacer 82 is formed under the covering layer 80. By providing the spacer 82, the surface of the coating layer 80 is raised in the region adjacent to the common wires 30, 32, and 34. By doing so, the height difference (step) between the region above the common wires 30, 32, and 34 and the region above the spacer 82 may be reduced or eliminated on the surface of the coating layer 80. Alternatively, the slope or unevenness of the surface of the covering layer 80 may be reduced or flattened from the region above the common wirings 30, 32, and 34 to the region above the spacer 82.

  The substrate 10 is provided with a sealing member 84 for the electro-optic element 60. When at least a part of the electro-optical element 60 is easily deteriorated by moisture, oxygen, or the like, the electro-optical element 60 can be protected by the sealing member 84. The sealing member 84 has an attachment portion 90 for the substrate 10. 7 is a cross-sectional view taken along line VII-VII in FIG. As shown in FIG. 7, the attachment portion 90 is positioned so as to overlap the peripheral circuit 14. The overlap means that at least a part of the attachment portion 90 and at least a part of the peripheral circuit 14 overlap. All of the plurality of peripheral circuits 14 may overlap with the attachment portion 90. Alternatively, the remaining peripheral circuits 14 excluding at least one of the plurality of peripheral circuits 14 may overlap the mounting portion 90. As shown in FIG. 7, the entire peripheral circuit 14 may be disposed in the region of the attachment portion 90. According to the present embodiment, since the attachment portion 90 of the sealing member 84 and the peripheral circuit 14 overlap, the apparatus can be reduced in size.

8 and 9 are diagrams for describing a modification of the present embodiment. In FIG. 8, only a part of the peripheral circuit 92 is disposed in the region of the attachment portion 90. In such a case, a spacer 94 may be formed next to the peripheral circuit 92. The attachment portion 90 may be located above both the peripheral circuit 92 and the spacer 92.
By providing the spacer 94, the surface of the covering layer 80 is raised in a region adjacent to the peripheral circuit 92. By doing so, the height difference (step) between the region above the peripheral circuit 92 and the region above the spacer 94 may be reduced or eliminated on the surface of the coating layer 80. Alternatively, the slope or unevenness of the surface of the covering layer 80 may be reduced or flattened from the region above the peripheral circuit 92 to the region above the spacer 94. The spacer 94 may be formed of the same material as the wiring 54 that electrically connects the electro-optical element 60 and the peripheral circuit 92, and this may be referred to as a dummy wiring.

  In FIG. 9, the entire peripheral circuit 96 is disposed in the region of the attachment portion 90. Even in such a case, the spacer 98 may be formed next to the peripheral circuit 96, and the mounting portion 90 may be disposed above both the peripheral circuit 92 and the spacer 92. The effect is the same as that of the modification shown in FIG.

  The attachment portion 90 of the sealing member 84 with respect to the substrate 10 (for example, the covering portion 80) may be disposed avoiding the side wiring 22 or the conductive portion 74 (so as not to contact). For this purpose, the mounting portion 90 of the sealing member 84 may be disposed outside the side wiring 22 and the conductive portion 74 (a position away from the operation region 12 or a position close to the end of the substrate 10). In this way, even when at least the surface of the side wiring 22 or the conductive portion 74 is formed of a material having low adhesion to the adhesive 86 (for example, metal), the adhesive 86 is used to seal the sealing member 84. It can be securely fixed to the substrate 10 (for example, the covering portion 80). Note that the covering portion 80 may be higher in adhesiveness with the adhesive 86 than the metal.

  In the present embodiment, the common wirings 30, 32, and 34 are formed outside the side wiring 22 (a position away from the operation region 12 or a position close to the end of the substrate 10). Therefore, the attachment portion 90 of the sealing member 84 and at least a part of the common wires 30, 32, 34 can be overlapped. Thereby, the sealing member 84 can be reduced in size, and the electro-optical device 1 can be reduced in size. Further, the attachment portion 90 of the sealing member 84 may be positioned above both at least a part of the spacer 82 and at least a part of the common wirings 30, 32, 34. According to this, since the attachment portion 90 of the sealing member 84 is disposed in a region (for example, a flat region) having a small inclination or unevenness on the surface of the covering layer 80, the attachment thereof can be performed satisfactorily.

FIG. 10 is a circuit diagram for explaining the operation of the electro-optical device according to the present embodiment.
The electro-optical device 1 has elements corresponding to the circuit shown in FIG. The circuit configuration (element connection state) is as shown in FIG. In the present embodiment, the side wiring 22 is connected to a low potential (for example, a ground potential), and the common wirings 30, 32, and 34 are connected to a higher potential. Different voltages V _dd1 , V _dd2 , and V _dd3 are supplied to the common wirings 30, 32, and 34, respectively. The voltages V _dd1 , V _dd2 , and V _dd3 are voltages corresponding to the light emission efficiency of the light emitting layer 62, respectively. A current I _data flows through the wiring (data line) 52. The current I _data is a signal corresponding to the current supplied to the electro-optical element 60. A selection signal is input to the wiring (scanning line) 54. The selection signal is a high potential H signal or a low potential L signal. Hereinafter, the operation of one unit circuit including the electro-optical element 60 will be described.

In the programming period, for example, the voltage V _dd2 is supplied to the wiring 46, and the current I _data flows through the wiring 52. In the programming period, an H signal is input to the wiring 54, the switching elements 110 and 116 are turned on, and the switching element 112 is turned off. When the current I _data flows from the wiring 46 through the switching elements 114 and 116 to the wiring 52, the control voltage of the switching element 114 (the gate voltage when the switching element 114 is a MOS transistor) is the current I _data. The electric charge corresponding to the control voltage is stored in the capacitor 120.

  In an operation period (for example, a light emission period), an L signal is input to the wiring 54, the switching elements 110 and 116 are turned off, and the switching element 112 is turned on. Then, the switching element 114 is controlled (for example, ON) by a control voltage (a gate voltage when the switching element 114 is a MOS transistor) corresponding to the charge stored in the capacitor 120 during the programming period, and a current corresponding to the control voltage is generated. The electro-optical element 60 flows from the wiring 46 through the switching elements 114 and 112.

  The element described above is provided for each electro-optical element 60. The switching elements 110, 112, 114, 116, etc. may be formed by a polysilicon thin film or the like. In the present embodiment, the side wiring (for example, cathode wiring) 22, the wirings 44, 46, and 48 electrically connected to the common wiring (for example, anode wiring) 30, 32, and 34, and the insulator therebetween, A capacitor 122 is formed. Therefore, a rapid voltage drop of the common wiring (for example, anode wiring) 30, 32, and 34 can be prevented.

  In the electro-optical device manufacturing method according to the present embodiment, a plurality of electro-optical elements 60 are provided in the operation region 12 of the substrate 10. At least one peripheral circuit 14 having an active element 88 is formed around the operation region 12 of the substrate 10. A sealing member 84 that seals the electro-optic element 60 is attached to the substrate 10 such that the attachment portion 90 overlaps the peripheral circuit 14. According to the present embodiment, since the attachment portion 90 of the sealing member 84 and the peripheral circuit 14 are overlapped, the apparatus can be reduced in size. Note that the overlap means that at least a part of the attachment portion 90 and at least a part of the peripheral circuit 14 overlap.

  As an electronic apparatus having the electro-optical device according to the embodiment of the present invention, a notebook personal computer 1000 is shown in FIG. 11, and a mobile phone 2000 is shown in FIG.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

FIG. 1 is a diagram illustrating an electro-optical device according to an embodiment of the invention. FIG. 2 is a diagram illustrating details of the electro-optical device according to the embodiment of the invention. FIG. 3A to FIG. 3C are diagrams showing conductive patterns of each layer in order from the bottom to the top. 4 is a cross-sectional view taken along line IV-IV in FIG. 5 is a cross-sectional view taken along the line VV in FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. FIG. 8 is a diagram illustrating an electro-optical device according to a modification of the embodiment of the present invention. FIG. 9 is a diagram illustrating an electro-optical device according to a modification of the embodiment of the present invention. FIG. 10 is a circuit diagram for explaining the operation of the electro-optical device according to the embodiment of the invention. FIG. 11 is a diagram illustrating an electronic apparatus according to an embodiment of the present invention. FIG. 12 is a diagram illustrating an electronic apparatus according to an embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 10 ... Board | substrate, 12 ... Operation | movement area | region, 18 ... End part area | region, 20 ... External terminal, 22 ... Side wiring, 24 ... 1st part, 26 ... 2nd part, 30, 32, 34 ... Common wiring, 36 ... First part, 38 ... Second part, 44, 46, 48 ... Wiring, 50 ... First contact part, 60 ... Electro-optic element, 70 ... First electrode, 72 ... First Two electrodes, 74 ... conductive part, 76 ... second contact part, 80 ... coating layer, 82 ... spacer, 84 ... sealing member, 88 ... active element, 90 ... attachment part.

Claims (6)

A substrate,
A plurality of unit circuits each including an electro-optic element, provided corresponding to the intersections of the plurality of scanning lines and the plurality of data lines in the operation region of the substrate;
At least one peripheral circuit having active elements and formed around the operating region;
A sealing member that is positioned so as to overlap with the peripheral circuit and has a mounting portion for the substrate, and seals the electro-optic element;
Have
The peripheral circuit includes a scanning line driving circuit for supplying a scanning signal to the unit circuit through the plurality of scanning lines, an inspection circuit for inspecting the quality of the unit circuit, and precharging the plurality of data lines. An electro-optical device that is one of precharge circuits that output signals. The electro-optical device according to claim 1.
A spacer next to the peripheral circuit;
The mounting portion is an electro-optical device that is located above both the peripheral circuit and the spacer. The electro-optical device according to claim 2.
The spacer is an electro-optical device formed of the same material as a wiring that electrically connects the electro-optical element and the peripheral circuit. The electro-optical device according to any one of claims 1 to 3,
Each of the electro-optical elements is an electro-optical device having any one of a plurality of light emitting layers.   An electronic apparatus comprising the electro-optical device according to claim 1. Providing a plurality of unit circuits each including an electro-optic element corresponding to the intersections of the plurality of scanning lines and the plurality of data lines in the operation region of the substrate;
Forming at least one peripheral circuit with active elements around the operating region of the substrate; and
Attaching a sealing member for sealing the electro-optic element to the substrate such that the attaching portion overlaps the peripheral circuit;
Including
The peripheral circuit includes a scanning line driving circuit for supplying a scanning signal to the unit circuit through the plurality of scanning lines, an inspection circuit for inspecting the quality of the unit circuit, and precharging the plurality of data lines. A method for manufacturing an electro-optical device, which is one of precharge circuits that output signals.

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