JP2002032057A - Light emitting device and driving method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type light emitting device permitting sharp multi-gradation color display. SOLUTION: Each of the plural pixels included in a pixel part has an EL element, a switching use TFT, and an EL driving use TFT respectively, and the EL element has a pixel electrode, a counter electrodes, and an EL layer arranged between the pixel electrode and the counter electrodes, and time- division gradation display is performed by controlling a potential of the counter electrodes and that of the pixel electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electronic display formed by forming an EL (electroluminescence) element on a substrate. In particular, the present invention relates to an EL display using a semiconductor element (an element using a semiconductor thin film). Further, the present invention relates to a light emitting device using an EL display as a display portion and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, the technology for forming a TFT on a substrate has been greatly advanced, and its application to an active matrix type electronic display has been developed. In particular, a TFT using a polysilicon film has higher field-effect mobility (also referred to as mobility) than a TFT using a conventional amorphous silicon film, and thus can operate at high speed. for that reason,
The control of pixels, which has been performed by a drive circuit provided outside the substrate in the related art, can be performed by a drive circuit formed on the same substrate as the pixels.

[0003] Such an active matrix type electronic display can be manufactured by various circuits and elements on the same substrate to reduce various manufacturing costs, downsize the electronic display, increase the yield, and reduce the throughput. Benefits are obtained.

Further, active matrix EL displays having EL elements as self-luminous elements have been actively studied. EL display is organic EL
Display (OELD: Organic EL Display) or Organic Light Emitting Diode (OLED: Organic)
c Light Emitting Diode).

An EL display is a self-luminous type unlike a liquid crystal display. An EL element has a structure in which an EL layer is sandwiched between a pair of electrodes (anode and cathode).
The layers usually have a laminated structure. A typical example is a laminated structure of “hole transport layer / light emitting layer / electron transport layer” proposed by Tang et al. Of Kodak Eastman Company. This structure has a very high luminous efficiency, and almost all EL displays currently under research and development adopt this structure.

In addition, a hole injection layer / hole transport layer / light-emitting layer / electron transport layer, or a hole injection layer / hole transport layer / light-emitting layer / electron transport layer / electron injection layer may be provided on the anode. A structure in which layers are sequentially stacked may be used. The light emitting layer may be doped with a fluorescent dye or the like.

The luminescence in the EL layer includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. The light emitting device may use any one of the above-described light emissions or may use both light emissions.

In this specification, all layers provided between a cathode and an anode are collectively called an EL layer. Therefore, the above-described hole injection layer, hole transport layer, light-emitting layer, electron transport layer, electron injection layer, and the like are all included in the EL layer.

Then, a predetermined voltage is applied to the EL layer having the above structure from a pair of electrodes, whereby recombination of carriers occurs in the light emitting layer to emit light. Note that in this specification, emission of an EL element is referred to as driving of the EL element. In this specification, a light-emitting element including an anode, an EL layer, and a cathode is referred to as an EL element.

As a driving method of the EL display, there is an analog driving method (analog driving). E
The analog driving of the L display will be described with reference to FIGS.

FIG. 23 shows a structure of a pixel portion of an analog display EL display. Gate signal lines (G1 to Gy) for inputting a gate signal from the gate signal line driving circuit are connected to a gate electrode of a switching TFT 1801 included in each pixel. One of a source region and a drain region of the switching TFT 1801 included in each pixel is connected to source signal lines (also referred to as data signal lines) S1 to Sx for inputting analog video signals, and the other is used for EL driving included in each pixel. It is connected to the gate electrode of the TFT 1804 and the capacitor 1808 of each pixel.

Each pixel has an EL driving TFT 1804
Are connected to power supply lines V1 to Vx, and the drain region is connected to an EL element 1806. The potentials of the power supply lines V1 to Vx are called power supply potentials. The power supply lines V1 to Vx are connected to a capacitor 1808 included in each pixel.

The EL element 1806 has an anode, a cathode, and an EL layer provided between the anode and the cathode. EL element 1
When the anode 806 is connected to the drain region of the EL driving TFT 1804, the anode of the EL element 1806 is a pixel electrode and the cathode is a counter electrode. Conversely, when the cathode of the EL element 1806 is connected to the drain region of the EL driving TFT 1804, the anode of the EL element 1806 serves as a counter electrode and the cathode serves as a pixel electrode.

In this specification, the potential of the counter electrode is called a counter potential. Note that a power supply that applies a counter potential to the counter electrode is referred to as a counter power supply. The potential difference between the potential of the pixel electrode and the potential of the counter electrode is the EL drive voltage.
Hang on layers.

FIG. 2 is a timing chart when the EL display shown in FIG. 23 is driven in an analog system.
It is shown in FIG. A period from when one gate signal line is selected to when another gate signal line is selected next is called one line period (L). In analog driving, a period from the display of one image to the display of the next image corresponds to one frame period (F). In the case of the EL display of FIG. 23, since there are y gate signal lines, y line periods (L1 to Ly) are provided in one frame period.

As the resolution increases, the number of line periods in one frame period increases, and the driving circuit must be driven at a high frequency.

First, the power supply lines V1 to Vx are maintained at a constant power supply potential. The counter potential, which is the potential of the counter electrode, is also kept at a constant potential. The opposing potential has a potential difference from the power supply potential to such an extent that the EL element emits light.

In the first line period (L1), the gate signal line G1 is selected by a gate signal input from the gate signal line driving circuit to the gate signal line G1.

Note that in this specification, selecting a gate signal line means that all the thin film transistors whose gate electrodes are connected to the gate signal line are turned on.

Then, analog video signals are sequentially input to the source signal lines S1 to Sx. Since all the switching TFTs 1801 connected to the gate signal line G1 are turned on, the analog video signals input to the source signal lines S1 to Sx are
The signal is input to the gate electrode of the EL driving TFT 1804 through T1801.

The amount of current flowing through the channel forming region of the EL driving TFT 1804 is controlled by the height (voltage) of the signal input to the gate electrode of the EL driving TFT 1804. Therefore, the potential applied to the pixel electrode of the EL element 1806 is determined by the level of the potential of the analog video signal input to the gate electrode of the EL driving TFT 1804. The EL element 1806 emits light under the control of the potential of the analog video signal.

The above operation is repeated, and the source signal line S
When the input of the analog video signal to 1 to Sx ends, the first line period (L1) ends. Note that the period until the input of the analog video signal to the source signal lines S1 to Sx ends and the horizontal retrace period may be combined into one line period.

Then, the second line period (L2) starts, and the gate signal line G2 is selected by the gate signal. Then, analog video signals are sequentially input to the source signal lines S1 to Sx as in the first line period (L1).

Then, all the gate signal lines (G1 to Gy)
When the gate signal is input to all the line periods (L1
To Ly) ends. All line periods (L1 to Ly)
Is completed, one frame period ends. All the pixels display during one frame period, and one image is formed. Note that all the line periods (L1 to Ly) and the vertical flyback period may be combined into one frame period.

As described above, the light emission amount of the EL element is controlled by the analog video signal, and the gradation display is performed by controlling the light emission amount. This method is a so-called analog driving method, and gradation display is performed by changing the potential of an analog video signal input to a source signal line.

[0026]

FIG. 25 shows how the amount of current supplied to the EL element is controlled by the gate voltage of the EL driving TFT in the analog driving method described above.
This will be described in detail with reference to FIG.

FIG. 25A is a graph showing the transistor characteristics of the EL driving TFT. Reference numeral 2801 denotes I _DS -V _GS.
It is called the characteristic (or I _DS -V _GS curve). Where I
_DS is a drain current, and V _GS is a voltage (gate voltage) between the gate electrode and the source region. From this graph, the amount of current flowing for an arbitrary gate voltage can be known.

When gradation display is performed by the analog driving method, the EL element is driven by using the region indicated by the dotted line 2802 of the I _DS -V _GS characteristics. FIG. 25B is an enlarged view of a region surrounded by 2802.

In FIG. 25 (B), a region indicated by oblique lines is called a saturation region. Specifically, assuming that the threshold voltage is V _TH , it indicates a region where the gate voltage satisfies | V _GS −V _TH | <| V _DS | The drain current changes functionally. The current control by the gate voltage is performed using this region.

When the switching TFT is turned on, the pixel
The analog video signal input into the
It becomes the gate voltage of T. At this time, as shown in FIG.
I _DS-V_GSDrain to gate voltage according to characteristics
The current is determined on a one-to-one basis. That is, the game of the EL driving TFT
Compatible with analog video signal voltage input to
As a result, the potential of the drain region is determined, and a predetermined drain voltage is set.
Current flows to the EL element, and the light emission amount
The EL element emits light.

As described above, the light emission amount of the EL element is controlled by the video signal, and gradation control is performed by controlling the light emission amount.

However, the analog driving is performed by using a TFT.
Has the drawback that it is very weak to the variation in the characteristics. Even if the same gate voltage is applied to the EL driving TFT of each pixel, the same drain current cannot be output if the I _DS -V _GS characteristics of the EL driving TFT vary. Further, as is clear from FIG. 25A, since the saturation region where the drain current changes exponentially with respect to the change in the gate voltage is used, even if the I _DS -V _GS characteristics are slightly shifted, Even if the same gate voltage is applied, a situation may occur in which the amount of output current is significantly different. In such a case, even if a signal of the same voltage is input, the light emission amount of the EL element greatly differs between the adjacent pixels due to slight variations in the I _DS -V _GS characteristics.

As described above, the analog driving is performed by the EL driving T
It is extremely sensitive to variations in the characteristics of the FT, which has been an obstacle in the gradation display of the conventional active matrix EL display.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an active matrix type EL display capable of displaying clear multi-tone colors. And such an active matrix EL
It is an object to provide a high-performance light-emitting device (electronic device) including a display as a display.

[0035]

The inventor of the present invention has found that the problem of the analog drive is affected by the variation of the I _DS -V _GS characteristic because the drain current changes exponentially with the change of the gate voltage. This is considered to be caused by performing gradation display using an easily saturated region.

That is, when there is a variation in the I _DS -V _GS characteristics, the drain current changes exponentially with the change in the gate voltage in the saturation region. (Drain current) is output, and as a result, a problem occurs that a desired gradation cannot be obtained.

Therefore, the present inventor has considered that the amount of light emitted from the EL element is controlled not by controlling the current using the saturation region but mainly by controlling the time during which the EL element emits light. . That is, in the present invention, the amount of light emitted from the EL element is controlled by time to perform gradation display. This is referred to as a time-division driving method (hereinafter referred to as digital driving) in which gradation display is performed by controlling the emission time of an EL element. Note that the gradation display performed by the time-division driving method is referred to as time-division gradation display.

With the above structure, according to the present invention, even if the I _DS -V _GS characteristics of the EL driving TFT are slightly varied,
It is possible to avoid a situation in which the light emission amount of the EL element greatly differs between adjacent pixels when a signal of the same voltage is input.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an EL display according to the present invention and a method for driving the EL display will be described below. Here, a case where 2 ⁿ gray scale display is performed by an n-bit digital video signal will be described.

FIG. 1 shows an example of a block diagram of an EL display of the present invention. The EL display shown in FIG. 1 includes a pixel portion 101 and a pixel portion 10 formed by TFTs formed on a substrate.
1, a source signal line driving circuit 102, a gate signal line driving circuit 103, and a counter power line driving circuit 104
have. Note that the EL display described in this embodiment includes one source signal line driver circuit, one gate signal line driver circuit, and one counter power supply line driver circuit; however, the present invention is not limited to this. The numbers of the source signal line driving circuits, the gate signal line driving circuits, and the opposing power supply line driving circuits can be arbitrarily determined.

In the present invention, the source signal line driving circuit 102, the gate signal line driving circuit 103, or the opposing power supply line driving circuit 104 may be provided on a substrate on which the pixel portion 101 is provided, or may be provided on an IC chip. And connected to the pixel portion 101 via FPC or TAB.

FIG. 2 is an enlarged view of the pixel portion 101. The source signal lines S1 to Sx, the power supply lines V1 to Vx, the gate signal lines G1 to Gy, and the opposing power lines E1 to Ey include the pixel unit 101.
It is provided in.

The source signal lines S1 to Sx and the power supply line V
1 to Vx; gate signal lines G1 to Gy;
A region having one of the pixels 1 to Ey is the pixel 105.
In the pixel portion 101, a plurality of pixels 105 are arranged in a matrix.

FIG. 3 is an enlarged view of the pixel 105. 107
Is a switching TFT, 108 is an EL driving TFT,
110 is an EL element, 112 is a capacitor.

The gate electrode of the switching TFT 107 is connected to a gate signal line G (any one of G1 to Gy). One of a source region and a drain region of the switching TFT 107 has one of source signal lines S (S1 to S
x) and the other is EL
The gate electrode of the driving TFT 108 is connected to the capacitor 112 of each pixel.

The capacitor 112 is a switching TFT.
When the gate 107 is in a non-selected state (off state), it is provided to hold a gate voltage of the EL driving TFT 108. Note that although a structure in which the capacitor 112 is provided is described in this embodiment, the present invention is not limited to this structure, and a structure without the capacitor 112 may be employed.

The source region of the EL driving TFT 108 is connected to the power supply line V (one of V1 to Vx), and the drain region is connected to the EL element 110. The power supply line V is connected to a power supply (not shown) provided outside the substrate having the pixel portion 101, and is always supplied with a constant power supply potential.

In a current typical EL display, when the amount of light emission per pixel area is 200 cd / m ² , a current per pixel area is required to be about several mA / cm ² . Therefore, when the size of the pixel portion is increased, it becomes difficult to control a potential applied to a power supply line from a power supply provided in an IC or the like with a switch. In the present invention,
The power supply potential is always kept constant, and there is no need to control the height of the potential given from the power supply provided in the IC with a switch, which is useful for realizing a panel with a larger screen size.

The power supply line V is connected to the capacitor 112.

The EL element 110 includes an anode and a cathode, and an EL layer provided between the anode and the cathode. When the anode is connected to the drain region of the EL driving TFT 108,
The anode serves as a pixel electrode and the cathode serves as a counter electrode. Conversely, the cathode is E
When connected to the drain region of the L driving TFT 108, the cathode serves as a pixel electrode and the anode serves as a counter electrode.

The opposing electrode of the EL element 110 is connected to the opposing power supply line E (any one of E1 to Ey). In this specification, the potential of the opposing power supply line E is referred to as an opposing potential.

As the switching TFT 107 and the EL driving TFT 108, either an n-channel TFT or a p-channel TFT can be used. Where E
When the anode of the L element 110 is a pixel electrode and the cathode is a counter electrode, the EL driving TFT 108 is preferably a p-channel TFT. Conversely, when the anode of the EL element 110 is a counter electrode and the cathode is a pixel electrode, the EL driving TFT 10
8 is preferably an n-channel TFT.

The switching TFT 107 and the EL driving TFT 108 may have a multi-gate structure such as a double gate structure or a triple gate structure instead of a single gate structure.

Next, a method of driving the EL display of the present invention shown in FIGS. 1 to 3 will be described with reference to FIG.

First, the opposing potential applied to the opposing power supply line E1 by the opposing electrode power supply line driving circuit 104 is
To the extent that the EL element emits light when the power supply potential is applied to the pixel electrode, it is maintained at a potential (ON counter potential) having a potential difference from the power supply potential.

Then, the gate signal line G1 is selected by the gate signal input from the gate signal line driving circuit 103 to the gate signal line G1. Therefore, the switching TFTs 107 of all the pixels (pixels on the first line) connected to the gate signal line G1 are turned on.

Then, the first bit digital video signal input to the source signal lines S1 to Sx from the source signal line driving circuit 102 is input to the gate electrode of the EL driving TFT 108 via the switching TFT 107.
Note that in this specification, a case where a digital video signal is input to the gate electrode of the EL driving TFT 108 through the switching TFT 107 is referred to as a case where a digital video signal is input to a pixel.

The digital video signal is "0" or "1"
The digital video signals of “0” and “1” are signals having one Hi voltage and one Lo voltage.

In this embodiment, when the digital video signal has information of “0”, the EL driving TFT 10
8 turns off. Therefore, no power supply potential is applied to the pixel electrode of the EL element 110. As a result, the EL element 110 included in the pixel to which the digital video signal having the information “0” is input does not emit light.

Conversely, when the digital video signal has information of “1”, the EL driving TFT 108 is turned on. Accordingly, a power supply potential is applied to the pixel electrode of the EL element 110. As a result, the EL element 110 included in the pixel to which the digital video signal having the information of “1” is input is provided.
Emits light.

In this embodiment, when the digital video signal has information of “0”, the EL driving TFT 1
08 is in an off state, and when the information has “1”, the EL driving TFT 108 is in an on state, but the present invention is not limited to this configuration. If the digital video signal has information of “0”, the EL driving TFT 10
8 may be turned on and the EL driving TFT 108 may be turned off when the information has the information “1”.

As described above, at the same time when the digital video signal is input to the pixels on the first line, the EL element 110 emits light or does not emit light, and the pixels on the first line perform display. A period during which the pixel performs display is called a display period Tr. In particular, a display period started when the first bit digital video signal is input to the pixel is referred to as Tr1. The timing at which the display period of each line is started has a time difference.

Next, when the selection of the gate signal line G1 is completed, the opposing power supply line E1 is maintained by the opposing power supply line driving circuit 104 while the opposing power supply line E1 is kept at the ON opposing potential.
2 is kept at the ON counter potential. And the gate signal line G
2 is selected by the gate signal, the switching TFTs 107 of all the pixels connected to the gate signal line G2 are turned on, and the pixels of the second line are set to the first bit from the source signal lines S1 to Sx. Is input.

As described above, all the opposing power supply lines E1 to E1
Ex is kept at the opposite potential. Then, all the gate signal lines G1 to Gy are selected, and the first bit digital video signal is input to all the pixels. The period until the digital video signal of the first bit is input to all the pixels is the writing period Ta1.

On the other hand, before the digital video signal of the first bit is input to all the pixels, in other words, before the end of the writing period Ta1, in parallel with the input of the digital video signal of the first bit to the pixels, Counter power line drive circuit 10
4 keeps the opposing potential applied to the opposing power supply line E1 at the same level as the power supply potential (the off opposing potential). Then, all the EL elements whose counter electrodes are connected to the counter power supply line E1 are in a non-light emitting state. Therefore, all the pixels (pixels on the first line) having the EL element whose counter electrode is connected to the counter power supply line E1 do not perform display.

A period in which the pixel does not perform display is defined as a non-display period T
Called d. In the pixels on the first line, the opposite power line E1
Is maintained at the off counter potential, and at the same time, the display period Tr1 ends, and the non-display period Td1 starts. Like the display period,
The timing at which the non-display period of each line is started has a time difference.

Then, while the opposing power supply line E1 is kept at the off-facing potential, the opposing power supply line E2 is kept at the off-facing potential. Therefore, all pixels (pixels on the second line) having an EL element whose counter electrode is connected to the counter power supply line E2
Is in a non-display state in which no display is performed.

Then, in turn, all the opposing power supply lines are kept at the off opposing potential. An erasing period Te1 is a period in which all of the opposing power supply lines E1 to Ey are kept at the opposing potential of OFF and all the pixels that have been displaying by the first bit digital signal are in a non-display state.

On the other hand, before all the opposing power supply lines E1 to Ey are kept at the off opposing potential, in other words, the erasing period Te1
Before the operation is completed, the opposing power supply line E1 is again kept at the ON opposing potential in parallel with the pixel being in the non-display state.
Then, the gate signal line G1 is selected by the gate signal, and the digital video signal of the second bit is input to the pixels of the first line. As a result, the pixels on the first line perform display again, so that the non-display period Td1 ends and the display period Td1 ends.
r2.

Similarly, all the opposing power supply lines are sequentially kept at the ON opposing potential. Then, all the gate signal lines are sequentially selected, and the digital video signal of the second bit is input to all the pixels. A period until the input of the second bit digital video signal to all the pixels is called a writing period Ta2.

On the other hand, before the input of the second bit digital video signal to all the pixels, in other words, before the end of the writing period Ta2, in parallel with the input of the second bit digital video signal to the pixels. , The opposing power supply line E1 is kept at the opposing potential that is off. Accordingly, the EL elements of the pixels on the first line are all in a non-light emitting state, and the pixels on the first line do not perform display. Accordingly, the display period Tr2 ends in the pixels on the first line, and the non-display period Td2 is set.

Then, in turn, all the opposing power supply lines are kept at the off opposing potential. An erasing period Te2 is a period from when all the opposing power supply lines E1 to Ey are kept at the opposing electric potential in the off state, and until all the pixels that have been displaying with the digital signal of the second bit enter the non-display state.

The above operation is repeated until the m-th bit digital video signal is input to the pixel, and the display period Tr and the non-display period Td appear repeatedly. During the display period Tr1 of the pixels in each line, during the writing period Ta1, an ON counter potential is applied to the counter electrode of the pixels in each line to write a digital video signal to the pixels in each line. This is a period until an off counter potential is applied to the counter electrode of the pixel. In the non-display period Td1 of the pixels in each line, the line is turned off in the next writing period (in this case, the writing period Ta2) after the off counter potential is applied to the counter electrode of the pixel in each line in the erasing period Te1. This is a period from when an on-potential is applied to the opposing electrode of the pixel and a digital video signal is written to the pixel on each line. The display periods Tr2, Tr3,..., Tr (m−
1) and non-display periods Td2, Td3,..., Td (m-1)
Also, each period is determined similarly to the display period Tr1 and the non-display period Td1.

For the sake of simplicity, FIG.
The case of -2 is shown as an example, but it goes without saying that the present invention is not limited to this. In the present invention, m can arbitrarily select a value from 1 to n.

Next, the opposing power supply line E1 is kept at the ON opposing potential, and the digital video signal of the m-th (n-2 (hereafter, parentheses show the case of m = n-2)) bit is one line. Input to the pixel of the eye. Therefore, the pixels on the first line enter the display period Trm [n-2] and display is performed.

In the same manner, all the opposing power supply lines are sequentially kept at the ON opposing potential. Then, the digital video signal of the m [n-2] th bit is input to the pixels of all the lines, and the pixels of all the lines enter the display period Trm [n-2] to perform display.

The m [n-2] th bit digital video signal is held in the pixel until the next bit digital video signal is input.

Next, when the digital video signal of the (m + 1) [n-1] th bit is input to the pixels of the first line while all the opposing power supply lines are maintained at the ON opposing potential, the pixels are held in the pixels. The digital video signal of the m [n-2] th bit is rewritten to the digital video signal of the (m + 1) [n-1] th bit. Then, the pixels on the first line enter a display period Tr (m + 1) [n-1], and display is performed.

Similarly, the digital video signal of the (m + 1) [n-1] th bit is input to the pixels of all the lines while all the opposite power supply lines are kept at the on-potential in order. The pixels in the line are in the display period Tr (m + 1)
[N-1] is displayed.

Until the next bit of the digital video signal is input, the (m + 1) [n-1] th bit of the digital video signal is held in the pixel.

The above operation is repeated until the n-th bit digital video signal is input to the pixel. Display period Trm [n-2],..., Trn of the pixels of each line
Appears in the writing period Tam [n-2],..., Tan, after an on-potential is applied to the opposing electrode of the pixel on each line to write a digital video signal to the pixel on each line. In the writing period, this is a period from when an ON counter potential is applied to the counter electrode of the pixel in each line and a digital video signal is written in the pixel in each line.

When all the display periods Tr1 to Trn are completed, one image can be displayed. In the present invention, a period during which one image is displayed is called one frame period (F). In the driving method of the present invention, the frame period (F) differs for each pixel in each line. y
The frame period of the pixel on the line is almost equal to the writing period T
It starts after the start of the frame period of the pixels of the first line by the length of a1.

After the end of one frame period, the opposing power supply lines E1 to Ey are again kept at the opposing potential of ON, and the gate signal line G1 is selected by the gate signal. And 1
The digital video signal of the bit is input to the pixel, and the pixel of the first line is again in the display period Tr1. Then, the above operation is repeated again.

The EL display preferably has 60 or more frame periods per second. When the number of images displayed in one second is less than 60, flickering of the images may start to be noticeable.

In the present invention, it is important that the sum of the lengths of all the writing periods is shorter than the length of one frame period. In addition, the length of the display period is Tr1: Tr2: Tr
3 ::: Tr (n-1): Trn = 2 ⁰ : 2 ¹ : 2 ² :
…: 2 ⁽ⁿ⁻²⁾ : 2 ⁽ⁿ⁻¹⁾ . A desired gradation display out of 2 ⁿ gradations can be performed by the combination of the display periods.

By calculating the sum of the lengths of the display periods during which the EL element emits light during one frame period, the displayed gradation of the pixel in the frame period is determined. For example, assuming that when the pixel emits light in all display periods when n = 8, the luminance is 100%, and when the pixel emits light in Tr1 and Tr2, 1% luminance can be expressed.
When Tr5 and Tr8 are selected, 60% luminance can be expressed.

It is important that the writing period Tam in which the m-th bit digital video signal is written to the pixel is shorter than the length of the display period Trm. Therefore, the value of the bit number m is such that the writing period Tam is the display period T among 1 to n.
The value must be shorter than the length of rm.

The display periods Tr1 to Trn may appear in any order. For example, during one frame period, the display periods can appear in the order of Tr1, Tr5, Tr2,... Next to Tr1. However, the order in which the display periods Tr1 to Trn do not overlap each other is more preferable. Further, it is more preferable that the erasing periods Te1 to Ten are not overlapped with each other.

According to the present invention, the EL driving T
Even if there is some variation in the I _DS -V _GS characteristics of the FT, it is possible to avoid a situation in which the light emission amount of the EL element greatly differs between adjacent pixels when a signal of the same voltage is input.

In the present invention, a non-display period in which no display is performed can be provided. In the case of the conventional analog drive, when an all-white image is displayed on the EL display, the EL element always emits light, which causes deterioration of the EL layer earlier. According to the present invention, since a non-display period can be provided, deterioration of the EL layer can be suppressed to some extent.

In the present invention, the display period and the writing period partially overlap. In other words, the pixels can be displayed even in the writing period. Therefore, the ratio (duty ratio) of the total length of the display periods in one frame period is not determined only by the length of the writing period.

In the structure of the present invention, the transistor provided in each pixel is replaced with a switching TFT as in the prior art.
And the EL driving TFT, the aperture ratio of the pixel is not reduced.

In this embodiment mode, the EL driving TFT is used.
Although a capacitor is provided to hold the voltage applied to the gate electrode, the capacitor may be omitted. When the EL driving TFT has an LDD region provided so as to overlap the gate electrode via the gate insulating film, a parasitic capacitance generally called a gate capacitance is formed in the overlapping region. This gate capacitance may be positively used as a capacitor for holding a voltage applied to the gate electrode of the EL driving TFT.

Since the capacitance value of the gate capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

The above-described structure of the present invention is not limited to application to an EL display, but can be applied to an apparatus using another electro-optical element. Further, when a liquid crystal that responds at a high speed with a response time of about several tens of microseconds or less has been developed, it can be applied to a liquid crystal display.

[0096]

Embodiments of the present invention will be described below.

Example 1 In this example, the EL of the present invention was used.
The case where a display of ²⁶ gradations is performed on a display using a 6-bit digital video signal will be described with reference to FIG. The EL display according to the present embodiment is shown in FIGS.
It has the structure shown in FIG.

First, the opposing potential applied to the opposing power supply line E1 by the opposing electrode power supply line driving circuit 104 is
To the extent that the EL element emits light when the power supply potential is applied to the pixel electrode, it is maintained at a potential (ON counter potential) having a potential difference from the power supply potential.

Then, the gate signal line G1 is selected by the gate signal input from the gate signal line driving circuit 103 to the gate signal line G1. And the gate signal line G1
, The switching TFTs 107 of all the pixels (pixels on the first line) connected to are turned on.

Then, the first bit digital video signal is input from the source signal line drive circuit 102 to the source signal lines S1 to Sx. The digital video signal is input to the gate electrode of the EL driving TFT 108 via the switching TFT 107.

In this embodiment, when the digital video signal has information of “0”, the EL driving TFT 10
8 turns off. Therefore, no power supply potential is applied to the pixel electrode of the EL element 110. As a result, the EL element 110 included in the pixel to which the digital video signal having the information “0” is input does not emit light.

Conversely, when the digital video signal has information of “1”, the EL driving TFT 108 is turned on. Therefore, a power supply potential is applied to the pixel electrode of the EL element 110. As a result, the EL element 11 included in the pixel to which the digital video signal having the information “1” is input is provided.
0 emits light.

As described above, in the pixels on the first line, at the same time when the digital video signal is input, the EL element 110 emits light or does not emit light, and the display period Tr1 is established. The timing at which the display period of each line is started has a time difference.

Next, when the selection of the gate signal line G1 is completed, the opposing power supply line E1 is maintained by the opposing power supply line driving circuit 104 while the opposing power supply line E1 is kept at the ON opposing potential.
2 is kept at the ON counter potential. When the gate signal line G2 is selected by the gate signal, the switching TFTs 107 of all the pixels connected to the gate signal line G2 are turned on, and the source signal lines S1 to Sx are connected to the pixels on the second line. , A first bit digital video signal is input.

In this manner, all the opposing power supply lines E1 to E1
Ex is kept at the opposite potential. Then, all the gate signal lines G1 to Gy are selected, and the first bit digital video signal is input to all the pixels. The period until the digital video signal of the first bit is input to all the pixels is the writing period Ta1.

On the other hand, before the digital video signal of the first bit is input to all the pixels, in other words, before the end of the writing period Ta1, in parallel with the input of the digital video signal of the first bit to the pixels, Counter power line drive circuit 10
4 keeps the opposing potential applied to the opposing power supply line E1 at the same level as the power supply potential (the off opposing potential). Then, all the EL elements whose counter electrodes are connected to the counter power supply line E1 are in a non-light emitting state. Therefore, all the pixels (pixels on the first line) having the EL element whose counter electrode is connected to the counter power supply line E1 do not perform display.

A period during which the pixel does not perform display is defined as a non-display period T
Called d. In the pixels on the first line, the opposite power line E1
Is maintained at the off counter potential, and at the same time, the display period Tr1 ends, and the non-display period Td1 starts. Like the display period,
The timing at which the non-display period of each line is started has a time difference.

Then, while the opposing power supply line E1 is kept at the off-facing potential, the opposing power supply line E2 is kept at the off-facing potential. Therefore, all pixels (pixels on the second line) having an EL element whose counter electrode is connected to the counter power supply line E2
Is in a non-display state in which no display is performed.

Then, in turn, all the opposing power supply lines are kept at the off opposing potential. An erasing period Te1 is a period in which all of the opposing power supply lines E1 to Ey are kept at the opposing potential of OFF and all the pixels that have been displaying by the first bit digital signal are in a non-display state.

On the other hand, before all the opposing power supply lines E1 to Ey are kept at the off opposing potential, in other words, the erasing period Te1
Before the operation is completed, the opposing power supply line E1 is again kept at the ON opposing potential in parallel with the pixel being in the non-display state.
Then, the gate signal line G1 is selected by the gate signal, and the digital video signal of the second bit is input to the pixels of the first line. As a result, the pixels on the first line perform display again, so that the non-display period Td1 ends and the display period Td1 ends.
r2.

Then, similarly, all the opposing power supply lines are sequentially kept at the ON opposing potential. Then, all the gate signal lines are sequentially selected, and the digital video signal of the second bit is input to all the pixels. A period until the input of the second bit digital video signal to all the pixels is called a writing period Ta2.

On the other hand, before the digital video signal of the second bit is input to all the pixels, in other words, before the end of the writing period Ta2, the digital video signal of the second bit is input to the pixels in parallel. , The opposing power supply line E1 is kept at the opposing potential that is off. Accordingly, the EL elements of the pixels on the first line are all in a non-light emitting state, and the pixels on the first line do not perform display. Accordingly, the display period Tr2 ends in the pixels on the first line, and the non-display period Td2 is set.

Then, in turn, all the opposing power supply lines are kept at the off opposing potential. An erasing period Te2 is a period from when all the opposing power supply lines E1 to Ey are kept at the opposing electric potential in the off state, and until all the pixels that have been displaying with the digital signal of the second bit enter the non-display state.

The above-described operation is repeatedly performed until the fifth-bit digital video signal is input to the pixel. The display period Tr1 of the pixel of each line is turned on to the opposing electrode of the pixel of each line in the writing period Ta1. This is a period from when the potential is applied and the digital video signal is written to the pixels in each line to when an off counter potential is applied to the counter electrode of the pixel in each line in the erasing period Te1. In the non-display period Td1 of the pixels in each line, the line is turned off in the next writing period (in this case, the writing period Ta2) after the off counter potential is applied to the counter electrode of the pixel in each line in the erasing period Te1. This is a period from when an on-potential is applied to the opposing electrode of the pixel and a digital video signal is written to the pixel on each line. The display periods Tr2, Tr3, Tr4 and the non-display periods Td2, Td3, Td4 have their respective periods determined similarly to the display period Tr1 and the non-display period Td1.

Next, the opposing power supply line E1 is kept at the ON opposing potential, and the digital video signal of the fifth bit is input to the pixels of the first line. Therefore, the pixels on the first line are in the display period Tr5 and display is performed. Then, the digital video signal of the fifth bit is held in the pixel until the digital video signal of the next bit is input. Then, similarly, all the opposing power supply lines are maintained at the opposing electric potential of ON. And 5
The digital video signal of the bit is input to the pixels of all the lines, and the pixels of all the lines enter the display period Tr5 to perform display.

Next, when the digital video signal of the sixth bit is input to the pixels of the first line while all the opposite power supply lines are kept at the on-potential, the fifth bit held in the pixels Is rewritten into a 6-bit digital video signal. Then, the pixels on the first line are in the display period Tr6, and display is performed. The 6-bit digital video signal is held in the pixel until the 1-bit digital video signal in the next frame period is input again. Similarly, the digital video signal of the sixth bit is sequentially input to the pixels of all the lines, and the pixels of all the lines enter the display period Tr6 to perform display.

When the digital video signal of the first bit in the next frame period is input to the pixel again, the display period Tr6
Ends, and the frame period ends at the same time. When all display periods (Tr1 to Tr6) end, the frame period ends and one image can be displayed. The above operation is repeated also in the next frame period.

The display period Tr5 of the pixels in each line is a writing period that appears after the ON voltage is applied to the counter electrode of the pixels in each line and the digital video signal is written into the pixels of each line. In this case (write period Ta6), this is a period from when an ON counter potential is applied to the counter electrode of the pixel in each line and a digital video signal is written in the pixel in each line. In the display period Tr6 of the pixels in each line, the ON period is applied to the opposing electrodes of the pixels in each line, and the digital video signal is written in the pixels in each line. The case is a period from the writing period Ta1) of the next frame period until the ON counter potential is applied to the counter electrode of the pixel of each line and the digital video signal is written to the pixel of each line.

The length of the display period Tr is Tr1: Tr2:
…: Tr5: Tr6 = 2 ⁰ : 2 ¹ :…: 2 ⁴ : 2 ⁵ A desired gradation display among the ²⁶ gradations can be performed by the combination of the display periods.

By calculating the sum of the lengths of the display periods in which the EL element emits light during one frame period, the displayed gradation of the pixel in the frame period is determined. Assuming that the luminance when the pixel emits light in all display periods is 100%, the luminance of 5% can be expressed when the pixel emits light in Tr1 and Tr2, and the luminance of 32% when Tr3 and Tr5 are selected. Can be expressed.

In this embodiment, a write period Ta5 in which the digital video signal of the fifth bit is written to the pixel
Is shorter than the length of the display period Tr5.

The display periods (Tr1 to Tr6) may appear in any order. For example, during one frame period, Tr1, Tr5, Tr2,.
It is also possible to make the display periods appear in this order.
However, the order in which the erasing periods (Te1 to Te6) do not overlap each other is more preferable. The display period (Tr1 to T
The order in which r6) does not overlap with each other is more preferable.

According to the present invention, with the above-described structure, even if the I _DS -V _GS characteristics are slightly varied depending on the TFT, the light emission amount of the EL element greatly differs between adjacent pixels when a signal of the same voltage is input. Things can be avoided.

In the present invention, a non-display period in which no display is performed can be provided. In the case of the conventional analog drive, when an all-white image is displayed on the EL display, the EL element always emits light, which causes deterioration of the EL layer earlier. According to the present invention, since a non-display period can be provided, deterioration of the EL layer can be suppressed to some extent.

(Embodiment 2) In this embodiment, the order in which the display periods Tr1 to Tr6 appear in the driving method of the present invention corresponding to a 6-bit digital video signal will be described.

FIG. 6 is a timing chart showing the driving method of this embodiment. A detailed driving method of the pixel may be referred to in the first embodiment, and thus the description is omitted here. In the driving method of this embodiment, the longest non-display period (Td1 in this embodiment) in one frame period is provided at the end of one frame period. With the above configuration, the non-display period Td1
The first display period of the next frame period (in this embodiment, Tr
4) It appears to the human eye that there is a break in the frame period. This makes it possible to make it difficult for human eyes to recognize display unevenness caused by adjacent display periods that emit light between adjacent frame periods when displaying an intermediate gradation.

Although the present embodiment has been described with reference to a case of a 6-bit digital video signal, the present invention is not limited to this. This embodiment can be implemented without being limited to the number of bits of the digital video signal.

(Embodiment 3) In this embodiment, the EL of the present invention is used.
In the display, it will be described with reference to FIG. 7, the case of displaying the 2 ⁴ gradations by 4 bit digital video signal. The EL display according to the present embodiment is shown in FIGS.
It has the structure shown in FIG.

First, the opposing potential applied to the opposing power supply line E1 by the opposing electrode power supply line driving circuit 104 is
To the extent that the EL element emits light when the power supply potential is applied to the pixel electrode, it is maintained at a potential (ON counter potential) having a potential difference from the power supply potential.

The gate signal line G1 is selected by a gate signal input from the gate signal line driving circuit 103 to the gate signal line G1. Therefore, the gate signal line G1
, The switching TFTs 107 of all the pixels (pixels on the first line) connected to are turned on.

At the same time, the source signal line driving circuit 10
2, the first bit digital video signal is input to the source signal lines S1 to Sx. The digital video signal is supplied to the EL driving TFT 10 through the switching TFT 107.
8 is input to the gate electrode.

In this embodiment, when the digital video signal has information of “0”, the EL driving TFT 10
8 turns off. Therefore, no power supply potential is applied to the pixel electrode of the EL element 110. As a result, the EL element 110 included in the pixel to which the digital video signal having the information “0” is input does not emit light.

Conversely, when the digital video signal has the information of “1”, the EL driving TFT 108 is turned on. Accordingly, a power supply potential is applied to the pixel electrode of the EL element 110. As a result, the EL element 110 included in the pixel to which the digital video signal having the information of “1” is input is provided.
Emits light.

In this embodiment, when the digital video signal has information of “0”, the EL driving TFT 10
Reference numeral 8 denotes an off state, and when the information has information "1", the EL driving TFT 108 is turned on. However, the present invention is not limited to this configuration. If the digital video signal has information of “0”, the EL driving TFT 10
8 may be turned on and the EL driving TFT 108 may be turned off when the information has the information “1”.

As described above, the pixels on the first line emit light or do not emit light at the same time as the input of the digital video signal, and the pixels on the first line perform display. A period during which the pixel performs display is called a display period Tr. The timing at which the display period of each line is started has a time difference.

Next, when the selection of the gate signal line G1 is completed, the opposing power supply line E1 is maintained by the opposing power supply line driving circuit 104 while the opposing power supply line E1 is kept at the ON opposing potential.
2 is kept at the ON counter potential. When the gate signal line G2 is selected by the gate signal, the switching TFTs 107 of all the pixels connected to the gate signal line G2 are turned on, and the source signal lines S1 to Sx are connected to the pixels on the second line. , A first bit digital video signal is input.

In this manner, all the opposite power supply lines E1 to E1
Ex is kept at the opposite potential. Then, all the gate signal lines G1 to Gy are selected, and the first bit digital video signal is input to all the pixels. The period until the digital video signal of the first bit is input to all the pixels is the writing period Ta1.

On the other hand, before the digital video signal of the first bit is input to all the pixels, in other words, before the end of the writing period Ta1, in parallel with the input of the digital video signal of the first bit to the pixels, Counter power line drive circuit 10
4 keeps the opposing potential applied to the opposing power supply line E1 at the same level as the power supply potential (the off opposing potential). Then, all the EL elements whose counter electrodes are connected to the counter power supply line E1 are in a non-light emitting state. Therefore, all the pixels (pixels on the first line) having the EL element whose counter electrode is connected to the counter power supply line E1 do not perform display.

A period during which the pixel does not perform display is referred to as a non-display period T.
Called d. In the pixels on the first line, the opposite power line E1
Is maintained at the off counter potential, and at the same time, the display period Tr1 ends, and the non-display period Td1 starts. Like the display period,
The timing at which the non-display period of each line is started has a time difference.

Then, while the opposing power supply line E1 is kept at the off-facing potential, the opposing power supply line E2 is kept at the off-facing potential. Therefore, all pixels (pixels on the second line) having an EL element whose counter electrode is connected to the counter power supply line E2
Is in a non-display state in which no display is performed.

Then, in turn, all the opposing power supply lines are kept at the off opposing potential. An erasing period Te1 is a period in which all of the opposing power supply lines E1 to Ey are kept at the opposing potential of OFF and all the pixels that have been displaying by the first bit digital signal are in a non-display state.

On the other hand, before all the opposing power supply lines E1 to Ey are kept at the off opposing potential, in other words, the erasing period Te1
Before the operation is completed, the opposing power supply line E1 is again kept at the ON opposing potential in parallel with the pixel being in the non-display state.
Then, the gate signal line G1 is selected by the gate signal, and the digital video signal of the second bit is input to the pixels of the first line. As a result, the pixels on the first line perform display again, so that the non-display period Td1 ends and the display period Td1 ends.
r2.

Then, similarly, all the opposing power supply lines are sequentially kept at the ON opposing potential. Then, all the gate signal lines are sequentially selected, and the digital video signal of the second bit is input to all the pixels. A period until the input of the second bit digital video signal to all the pixels is called a writing period Ta2.

On the other hand, before the second bit digital video signal is input to all the pixels, in other words, before the writing period Ta2 ends, in parallel with the input of the second bit digital video signal to the pixels. , The opposing power supply line E1 is kept at the opposing potential that is off. Accordingly, the EL elements of the pixels on the first line are all in a non-light emitting state, and the pixels on the first line do not perform display. Accordingly, the display period Tr2 ends in the pixels on the first line, and the non-display period Td2 is set.

Then, in turn, all the opposing power supply lines are kept at the off opposing potential. An erasing period Te2 is a period from when all the opposing power supply lines E1 to Ey are kept at the opposing electric potential in the off state, and until all the pixels that have been displaying with the digital signal of the second bit enter the non-display state.

In the display period Tr1 of the pixels in each line, the erasing period Te1 is performed after the ON potential is applied to the counter electrode of the pixels in each line in the writing period Ta1 and the digital video signal is written to the pixels in each line. Is a period until an off counter potential is applied to the counter electrode of the pixel in each line. In the non-display period Td1 of the pixels in each line, the line is turned off in the next writing period (in this case, the writing period Ta2) after the off counter potential is applied to the counter electrode of the pixel in each line in the erasing period Te1. This is a period from when an on-potential is applied to the opposing electrode of the pixel and a digital video signal is written to the pixel on each line. And the display period Tr2 of each line
And the non-display period Td2, the display period Tr1 and the non-display period T
Each period is determined similarly to d1.

Next, when the opposing power supply line E1 is kept at the ON opposing potential and the digital video signal of the third bit is input to the pixels of the first line, the pixels of the first line are displayed in the display period T.
r3 is displayed. Then, similarly, all the opposing power supply lines are maintained at the opposing electric potential of ON. Then, the digital video signal of the third bit is input to the pixels of all the lines, and the pixels of all the lines enter the display period Tr3 to perform display. Then, the digital video signal of the third bit is held in the pixel until the digital video signal of the next bit is input.

Next, when the digital video signal of the fourth bit is input to the pixels of the first line while all of the opposing power supply lines are kept at the on-potential, the 3
The bit digital video signal is rewritten to a fourth bit digital video signal. Then, the pixels on the first line are in the display period Tr4, and display is performed. Similarly, the digital video signal of the fourth bit is input to the pixels of all the lines while all the opposing power lines are kept at the on-potential in the same manner, and the pixels of all the lines are displayed during the display period Tr.
4 is displayed. The fourth bit digital video signal is held in the pixel until the first bit digital video signal in the next frame period is input again.

When the digital video signal of the first bit in the next frame period is input to the pixel again, the display period Tr4
Ends, and the frame period ends at the same time. When all the display periods (Tr1 to Tr4) end, one image can be displayed. Then, the above operation is repeated also in the next frame period.

The display period Tr3 for the pixels in each line is a writing period that appears after the digital video signal is written in the pixels in each line by applying the ON counter potential to the counter electrode of the pixels in each line. In this case (write period Ta4), this is a period from when an ON counter potential is applied to the counter electrode of the pixel in each line and a digital video signal is written in the pixel in each line. In the display period Tr4 of the pixels in each line, the ON period is applied to the opposing electrodes of the pixels in each line, and the digital video signal is written in the pixels in each line. The case is a period from the writing period Ta1) of the next frame period until the ON counter potential is applied to the counter electrode of the pixel of each line and the digital video signal is written to the pixel of each line.

The length of the display period Tr is Tr1: Tr2:
It is set so that Tr3: Tr4 = 2 ⁰ : 2 ¹ : 2 ² : 2 ³ . It can perform a desired gradation display among 2 ⁴ gradations by a combination of the display periods.

By calculating the sum of the lengths of the display periods in which the EL element emits light during one frame period, the displayed gradation of the pixel in the frame period is determined. Assuming that the luminance when the pixel emits light in all display periods is 100%, 20% luminance can be expressed when the pixel emits light in Tr1 and Tr2, and 27% luminance is expressed when only Tr3 is selected. it can.

In this embodiment, a write period Ta3 in which the digital video signal of the third bit is written to the pixel
Is shorter than the length of the display period Tr3.

The display periods (Tr1 to Tr4) may appear in any order. For example, during one frame period, a display period can appear in the order of Tr1, Tr4, and Tr2 next to Tr1. However, the order in which the erasing periods (Te1 to Te4) do not overlap each other is more preferable. In addition, the display period (Tr1 to Tr
It is more preferable that the order of 4) does not overlap with each other.

According to the present invention, with the above structure, even if the I _DS -V _GS characteristics are slightly varied depending on the TFT, even if a signal of the same voltage is input, the light emission amount of the EL element is greatly different between adjacent pixels. Things can be avoided.

In the present invention, a non-display period in which no display is performed can be provided. In the case of the conventional analog drive, when an all-white image is displayed on the EL display, the EL element always emits light, which causes deterioration of the EL layer earlier. According to the present invention, since a non-display period can be provided, deterioration of the EL layer can be suppressed to some extent.

Note that this embodiment can be implemented in combination with the second embodiment.

Embodiment 4 In this embodiment, a top view (FIG. 8) of the pixel of the EL display of the present invention shown in FIG. 3 will be described. FIGS. 3 and 8 use the same reference numerals and may be referred to each other.

In FIG. 8A, the pixel 105 has a switching TFT 107 and an EL driving TFT.

The switching TFT 107 includes the active layer 1.
07a and a gate electrode 107b which is a part of the gate signal line (G). The EL driving TFT 108 includes:
It has an active layer 108a and a gate electrode 108b which is a part of the gate wiring 121.

Active layer 10 of switching TFT 107
One of the source region and the drain region 7a has a source signal line (S), and the other has a connection wiring 113.
Is connected to the gate wiring 121 through the gate. Note that the connection wiring 113 is called a source wiring or a drain wiring depending on the potential of a signal input to the source signal line (S).

Active layer 108a of EL driving TFT 108
Are connected to a power supply line (V) and a drain wiring 114, respectively. The drain wiring 114 is connected to the pixel electrode 117.

The capacitance wiring 116 is formed of a semiconductor film. The capacitor 112 is formed between the capacitor wiring 116 electrically connected to the power supply line (V), an insulating film (not shown) in the same layer as the gate insulating film, and the gate wiring 121. Further, a capacitor formed by the gate wiring 121, the same layer (not shown) as the first interlayer insulating film, and the power supply line (V) can also be used as a capacitor.

Note that a bank provided with an opening 131 is formed on the pixel electrode 117 by etching the organic resin film (FIG. 8B). Although not shown, an EL layer and a counter power supply line (E) including a counter electrode are sequentially stacked on the pixel electrode 117. The pixel electrode 105 and the EL layer are in contact at the opening 131 of the bank, and the EL layer emits light only at a portion sandwiched between the opposing power supply line (E) and the pixel electrode.

The source signal line (S) and the power supply line (V)
And a region 105 having one gate signal line (G) and one counter power supply line (E) is a pixel.

Note that the top view of the pixel portion of the EL display of the present invention is not limited to the structure shown in FIG.

This embodiment can be implemented in combination with the first to third embodiments.

(Embodiment 5) In this embodiment, the detailed structure of the driving circuit of the EL display of the present invention shown in FIG. 1 will be described with reference to FIG.

The source signal line driving circuit 102 basically includes a shift register 102a, a latch (A) (first latch)
102b, and a latch (B) (second latch) 102c.

In the source signal line driving circuit 102, a clock signal (CLK) and a start pulse (SP) are input to the shift register 102a. The shift register 102a sequentially generates a timing signal based on the clock signal (CLK) and the start pulse (SP) and inputs the timing signal to the latch (A) 102b.

Although not shown in FIG. 9, the timing signal output from shift register 102a is buffer-amplified by a buffer or the like (not shown) and then input to latch (A) 102b, which is a subsequent circuit. May be. The wiring to which the timing signal is supplied has a large load capacitance (parasitic capacitance) because many circuits or elements are connected. This buffer is provided to prevent "dulling" of the rise or fall of the timing signal caused by the large load capacitance.

The latch (A) 102b has a plurality of stages of latches for processing n-bit digital video signals. When the timing signal is input, the latch (A) 102b sequentially captures and holds an n-bit digital video signal input from outside the source signal line driving circuit 102.

When a digital video signal is taken into the latch (A) 102b, the digital video signal may be sequentially input to a plurality of stages of latches of the latch (A) 102b. However, the present invention is not limited to this configuration. The latches of the plurality of stages included in the latch (A) 102b may be divided into several groups, and a so-called divided drive in which digital video signals are input simultaneously in parallel for each group may be performed. The number of groups at this time is called a division number. For example, when the latch is divided into groups for every four stages, it is referred to as divided drive in four divisions.

The time until the writing of the digital video signal to the latches of all the stages of the latch (A) 102b is completed is called a line period. That is, a time interval from the time when the writing of the digital video signal to the latch of the leftmost stage in the latch (A) 102b starts to the time when the writing of the digital video signal to the latch of the rightmost stage ends. Is a line period.
Actually, the line period may include a period obtained by adding the horizontal retrace period to the line period.

When one line period ends, the latch (B)
A latch signal (LatchSignal) is supplied to 102c. At this moment, the digital video signal written and held in the latch (A) 102b is
c, and is written to and held by the latches of all the stages of the latch (B) 102c.

The digital video signal is latched (B) 102
The digital video signal input from the outside of the source signal line driving circuit 102 is sequentially written into the latch (A) 102b which has finished sending the data to c, based on the timing signal from the shift register 102a.

During the second one line period, the digital video signal written and held in the latch (B) 102c is input to the source signal line.

On the other hand, the gate signal line driving circuit 103 has a shift register 103a and a buffer 103b. In some cases, a level shift may be provided in addition to the shift register 103a and the buffer 103b.

The opposing power supply line driving circuit 104 has a shift register 104a and a buffer 104b. In some cases, the shift register 104a and the buffer 10
A level shift may be provided in addition to 4b.

In the gate signal line driving circuit 103 and the counter power supply line driving circuit 104, the shift register 103a,
The timing signal from 104a is buffered (not shown)
And supplied to the corresponding gate signal line and counter power line, respectively.

A gate signal line has a pixel TF for one line.
Since the gate electrode of T is connected and all the pixel TFTs for one line must be turned on at the same time, a buffer 103b capable of flowing a large current is used. Further, the counter power supply line includes a counter electrode included in a pixel for one line, and an on counter potential or an off counter potential must be simultaneously applied to all counter electrodes for one line. The one capable of flowing a large current is used.

This embodiment can be implemented in combination with the first to fourth embodiments.

(Embodiment 6) In this embodiment, the EL of the present invention will be described.
A method for simultaneously manufacturing TFTs of a pixel portion of a display and a driver circuit portion (a source signal line driver circuit, a gate signal line driver circuit, and a counter power line driver circuit) provided therearound will be described. However, for the sake of simplicity, a CMOS circuit, which is a basic unit for the drive circuit, is illustrated.

First, as shown in FIG. 10A, a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass is oxidized. A base film 5002 made of an insulating film such as a silicon film, a silicon nitride film, or a silicon oxynitride film is formed.
For example, a plasma CVD method SiH _4, NH _3, N ₂ silicon oxynitride film 5002a made from O 10 to 2
00 [nm] (preferably 50 to 100 [nm]) is formed, similarly SiH _4, N ₂ O hydrogenated silicon oxynitride film 5002b made from 50 to 200 [nm] (preferably 100
１５０150 [nm]). Although the base film 5002 has a two-layer structure in this embodiment, the base film 5002 may have a single-layer structure or a structure in which two or more insulating films are stacked.

Each of the island-shaped semiconductor layers 5003 to 5006 is formed of a crystalline semiconductor film formed by using a semiconductor film having an amorphous structure by a laser crystallization method or a known thermal crystallization method.
The thickness of the island-shaped semiconductor layers 5003 to 5006 is 25 to 8
It is formed with a thickness of 0 [nm] (preferably 30 to 60 [nm]). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 [Hz], and the laser energy density is set to 100 to 400 [mJ / cm ² ] (typically, 200 to 300 [mJ / cm ² ]). When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 30 to 300 [kHz], and the laser energy density is set to 300 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ / cm ² ]).
[mJ / cm ² ]). And a width of 100 to 1000 [μ
m], for example, a laser beam condensed linearly at 400 [μm] is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is 80 to 80 in the case of an excimer laser. 98%, 50-90 for YAG laser
Perform as%.

Next, island-like semiconductor layers 5003 to 5006
Is formed to cover the gate insulating film 5007. Gate insulating film
5007 uses a plasma CVD method or a sputtering method,
With an insulating film containing silicon with a thickness of 40 to 150 [nm]
Form. In this embodiment, oxynitridation is performed at a thickness of 120 [nm].
It is formed of a silicon film. Of course, the gate insulating film 5007
It is not limited to such a silicon oxynitride film.
In addition, other insulating films containing silicon can be
You may use it. For example, when using a silicon oxide film
In this case, TEOS (Tetraethyl Ort
hosilicate) and O _TwoAnd a reaction pressure of 40 [Pa]
A plate temperature of 300 to 400 [° C] and a high frequency (13.56 [M
Hz]), power density 0.5-0.8 [W / cm^Two] To discharge
Can be achieved. The oxide silicon thus produced is
The recon film is then subjected to thermal annealing at 400 to 500 [° C].
Good characteristics can be obtained as a gate insulating film
You.

[0188] Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed of Ta to a thickness of 50 to 100 [nm],
A second conductive film 5009 is formed with W to a thickness of 100 to 300 [nm].

The Ta film is formed by a sputtering method by sputtering a Ta target with Ar. in this case,
When an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. Also, α
The phase Ta film has a resistivity of about 20 [μΩcm] and can be used as a gate electrode, but the β-phase Ta film has a resistivity of about 180 [μΩcm] and is not suitable for a gate electrode. . In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to the Ta α-phase is formed on a Ta base with a thickness of about 10 to 50 [nm]. Can be easily obtained.

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
[μΩcm] or less is desirable. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, the crystallization is inhibited and the resistance is increased. From this, when the sputtering method is used, the purity is 99.9999% or 99.99%.
A resistivity of 9 to 20 [μΩcm] can be realized by using a W target of [%] and forming a W film with sufficient care so as not to mix impurities from the gas phase during film formation. it can.

In this embodiment, the first conductive film 500
8 was Ta, and the second conductive film 5009 was W. However, there is no particular limitation, and any of Ta, W, Ti, Mo, Al, and Cu was used.
Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Another example of the combination other than the present embodiment is that the first conductive film is formed of tantalum nitride (T
aN), and the second conductive film is made of W,
Forming a first conductive film of tantalum nitride (TaN);
Preferably, the first conductive film is formed of tantalum nitride (TaN), and the second conductive film is formed of Cu.

Next, a mask 5010 made of a resist is formed, and a first etching process for forming electrodes and wirings is performed. In this embodiment, ICP (Inductively Coupled)
d Plasma: Inductively coupled plasma) etching method,
CF ₄ and Cl ₂ are mixed as an etching gas, and RF (13.56 [MH]) of 500 [W] is applied to the coil-type electrode at a pressure of 1 [Pa].
z]) Power is supplied to generate plasma. 100 [W] RF (13.56 [MH] also on the substrate side (sample stage)
z]) Apply power and apply a substantially negative self-bias voltage. When CF ₄ and Cl ₂ are mixed, the W film and Ta
The film is etched to the same extent.

[0193] Under the above etching conditions, the shape of the resist mask is made appropriate, so that the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 [nm] by over-etching. become. Thus, by the first etching process, the first conductive layer and the second conductive layer
Conductive layers 5011 to 5016 (first conductive layer 50
11a to 5016a and second conductive layers 5011b to 501
6b) is formed. At this time, in the gate insulating film 5007, a region which is not covered with the first shape conductive layers 5011 to 5016 is etched to a thickness of about 20 to 50 [nm] to form a thinned region. (FIG. 10A)

Then, a first doping process is performed to add an impurity element imparting n-type. (FIG. 10B) The doping method may be an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 ×
10 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and acceleration voltage of 60
It is performed as １００100 [keV]. An element belonging to Group XV, typically phosphorus (P) or arsenic (As) is used as the n-type impurity element. Here, phosphorus (P) is used. In this case, the conductive layers 5011 to 5015 serve as a mask for the impurity element imparting n-type, and the first impurity regions 5017 to 5025 are formed in a self-aligned manner. First
1 × 10 ²⁰ to 1 ×
An impurity element for imparting n-type is added within a concentration range of 10 ²¹ [atoms / cm ³ ].

Next, as shown in FIG. 10C, a second etching process is performed without removing the resist mask. Using CF ₄ , Cl ₂ and O _{2 as an} etching gas,
The film is selectively etched. At this time, the second shape conductive layers 5026 to 5031 are formed by the second etching process.
(First conductive layers 5026a to 5031a and second conductive layers 5026b to 5031b) are formed. At this time, in the gate insulating film 5007, the second shape conductive layer 50 is formed.
The area not covered by 26 to 5031 is further 20 to 50 [n
m] to form a thinned region.

The etching reaction of the W film or the Ta film by the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ionic species and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, the dose is lower than that of the first doping process, and n is set as a condition of a high acceleration voltage.
Doping with an impurity element for giving a mold. For example, the acceleration voltage is set to 70 to 120 [keV], and 1 × 10 ¹³ [atoms / cm]
² ], a new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. Doping is performed in the second shape conductive layer 5026.
To 5030 are used as masks for the impurity elements, and doping is performed so that the impurity elements are also added to regions below the first conductive layers 5026a to 5030a. Thus, third impurity regions 5032 to 5036 are formed. The concentration of phosphorus (P) added to third impurity regions 5032 to 5036 depends on that of first conductive layers 5026 a to 5026 a to 5 a.
030a has a gentle concentration gradient according to the thickness of the tapered portion. Note that the first conductive layers 5026a to 503
In the semiconductor layer overlapping the tapered portion of Oa, the impurity concentration is slightly reduced from the end of the tapered portion of the first conductive layers 5026a to 5030a toward the inside, but is substantially the same.

A third etching process is performed as shown in FIG. This is performed using a reactive ion etching method (RIE method) using CHF ₆ as an etching gas. Third
Of the first conductive layers 5026a to 5026a-5
031a is partially etched to form the first portion.
The region where the conductive layer overlaps with the semiconductor layer is reduced. By the third etching treatment, the third shape conductive layer 5037 is formed.
To 5042 (first conductive layers 5037a to 5041a and second conductive layers 5037b to 5042b). At this time, in the gate insulating film 5007, a region that is not covered with the third shape conductive layers 5037 to 5042 is two more.
A region that is etched and thinned by about 0 to 50 [nm] is formed.

By the third etching process, third impurity regions 5032a to 5036a overlapping with first conductive layers 5037a to 5041a and a second impurity region between the first impurity region and the third impurity region are formed. 5032b-50
36b.

Then, as shown in FIG. 11C, island-shaped semiconductor layers 5004 to 504 forming p-channel TFTs are formed.
In 06, fourth impurity regions 5052 to 5074 having a conductivity type opposite to the first conductivity type are formed. Second conductive layer 5038
Using b to 5041b as a mask for the impurity element, an impurity region is formed in a self-aligned manner. At this time, n
The entire surface of the island-shaped semiconductor layer 5003 and the wiring portion 5031 forming the channel type TFT is covered with a resist mask 5200. Phosphorus is added at a different concentration to each of the impurity regions 5052 to 5074, but diborane (B
₂ H ₆ ) and an impurity concentration of 2 × 10 ²⁰ to 2 × 10 ²¹ [a
toms / cm ³ ].

Through the above steps, impurity regions are formed in the respective island-like semiconductor layers. Third overlapping with the island-shaped semiconductor layer
The conductive layers 5037 to 5041 each having the shape described above function as gate electrodes. 5042 functions as an island-shaped source signal line.

After removing the resist mask 5200, a step of activating the impurity elements added to the respective island-shaped semiconductor layers is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace.
In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 400 to 700 in a nitrogen atmosphere of 1 [ppm] or less, preferably 0.1 [ppm] or less.
In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours.
However, when the wiring material used for the third shape conductive layers 5037 to 5042 is weak to heat, activation is performed after an interlayer insulating film (mainly containing silicon) is formed to protect the wiring and the like. It is preferred to do so.

Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, as shown in FIG.
Of the interlayer insulating film 5075 from the silicon oxynitride film to 100
It is formed with a thickness of about 200 [nm]. After a second interlayer insulating film 5076 made of an organic insulating material is formed thereon, a first interlayer insulating film 5075, a second interlayer insulating film 5076,
And a contact hole is formed in the gate insulating film 5007, and each wiring (including a connection wiring and a signal line) 5077 is formed.
After patterning and forming the patterns 5082 and 5084, the pixel electrode 5083 in contact with the connection wiring 5082 is formed by patterning.

As the second interlayer insulating film 5076, a film made of an organic resin is used, and as the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 5076 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, an acrylic film is formed with a thickness that can sufficiently flatten a step formed by a TFT. Preferably, it is 1 to 5 [μm] (more preferably, 2 to 4 [μm]).

The contact holes are formed by dry etching or wet etching to form n-type impurity regions 5017 and 5018 or p-type impurity regions 5052.
A contact hole reaching to 5074, a contact hole reaching the wiring 5031, a contact hole (not shown) reaching the power supply line, and a contact hole (not shown) reaching the gate electrode are formed.

In addition, wiring (including connection wiring and signal line) 5
077 to 5082 and 5084, the Ti film is 100 [n
m], an aluminum film containing Ti is 300 [nm], and a Ti film 1
A laminate film having a three-layer structure in which 50 nm is continuously formed by a sputtering method and patterned into a desired shape is used. Of course,
Other conductive films may be used.

In this embodiment, an ITO film having a thickness of 110 [nm] was formed as the pixel electrode 5083, and was patterned. A contact is made by arranging the pixel electrode 5083 so as to be in contact with and overlap with the connection wiring 5082. Alternatively, a transparent conductive film in which 2 to 20% of zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 5083 becomes an anode of the EL element. (FIG. 12
(A))

Next, as shown in FIG. 12B, an insulating film containing silicon (a silicon oxide film in this embodiment) having a thickness of 500 nm is formed at a position corresponding to the pixel electrode 5083. An opening is formed, and a third interlayer insulating film 5085 functioning as a bank is formed. When the opening is formed, a tapered side wall can be easily formed by using a wet etching method. If the side wall of the opening is not sufficiently gentle, the deterioration of the EL layer due to the step becomes a significant problem.

Next, the EL layer 5086 and the cathode (MgA
g electrode) 5087 is continuously formed using a vacuum deposition method without opening to the atmosphere. Note that the thickness of the EL layer 5086 is 80
~ 200 [nm] (typically 100-120 [nm]), and the thickness of the cathode 5087 is 180-300 [nm] (typically 20-nm).
0 to 250 [nm]).

In this step, an EL layer and a cathode are sequentially formed for a pixel corresponding to red, a pixel corresponding to green, and a pixel corresponding to blue. However, since the EL layer has poor resistance to a solution, it must be formed individually for each color without using a photolithography technique. Therefore, it is preferable that a metal mask is used to hide portions other than the desired pixels, and that the EL layer and the cathode are selectively formed only in necessary portions.

That is, first, a mask for hiding all pixels other than pixels corresponding to red is set, and an EL layer for emitting red light is selectively formed using the mask. Next, a mask for hiding all pixels other than pixels corresponding to green is set, and a green light-emitting EL layer is selectively formed using the mask. Next, a mask for covering all pixels other than the pixel corresponding to blue is similarly set, and an EL layer for emitting blue light is selectively formed using the mask. Note that all the masks are described herein as being different, but the same mask may be used again.

Here, a method of forming three types of EL elements corresponding to RGB is used. However, a method of combining a white light emitting EL element and a color filter, a blue or blue-green light emitting EL element and a phosphor (fluorescent And a method in which an EL element corresponding to RGB is stacked on a cathode (a counter electrode) using a transparent electrode.

[0214] As the EL layer 5086, a known material can be used. As a known material, it is preferable to use an organic material in consideration of a driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the EL layer.

Next, a cathode 5087 is formed using a metal mask on a pixel having a switching TFT in which a gate electrode is connected to the same gate signal line (a pixel on the same line). In this embodiment, the cathode 5087 is made of MgA.
Although g was used, the present invention is not limited to this. Cathode 50
Other known materials may be used as 87.

Finally, a passivation film 5089 made of a silicon nitride film is formed to a thickness of 300 [nm]. By forming the passivation film 5089 in advance, the EL layer 50
86 can be protected from moisture and the like, and the reliability of the EL element can be further improved.

Thus, an EL display having a structure as shown in FIG. 12B is completed. In the manufacturing process of the EL display in this embodiment, a source signal line is formed by Ta and W which are materials forming a gate electrode, and a source and a drain electrode are formed due to a circuit configuration and a process. Although the gate signal line is formed of Al, which is the wiring material used, a different material may be used.

By the way, the EL display of this embodiment has a TF having an optimum structure not only for the pixel portion but also for the drive circuit portion.
By arranging T, very high reliability can be exhibited and operating characteristics can be improved. It is also possible to add a metal catalyst such as Ni in the crystallization step to enhance the crystallinity.
As a result, the driving frequency of the source signal line driving circuit becomes 1
It can be set to 0 [MHz] or more.

First, a TFT having a structure in which hot carrier injection is reduced so as not to reduce the operation speed as much as possible,
N-channel type TF of CMOS circuit forming drive circuit section
Used as T. In addition, as the drive circuit here,
It includes a shift register, a buffer, a level shifter, a latch in line-sequential driving, a transmission gate in point-sequential driving, and the like.

In this embodiment, the active layer of the n-channel TFT has an LDD region (Lov region) overlapping the gate electrode with the source region, the drain region and the gate insulating film interposed therebetween, and the gate insulating film interposed therebetween. And an LDD region (Loff region) and a channel forming region which do not overlap with the gate electrode.

Also, a p-channel type TFT of a CMOS circuit
Since there is almost no concern about deterioration due to hot carrier injection, it is not necessary to provide an LDD region. Needless to say, it is also possible to provide an LDD region similarly to the n-channel type TFT and take measures against hot carriers.

In addition, when a CMOS circuit in which a current flows bidirectionally in the channel formation region, that is, a CMOS circuit in which the roles of the source region and the drain region are exchanged is used in the driver circuit, n In the channel type TFT, it is preferable to form an LDD region on both sides of the channel formation region so as to sandwich the channel formation region. An example of such a transmission gate is a transmission gate used for dot-sequential driving. In the case where a CMOS circuit in which off-state current needs to be suppressed as low as possible is used in the driver circuit, the n-channel TFT forming the CMOS circuit preferably has a Lov region. As such an example, a transmission gate used for dot-sequential driving is also mentioned.

In fact, when the structure shown in FIG. 12B is completed, a protective film (laminate film, ultraviolet curable resin film, etc.) with high airtightness and low degassing or a transparent film is provided so as not to be further exposed to the outside air. It is preferable to package (enclose) with an optical sealing material. At this time, the reliability of the EL element is improved by setting the inside of the sealing material to an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.

When the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting terminals routed from elements or circuits formed on the substrate to external signal terminals. To complete the product. Such a state in which it can be shipped is referred to as an EL display in this specification.

According to the steps shown in this embodiment, the EL
The number of photomasks required for manufacturing a display can be reduced. As a result, the process can be shortened, which can contribute to a reduction in manufacturing cost and an improvement in yield.

This embodiment can be implemented in combination with Embodiments 1 to 5.

(Embodiment 7) In this embodiment, the EL of the present invention is used.
An example of a cross-sectional structure of the display, which is different from FIG. 12, will be described with reference to FIG. In FIG. 12, the switching TFT and the EL driving TFT are top gate type TFTs.
Although the example of the FT is described, in this embodiment, an example in which a bottom gate thin film transistor is used as a TFT will be described.

In FIG. 13, reference numeral 811 denotes a substrate, and 812, an insulating film serving as a base (hereinafter, referred to as a base film). As the substrate 811, a light-transmitting substrate, typically, a glass substrate, a quartz substrate, a glass ceramic substrate, or a crystallized glass substrate can be used. However, it must withstand the maximum processing temperature during the manufacturing process.

Although the base film 812 is particularly effective when a substrate containing mobile ions or a substrate having conductivity is used, it may not be provided on a quartz substrate. Base film 812
May be used as an insulating film containing silicon (silicon). Note that, in this specification, the “insulating film containing silicon” refers specifically to silicon such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film (SiOxNy: x and y are arbitrary integers). On the other hand, it refers to an insulating film containing oxygen or nitrogen at a predetermined ratio.

Reference numeral 8201 denotes a switching TFT, 820
Reference numeral 2 denotes an EL driving TFT, each of which is an n-channel TFT.
It is formed of FT and p-channel TFT. In the case where the EL emission direction is the lower surface of the substrate (the surface on which the TFT and the EL layer are not provided), the above structure is preferable. However, the present invention is not limited to this configuration. T for switching
FT and EL driving TFTs are p-channel even for n-channel TFTs.
Either channel type TFT may be used.

The switching TFT 8201 includes a source region 813, a drain region 814, and an LDD region 815a.
To 815d, the isolation region 816 and the channel formation region 81
An active layer including 7a and 817b, a gate insulating film 818,
Gate electrodes 819a and 819b and first interlayer insulating film 820
And a source signal line 821 and a drain wiring 822. Note that the gate insulating film 818 or the first interlayer insulating film 820 may be common to all TFTs on the substrate,
It may be different depending on the circuit or element.

The switching TFT shown in FIG.
8201 is a so-called double gate structure in which gate electrodes 817a and 817b are electrically connected.
Of course, not only a double gate structure but also a so-called multi-gate structure such as a triple gate structure (a structure including an active layer having two or more channel formation regions connected in series)
It may be.

The multi-gate structure is extremely effective in reducing the off-state current. If the off-state current of the switching TFT is sufficiently reduced, the EL drive TFT 820 will be reduced accordingly.
The minimum capacitance required by the capacitor connected to the second gate electrode can be suppressed. That is, since the area of the capacitor can be reduced, the multi-gate structure is effective in increasing the effective light emitting area of the EL element.

Further, in the switching TFT 8201, the LDD regions 815a to 815d are provided so as not to overlap the gate electrodes 819a and 819b via the gate insulating film 818. Such a structure is very effective in reducing off-state current. Also, the LDD region 815a
The length (width) of .about.815d may be 0.5-3.5 .mu.m, typically 2.0-2.5 .mu.m.

It is more preferable to provide an offset region (a region formed of a semiconductor layer having the same composition as the channel formation region and to which a gate voltage is not applied) between the channel formation region and the LDD region in order to reduce off-state current. . Also,
In the case of a multi-gate structure having two or more gate electrodes, an isolation region 816 provided between channel formation regions
(A region where the same impurity element is added at the same concentration as the source region or the drain region) is effective in reducing off-state current.

Next, the EL driving TFT 8202 includes an active layer including a source region 826, a drain region 827, and a channel formation region 829, a gate insulating film 818, a gate electrode 830, a first interlayer insulating film 820, It is formed to have a signal line 831 and a drain wiring 832. In this embodiment, the EL driving TFT 8202 is a p-channel TFT.

The drain region 814 of the switching TFT 8201 is connected to the gate electrode 830 of the EL driving TFT 8202. Although not shown, specifically, the gate electrode 830 of the EL driving TFT 8202
Is the drain region 814 of the switching TFT 8201
And a drain wiring (also referred to as a connection wiring) 822. The EL driving TFT 82
The 02 source signal line 831 is connected to a power supply line (not shown).

The EL driving TFT 8202 is an EL element 82
06 is an element for controlling the amount of current supplied to
A relatively large amount of current flows. Therefore, the EL driving TF
The channel width (W) of T8202 is the switching TF
It is preferable to design so as to be longer than the channel width of T8201. Further, it is preferable that the channel length (L) is designed to be long so that an excessive current does not flow to the EL driving TFT 8202. Desirably 0.5 to
2 μA (preferably 1 to 1.5 μA).

Further, the thickness of the active layer (particularly, the channel formation region) of the EL driving TFT 8202 is increased (preferably 50 to 100 nm, more preferably 60 to 8 nm).
0 nm), deterioration of the TFT may be suppressed.
Conversely, in the case of the switching TFT 8201, from the viewpoint of reducing the off-state current, the thickness of the active layer (particularly, the channel formation region) is reduced (preferably 20 to 5).
0 nm, more preferably 25 to 40 nm) is also effective.

The structure of the TFT provided in the pixel has been described above. At this time, a drive circuit is also formed. FIG. 13 shows a CM which is a basic unit forming a drive circuit.
The OS circuit is shown.

In FIG. 13, a TFT having a structure for reducing hot carrier injection while keeping the operation speed from decreasing as much as possible is replaced with an n-channel TFT 82 of a CMOS circuit.
04. Note that the driver circuits here include a source signal line driver circuit, a gate signal line driver circuit, and a counter power supply line driver circuit. Of course, other logic circuits (such as a level shifter, an A / D converter, and a signal dividing circuit) can be formed.

An n-channel TFT 820 of a CMOS circuit
The active layer 4 has a source region 835 and a drain region 83.
6, an LDD region 837 and a channel formation region 838, and the LDD region 837 overlaps with the gate electrode 839 via the gate insulating film 818.

The LDD region 8 is formed only on the drain region 836 side.
The reason why 37 is formed is that the operation speed is not reduced. In addition, the n-channel TFT 8204 does not require much attention to the off-state current, and it is better to attach importance to the operation speed. Therefore, it is better to eliminate the offset.

Also, a p-channel type TFT of a CMOS circuit
In the case of 8205, the deterioration due to hot carrier injection is hardly noticeable, so that an LDD region does not need to be provided. Therefore, the active layer includes a source region 840, a drain region 841, and a channel formation region 842, over which a gate insulating film 818 and a gate electrode 843 are provided. Of course, n
An LDD region is provided similarly to the channel type TFT 8204,
It is also possible to take hot carrier measures.

Reference numerals 861 to 865 denote channel formation regions 8
42, 838, 817a, 817b, and 829.

The n-channel TFT 8204 and the p-channel TFT
Each of the channel type TFTs 8205 has a source signal line 84 on a source region with a first interlayer insulating film 820 interposed therebetween.
4,845. Further, an n-channel TFT 8204 and a p-channel TF
The drain regions of T8205 are electrically connected to each other.

Next, reference numeral 847 denotes a first passivation film having a thickness of 10 nm to 1 μm (preferably 200 to 5 μm).
00 nm). As a material, an insulating film containing silicon (especially a silicon nitride oxide film or a silicon nitride film is preferable)
Can be used. This passivation film 847
Has a role of protecting the formed TFT from alkali metals and moisture. Finally, the TFT (especially the EL driving T
The EL layer 851 provided above the FT) contains an alkali metal such as sodium. That is, the first passivation film 847 also functions as a protective layer that prevents these alkali metals (mobile ions) from entering the TFT side.

Reference numeral 848 denotes a second interlayer insulating film.
It has a function as a flattening film for flattening a step formed by FT. As the second interlayer insulating film 848, an organic resin film is preferable, and polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like is preferably used.
These organic resin films have an advantage that a good flat surface is easily formed and the relative dielectric constant is low. Since the EL layer is very sensitive to unevenness, it is desirable that the step due to the TFT is almost completely absorbed by the second interlayer insulating film 848. In order to reduce the parasitic capacitance formed between the gate signal line or the source signal line and the cathode of the EL element, it is desirable to provide a thick material having a low relative dielectric constant. Therefore, the film thickness is 0.
5-5 μm (preferably 1.5-2.5 μm) is preferred.

Reference numeral 849 denotes a pixel electrode (anode of an EL element) made of a transparent conductive film, which is formed after opening a contact hole (opening) in the second interlayer insulating film 848 and the first passivation film 847. The opening is formed so as to be connected to the drain wiring 832 of the EL driving TFT 8202. If the pixel electrode 849 and the drain region 827 are not directly connected as shown in FIG. 13, it is possible to prevent the alkali metal of the EL layer from entering the active layer via the pixel electrode.

A third interlayer insulating film 85 made of a silicon oxide film, a silicon nitride oxide film or an organic resin film is formed on the pixel electrode 849.
0 is provided for a thickness of 0.3-1 μm. This third interlayer insulating film 850 functions as a bank. Pixel electrode 849
An opening is provided on the substrate by etching, and the edge of the opening is etched so as to have a tapered shape. The angle of the taper is 10-60 ° (preferably 30-50 °)
It is good to Particularly, the third interlayer insulating film 850 is formed by forming the pixel electrode 849 and the drain wiring 83 of the EL driving TFT 8202.
By providing the pixel electrode 849 over a portion where the second electrode 2 is connected, it is possible to prevent a light emission failure of the EL layer 851 due to a step of the pixel electrode 849 generated in a contact hole portion.

On the third interlayer insulating film 850, an EL layer 85 is formed.
1 is provided. The EL layer 851 is used in a single layer or a stacked structure; however, the use of the EL layer 851 in a stacked structure has higher luminous efficiency. Generally, a hole injection layer / a hole transport layer / a light emitting layer / an electron transport layer are formed in this order on a pixel electrode. A structure such as a hole transport layer / light emitting layer / electron transport layer / electron injection layer may be used. In the present invention, any known structure may be used, and the EL layer may be doped with a fluorescent dye or the like.

The structure shown in FIG. 13 is an example in the case where a method of forming three types of EL elements corresponding to RGB is used. Although only one pixel is shown in FIG. 13, pixels having the same structure are formed corresponding to the respective colors of red, green, and blue, whereby color display can be performed. The present invention can be implemented regardless of the light emitting method.

On the EL layer 851, E as a counter electrode is formed.
A cathode 852 for the L element is provided. As the cathode 852, a material containing magnesium (Mg), lithium (Li), or calcium (Ca) having a small work function is used. Preferably, MgAg (Mg and Ag are Mg: Ag = 1)
An electrode made of a material mixed at 0: 1) may be used. In addition, MgAgAl electrode, LiAl electrode, LiFA
l electrode.

After the EL layer 851 is formed, the cathode 852 is
It is desirable to form continuously without opening to the atmosphere. This is because the interface state between the cathode 852 and the EL layer 851 greatly affects the luminous efficiency of the EL element. Note that in this specification, a light-emitting element formed using a pixel electrode (anode), an EL layer, and a cathode is referred to as an EL element 8206.

The laminate composed of the EL layer 851 and the cathode 852 must be formed individually for each pixel.
Since No. 1 is extremely weak to moisture, ordinary photolithography cannot be used. Therefore, using a physical mask material such as a metal mask, a vacuum evaporation method, a sputtering method,
It is preferable to selectively form by a gas phase method such as a plasma CVD method.

As a method for selectively forming the EL layer, an ink-jet method, a screen printing method, a spin coating method, or the like can be used. It can be said that the method is more preferable.

Reference numeral 854 denotes a second passivation film having a thickness of 10 nm to 1 μm (preferably 200 to 5 μm).
00 nm). Second passivation film 85
The purpose of providing 4 is mainly to protect the EL layer 851 from moisture, but it is also effective to have a heat radiation effect. However, since the EL layer is weak to heat as described above, the temperature should be as low as possible (preferably in a temperature range from room temperature to 120 ° C.)
It is desirable to form a film. Therefore, the plasma CVD method,
It can be said that a sputtering method, a vacuum evaporation method, an ion plating method or a solution coating method (spin coating method) is a desirable film forming method.

Note that all of the TFTs shown in FIG.
It goes without saying that the polysilicon film used in the present invention may be provided as an active layer.

The present invention is not limited to the structure of the EL display shown in FIG. 13, and the structure shown in FIG. 13 is only one of preferred embodiments for implementing the present invention.

This embodiment can be implemented in combination with Embodiments 1 to 5.

(Embodiment 8) In this embodiment, a process for manufacturing an EL display of the present invention by sealing a substrate on which an EL element is formed so that the EL element does not come into contact with the atmosphere will be described. FIG. 14A is a top view of the EL display of the present invention, and FIG. 14B is a cross-sectional view thereof.

In FIGS. 14A and 14B, 4001
, A substrate; 4002, a pixel portion; 4003, a source signal line driver circuit; 4004a, a gate signal line driver circuit;
Reference numeral b denotes a counter power supply line driving circuit. Each driving circuit reaches an FPC (flexible print circuit) 4006 via a wiring 4005 and is connected to an external device.

At this time, the first portion is surrounded by the pixel portion 4002, the source signal line driving circuit 4003, the gate signal line driving circuit 4004a, and the opposing power supply line driving circuit 4004b.
Sealing material 4101, cover material 4102, filler 4103
And a second sealing material 4104.

FIG. 14B corresponds to a cross-sectional view taken along line AA ′ of FIG. 14A, and a driving TFT (here, n) included in a source signal line driving circuit 4003 is provided over a substrate 4001. A channel type TFT and a p-channel type TFT are illustrated.) 4201 and E included in the pixel portion 4002 are illustrated.
L driving TFT (TF controlling current flowing through EL element)
T) 4202 is formed.

In this embodiment, a p-channel TFT or an n-channel TFT manufactured by a known method is used as the driving TFT 4201, and a p-channel TFT manufactured by a known method is used as the EL driving TFT 4202. Used. The pixel portion 4002 includes an EL driving TFT 42.
Capacitor (not shown) connected to 02 gate electrode
Is provided.

Driving TFT 4201 and EL Driving TFT
An interlayer insulating film (flattening film) 4301 made of a resin material is formed on 4202, and an EL driving TFT 4301 is formed thereon.
A pixel electrode (anode) 4302 electrically connected to the drain region 202 is formed. As the pixel electrode 4302, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used.

An insulating film 4303 is formed on the pixel electrode 4302, and the insulating film 4303 is formed on the pixel electrode 430.
2, an opening is formed. In this opening, an EL layer 4304 is formed over the pixel electrode 4302. For the EL layer 4304, a known organic EL material or inorganic EL material can be used. As the organic EL material, there are a low-molecular (monomer) material and a high-molecular (polymer) material, and either may be used.

As a method for forming the EL layer 4304, a known vapor deposition technique or coating technique may be used. The EL layer may have a stacked structure or a single-layer structure by freely combining a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer.

On the EL layer 4304, a cathode 4305 made of a light-shielding conductive film (typically, a conductive film containing aluminum, copper, or silver as a main component or a laminated film of these and another conductive film) is provided. It is formed. The cathode 4305 is a part of the opposing power supply line and is formed simultaneously with the opposing power supply line.
It is preferable that moisture and oxygen existing at the interface between the cathode 4305 and the EL layer 4304 be eliminated as much as possible. Therefore, it is necessary to devise a method in which both are continuously formed in a vacuum or the EL layer 4304 is formed in a nitrogen or rare gas atmosphere, and the cathode 4305 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

The cathode 4305 is electrically connected to the wiring 4005 in a region indicated by 4306. A wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305, and an FPC through an anisotropic conductive film 4307.
4006.

As described above, the pixel electrode (anode) 43
02, an EL element including the EL layer 4304 and the cathode 4305 is formed. This EL element has a first sealing material 410
Are surrounded by a cover material 4102 bonded to the substrate 4001 by the first and first seal materials 4101,
3 enclosed.

As the cover material 4102, a glass material, a metal material (typically, a stainless steel material), a ceramic material, and a plastic material (including a plastic film) can be used. As a plastic material, FRP (Fi
Berglass-Reinforced Plast
ics) plate, PVF (polyvinyl fluoride) film, mylar film, polyester film or acrylic resin film. Further, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

However, when the direction of light emission from the EL element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

As the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used. Acetate) can be used. By providing a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen inside the filler 4103, deterioration of the EL element can be suppressed.

Further, a spacer may be contained in the filler 4103. At this time, if the spacer is made of barium oxide, the spacer itself can have hygroscopicity. In the case where a spacer is provided, it is also effective to provide a resin film on the cathode 4305 as a buffer layer for relaxing pressure from the spacer.

[0276] The wiring 4005 is electrically connected to the FPC 4006 via the anisotropic conductive film 4307. A wiring 4005 transmits a signal sent to the pixel portion 4002, the source signal line driver circuit 4003, the gate signal line driver circuit 4004a, and the counter power line driver circuit 4004b to the FPC4.
006 to be electrically connected to an external device by the FPC 4006.

Also, in this embodiment, the first sealing material 4101
A second sealing material 4104 is provided so as to cover the exposed part of the FPC 4006 and a part of the FPC 4006, and the EL element is completely shut off from the outside air. Thus, an EL display having the cross-sectional structure of FIG.

This embodiment can be implemented in combination with Embodiments 1 to 7.

Embodiment 9 In this embodiment, a circuit diagram of a pixel having a structure different from that of FIG. 3 will be described with reference to FIG. In this embodiment, 4801 is a source signal line, 4802 is a switching TFT, 4803 is a gate signal line, 4804 is an EL driving TFT, 4805
Is a capacitor, 4806 is a power supply line, 4808 is a counter power line, and 4809 is an EL element.

The circuit diagram shown in FIG. 15 is an example in which the same power supply line 4806 is provided between two adjacent pixels on the same line. That is, the feature is that two pixels are formed so as to be line-symmetric with respect to the power supply line 4806. The power supply line 4806 is connected to the source region of the EL driving TFT 4804 of two adjacent pixels.

In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of this embodiment can be implemented in combination with the structures of Embodiments 1 to 8.

(Embodiment 10) In this embodiment, a detailed configuration of the source signal line driving circuit 102 shown in FIG. 9 will be described.

The shift register 801, the latch (A) (8
02) and the latch (B) (803) are arranged as shown in FIG. In this embodiment, one set of latches (A) (802) and one set of latches (B) (803)
It corresponds to four source signal lines St to S (t + 3). In this embodiment, the level shift for changing the amplitude of the voltage of the signal is not provided. However, the level shift may be appropriately provided by the designer.

The clock signals CLK, the clock signal CLKB whose polarity is inverted, the start pulse signal SP,
The driving direction switching signals SL / R are input to the shift register 801 from the wirings shown in the figure. A digital video signal VD input from the outside is input to the latch (A) (802) from the wiring shown in the figure. Latch signal S_LAT, signal S_LA with inverted polarity of S_LAT
Tb is calculated from the wiring shown in FIG.
Input to 3).

With respect to the detailed configuration of the latches (A) (802), the latches (A) (80) corresponding to the source signal line St
A description will be given by taking a part 804 of 2) as an example. Latch (A)
Part 804 of (802) has two clocked inverters and two inverters.

FIG. 17 is a top view of a part 804 of the latch (A) (802). 831a and 831b are respectively
A part 804 of the latch (A) (802) is an active layer of a TFT forming one of the inverters, and 836 is a common gate electrode of the TFT forming one of the inverters. Reference numerals 832a and 832b denote active layers of a TFT forming another inverter included in a part 804 of the latch (A) (802).
837b is a gate electrode provided on each of the active layers 832a and 832b. Note that the gate electrodes 837a and 837a
37b is electrically connected.

Reference numerals 833a and 833b denote active layers of a TFT forming one of the clocked inverters included in a part 804 of the latch (A) (802). Gate electrodes 838a and 838b are provided on the active layer 833a, and have a double gate structure. On the active layer 833b, gate electrodes 838b and 839 are provided to form a double gate structure.

Reference numerals 834a and 834b denote active layers of a TFT forming another clocked inverter included in a part 804 of the latch (A) (802).
Gate electrodes 839 and 840 are provided on the active layer 834a to form a double gate structure. Further, gate electrodes 840 and 841 are provided on the active layer 834b to form a double gate structure.

(Embodiment 11) In the EL display of the present invention, the material used for the EL layer of the EL element is not limited to the organic EL material, but can be implemented using an inorganic EL material. However, since a current inorganic EL material has a very high driving voltage, a TFT having a withstand voltage characteristic capable of withstanding such a driving voltage must be used.

Alternatively, if an inorganic EL material having a further lower driving voltage is developed in the future, it can be applied to the present invention.

The structure of this embodiment is similar to that of the first to tenth embodiments.
It is possible to implement in combination with.

Embodiment 12 In the present invention, the organic substance used for the EL layer may be a low molecular organic substance or a polymer (polymer) organic substance. As the low molecular weight organic substance, materials mainly including Alq ₃ (tris-8-quinolilite-aluminum), TPD (triphenylamine derivative) and the like are known. Examples of the polymer-based organic substance include a π-conjugated polymer-based substance. Typically, PPV (polyphenylene vinylene), PVK (polyvinyl carbazole), polycarbonate and the like can be mentioned.

The polymer (polymer) organic substance can be formed by a simple thin film forming method such as a spin coating method (also referred to as a solution coating method), a dipping method, a dispensing method, a printing method or an ink jet method. High heat resistance compared to substances.

The EL display of the present invention has the E
In the L element, when the EL layer of the EL element has an electron transporting layer and a hole transporting layer, the electron transporting layer and the hole transporting layer are made of an inorganic material such as amorphous Si or It may be made of an amorphous semiconductor such as amorphous Si _1-x C _x .

[0296] A large amount of trap states exist in an amorphous semiconductor, and a large amount of interface states are formed at an interface where the amorphous semiconductor is in contact with another layer. Therefore, the EL element can emit light at a low voltage and can achieve high luminance.

[0297] A dopant (impurity) may be added to the organic EL layer to change the color of light emitted from the organic EL layer. As a dopant, DCM1, Nile Red, Rubrene,
Coumarin 6, TPB, quinacridone and the like.

This embodiment can be implemented in combination with Embodiments 1 to 11.

(Embodiment 13) In this embodiment, the present invention will be described.
With reference to FIGS. 18 to 20, description will be given of what voltage-current characteristics are preferable to drive the EL driving TFT when the L display driving method is used.

In the EL element, even if the applied voltage changes even slightly, the current flowing through the EL element greatly changes exponentially. From another viewpoint, even when the magnitude of the current flowing through the EL element changes, the voltage value applied to the EL element does not change much. The luminance of the EL element increases almost directly in proportion to the current flowing through the EL element. Therefore, rather than controlling the brightness (voltage value) of the voltage applied to the EL element to control the luminance of the EL element, the EL element is controlled by controlling the magnitude of the current flowing through the EL element (current amount). It is better to control the brightness of the TFT
And the luminance of the EL element can be easily controlled.

Referring to FIG. FIG. 18A shows FIG.
In the pixel of the EL display of the present invention shown in FIG.
FIG. 2 illustrates only constituent parts of the L driving TFT 108 and the EL element 110.

FIG. 18B shows voltage-current characteristics of the EL driving TFT 108 and the EL element 110 shown in FIG. 18A. The EL driving TFT 10 shown in FIG.
8 is a graph showing the voltage-current characteristics of the EL driving TFT 1 with respect to the voltage V _DS between the source region and the drain region.
08 shows the magnitude of the current flowing in the drain region, and FIG. 18 shows a plurality of graphs having different values of V _GS which is the voltage between the source region and the gate electrode of the EL driving TFT 108.

As shown in FIG. 18A, EL element 1
The voltage applied between the pixel electrode 10 and the counter electrode 111 is V
_EL , terminal 3601 connected to power supply line and EL element 1
10 voltage applied between the opposing electrodes 111 of the V _T.
Note V _T is the value is fixed by the potential of the power supply line. The voltage between the source region and the drain region of the EL driving TFT 108 is V _DS , the voltage between the wiring 3602 connected to the gate electrode of the EL driving TFT 108 and the source region, that is, the gate electrode and the source of the EL driving TFT 108 The voltage between the regions is V _GS .

The EL driving TFT 108 is an n-channel type TFT.
Either FT or p-channel TFT may be used

The EL driving TFT 108 and the EL element 110 are connected in series. Therefore, both elements (E
The amount of current flowing through the L driving TFT 108 and the EL element 110) is the same. Therefore, the EL driving TFT 108 and the EL element 110 shown in FIG. 18A are driven at the intersection (operating point) of the graph showing the voltage-current characteristics of both elements. In FIG. 18B, V _EL is a voltage between the potential of the counter electrode 111 and the potential at the operating point. V _DS is E
It becomes a voltage between the potential at the terminal 3601 of the L driving TFT 108 and the potential at the operating point. In other words, V _T is equal to the sum of V _EL and V _DS.

Here, the case where V _GS is changed will be considered. As can be seen from FIG.
As | V _GS −V _TH | of T108 increases, in other words, as | V _GS | increases, the EL driving T
The amount of current flowing to the FT 108 increases. V _TH is a threshold voltage of the EL driving TFT 108. Therefore, as can be seen from FIG. 18B, when | V _GS | increases, the amount of current flowing through the EL element 110 at the operating point naturally increases. The luminance of the EL element 110 is
It increases in proportion to the amount of current flowing through zero.

When the amount of current flowing through the EL element 110 increases due to the increase in | V _GS |, the value of V _EL also increases in accordance with the amount of current. And the size of the V _T is definite by the potential of the power supply line, the V _EL increases, correspondingly V _DS becomes smaller.

As shown in FIG. 18B, the voltage-current characteristics of the EL driving TFT are divided into two regions according to the values of V _GS and V _DS . The region where | V _GS −V _TH | <| V _DS | is the saturation region, and the region where | V _GS −V _TH |> | V _DS | is the linear region.

In the saturation region, the following equation 1 holds. Note that I _DS is the amount of current flowing through the channel forming region of the EL driving TFT 108. Β = μC ₀ W / L, μ is the mobility of the EL driving TFT 108, C ₀ is the gate capacitance per unit area, and W / L is the ratio of the channel width W to the channel length L of the channel formation region. .

[0310]

[Equation 1] _{I DS = β (V GS -V} TH) 2/2

In the linear region, the following equation 2 holds.

[0312]

[Formula 2] _{I DS = β {(V GS} -V TH) V DS -V DS 2/2}

As can be seen from Expression 1, the amount of current hardly changes with V _DS in the saturation region, and the amount of current is determined only by V _GS .

On the other hand, as can be seen from Equation 2, in the linear region, the amount of current is determined by V _DS and V _GS . As | V _GS | is increased, the EL driving TFT 108 operates in the linear region. And _VEL gradually increases. Thus, by an amount corresponding to V _EL is increased, V _DS becomes smaller. In the linear region, the amount of current decreases as V _DS decreases. Therefore, even if | V _GS | is increased, the amount of current becomes difficult to increase. | V _GS | = ∞
, The current amount = I _MAX . That is, | V _GS |
No matter how large, I _MAX or more current does not flow.
Here, I _MAX is the amount of current flowing through the EL element 110 when V _EL = V _T.

By controlling the magnitude of | V _GS | in this manner, the operating point can be set to a saturation region or a linear region.

It is desirable that all the EL driving TFTs have ideally the same characteristics. However, in practice, the threshold V _TH and the mobility μ are different between the individual EL driving TFTs. Often. And each EL drive T
When the threshold value V _{TH of the} FT and the mobility μ are different from each other, as can be seen from Expressions 1 and 2, even if the value of V _GS is the same, EL
The amount of current flowing through the channel forming region of the driving TFT 108 differs.

FIG. 19 shows the current-voltage characteristics of the EL driving TFT in which the threshold value V _TH and the mobility μ deviate. Solid line 370
1 is a graph of ideal current-voltage characteristics, and 3702, 3
Reference numeral 703 denotes the current-voltage characteristics of the EL driving TFT when the threshold value V _TH and the mobility μ are different from ideal values. Graphs of current-voltage characteristics 3702, 37
03 deviates from the graph 3701 of the current-voltage characteristic having the ideal characteristic by the same amount of current ΔI ₁ in the saturation region, and the operating point 370 of the graph 3702 of the current-voltage characteristic.
5 is in the saturation region, and the operating point 3706 of the graph 3703 of the current-voltage characteristic is in the linear region. In that case,
The difference between the current amount at the operating point 3704 and the current amount at the operating point 3705 and the operating point 3706 in the graph 3701 of the current-voltage characteristic having ideal characteristics is ΔI ₂ ,
Assuming that ΔI ₃ , the operating point 3706 in the linear region is smaller than the operating point 3705 in the saturated region.

Therefore, when the digital driving method shown in the present invention is used, the EL driving TFT and the EL element are driven so that the operating point exists in the linear region, and the EL driving is performed.
It is possible to perform gradation display in which unevenness in luminance of an EL element due to a shift in characteristics of a driving TFT is suppressed.

In the case of the conventional analog drive, | V _GS
It is preferable to drive the EL driving TFT and the EL element such that the operating point exists in a saturation region where the current amount can be controlled only by |.

As a summary of the above operation analysis, FIG. 20 shows a graph of the amount of current with respect to the gate voltage | V _GS | of the EL driving TFT. When | V _GS | is increased and becomes larger than the absolute value | V _TH | of the threshold voltage of the EL driving TFT, the EL driving TFT becomes conductive and current starts to flow. In this specification, | V _GS | at this time is referred to as a lighting start voltage. When | V _GS | is further increased, | V _GS | becomes a value that satisfies | V _GS −V _TH | = | V _DS | (here, temporarily assumed to be A). It becomes a linear region 3802. More | V _GS
As | increases, the amount of current increases and finally
The amount of current is saturated. At that time, | V _GS | = ∞.

As can be seen from FIG. 20, | V _GS | ≦ | V _TH
In the region of |, almost no current flows. | V _TH | ≦ |
The region where V _GS | ≦ A is a saturation region, and the amount of current changes according to | V _GS |. The region where A ≦ | V _GS | is a linear region, and the amount of current flowing through the EL element is | V _GS | and |
V _DS | changes the amount of current.

In the digital drive of the present invention, | V _GS | ≦ |
It is preferable to use a region of V _TH | and a linear region of A ≦ | V _GS |.

This embodiment can be implemented in combination with Embodiments 1 to 12.

Embodiment 14 An EL display formed by carrying out the present invention is of a self-luminous type, so that it has better visibility in a bright place than a liquid crystal display and has a wide viewing angle. Therefore, it can be used for display portions of various electronic devices (light-emitting devices). For example, to watch a TV broadcast or the like on a large screen, the EL display of the present invention may be used as a display unit of a display having a diagonal of 30 inches or more (typically, 40 inches or more).

[0325] The EL display includes all displays for displaying information, such as displays for personal computers, displays for receiving TV broadcasts, and displays for displaying advertisements. In addition, the EL display of the present invention can be used as a display portion of various electronic devices.

Examples of such electronic equipment of the present invention include a video camera, a digital camera, a goggle-type display (head-mounted display), a navigation system, a sound reproducing device (car audio, audio component, etc.), a notebook personal computer, a game Devices, personal digital assistants (mobile computers, mobile phones,
An image reproducing apparatus provided with a recording medium (specifically, a digital video disc (D
VD) and the like, which reproduces a recording medium and has a display capable of displaying the image. In particular, for a portable information terminal that is often viewed from an oblique direction, a wide viewing angle is regarded as important, and it is desirable to use an EL display. Specific examples of these electronic devices are shown in FIGS.

[0327] FIG. 21A illustrates a display, which includes a housing 2001, a support base 2002, a display portion 2003, and the like.
The EL display of the present invention can be used for the display portion 2003. Since the EL display is a self-luminous type, it does not require a backlight and can be a display portion thinner than a liquid crystal display.

FIG. 21B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The EL display of the present invention has a display unit 210.
2 can be used.

FIG. 21C shows a part (right side) of the head-mounted light emitting device, and includes a main body 2201, a signal cable 2202, a head fixing band 2203, and a screen section 22.
04, an optical system 2205, a display unit 2206, and the like. The EL display of the present invention can be used for the display portion 2206.

FIG. 21D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1, recording medium (DVD or the like) 2302, operation switch 23
03, a display unit (a) 2304, a display unit (b) 2305, and the like. The display portion (a) 2304 mainly displays image information, and the display portion (b) 2305 mainly displays character information. The EL display of the present invention is used for these display portions (a) and (b) 2304 and 2305. be able to. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 21E shows a goggle type display (head-mounted display).
1, a display unit 2402, and an arm unit 2403. The EL display of the present invention can be used for the display portion 2402.

[0332] FIG. 21F illustrates a personal computer, which includes a main body 2501, a housing 2502, a display portion 2503,
A keyboard 2504 and the like are included. The EL display of the present invention can be used for the display portion 2503.

If the emission luminance of the EL material becomes higher in the future, it becomes possible to enlarge and project the light containing the output image information with a lens or the like and use it for a front-type or rear-type projector.

[0334] Further, the above-mentioned electronic equipment is connected to the Internet,
Information distributed through an electronic communication line such as an ATV (cable television) is frequently displayed, and in particular, opportunities to display moving image information are increasing. Since the response speed of the EL material is very high, the EL display is preferable for displaying moving images.

[0335] In the EL display, since the light emitting portion consumes power, it is desirable to display information so that the light emitting portion is reduced as much as possible. Therefore, when an EL display is used for a portable information terminal, particularly a display unit mainly including character information such as a mobile phone or a sound reproducing device,
It is desirable to drive such that character information is formed in the light emitting portion with the non-light emitting portion as a background.

Here, FIG. 22A shows a mobile phone, which includes a main body 2601, an audio output unit 2602, and an audio input unit 260.
3, including a display unit 2604, operation switches 2605, and an antenna 2606. The EL display of the present invention has a display unit 2
604. Note that the display portion 2604 can display power of the mobile phone by displaying white characters on a black background.

FIG. 22B shows an audio reproducing apparatus, specifically, a car audio system.
702, and operation switches 2703 and 2704. The EL display of the present invention can be used for the display portion 2702. In this embodiment, the in-vehicle audio is shown, but the present invention may be applied to a portable or home-use audio reproducing apparatus. Note that the display portion 2702 can suppress power consumption by displaying white characters on a black background. This is particularly effective in a portable sound reproducing device.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. This embodiment can be implemented in combination with Embodiments 1 to 13.

[0339]

As described above, according to the present invention, even if the I _DS -V _GS characteristics vary somewhat depending on the TFT, the variation in the amount of current output when the same gate voltage is applied can be suppressed. Therefore, even if a signal of the same voltage is input, it is possible to avoid a situation in which the amount of light emitted from the EL element greatly differs between adjacent pixels due to the variation of the I _DS -V _GS characteristics.

In the present invention, a non-display period in which display is not performed can be provided. In the case of the conventional analog drive, when an all-white image is displayed on the EL display, the EL element always emits light, which causes deterioration of the EL layer earlier. According to the present invention, since a non-display period can be provided, deterioration of the EL layer can be suppressed to some extent.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an EL display of the present invention.

FIG. 2 is a circuit diagram of a pixel portion of an EL display according to the present invention.

FIG. 3 is a circuit diagram of a pixel of the EL display of the present invention.

FIG. 4 is a diagram showing a driving method of an EL display of the present invention.

FIG. 5 is a diagram showing a driving method of an EL display according to the present invention.

FIG. 6 is a diagram showing a driving method of an EL display of the present invention.

FIG. 7 is a diagram showing a driving method of an EL display of the present invention.

FIG. 8 is a top view of a pixel of the EL display of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a driving circuit of an EL display of the present invention.

FIG. 10 is a diagram showing a manufacturing process of the EL display of the present invention.

FIG. 11 is a view showing a manufacturing process of the EL display of the present invention.

FIG. 12 is a diagram showing a manufacturing process of the EL display of the present invention.

FIG. 13 is a detailed sectional view of the EL display of the present invention.

FIG. 14 is a top view and a cross-sectional view of an EL display of the present invention.

FIG. 15 is a pixel circuit diagram of the EL display of the present invention.

FIG. 16 is a circuit diagram of a source signal line driving circuit of an EL display according to the present invention.

FIG. 17 is a top view of a latch of a source signal line driving circuit of an EL display according to the present invention.

18A and 18B are diagrams illustrating a connection structure between an EL element and an EL driving TFT, and a diagram illustrating voltage-current characteristics of the EL element and the EL driving TFT.

FIG. 19 shows voltage-current characteristics of an EL element and an EL driving TFT.

FIG. 20 illustrates a relationship between a gate voltage and a drain current of an EL driving TFT.

FIG. 21 is a diagram of an electronic device using the EL display of the present invention.

FIG. 22 is a diagram of an electronic device using the EL display of the present invention.

FIG. 23 is a circuit diagram of a pixel portion of a conventional EL display.

FIG. 24 is a timing chart showing a driving method of a conventional EL display.

FIG. 25 is a diagram showing an I _DS -V _GS characteristic of a TFT.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H05B 33/04 H05B 33/04 33/08 33/08 33/12 33/12 B 33/14 33/14 B 33 / 22 33/22 ZF term (reference) 3K007 AB02 AB04 AB11 AB18 BA06 BB01 BB04 BB05 BB07 CA01 CB01 DA01 DB03 EB00 GA02 GA04 5C080 AA06 BB05 DD05 EE29 FF11 JJ02 JJ03 JJ04 JJ05 JJ06 KK43 A53A03A53A03A03A53A03A53A03A53A53A03A53A3A BA27 CA19 CA24 DA09 DA13 DB01 DB04 DB10 EA04 EA05 EA10 EB02 EC03 FA01 FB01 FB12 FB14 FB15 GA10 GB10 JA01

Claims (25)

[Claims] 1. A light-emitting device provided with a plurality of pixels each having an EL element, wherein the EL element includes a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. The light emitting device according to claim 1, wherein the plurality of pixels have a counter electrode of the EL element connected to each other for each line, and a potential of the pixel electrode is controlled by a digital video signal. 2. A light emitting device having a source signal line drive circuit, a gate signal line drive circuit, a counter power supply line drive circuit, and a pixel portion, wherein the pixel portion has a plurality of pixels, The plurality of pixels include an EL element and a switching TFT.
And an EL driving TFT. The EL element has a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. The gate signal line driving circuit controls the driving of the switching TFT, and the switching TFT controls the EL driving TF.
A light-emitting device, wherein driving of T is controlled, and a potential of the pixel electrode is controlled by the EL driving TFT. 3. A light emitting device having a source signal line driving circuit, a gate signal line driving circuit, a counter power line driving circuit, and a pixel portion, wherein the pixel portion has a plurality of pixels, The plurality of pixels include an EL element and a switching TFT.
And an EL driving TFT. The EL element includes a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. The driving of the switching TFT is controlled by the switching TFT, and the EL driving TF is controlled by the switching TFT.
The driving of T is controlled, the potential of the pixel electrode is controlled by the EL driving TFT, and the potential of the counter electrode is controlled by the counter power supply line driving circuit, so that the light emission time of the EL element is controlled. A light emitting device for performing gradation display. 4. A source signal line driving circuit, a gate signal line driving circuit, a counter power supply line driving circuit, a pixel portion, and a plurality of source signal lines connected to the source signal line driving circuit.
A light emitting device having a plurality of gate signal lines connected to the gate signal line driving circuit, a plurality of opposed power lines connected to the opposed power line driving circuit, and a plurality of power supply lines, wherein the pixel The unit has a plurality of pixels, the plurality of pixels each include a switching TFT, an EL driving TFT, and an EL element, and the gate electrode of the switching TFT includes the plurality of gates. Connected to one of the signal lines,
One of the source region and the drain region of the switching TFT is one of the plurality of source signal lines.
And the other is connected to a gate electrode of the EL driving TFT. The EL element includes a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. A source region of the EL driving TFT is connected to any one of the plurality of power supply lines;
A light-emitting device, wherein a drain region of the driving TFT is connected to the pixel electrode, and the counter electrode is connected to any one of the plurality of counter power lines. 5. A source signal line driving circuit, a gate signal line driving circuit, a counter power supply line driving circuit, a pixel portion, and a plurality of source signal lines connected to the source signal line driving circuit.
A light emitting device having a plurality of gate signal lines connected to the gate signal line driving circuit, a plurality of opposed power lines connected to the opposed power line driving circuit, and a plurality of power supply lines, wherein the pixel The unit has a plurality of pixels, the plurality of pixels each include a switching TFT, an EL driving TFT, and an EL element, and the gate electrode of the switching TFT includes the plurality of gates. Connected to one of the signal lines,
One of the source region and the drain region of the switching TFT is one of the plurality of source signal lines.
And the other is connected to a gate electrode of the EL driving TFT. The EL element includes a pixel electrode, a counter electrode maintained at a fixed potential, and a pixel electrode and a counter electrode. E provided in
A source region of the EL driving TFT, the source region being connected to any one of the plurality of power supply lines;
A light-emitting device, wherein a drain region of the driving TFT is connected to the pixel electrode, and the counter electrode is connected to any one of the plurality of counter power lines. 6. The light emitting device according to claim 2, wherein when the pixel electrode is an anode, the EL driving TFT is a p-channel TFT. 7. The light emitting device according to claim 2, wherein when the pixel electrode is a cathode, the EL driving TFT is an n-channel TFT. 8. The pixel according to claim 2, wherein the pixel electrode and the drain region of the EL driving TFT are connected directly or via at least one wiring. A light-emitting device, wherein the pixel electrode has a bank formed on a drain region of the EL driving TFT or a region connected to the at least one wiring. 9. A light emitting device according to claim 8, wherein said bank has a light shielding property. 10. The light emitting device according to claim 2, wherein the switching TFT or the EL driving TFT is a top gate type. 11. The light emitting device according to claim 2, wherein the switching TFT or the EL driving TFT is a bottom gate type. 12. A light emitting device according to claim 1, wherein said EL layer is made of a low molecular weight organic material or a polymer organic material. 13. The light emitting device according to claim 12, wherein the low molecular weight organic substance is made of Alq ₃ (tris-8-quinolilite-aluminum) or TPD (triphenylamine derivative). 14. The method according to claim 12, wherein said polymer organic substance is PPV (polyphenylene vinylene), PVK
A light-emitting device comprising (polyvinyl carbazole) or polycarbonate. 15. The light emitting device according to claim 1, wherein the light emitting device is a computer. 16. A light-emitting device according to claim 1, wherein the light-emitting device is a video camera. 17. A light emitting device according to claim 1, wherein the light emitting device is a DVD player. 18. A method for driving a light emitting device including a source signal line driving circuit, a gate signal line driving circuit, a counter power supply line driving circuit, and a pixel portion, wherein the pixel portion has a plurality of pixels. The plurality of pixels are an EL element and a switching TFT
And an EL driving TFT. The EL element has a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. The gate signal line driving circuit controls the driving of the switching TFT, and the switching TFT controls the EL driving TF.
The driving of T is controlled, the electric potential of the pixel electrode is controlled by the EL driving TFT, and n display periods Tr1, Tr2,... Trn and j non-display periods Td1, Td2,.
dj appear, and an arbitrary display period Tri (i = 1,..., n) of the n display periods Tr1, Tr2,... or Trn corresponds to n write periods Ta1, Ta2,. In an arbitrary writing period Tai, a digital video signal is input to the pixels of each line of the pixel portion, and all the ELs of the pixels of each line of the pixel portion are provided.
The digital video signal is applied to the pixel section in a writing period that appears next to the writing period Tai of the n writing periods Ta1, Ta2,... Or Tan after the on-potential is applied to the counter electrode of the element. Until the ON counter potential is applied to the counter electrodes of all the EL elements included in the pixels of each line of the pixel section, or j erase periods Te1, Te2, .. Or Tej in an arbitrary erasing period Tek (k = 1,..., J) until an off counter potential is applied to the counter electrodes of all the EL elements of the pixels in each line of the pixel portion. , Or Tj, the j non-display periods Td1, Td2,.
Among the j erasing periods Te1, Te2,... Or Tej, the non-display period Tdk is opposite to all of the EL elements of the pixels of each line of the pixel section. After the off counter potential is applied to the electrodes, the n writing periods Ta
The erasing period Tek of 1, Ta2,.
In the next writing period, the digital video signal is input to the pixels of each line of the pixel portion, and all the E that each pixel of each line of the pixel portion has
.., Or Ta, which is a period until an on-potential is applied to the opposing electrode of the L element, and the n writing periods Ta1, Ta2,.
n is one of the j erase periods Te1 and Te
, Or Tej, and partially overlaps with any one or two of the Tej, and the n write periods Ta1, Ta2,.
After all have appeared, the n write periods Ta
, Ta2,... Or Tan appears, and the digital video signal selects whether the EL element emits or does not emit light in the n display periods Tr1, Tr2,. n display periods Tr1, Tr2, ..., and the ratio of the length Trn is 2 ^0: 2 ^1: ..., 2 a driving method of a light-emitting device characterized by being represented by ^(n-1). 19. A driving method of a light emitting device including a source signal line driving circuit, a gate signal line driving circuit, a counter power supply line driving circuit, and a pixel portion, wherein the pixel portion has a plurality of pixels. The plurality of pixels are an EL element and a switching TFT
And an EL driving TFT. The EL element includes a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. The driving of the switching TFT is controlled by the switching TFT, and the EL driving TF is controlled by the switching TFT.
The driving time of the EL element is controlled by controlling the driving of T, controlling the potential of the pixel electrode by the EL driving TFT, and controlling the potential of the counter electrode by the counter power supply line driving circuit. .., Trn, and j non-display periods Td1, Td2,..., Tn in one frame period in each pixel of each line of the pixel portion. … And T
dj appear, and an arbitrary display period Tri (i = 1,..., n) of the n display periods Tr1, Tr2,... or Trn corresponds to n write periods Ta1, Ta2,. In an arbitrary writing period Tai, a digital video signal is input to the pixels of each line of the pixel portion, and all the ELs of the pixels of each line of the pixel portion are provided.
The digital video signal is applied to the pixel section in a writing period that appears next to the writing period Tai of the n writing periods Ta1, Ta2,... Or Tan after the on-potential is applied to the counter electrode of the element. Until the ON counter potential is applied to the counter electrodes of all the EL elements included in the pixels of each line of the pixel section, or j erase periods Te1, Te2, .. Or Tej in an arbitrary erasing period Tek (k = 1,..., J) until an off counter potential is applied to the counter electrodes of all the EL elements of the pixels in each line of the pixel portion. , Or Tj, the j non-display periods Td1, Td2,.
Among the j erasing periods Te1, Te2,... Or Tej, the non-display period Tdk is opposite to all of the EL elements of the pixels of each line of the pixel unit in the erasing period Tek. After the off counter potential is applied to the electrodes, the n writing periods Ta
The erasing period Tek of 1, Ta2,.
In the next writing period, the digital video signal is input to the pixels of each line of the pixel portion, and all the E that each pixel of each line of the pixel portion has
.., Or Ta, which is a period until an on-potential is applied to the opposing electrode of the L element, and the n writing periods Ta1, Ta2,.
n is one of the j erase periods Te1 and Te
, Or Tej, and partially overlaps with any one or two of the Tej, and the n write periods Ta1, Ta2,.
After all have appeared, the n write periods Ta
, Ta2,... Or Tan appears, and the digital video signal selects whether the EL element emits or does not emit light in the n display periods Tr1, Tr2,. n display periods Tr1, Tr2, ..., and the ratio of the length Trn is 2 ^0: 2 ^1: ..., 2 a driving method of a light-emitting device characterized by being represented by ^(n-1). 20. A source signal line driving circuit, a gate signal line driving circuit, a counter power supply line driving circuit, a pixel portion, a plurality of source signal lines connected to the source signal line driving circuit, and the gate signal A method for driving a light emitting device, comprising: a plurality of gate signal lines connected to a line driving circuit; a plurality of opposing power lines connected to the opposing power line driving circuit; and a plurality of power supply lines. The unit has a plurality of pixels, the plurality of pixels each include a switching TFT, an EL driving TFT, and an EL element, and the gate electrode of the switching TFT includes the plurality of gates. Connected to one of the signal lines,
One of the source region and the drain region of the switching TFT is one of the plurality of source signal lines.
And the other is connected to a gate electrode of the EL driving TFT. The EL element includes a pixel electrode, a counter electrode, and an EL layer provided between the pixel electrode and the counter electrode. A source region of the EL driving TFT is connected to any one of the plurality of power supply lines;
A drain region of the driving TFT is connected to the pixel electrode; the counter electrode is connected to any one of the plurality of counter power lines; .. And Trn, and j non-display periods Td1, Td2,.
dj appear, and an arbitrary display period Tri (i = 1,..., n) of the n display periods Tr1, Tr2,... or Trn corresponds to n write periods Ta1, Ta2,. In an arbitrary writing period Tai, a digital video signal is input to the pixels of each line of the pixel portion, and all the ELs of the pixels of each line of the pixel portion are provided.
The digital video signal is applied to the pixel section in a writing period that appears next to the writing period Tai of the n writing periods Ta1, Ta2,... Or Tan after the on-potential is applied to the counter electrode of the element. Until the ON counter potential is applied to the counter electrodes of all the EL elements included in the pixels of each line of the pixel section, or j erase periods Te1, Te2, .. Or Tej in an arbitrary erasing period Tek (k = 1,..., J) until an off counter potential is applied to the counter electrodes of all the EL elements of the pixels in each line of the pixel portion. , Or Tj, the j non-display periods Td1, Td2,.
Among the j erasing periods Te1, Te2,... Or Tej, the non-display period Tdk is opposite to all of the EL elements of the pixels of each line of the pixel unit in the erasing period Tek. After the off counter potential is applied to the electrodes, the n writing periods Ta
The erasing period Tek of 1, Ta2,.
In the next writing period, the digital video signal is input to the pixels of each line of the pixel portion, and all the E that each pixel of each line of the pixel portion has
.., Or Ta, which is a period until an on-potential is applied to the opposing electrode of the L element, and the n writing periods Ta1, Ta2,.
n is one of the j erase periods Te1 and Te
, Or Tej, and partially overlaps with any one or two of the Tej, and the n write periods Ta1, Ta2,.
After all have appeared, the n write periods Ta
, Ta2,... Or Tan appears, and the digital video signal selects whether the EL element emits or does not emit light in the n display periods Tr1, Tr2,. n display periods Tr1, Tr2, ..., and the ratio of the length Trn is 2 ^0: 2 ^1: ..., 2 a driving method of a light-emitting device characterized by being represented by ^(n-1). 21. A source signal line drive circuit, a gate signal line drive circuit, a counter power supply line drive circuit, a pixel portion, a plurality of source signal lines connected to the source signal line drive circuit, and the gate signal A method for driving a light emitting device, comprising: a plurality of gate signal lines connected to a line driving circuit; a plurality of opposing power lines connected to the opposing power line driving circuit; and a plurality of power supply lines. The unit has a plurality of pixels, the plurality of pixels each include a switching TFT, an EL driving TFT, and an EL element, and the gate electrode of the switching TFT includes the plurality of gates. Connected to one of the signal lines,
One of the source region and the drain region of the switching TFT is one of the plurality of source signal lines.
And the other is connected to a gate electrode of the EL driving TFT. The EL element includes a pixel electrode, a counter electrode maintained at a fixed potential, and a pixel electrode and a counter electrode. E provided in
A source region of the EL driving TFT, the source region being connected to any one of the plurality of power supply lines;
A drain region of the driving TFT is connected to the pixel electrode; the counter electrode is connected to any one of the plurality of counter power lines; .. And Trn, and j non-display periods Td1, Td2,.
dj appear, and an arbitrary display period Tri (i = 1,..., n) of the n display periods Tr1, Tr2,... or Trn corresponds to n write periods Ta1, Ta2,. In an arbitrary writing period Tai, a digital video signal is input to the pixels of each line of the pixel portion, and all the ELs of the pixels of each line of the pixel portion are provided.
The digital video signal is applied to the pixel section in a writing period that appears next to the writing period Tai of the n writing periods Ta1, Ta2,... Or Tan after the on-potential is applied to the counter electrode of the element. Until the ON counter potential is applied to the counter electrodes of all the EL elements included in the pixels of each line of the pixel section, or j erase periods Te1, Te2, .. Or Tej in an arbitrary erasing period Tek (k = 1,..., J) until an off counter potential is applied to the counter electrodes of all the EL elements of the pixels in each line of the pixel portion. , Or Tj, the j non-display periods Td1, Td2,.
Among the j erasing periods Te1, Te2,... Or Tej, the non-display period Tdk is opposite to all of the EL elements of the pixels of each line of the pixel unit in the erasing period Tek. After the off counter potential is applied to the electrodes, the n writing periods Ta
The erasing period Tek of 1, Ta2,.
In the next writing period, the digital video signal is input to the pixels of each line of the pixel portion, and all the E that each pixel of each line of the pixel portion has
.., Or Ta, which is a period until an on-potential is applied to the opposing electrode of the L element, and the n writing periods Ta1, Ta2,.
n is one of the j erase periods Te1 and Te
, Or Tej, and partially overlaps with any one or two of the Tej, and the n write periods Ta1, Ta2,.
After all have appeared, the n write periods Ta
, Ta2,... Or Tan appears, and the digital video signal selects whether the EL element emits or does not emit light in the n display periods Tr1, Tr2,. n display periods Tr1, Tr2, ..., and the ratio of the length Trn is 2 ^0: 2 ^1: ..., 2 a driving method of a light-emitting device characterized by being represented by ^(n-1). 22. One of claims 18 to 21.
In the paragraph, the longest non-display period among the non-display periods Td1, Td2,..., Tdj appears last in a frame period. 23. Any one of claims 18 to 22.
, The writing periods Ta1, Ta2,..., T
a is a driving method of a light emitting device, wherein an does not overlap each other. 24. Any one of claims 18 to 23.
, The erase periods Te1, Te2,..., Tej
Are driving methods for a light-emitting device, which do not overlap each other. 25. One of claims 18 to 24.
9. The method for driving a light emitting device according to claim 1, wherein the EL driving TFT is driven in a linear region.