JP2010232276A - Light-emitting device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light-emitting device which has a panel structure allowing a narrower frame of a display panel, and to provide its manufacturing method. <P>SOLUTION: On a pixel array substrate 10, a plurality of display pixels PIX are arranged in a display region 12, and a plurality of signal lines (scan line Ls, power supply voltage line La, and data line Ld) are connected to each of the display pixels PIX are arranged. On a counter substrate 20, pixel array connection pads 22s, 22a, and 22d are so arranged as to correspond to the ends of the signal lines on one surface side, and an IC chip 26, which is connected to respective pixel array connection pads 22s, 22a, and 22d, is mounted on the other surface side by routing wirings 23s, 23a, and 23d. The pixel array substrate 10 and the counter substrate 20 are opposed and joined each other with a seal material BND, and the ends of signal lines and respective pixel array connection pads 22s, 22a, and 22d are electrically and separately connected. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a light emitting device and a method for manufacturing the same, and more particularly to a light emitting device including a display panel in which a plurality of display pixels each having a self light emitting element are arranged on a substrate, and a method for manufacturing the same.

  In recent years, as a next-generation display device following a liquid crystal light-emitting device (LCD), a light-emitting device including a light-emitting element type display panel in which a plurality of display pixels having self-light-emitting elements are two-dimensionally arranged has been widespread. For example, a display panel (organic EL display panel) in which organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”) are two-dimensionally arranged is known as a display device for electronic devices such as mobile phones and portable music players. Yes.

  As is well known, an organic EL element has an element structure in which, for example, an anode (anode) electrode, an organic EL layer (light emitting functional layer), and a cathode (cathode) electrode are sequentially laminated on one side of a glass substrate or the like. Have. Then, by applying a voltage to the anode electrode and the cathode electrode so that the light emission threshold is exceeded in the organic EL layer, light is generated based on the energy generated when the holes and electrons injected in the organic EL layer recombine. (Excitation light) is emitted. The organic EL layer generally has a configuration in which a carrier transport layer such as a hole transport layer or an electron transport layer, and a light emitting layer are sequentially laminated.

  Here, in order to prevent the organic EL layer from being deteriorated by moisture in the organic EL display panel, for example, Patent Document 1 includes a glass substrate or the like so as to face the element substrate on which the organic EL element is formed. A sealing structure in which a sealing substrate is sealed with an adhesive to block outside air is disclosed.

JP 2000-0608048 A

  In the organic EL display panel as described above, generally, an organic EL element is arranged on a substrate to form a display area, and the organic EL element is driven to emit light in a peripheral area surrounding the display area on the substrate. Various wirings for supplying signals and power supply voltages are provided. For this reason, a space for wiring must be provided outside the display area, which increases the size of the peripheral area of the display panel, and restricts the product design and size. In addition, when the size of the peripheral area (frame) of the display panel is large, the number of panel substrates cut out from one mother glass is reduced at the time of manufacturing the display panel, resulting in an increase in product cost. Had.

  In view of the above-described problems, an object of the present invention is to provide a light emitting device having a panel structure capable of narrowing the frame of a display panel and a manufacturing method thereof.

  The light-emitting device according to the first aspect of the present invention includes a display area in which a plurality of display pixels are arranged on one surface side, and a peripheral edge portion at which ends of a plurality of signal lines connected to each of the display pixels are exposed. , A plurality of connection pads arranged on one surface side so as to correspond to end portions of the signal lines, and provided on the other surface side to drive the display pixels on the signal lines. A second circuit board having a control circuit for supplying a control signal for the control circuit, a plurality of connection wirings for individually connecting the plurality of connection pads and the control circuit, and the one surface side of the first board; And a joining member that joins the one surface side of the second substrate and electrically connects the end portions of the plurality of signal lines and the plurality of connection pads individually. .

According to a second aspect of the present invention, in the light emitting device according to the first aspect, a separation distance between the first substrate and the second substrate is greater than a separation distance between the plurality of connection pads on the second substrate. Is also set to be small.
According to a third aspect of the present invention, in the light emitting device according to the first or second aspect, a separation distance between the first substrate and the second substrate is set smaller than a height of the control circuit. And
According to a fourth aspect of the present invention, in the light emitting device according to any one of the first to third aspects, the control circuit has a region corresponding to a region of the second substrate to which the first substrate is bonded. It is arrange | positioned inside, It is characterized by the above-mentioned.
According to a fifth aspect of the present invention, in the light emitting device according to any one of the first to fourth aspects, the first substrate and the second substrate have the same external shape and external dimensions, and The first substrate and the second substrate are joined so that end portions of the entire circumference are aligned with each other.
According to a sixth aspect of the present invention, in the light emitting device according to any one of the first to fifth aspects, the plurality of signal lines are applied with at least a plurality of selection signals for setting the display pixels in a selected state. And a plurality of data lines to which display data for driving the display pixels in a predetermined display state is supplied.
According to a seventh aspect of the present invention, in the light emitting device according to any one of the first to sixth aspects, the second substrate is electrically connected to the outside of the second substrate on the other surface side. A plurality of external connection pads, and a plurality of external connection wirings for individually connecting the plurality of external connection pads and the control circuit.

  In the method for manufacturing a light emitting device according to claim 8, a plurality of display pixels are arranged in a display region, and ends of a plurality of signal lines connected to each of the display pixels are exposed on an outer periphery of the display region. Forming a plurality of connection pads arranged on one surface side of the second substrate facing the first substrate so as to correspond to end portions of the plurality of signal lines; and the second substrate. A step of forming a plurality of through holes penetrating from the one surface side to the other surface side of the first substrate, and one end side of the plurality of connection pads on the other surface side of the second substrate via the plurality of through holes. Forming the plurality of connection wirings connected to each other, connecting the control circuit to the other end of the plurality of connection wirings, and using the bonding member, the first substrate and the second substrate And the ends of the plurality of signal lines and the composite Characterized in that it comprises a and a step of electrically connecting individual connection pads.

According to a ninth aspect of the present invention, in the method for manufacturing a light emitting device according to the eighth aspect, the first substrate and the second substrate are joined when the first substrate and the second substrate are bonded. The separation distance is set to be smaller than the separation distance between the plurality of connection pads on the second substrate.
According to a tenth aspect of the present invention, in the method for manufacturing a light emitting device according to the eighth or ninth aspect, a separation distance between the first substrate and the second substrate is set smaller than a height of the control circuit. It is characterized by that.

  According to the light emitting device and the manufacturing method thereof according to the present invention, the area of the peripheral area of the display panel can be suppressed, so that the product design and size of the display panel can be improved and the product cost can be reduced. can do.

1 is a schematic configuration diagram illustrating a first embodiment of a light emitting device according to the present invention. It is a schematic plan view which shows an example of the pixel array substrate applied to the light-emitting device concerning this embodiment. It is a schematic block diagram which shows an example of the opposing board | substrate applied to the light-emitting device which concerns on this embodiment. FIG. 3 is an equivalent circuit diagram illustrating a circuit configuration example of display pixels that are two-dimensionally arranged on the display panel according to the embodiment. It is a schematic block diagram of the light-emitting device which concerns on a comparison object. It is a schematic plan view which shows an example of the pixel array board | substrate applied to the light-emitting device which concerns on a comparison object. It is a schematic block diagram of the opposing board | substrate applied to 2nd Embodiment of the light-emitting device which concerns on this invention. It is a schematic block diagram of the counter substrate applied to 3rd Embodiment of the light-emitting device which concerns on this invention. It is a schematic block diagram which shows 4th Embodiment of the light-emitting device which concerns on this invention. It is a schematic block diagram which shows 5th Embodiment of the light-emitting device which concerns on this invention. It is a schematic plan view which shows an example of the pixel array substrate applied to the light-emitting device concerning this embodiment. It is a schematic plan view which shows an example of the opposing board | substrate applied to the light-emitting device which concerns on this embodiment.

Hereinafter, a light emitting device and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments.
<First Embodiment>
(Light emitting device)
First, the panel structure applied to the light emitting device according to the present invention will be described.

  FIG. 1 is a schematic configuration diagram showing a first embodiment of a light emitting device according to the present invention. FIG. 1A is a schematic plan view of the light emitting device according to the present embodiment as viewed from the back side (counter view side), and FIG. 1B is a schematic side sectional view of the light emitting device according to the present embodiment. It is.

  FIG. 2 is a schematic plan view showing an example of a pixel array substrate applied to the light emitting device according to this embodiment. Here, FIG. 2 shows the pixel array substrate applied to the light emitting device according to the present embodiment as viewed from the side of the joint surface with the counter substrate (that is, along the line IIA-IIA shown in FIG. 1B). It is a schematic plan view). In this specification, “II” is used for convenience for the symbol corresponding to the Roman numeral “2” shown in FIG. In the plan view shown in FIG. 2, for convenience of explanation, only the relationship between each wiring layer provided on the insulating substrate, the display region, and the peripheral portion is shown, and a light emitting element ( The display of an organic EL element) and a pixel driving circuit (see FIG. 4 described later) for driving the light emitting element to emit light is omitted.

  FIG. 3 is a schematic configuration diagram illustrating an example of a counter substrate applied to the light emitting device according to the present embodiment. Here, FIG. 3A is a schematic cross-sectional view of a counter substrate applied to the light emitting device according to the present embodiment (that is, a schematic cross-section showing a cross section taken along line IIIB-IIIB shown in FIG. 1A). FIG. 3B shows the counter substrate applied to the light emitting device according to the present embodiment as viewed from the side of the joint surface with the pixel array substrate (that is, the IIIC shown in FIG. 1B). FIG. 3 is a schematic plan view taken along the line -IIIC. In this specification, “III” is used as a symbol corresponding to the Roman numeral “3” shown in FIG. In FIG. 2 and FIG. 3B, hatching is shown for convenience in order to clarify the region where the adhesive for bonding the pixel array substrate and the counter substrate is provided.

  The light emitting device according to this embodiment includes a pixel array substrate (first substrate) 10 and a counter substrate (second substrate) 20 as shown in FIGS. Yes. The pixel array substrate 10 and the counter substrate 20 are bonded so as to face each other through a sealing material BND such as an anisotropic conductive adhesive (or a sealing material with an anisotropic conductive connector; a bonding member). The surfaces are electrically connected to each other and the opposing surfaces are separated from each other at a predetermined interval. Here, as shown in FIGS. 1A and 1B, each of the pixel array substrate 10 and the counter substrate 20 is a parallel plate having a rectangular planar shape, and is a counter substrate than the pixel array substrate 10. 20 is set to be larger. In particular, in the present embodiment, as shown in FIG. 1A, the positions of the end surfaces of the left side and the upper and lower sides of the pixel array substrate 10 and the counter substrate 20 are aligned, and the right side of the counter substrate 20 is drawn. The end surface of the pixel array substrate 10 protrudes from the position of the end surface on the right side of the pixel array substrate 10, and the pixel array substrate 10 is bonded to the counter substrate 20 at the peripheral edge of each side.

  As shown in FIGS. 1B and 2, the pixel array substrate 10 is made of an insulating substrate 11 such as glass and is surrounded by a bonding surface with the counter substrate 20 (hereinafter referred to as “one surface” for convenience). A display area 12 is provided in this area. In addition, a peripheral portion where the sealing material BND is provided is set on the outer periphery of the display region 12. In the display area 12, for example, a plurality of display pixels PIX having light emitting elements such as organic EL elements are two-dimensionally arranged in a matrix, and control signals and display data for driving the light emitting elements of the display pixels PIX to emit light, Signal lines for supplying a power supply voltage and the like are arranged in the row direction and the column direction of the display region 12 corresponding to the arrangement of the display pixels PIX. In FIG. 1B, description of a pixel drive circuit DC, a scanning line Ls, and a power supply voltage line La, which will be described later, is omitted.

  Specifically, scanning lines Ls and power supply voltage lines La are arranged in the vertical direction (row direction) in FIG. 2, and data lines Ld are arranged in the horizontal direction (column direction) in the drawing. At each intersection of the scanning line Ls (or power supply voltage line La) and the data line Ld, a display pixel PIX including a light emitting element such as an organic EL element is provided. As will be described later, a selection signal for setting the display pixel PIX in each row to a selected state is applied to the scanning line Ls. Further, as will be described later, a power supply voltage (for example, an anode voltage) Vdd for causing the light emitting elements of the display pixels PIX in each row to emit light is applied to the power supply voltage line La. As will be described later, display data (for example, gradation voltage) for causing the light emitting elements of the display pixels PIX in each column to emit light with a desired luminance is applied to the data line Ld. The details of the display pixel PIX and the relationship between the display pixel PIX and each signal line will be described in detail later.

  On the other hand, at the peripheral edge set on the outer periphery of the display region 12, the end portions on one end side of each of the signal lines (scanning line Ls, power supply voltage line La, and data line Ld) are exposed, and the seal material BND and the part are exposed. By overlapping, the counter substrate 20 side is electrically connected through the sealing material BND.

  Specifically, as shown in FIG. 2, the edge of the scanning line Ls of each row is provided to extend at the peripheral edge above the insulating substrate 11. In addition, at the lower peripheral portion of the insulating substrate 11, end portions of the power supply voltage lines La of the respective rows are provided so as to extend. Further, the end of the data line Ld of each column is provided to extend to the left peripheral edge of the insulating substrate 11. Here, the scanning lines Ls, the power supply voltage lines La, and the data lines Ld are arranged with a predetermined pitch. Note that the end of each signal line may be provided with a connection pad wider than the width of each signal line. In this case, the connection pads are preferably staggered in even rows (or even columns) and odd rows (or odd columns) so that adjacent connection pads do not short-circuit.

  In addition, the sealing material BND interposed between the peripheral edge of the pixel array substrate 10 and the counter substrate 20 is connected to each signal line (scanning line) in a binder (adhesive solvent) for bonding and fixing the substrates together. A conductive filler (conductive particle) CFL for electrically connecting the ends of Ls, the power supply voltage line La, and the data line Ld) and a connection pad on the counter substrate 20 described later is uniformly distributed. The adhesive can be applied. Here, the sealing material BND is irradiated with a paste type that can be printed on the insulating substrate 11, a liquid type that can be applied, a thin film type, a type that solidifies the binder by heat and pressure, or ultraviolet rays. From the solidification method such as the type to be solidified, an appropriate one can be selected according to the manufacturing process. Specifically, as the sealing material BND, fine particles such as nickel or gold-plated nickel, or gold-plated acrylic or polystyrene resin or the like are dispersed in a binder such as an epoxy or synthetic rubber resin. An anisotropic conductive paste can be used. For example, “Dotite” series by Fujikura Kasei Co., Ltd., “ThreeBond 3373” by ThreeBond Co., Ltd., etc. can be applied satisfactorily.

  The counter substrate 20 is made of an insulating substrate 21 such as a glass substrate or a resin substrate, as shown in FIGS. 1A, 3A, and 3B. The pixel array connection pads 22s, 22a, and 22d are provided on the “one side” for convenience. Further, on the other side of the counter substrate 20 (on the opposite side of the bonding surface; corresponding to the back side of the light emitting device), routing wirings (connection wirings) 23s, 23a, 23d, routing wirings (external connection wirings) 25, An external circuit connection pad (external connection pad) 24 and an IC chip (control circuit, integrated circuit) 26 are provided. Further, the insulating substrate 21 penetrates from one surface side to the other surface side, and a plurality of through holes 27 for individually connecting the pixel array connection pads 22s, 22a, 22d and the routing wirings 23s, 23a, 23d. Is provided.

  The routing wirings 23s, 23a, 23d, and 25 are constituted by thin film wirings, for example. As shown in FIGS. 1 (a), 3 (a), and 3 (b), one end side of each of the routing wirings 23s, 23a, and 23d penetrates the insulating substrate 21 at the peripheral portion of the insulating substrate 21. It is connected to the pixel array connection pads 22s, 22a, 22d provided on one surface side of the insulating substrate 21 through the provided through holes 27, and the other end side is connected to the other surface of the insulating substrate 21 (insulating substrate). 21 is connected to the connection terminal of the IC chip 26 mounted on the side opposite to the one surface. That is, the pitch Pt1 at the end of the routing wiring 23s and the pitch Ps of the pixel array connection pad 22s are set to the same or substantially the same length, and the pitch Pt2 at the end of the routing wiring 23a and the pixel array connection pad 22a. The pitch Pa is set to the same or substantially the same length, and the pitch Pt3 at the end of the lead wiring 23d and the pitch Pd of the pixel array connection pad 22d are set to the same or substantially the same length. Further, one end side of the routing wiring 25 is connected to the connection terminal of the IC chip 26, and the other end side is connected to the external circuit connection pad 24.

  As shown in FIG. 3B, the pixel array connection pads 22 s, 22 a, and 22 d are regions (to which the insulating substrate 11 of the pixel array substrate 10 is bonded in the insulating substrate 21 constituting the counter substrate 20). (Hereinafter referred to as a “joining region”), which is arranged in a region where the sealing material BND is interposed when joining to the pixel array substrate 10.

  Further, the pixel array connection pads 22s, 22a, and 22d are respectively between the scanning line Ls, the power supply voltage line La, and the end portions of the data line Ld that are arranged to extend to the peripheral portion of the pixel array substrate 10 described above. Thus, they have a predetermined pitch and are arranged at positions corresponding to each other so as to be electrically connected individually via the conductive fillers CFL in the sealing material BND. That is, the pitch Ps of the pixel array connection pads 22s arranged on the counter substrate 20 and the pitch of the scanning lines Ls arranged on the peripheral edge of the pixel array substrate 10 are set to the same or substantially the same length. The pitch Pa of the connection pads 22a and the pitch of the power supply voltage lines La arranged on the periphery of the pixel array substrate 10 are set to the same or substantially the same length, and the pitch Pd of the pixel array connection pads 22d and the pixel array The pitch of the data lines Ld arranged on the peripheral edge of the substrate 10 is set to the same or substantially the same length. More preferably, the pitch Ps, the pitch Pa, and the pitch Pd are set to the same or substantially the same length. Further, the lead wirings 23s, 23a, and 23d that connect the pixel array connection pads 22s, 22a, and 22d and the IC chip 26 constitute the counter substrate 20 as shown in FIGS. 1 (a) and 3 (a). The other surface side of the insulating substrate 21 is disposed inside a region corresponding to a bonding region with the pixel array substrate 10 (insulating substrate 11).

  Further, as shown in FIG. 1A, the external circuit connection pad 24 is on the other surface side of the insulating substrate 21 constituting the counter substrate 20, and is bonded to the pixel array substrate 10 (insulating substrate 11). It is an area other than the area corresponding to the area, and is arranged at the peripheral edge of the side where the pixel array connection pads 22s, 22a, 22d are not arranged. Here, the external circuit connection pads 24 are arranged with a predetermined pitch so as to be electrically connected individually to a control circuit, a power supply circuit, etc. (all of which are not shown) provided outside the light emitting device. Has been. The external circuit connection pad 24 is connected to each wiring of the flexible wiring board connected to an external circuit (not shown).

  The IC chip 26 is an existing and commercially available integrated circuit having the form of a general-purpose IC chip. As shown in FIGS. 1A, 3A, and 3B, an opposing substrate is used. 20 is disposed on the other surface side of the insulating substrate 21 constituting the substrate 20 inside the region corresponding to the bonding region of the pixel array substrate 10. The IC chip 26 generates various signals, drive voltages, and the like based on a control signal, a power supply voltage, and the like applied from an external circuit via the external circuit connection pad 24 and the routing wiring 25, for example, and leads the wiring 23s. , 23a, 23d, the wiring lines 23s, 23a, 23d in the through hole 27, the pixel array connection pads 22s, 22a, 22d, and the sealing material BND, and the scanning line Ls disposed on the pixel array substrate 10 and the power supply voltage The driver circuit functions to be applied to the line La and the data line Ld.

  In the light emitting device according to the present embodiment, the separation distance (inter-substrate gap) G when the pixel array substrate 10 and the counter substrate 20 are joined is equal to each other in the pixel array connection pads 22s, 22a, and 22d. Is set to be smaller than the separation distance (inter-terminal space) S. Specifically, the inter-substrate gap G between the pixel array substrate 10 and the counter substrate 20 is set to, for example, 5 μm or less, while the inter-terminal space S between the adjacent pixel array connection pads 22s, 22a, and 22d is, for example, It is set to 120 μm or less.

  According to this, the pixel array substrate 10 and the counter substrate 20 are excellent using the sealing material BND including the conductive filler CFL having a particle size larger than the inter-substrate gap G and smaller than the inter-terminal space S. Can be joined. That is, by using the sealing material BND including the conductive filler CFL that satisfies such conditions, the electrical connection between the pixel array substrate 10 and the counter substrate 20 can be prevented while preventing the pixel array connection pads 22s, 22a, and 22d from being short-circuited. Connection and a desired inter-substrate gap G can be realized satisfactorily. Further, a separation distance (inter-substrate gap) G when the pixel array substrate 10 and the counter substrate 20 are bonded is set to be shorter than the height of the IC chip 26 provided on the other surface side of the counter substrate 20. For this reason, a commercially available product (general-purpose product) having a relatively large thickness can be satisfactorily applied as the IC chip 26, and the light emitting device other than the IC chip 26 can be made thin, so that the device is small overall. Can be

(Display pixel)
Next, specific examples of display pixels applicable to the light emitting device according to this embodiment will be described.
FIG. 4 is an equivalent circuit diagram showing a circuit configuration example of display pixels that are two-dimensionally arranged on the display panel according to the present embodiment. FIG. 4A is a circuit configuration example of a display pixel having a pixel driving circuit composed of two transistors and one capacitor, and FIG. 4B is composed of three transistors and one capacitor. 3 is a circuit configuration example of a display pixel having a pixel driving circuit.

  As shown in FIGS. 4A and 4B, the display pixel PIX includes a pixel drive circuit DC and an organic EL element (light emitting element) OEL. The pixel drive circuit DC has a circuit configuration including a plurality of transistors (for example, amorphous silicon thin film transistors TFT). The organic EL element OEL emits light when a light emission drive current controlled by the pixel drive circuit DC is supplied to the anode terminal.

(Configuration example 1)
Specifically, the pixel drive circuit DC illustrated in FIG. 4A includes transistors Tr11 and Tr12 and a capacitor Cs. The transistor Tr11 has a gate terminal connected to a scanning line Ls arranged in the row direction of the display region 12 (corresponding to the vertical direction in FIG. 2), and a drain terminal in the column direction of the display region 12 (FIG. 2 corresponds to the data line Ld disposed in the horizontal direction of the drawing), and the source terminal is connected to the contact N11. The transistor Tr12 has a gate terminal connected to the contact N11, a drain terminal connected to the power supply voltage line La arranged in the row direction (corresponding to the vertical direction in FIG. 2), and a source terminal connected to the contact N12. Has been. The capacitor Cs is connected between the gate terminal (contact N11) and the source terminal (contact N12) of the transistor Tr12.

  The organic EL element OEL has an anode terminal (anode electrode) connected to the contact N12 of the pixel drive circuit DC and a cathode terminal (cathode electrode), for example, a predetermined low potential power supply (reference voltage Vss; for example, ground potential Vgnd). Connected directly or indirectly.

  As shown in FIG. 2, the scanning line Ls and the data line Ld are formed so that one end of each of them extends to the peripheral edge of the insulating substrate 11. As shown in FIG. 1, at the peripheral portion, the sealing material BND, the pixel array connection pads 22s and 22d provided on the counter substrate 20 side, the routing wirings 23s and 23d in the through hole 27, and the insulating property The wiring is connected to the IC chip 26 via routing wires 23 s and 23 d on the other surface of the substrate 21.

  Here, the IC chip 26 in this configuration example has a function of, for example, a scanning driver, and applies a selection signal (selection voltage) Vsel to the scanning line Ls of each row at a predetermined timing. Thereby, the display pixels PIX in each row arranged on the pixel array substrate 10 are sequentially set to the selected state. The IC chip 26 also has a function as a data driver, for example, and applies a gradation signal (gradation voltage) Vdata corresponding to display data to the data line Ld of each column at a predetermined timing. Thereby, the display data is written at a timing synchronized with the selection state of the display pixel PIX in each row.

  Similarly to the scanning line Ls and the data line Ld, the power supply voltage line La is also formed so that one end thereof extends to the peripheral edge of the insulating substrate 11 as shown in FIG. . As shown in FIG. 1, in addition to the sealing material BND, the pixel array connection pad 22 a provided on the counter substrate 20 side, the routing wiring 23 a in the through hole 27, and the insulating substrate 21 at the peripheral portion. It is connected to the external circuit connection pad 24 via the IC chip 26 or directly through the wiring 23a on the surface. The external circuit connection pad 24 to which the power supply voltage line La is connected is directly or indirectly connected to, for example, a predetermined high potential power supply. The power supply voltage line La is connected to the sealing material BND, the pixel array connection pad 22a provided on the counter substrate 20 side, the lead-out wiring in the through hole 27, the through hole 27 and the external circuit without passing through the IC chip 26. You may connect with the external circuit connection pad 24 through the lead wiring which connects the pad 24 directly.

  Here, a predetermined voltage is applied to the power supply voltage line La to flow a light emission driving current corresponding to the display data to the anode terminal (anode electrode) of the organic EL element OEL provided in each display pixel PIX. The This voltage is set to a constant high voltage (power supply voltage Vdd) having a higher potential than the cathode terminal (reference voltage Vss applied to the cathode electrode (for example, ground potential Vgnd)) of the organic EL element OEL.

(Display pixel drive control)
The drive control operation in the display pixel PIX having the circuit configuration as shown in FIG. 4A is first performed by a clock supplied from some external circuit connection pads 24 to the IC chip 26 in a predetermined selection period. Using the scan driver function of the IC chip 26 that is operated based on a control signal such as a signal or a start signal, the routing wiring 23 s on the other surface of the insulating substrate 21, the routing wiring 23 s in the through hole 27, and the pixel array connection pad A selection voltage Vsel of a selection level (on level; for example, high level) is applied to the scanning line Ls via 22s and the sealing material BND. As a result, the transistor Tr11 is turned on and the display pixel PIX is set to the selected state.

  In synchronization with this timing, the data driver function of the IC chip 26 operated based on control signals such as digital gradation display data and clock signals supplied from some external circuit connection pads 24 to the IC chip 26. The voltage corresponding to the display data is applied to the data line Ld via the routing wiring 23d on the other surface of the insulating substrate 21, the routing wiring 23d in the through hole 27, the pixel array connection pad 22d, and the sealing material BND. A gradation voltage Vdata having a value is applied. As a result, a potential corresponding to the gradation voltage Vdata is applied to the contact N11 (that is, the gate terminal of the transistor Tr12) via the transistor Tr11, so that the transistor Tr12 is turned on in a conductive state corresponding to the potential.

  Accordingly, the reference voltage Vss (ground potential Vgnd) on the low potential side is applied to the low potential side reference voltage Vss (ground potential Vgnd) from the power supply voltage line La to which the high potential side power supply voltage Vdd is applied via the transistor Tr12 and the organic EL element OEL. Since the light emission driving current having the current value flows, the organic EL element OEL emits light with a luminance gradation corresponding to the gradation voltage Vdata (that is, display data). At this time, charges are accumulated (charged) in the capacitor Cs between the gate and the source of the transistor Tr12 based on the gradation voltage Vdata applied to the contact N11. Here, the light emitted from the organic EL element OEL of the display pixel PIX is emitted to the visual field side (lower side of the drawing in FIG. 1B) through the insulating substrate 11 constituting the pixel array substrate 10. That is, the light emitting device according to this embodiment has a bottom emission type light emitting structure.

  Next, in the non-selection period after the end of the selection period, the transistor Tr11 is turned off by applying a selection voltage Vsel of a non-selection level (off level; for example, low level) from the IC chip 26 to the scanning line Ls. Thus, the display pixel PIX is set to a non-selected state. As a result, the data line Ld and the pixel drive circuit DC are electrically disconnected. At this time, the charge accumulated in the capacitor Cs is held, so that a voltage corresponding to the gradation voltage Vdata (that is, a potential difference between the gate and the source) is maintained at the gate terminal of the transistor Tr12.

  Therefore, similarly to the light emission operation in the selected state, a predetermined light emission drive current flows from the power supply voltage line La (power supply voltage Vdd) to the organic EL element OEL via the transistor Tr12, and light is emitted with the same luminance for a predetermined period. to continue. This light emitting operation state is controlled so as to continue, for example, for one frame period until the next gradation voltage Vdata is applied (written). Then, such a drive control operation is performed on all the display pixels PIX two-dimensionally arranged on the pixel array substrate 10, for example, for each row, thereby executing an image display operation for displaying desired image information. be able to.

  In the display pixel PIX shown in FIG. 4A, the IC chip 26 adjusts (specifies) the voltage value of the gradation voltage Vdata written to each display pixel PIX according to the display data, and the pixel driving circuit DC. Thus, the circuit configuration of the voltage designation type gradation control method in which the current value of the light emission driving current flowing through the organic EL element OEL is controlled to perform the light emission operation at a desired luminance gradation is shown. The present invention is not limited to this, the current value written to each display pixel PIX is adjusted (designated) according to display data by the IC chip 26, and the current is passed to the organic EL element OEL by the pixel driving circuit DC. It may have a circuit configuration of a current designation type gradation control system in which the light emission driving current is controlled to emit light at a desired luminance gradation. In the following configuration example 2, a display pixel PIX having a pixel driving circuit DC corresponding to a current designation type gradation control method will be described.

(Configuration example 2)
Specifically, the pixel drive circuit DC illustrated in FIG. 4B includes transistors Tr21, Tr22, Tr23, and a capacitor Cs. The transistor Tr21 has a gate terminal connected to the scanning line Ls, a drain terminal connected to the power supply voltage line La, and a source terminal connected to the contact N21. The transistor Tr22 has a gate terminal connected to the scanning line Ls, a source terminal connected to the data line Ld, and a drain terminal connected to the contact N22. The transistor Tr23 has a gate terminal connected to the contact N21, a drain terminal connected to the power supply voltage line La, and a source terminal connected to the contact N22. The capacitor Cs is connected between the gate terminal (contact N21) and the source terminal (contact N22) of the transistor Tr23.

  The organic EL element OEL has an anode terminal (anode electrode) connected to the contact N22 of the pixel drive circuit DC, and a cathode terminal (cathode electrode) directly to a predetermined low potential reference voltage Vss (for example, ground potential Vgnd). Or indirectly connected.

  Each of the scanning line Ls, the data line Ld, and the power supply voltage line La is formed so that one end of each of the scanning line Ls, the data line Ld, and the power supply voltage line La extends to the peripheral edge of the insulating substrate 11. In this section, the sealing material BND, the pixel array connection pads 22s, 22d, 22a provided on the counter substrate 20 side, the routing wirings 23s, 23d, 23a in the through hole 27, and the routing on the other surface side of the insulating substrate 21 are provided. It is connected to the IC chip 26 through wirings 23s, 23d, and 23a.

  The selection voltage Vsel is applied to the scanning line Ls by the IC chip 26 at a predetermined timing, and the gradation signal (gradation voltage Vdata or gradation) corresponding to the display data is applied to the data line Ld. Current Idata). On the other hand, the power supply voltage line La is connected to the external circuit connection pad 24 via the IC chip 26 provided on the counter substrate 20 side or directly. As will be described later, a predetermined low level or high level power supply voltage Vsc is applied to the power supply voltage line La in accordance with the operating state of the display pixel PIX.

  The reference voltage Vss applied to the cathode terminal (cathode electrode) of the organic EL element OEL is a constant voltage (for example, the ground potential Vgnd), and the power supply voltage Vsc applied to the power supply voltage line La is equal to the reference voltage Vss. Set based on. That is, in the writing operation period in which the gradation voltage Vdata or the gradation current Idata corresponding to the display data is supplied to the display pixel PIX (pixel driving circuit DC), the power supply voltage Vsc set to the low level is equal to or lower than the reference voltage Vss. In the light emission operation period in which the light emission drive current is supplied to the organic EL element (light emitting element) OEL and the light emission operation is performed at the luminance gradation according to the display data, the power supply voltage Vsc set to the high level is the reference. The potential is set sufficiently higher than the voltage Vss.

(Display pixel drive control)
The drive control operation in the display pixel PIX having the circuit configuration as shown in FIG. 4B is a write operation (write operation) for holding a voltage component corresponding to display data within a predetermined one processing cycle period. (Operation period) and a light emission operation (light emission operation period) for causing the organic EL element OEL to emit light at a luminance gradation according to display data.

  First, in the writing operation (writing operation period) to the display pixel PIX, the scan driver function of the IC chip 26 is used, and a clock signal and a start signal supplied from some external circuit connection pads 24 to the IC chip 26. In response to the control signal, the IC chip 26 is connected to the scanning line Ls via the routing wiring 23s on the other surface side of the insulating substrate 21, the routing wiring 23s in the through hole 27, the pixel array connection pad 22s, and the sealing material BND. Then, a selection voltage Vsel of a selection level (on level; for example, high level) is applied. In this writing operation (writing operation period), for example, the power supply driver function of the IC chip 26 is used, and the IC is controlled by a control signal such as a clock signal supplied from some external circuit connection pads 24 to the IC chip 26. The chip 26 has a low level with respect to the power supply voltage line La via the routing wiring 23s on the other surface side of the insulating substrate 21, the routing wiring 23s in the through hole 27, the pixel array connection pad 22a, and the sealing material BND. A power supply voltage Vsc is applied, or a power supply circuit (not shown) outside the light emitting device directly connects some external circuit connection pads 24, some external circuit connection pads 24 and through holes 27. The low level power supply voltage Vsc is applied to the power supply voltage line La through the lead wiring, the pixel array connection pad 22a and the sealing material BND. To do. In synchronism with this timing, the data driver function of the IC chip 26 is used to control the IC by the control signal such as the display data of digital gradation and the clock signal supplied from some external circuit connection pads 24 to the IC chip 26. The chip 26 applies the gradation voltage Vdata to the data line Ld through the routing wiring 23d on the other surface side of the insulating substrate 21, the routing wiring 23d in the through hole 27, the pixel array connection pad 22d, and the sealing material BND. Alternatively, the gradation current Idata is supplied, and a current having a current value corresponding to the display data is supplied.

  As a result, the display pixel PIX is set to the selected state, the transistors Tr21 and Tr22 are turned on, the low-level power supply voltage Vsc is applied to the gate terminal (contact N21) of the transistor Tr23, and the source terminal of the transistor Tr23 (Contact N22) is electrically connected to the data line Ld.

  Here, the gradation voltage Vdata or the gradation current Idata supplied to the data line Ld corresponds to the low-level power supply voltage Vsc according to the luminance gradation value included in the display data written to each display pixel PIX. Since the voltage is relatively negative, the write current Ia corresponding to the gradation voltage Vdata or the gradation current Idata flows from the power supply voltage line La to the data line Ld via the display pixel PIX. As a result, a voltage level lower than the low-level power supply voltage Vsc is applied to the source terminal (contact N22) of the transistor Tr23.

  Accordingly, a potential difference is generated between the contacts N21 and N22 (that is, between the gate and source of the transistor Tr23), so that the transistor Tr23 is turned on, and the transistor Tr23, the contact N22, the transistor Tr22, and the data line Ld are connected from the power supply voltage line La. Thus, a write current Ia corresponding to the gradation voltage Vdata or the gradation current Idata flows in the direction of the IC chip 26.

  At this time, charges corresponding to the potential difference generated between the contacts N21 and N22 are accumulated in the capacitor Cs and held as a voltage component. Further, a power supply voltage Vsc having a voltage level equal to or lower than the reference voltage Vss (ground potential Vgnd) is applied to the power supply voltage line La, and the write current Ia is controlled to flow from the display pixel PIX in the direction of the data line Ld. Has been. As a result, the potential applied to the anode terminal (contact N22) of the organic EL element OEL is lower than the potential of the cathode terminal (reference voltage Vss), so that no current flows through the organic EL element OEL and the light emission operation is performed. No (non-light emitting operation).

  Next, in the light emission operation (light emission operation period) after the end of the write operation, using the scan driver function of the IC chip 26, the routing wiring 23s on the other surface side of the insulating substrate 21, the routing wiring 23s in the through hole 27, A non-selection level (low level) selection voltage Vsel is applied to the scanning line Ls via the pixel array connection pad 22s and the sealing material BND. Then, in synchronization with this timing or at a predetermined timing, for example, by using a power driver function of the IC chip 26 or a power circuit outside the light emitting device (not shown), from some external circuit connection pads 24 In response to a control signal such as a clock signal supplied to the IC chip 26, the IC chip 26 causes the routing wiring 23a on the other surface side of the insulating substrate 21, the routing wiring 23a in the through hole 27, the pixel array connection pad 22a, and the sealing material BND. A high-level power supply voltage Vsc is applied to the power supply voltage line La via

  As a result, the transistors Tr21 and Tr22 are turned off, the application of the power supply voltage Vsc to the gate terminal (contact N21) of the transistor Tr23 is cut off, and the gradation voltage Vdata to the source terminal (contact N22) of the transistor Tr23 is cut off. Alternatively, the application of the voltage level due to the pull-in operation of the gradation current Idata is cut off. At this time, since the charge accumulated in the above-described write operation is held in the capacitor Cs, the transistor Tr23 maintains the on state. Further, since the power supply voltage Vsc higher than the reference voltage Vss (ground potential Vgnd) is applied to the power supply voltage line La, the potential applied to the anode terminal (contact N22) of the organic EL element OEL is the cathode terminal. Higher than the potential (ground potential).

  Therefore, since the predetermined light emission drive current Ib flows in the forward bias direction from the power supply voltage line La to the organic EL element OEL via the transistor Tr23 and the contact N22, the organic EL element OEL performs a light emission operation. At this time, the voltage component held by the capacitor Cs corresponds to a potential difference in the case where the write current Ia corresponding to the gradation voltage Vdata or the gradation current Idata is caused to flow in the transistor Tr23. Therefore, the light emission drive that flows through the organic EL element OEL. The current Ib has a current value (Ib≈Ia) substantially equal to the write current Ia. Thereby, the organic EL element OEL emits light at a luminance gradation corresponding to the display data. Here, the light emitted from the organic EL element OEL of the display pixel PIX is emitted to the visual field side (lower side of the drawing in FIG. 1B) through the insulating substrate 11 constituting the pixel array substrate 10.

  In each of the above-described configuration examples, the circuit configuration including two or three transistors as the pixel driving circuit DC is shown, but the present invention is not limited to this embodiment, and two or more transistors are included. It may have another circuit configuration including a transistor. In addition, the case where the organic EL element OEL is applied as the light emitting element driven to emit light by the pixel driving circuit DC is shown, but the present invention is not limited to this, and any current-controlled light emitting element can be used. Other light emitting elements such as light emitting diodes may be used.

(Production method)
Next, a method for manufacturing the above-described light emitting device will be described. Here, a light emitting device having the display pixel PIX composed of the pixel driving circuit DC and the organic EL element OEL as described above will be described. In the following description, FIGS.

  In the method for manufacturing the light emitting device described above, first, the pixel array substrate 10 and the counter substrate 20 are individually manufactured. As shown in FIG. 2, the method for manufacturing the pixel array substrate 10 includes the pixel driving described above on one side of the insulating substrate 11 made of, for example, glass, quartz, or transparent resin (on the side of the bonding surface with the counter substrate 20). A plurality of display pixels PIX each including a transistor and a capacitor constituting the circuit DC, various wiring layers and interlayer insulating films, and an organic EL element OEL are two-dimensionally arranged to form a pixel array in the display region 12.

  Here, on the insulating substrate 11 on which at least the pixel array is formed, for example, an inorganic insulating film is coated to protect the surface of the display region 12 of the pixel array substrate 10. Also, the end of each signal line (scanning line Ls, power supply voltage line La, data line Ld) for applying the selection signal Vsel, gradation signals Vdata, Idata, power supply voltages Vdd, Vsc to the pixel drive circuit DC and the organic EL element OEL. As shown in FIG. 2, the portions are arranged with a predetermined pitch along each side of the peripheral portion of the insulating substrate 11, and are formed so that the upper surface thereof is exposed.

  Note that the pixel array constituting the pixel array substrate 10 is regularly formed at a plurality of locations on one surface of the mother glass, for example, and finally separated into each pixel array substrate 10 to obtain a plurality of pixel arrays. The substrate 10 is cut out.

  On the other hand, as shown in FIG. 3, the manufacturing method of the counter substrate 20 is first made on one surface side of the insulating substrate 21 made of, for example, glass, quartz, transparent resin, or the like (on the bonding surface side with the pixel array substrate 10). Pixel array connection pads 22s, 22a, and 22d are formed so as to correspond to the signal lines arranged on the peripheral edge of the pixel array substrate 10 described above. The pixel array connection pads 22s, 22a, and 22d are collectively formed by patterning a conductive film formed on the insulating substrate 21 using a sputtering method or a vapor deposition method, or by wire bonding. Formed. Accordingly, the pixel array connection pads 22s, 22a, and 22d correspond to the pitch of each signal line formed on the pixel array substrate 10 side along the peripheral edge of the bonding region of the pixel array substrate 10 in the insulating substrate 21. Are arranged as follows.

  Next, as shown in FIGS. 1A and 3, the insulating substrate 21 is etched from the other surface side, and through holes 27 are formed at positions corresponding to the arrangement positions of the pixel array connection pads 22 s, 22 a, and 22 d, respectively. Form. Here, the through holes 27 are formed so that the pixel array connection pads 22 s, 22 a, and 22 d are exposed inside the through holes 27 when viewed from the other surface side of the insulating substrate 21. Thereby, the through holes 27 are regularly arranged at a predetermined interval along the peripheral edge portion of the bonding region of the pixel array substrate 10 in the insulating substrate 21.

  Next, a conductive film is formed on the other surface side of the insulating substrate 21 by using, for example, a sputtering method or a vapor deposition method. At this time, a conductive film is also formed in the through hole 27, and the conductive film is connected to the pixel array connection pads 22s, 22a, and 22d exposed in the through hole 27. Next, by patterning this conductive film, as shown in FIGS. 1 (a) and 3 (a), a plurality of routing wires 23s, 23a, 23d, 25, and 25 are formed on the other surface side of the insulating substrate 21. External circuit connection pads 24 are collectively formed. Here, each lead-out wiring 23s, 23a, 23d is connected to each pixel array connection pad 22s, 22a, 22d formed on one surface side of the insulating substrate 21 through a through hole 27, and an IC chip to be described later. It is formed so as to have a wiring pattern extending to 26 mounting positions. Further, the plurality of lead wirings 25 and the external circuit connection pads 24 are integrally formed so as to have a wiring pattern extending from the end portion position on the other surface side of the insulating substrate 21 to the mounting position of the IC chip 26. . The external circuit connection pads 24 are arranged at a predetermined pitch suitable for connection with an external circuit.

  Next, the IC chip 26 is mounted at a predetermined position in the region corresponding to the bonding region of the pixel array substrate 10 on the other surface side of the insulating substrate 21. Here, the IC chip 26 is joined so that connection terminals (not shown) are individually connected to the end portions of the plurality of routing wires 23s, 23a, 23d, and 25 described above.

  Next, the pixel array substrate 10 and the counter substrate 20 are bonded to each other through a sealing material BND, and the pixel array (display pixel PIX) formed in the display region 12 is sealed. Specifically, for example, a paste-like uncured sealing material BND is printed on the peripheral edge of one side of the insulating substrate 11 on the pixel array substrate 10 side, and each signal line (scanning line) arranged on the peripheral edge is printed. Ls and the end of the power supply voltage line La and the data line Ld) are insulated so that the positions of the pixel array connection pads 22s, 22a and 22d provided on the one surface side of the insulating substrate 21 on the counter substrate 20 side are aligned. The conductive substrates 11 and 21 are bonded to face each other.

  Next, for example, by applying heat and pressure to the sealing material BND, the binder of the sealing material BND is expanded, and the conductive filler CFL in the sealing material BND is transferred to each signal line (scanning line Ls and power source) on the pixel array substrate 10 side. The ends of the voltage line La and the data line Ld) are brought into contact with both the pixel array connection pads 22s, 22a, and 22d on the counter substrate 20 side, and the binder is solidified to seal the pixel array substrate 10 and the counter substrate 20 together. . As a result, the pixel array in the display area 12 is sealed between the pixel array substrate 10 and the counter substrate 20, and the pixel array substrate 10 and the counter substrate 20 are electrically connected via the sealing material BND. .

  Thereafter, the mother glass constituting the plurality of insulating substrates 11 is cut for each individual insulating substrate 11, and the mother glass constituting the plurality of insulating substrates 21 is cut for each individual insulating substrate 11. A light emitting panel is obtained. Then, the pixel array substrate 10 and the counter substrate 20 cut out from the mother glass are subjected to a predetermined inspection using an inspection device such as a prober. Specifically, a probe needle is brought into contact with a plurality of external circuit connection pads 24 on the insulating substrate 21 and a predetermined signal or voltage is applied to appropriately output a signal from the IC chip 26 to each display pixel PIX. Inspections such as operation characteristics and control functions of the IC chip 26 and the display pixel PIX are performed.

(Verification of effects)
Next, functions and effects unique to the light emitting device and the manufacturing method thereof according to the present embodiment will be described in detail.
FIG. 5 is a schematic configuration diagram schematically showing a light emitting device according to the related art corresponding to the present embodiment in order to verify the operation effect of the light emitting device according to the present embodiment (hereinafter, FIG. 5). The light emitting device shown is referred to as “comparative object”). FIG. 5A is a schematic plan view of the light-emitting device according to the comparison target as viewed from the view side, and FIG. 5B is a schematic side view of the light-emitting device according to the comparison target.

  FIG. 6 is a schematic plan view illustrating an example of a pixel array substrate applied to a light emitting device according to a comparison target. Here, FIG. 6 shows the pixel array substrate applied to the light emitting device according to the comparison target as viewed from the side of the bonding surface with the sealing substrate (that is, along the VID-VID line shown in FIG. 5B). It is a schematic plan view). In this specification, “VI” is used for convenience for the symbol corresponding to the Roman numeral “6” shown in FIG. Further, in the plan view shown in FIG. 6, for convenience of explanation, only the relationship between each wiring layer disposed on the insulating substrate, the display region, and the peripheral portion is shown, and a light emitting element ( The display of the organic EL element) and the pixel driving circuit (see FIG. 4 described above) is omitted. Further, in FIG. 6, hatching is shown for convenience in order to clarify a region where an adhesive for bonding the pixel array substrate and the sealing substrate is provided.

  As illustrated in FIGS. 5A, 5 </ b> B, and 6, the light emitting device according to the comparison target includes a pixel array substrate 110 and a sealing substrate 120. The pixel array substrate 110 and the sealing substrate 120 are bonded to each other with an insulating adhesive 130 therebetween. In the pixel array substrate 110, as shown in FIG. 6, a display region 112 in which a plurality of display pixels PIX are two-dimensionally arranged is set on one surface side of the insulating substrate 111 (the bonding surface side with the sealing substrate 120). ing. In the display area 112, scanning lines Ls and power supply voltage lines La are arranged in the vertical direction (row direction) in the drawing corresponding to a plurality of two-dimensionally arranged display pixels, and the data lines Ld are in the horizontal direction in the drawing. It is arranged in the (column direction).

  On the other hand, in the peripheral region on the outer periphery of the display region 112, a plurality of line lead pads 122s, 122a, 122d, a plurality of lead wirings 123s, 123a, 123d, 125, a plurality of external circuit connection pads 124, and a driver circuit 126 are provided. And are provided. The line lead-out pads 122s, 122a, and 122d are regularly arranged on the outer periphery of the display region 112, and are connected to the ends on one end side of the scanning line Ls, the power supply voltage line La, and the data line Ld, respectively. The lead-out wirings 123s, 123a, and 123d are disposed on the outer peripheral side of the line lead-out pads 122s, 122a, and 122d, and connect the line lead-out pads 122s, 122a, and 122d to the driver circuit 126.

  The external circuit connection pads 124 are arranged outside the display area 112 of the insulating substrate 111, for example, at the end of the right side of the insulating substrate 111. The lead wiring 125 connects the external circuit connection pad 124 and the driver circuit 126. The driver circuit 126 has an IC chip form, for example, and is disposed outside the display area 112 of the insulating substrate 111.

  The sealing substrate 120 is an insulating parallel plate such as glass, and is bonded so as to face at least the display region 112 of the pixel array substrate 110. 5 and 6, the sealing substrate 120 is bonded to the pixel array substrate 110 via an insulating adhesive 130, for example, at the outer periphery of the region where the line drawing pads 122s, 122a, and 122d are arranged. . That is, the area including the display area 112 of the pixel array substrate 110 and the area where the line drawing pads 122s, 122a, and 122d on the outer periphery thereof are arranged is sealed by the sealing substrate 120.

  As described above, in the light emitting device according to the comparison target (in the prior art), the line lead connected to each of the scanning line Ls, the power supply voltage line La, and the data line Ld on the outer periphery of the display region 112 of the pixel array substrate 110. The pads 122s, 122a, 122d are arranged, and the line lead-out pads 122s, 122a, 122d and the driver circuit 126 are connected by the lead wirings 123s, 123a, 123d arranged in the outer peripheral area. That is, since the scanning line Ls, the power supply voltage line La, and the data line Ld are arranged in the display area 112 of the pixel array substrate 110, the display wirings 123s, 123a, and 123d can be arranged on the pixel array substrate 110 by displaying. It had to be arranged on the outer periphery of the region 112.

  Therefore, an area (space) for disposing the wiring lines 123s, 123a, 123d must be provided in the peripheral area of the display area 112 of the pixel array substrate 110, and the size of the frame portion of the display panel increases. The problem was that the design and size were limited. In addition, since the outer size of the pixel array substrate 110 is increased by increasing the peripheral region of the display region 112, the number of the pixel array substrates 110 cut out from one mother glass is reduced when the display panel is manufactured. As a result, there was a problem of increasing the product cost. Further, in order to make the peripheral region of the display region 112 as narrow as possible, it is conceivable to reduce the wiring width by reducing the wiring width of the lead-out wirings 123s, 123a, 123d. The voltage drop due to the increase and the voltage variation due to the non-uniform wiring length become conspicuous, and there is a problem that the display characteristics are deteriorated, the manufacturing process is increased and complicated, and the manufacturing yield is deteriorated.

  On the other hand, in the light emitting device and the manufacturing method thereof according to the present embodiment, the lead wires 23s, 23a, 23d, and 25 are provided on the counter substrate 20 that is bonded to the pixel array substrate 10 via the sealing material BND. Since the IC chip 26 which is a circuit is provided, at least one of the lead-out wirings 23 s, 23 a, 23 d, and 25 of the counter substrate 20 in a plan view scans the display area 12 of the pixel array substrate 10. Since it may overlap with at least one of the line Ls, the power supply voltage line La, and the data line Ld, it is not necessary to provide a region for arranging the routing wiring on the outer periphery of the display region 12 of the pixel array substrate 10. That is, the size of the pixel array substrate 10 and the counter substrate 20 can be reduced as much as possible.

  Therefore, according to the light emitting device and the manufacturing method thereof according to the present embodiment, the size of the frame portion of the display panel can be reduced as much as possible, so that the degree of freedom can be improved without restricting the product design and size. it can. For this reason, since the pitch between wirings can be expanded as compared with the light emitting device according to the comparison object, it is possible to widen the wiring width and reduce the wiring resistance. Therefore, there is no need to make the routing wiring multilayer in the peripheral region or to narrow the pitch between the wirings, so that the manufacturing process can be simplified and the manufacturing yield can be improved. In particular, as shown in FIGS. 4A and 4B, each display pixel PIX is provided with a pixel driving circuit DC, and is arranged in the display region 12 when performing image display using an active matrix driving method. The number and type of signal lines to be increased. Even in such a case, according to the present embodiment, by arranging the routing wirings 23s, 23a, and 23d on the counter substrate 20 side, the restrictions on the wiring pattern, the pitch between wirings, the wiring structure, etc. are greatly reduced. Since it can be mitigated, it is extremely effective in simplifying the manufacturing process and improving the manufacturing yield. In addition, since the outer size of the pixel array substrate 10 and thus the outer size of the counter substrate 20 can be reduced, the number of pixel array substrates 10 cut out from one mother glass can be increased during the manufacture of the display panel. Product cost can be reduced.

  In the present embodiment, since the IC chip 26 that is a driver circuit is mounted on the other surface side of the counter substrate 20 bonded to the pixel array substrate 10, the thickness of the IC chip body is not limited. Therefore, an inexpensive and optimum general-purpose IC chip can be selected, and an increase in product cost can be suppressed.

  In addition, in the light emitting device and the manufacturing method thereof according to the present embodiment, the routing wirings 23 s, 23 a, 23 d and the IC chip 26 serving as the driver circuit are arranged in a region corresponding to the bonding region of the pixel array substrate 10 in the counter substrate 20. By providing it inside, the degree of freedom of the wiring path (wiring pattern) can be improved, and the wiring length is substantially shortened compared to the case shown in the light emitting device as a comparison target (see FIG. 6). And can be made substantially uniform. As a result, the wiring resistance can be reduced and the voltage drop can be suppressed, the voltage variation can be suppressed, and the display characteristics can be improved. In particular, when an organic EL element is used as a light emitting element provided in a display pixel, a current (light emission driving current) is required to perform a light emitting operation. Therefore, as shown in this embodiment, reducing the resistance of the power supply voltage line La, which is a power wiring, is extremely effective in improving display characteristics and saving power in the light emitting device.

  Further, in the light emitting device and the manufacturing method thereof according to the present embodiment, the distances between the signal lines (scanning line Ls, power supply voltage line La, and data line Ld) arranged in the display area 12 of the pixel array substrate 10. Further, the separation distance (inter-terminal space) S between the pixel array connection pads 22s, 22a, 22d arranged on the counter substrate 20 is defined as the separation distance (inter-substrate gap) when the pixel array substrate 10 and the counter substrate 20 are joined. ) Set based on G.

  Therefore, when the probe inspection is performed on the pixel array substrate 10 and the counter substrate 20, the distance between adjacent signal lines and connection pads can be set relatively wide. There is no need to use a prober (inspection device) with positioning accuracy, and the probe needle and the signal line or connection pad can be brought into good contact with a simple and inexpensive inspection device, thereby suppressing the occurrence of inspection errors. Can do.

  In the present embodiment, the configuration in which only one IC chip 26 is mounted on the other surface side of the insulating substrate 21 of the counter substrate 20 has been described, but the present invention is not limited to this. For example, a circuit element such as a chip capacitor, an inductor, or a resistor may be formed or mounted on the other surface side of the insulating substrate 21 in addition to the IC chip 26 described above. According to this, even when the standardized general-purpose IC chip 26 is applied to the present embodiment, the signal and voltage characteristics can be adjusted and controlled by the circuit elements on the counter substrate 20 side.

<Second Embodiment>
Next, a second embodiment of the light emitting device according to the present invention will be described. In the present embodiment, the configuration equivalent to that of the first embodiment described above is simplified or omitted with reference to FIGS. 1 to 4 as appropriate.

  FIG. 7 is a schematic configuration diagram of a counter substrate applied to the light emitting device according to the second embodiment. FIG. 7A is a schematic plan view of the light emitting device according to the present embodiment as viewed from the back side (counter view side), and FIG. 7B is a schematic side view of the light emitting device according to the present embodiment. FIG. 7C is a schematic cross-sectional view of the counter substrate applied to the light emitting device according to this embodiment (that is, a schematic cross-sectional view showing a cross section taken along the line VIIE-VIIE shown in FIG. 7A). ). In the present specification, “VII” is used for convenience as a symbol corresponding to the Roman numeral “7” shown in FIG.

  In the first embodiment described above, the insulating substrate 21 of the counter substrate 20 is larger than the insulating substrate 11 of the pixel array substrate 10 as shown in FIGS. A configuration in which the right region of 21 protrudes beyond the right end of the insulating substrate 11 is shown. In the present embodiment, as shown in FIGS. 7A and 7B, the outer shape and the outer dimension of the insulating substrate 21 and the insulating substrate 11 are set to be the same or substantially the same, and the insulating substrate. 21 and the four sides of the insulating substrate 11 (that is, end portions of the entire circumference) are joined to each other. In addition, the external circuit connection pads 24 provided on the counter substrate 20 side are arranged on the other side of the insulating substrate 21 on the right side of the drawing, or on the substrate inner side (left side of the drawing) with respect to the end. . That is, the pixel array connection pads 22s, 22a, and 22d are arranged on the peripheral portions of the three sides on the one surface side of the insulating substrate 21, and the external circuit connection pads are disposed on the peripheral portion of the one side of the insulating substrate 21 or in the vicinity thereof. 24 are arranged. In particular, the external circuit connection pad 24 is closer to the inside than the pad (pixel array connection pad 22a in FIG. 7) that is closest to the right side of the insulating substrate 21 among the pixel array connection pads 22s, 22a, and 22d. It is preferable that it is closer to the inside than the pad closest to the right side of the insulating substrate 21.

  By having such a configuration, the area of the insulating substrate 11 of the pixel array substrate 10 and the insulating substrate 21 of the counter substrate 20 other than the display region 12 can be minimized. The size of the frame portion of the display panel can be further reduced. In particular, in the present embodiment, the display area can be formed up to the vicinity of the end of the display panel (insulating substrate 11) by reducing the frame portions on all four sides of the display panel. When a display having a larger display area is configured by two-dimensionally arranging a plurality of display panels having a structure adjacent to each other, the frame portion (that is, the non-display portion) of the boundary region between adjacent display panels is made as inconspicuous as possible. Thus, a large-screen light-emitting device with excellent display characteristics can be realized easily and inexpensively.

<Third Embodiment>
Next, a third embodiment of the light emitting device according to the present invention will be described. In the present embodiment, the configuration equivalent to that of the first embodiment described above is simplified or omitted with reference to FIGS. 1 to 4 as appropriate.
FIG. 8 is a schematic configuration diagram of a counter substrate applied to the light emitting device according to the third embodiment. FIG. 8A is a schematic plan view of the light-emitting device according to the present embodiment as viewed from the back side (counter-view side), and FIG. 8B is an opposing view applied to the light-emitting device according to the present embodiment. It is a schematic sectional drawing of a board | substrate (namely, schematic sectional drawing which shows the cross section along the VIIIF-VIIIF line shown to Fig.8 (a)). In this specification, “VIII” is used as a symbol corresponding to the Roman numeral “8” shown in FIG.

  In the first embodiment described above, as shown in FIG. 1A, a configuration in which one IC chip 26 is mounted on the other surface side of the insulating substrate 21 constituting the counter substrate 20 is shown. . In this embodiment, as shown in FIGS. 8A and 8B, a plurality of IC chips 26 and 28 are mounted on the other surface side of the insulating substrate 21. Here, the IC chip 26 has various driver functions for driving and controlling the display pixels PIX arranged on the pixel array substrate 10 as in the first embodiment described above. The IC chip 28 is, for example, a memory module, and receives various control data necessary for driving and controlling the display pixels PIX by the IC chip 26 and display data including the luminance gradation value of the organic EL element OEL. Save temporarily.

  With such a configuration, the counter substrate 20 can be enhanced in function, so that a control circuit, a memory circuit, and the like provided outside the light emitting device can be simplified. In the present embodiment, the IC chip 26 has a driver function and the IC chip 28 has a memory function. However, the present invention is not limited to this. That is, both of the IC chips 26 and 28 have individual driver functions. For example, the IC chip 26 may have a scan driver and data driver function, and the IC chip 28 may have a power driver function. However, it may have other forms. Further, as shown in the second embodiment, the insulating substrate 21 of the counter substrate 20 is formed with the same outer shape and outer dimensions as the insulating substrate 11 of the pixel array substrate 10, and has four sides (ends of the entire circumference). Part) may be configured to be joined so as to match each other.

<Fourth Embodiment>
Next, a fourth embodiment of the light emitting device according to the present invention will be described. In the present embodiment, the configuration equivalent to that of the first embodiment described above is simplified or omitted with reference to FIGS. 1 to 4 as appropriate.
FIG. 9 is a schematic configuration diagram illustrating a light emitting device according to the fourth embodiment. FIG. 9A is a schematic plan view of the light emitting device according to the present embodiment as viewed from the back side, and FIG. 9B is a schematic side view of the light emitting device according to the present embodiment.

  In the first to third embodiments described above, as shown in FIGS. 1A, 7A, and 8A, the pixel array substrate in the insulating substrate 21 constituting the counter substrate 20 is used. The configuration in which one or a plurality of IC chips 26 and 28 are arranged inside an area corresponding to 10 bonding areas (that is, an area including the display area 12) is shown. In this embodiment, as shown in FIGS. 9A and 9B, the IC chip 26 is arranged in a region other than the region corresponding to the bonding region of the pixel array substrate 10 in the insulating substrate 21 of the counter substrate 20. Has been. That is, the pixel array connection pads 22 s, 22 a, and 22 d arranged on the one surface side of the insulating substrate 21 and at the periphery of the bonding region of the pixel array substrate 10 (insulating substrate 11), The IC chip 26 mounted on the surface side and outside the region corresponding to the bonding region is connected via the routing wires 23s, 23a, and 23d disposed in the region corresponding to the bonding region. Yes. Further, the IC chip 26 is connected to the external circuit connection pads 24 arranged on the other surface side of the insulating substrate 21 through the routing wiring 25 and outside the region corresponding to the bonding region. Yes. The routing wirings 23 s, 23 a, and 23 d are formed of a transparent conductive film such as ITO at least in the display area 12, and are not visually recognized in the display area 12.

  By having such a configuration, the IC chip 26 does not exist in a region corresponding to the bonding region between the pixel array substrate 10 (insulating substrate 11) and the counter substrate 20 (insulating substrate 21). That is, since the IC chip 26 is disposed outside the area corresponding to the display area 12 of the pixel array substrate 10 in the counter substrate 20 (insulating substrate 21), the light emitted from the organic EL element OEL of the display pixel PIX. However, a light emitting device having a top emission type light emitting structure that is emitted through the insulating substrate 21 constituting the counter substrate 20 can be obtained. In this case, the upper side in FIG. 9B is set as the visual field side.

<Fifth Embodiment>
Next, a fifth embodiment of the light emitting device according to the present invention will be described. In the present embodiment, the configuration equivalent to that of the first embodiment described above is simplified or omitted with reference to FIGS. 1 to 4 as appropriate.

  FIG. 10 is a schematic configuration diagram illustrating a light emitting device according to the fifth embodiment. FIG. 10A is a schematic plan view of the light emitting device according to the present embodiment as viewed from the back side, and FIG. 10B is a schematic side view of the light emitting device according to the present embodiment. FIG. 11 is a schematic plan view showing an example of a pixel array substrate applied to the light emitting device according to this embodiment. Here, FIG. 11 shows the pixel array substrate applied to the light emitting device according to the present embodiment as viewed from the side of the bonding surface with the counter substrate (that is, along the XIG-XIG line shown in FIG. 10B). It is a schematic plan view). In this specification, “XI” is used as a symbol corresponding to the Roman numeral “11” shown in FIG. FIG. 12 is a schematic plan view showing an example of a counter substrate applied to the light emitting device according to this embodiment. Here, FIG. 12 shows the counter substrate applied to the light emitting device according to the present embodiment as viewed from the side of the joint surface with the pixel array substrate (that is, along the line XIIH-XIIH shown in FIG. 10B). It is a schematic plan view). In this specification, “XII” is used as a symbol corresponding to the Roman numeral “12” shown in FIG.

  In the first to fourth embodiments described above, a light emitting device in which a pixel driving circuit DC is provided in each display pixel PIX that is two-dimensionally arranged on the pixel array substrate 10 and image display is performed by an active matrix driving method. The configuration of was explained. In the present embodiment, the light emitting device has a configuration corresponding to a case where image display is performed by a passive matrix driving method.

  Specifically, as shown in FIG. 11, a plurality of scanning lines Ls are arranged in the row direction (vertical direction in the drawing) corresponding to the plurality of display pixels PIX that are two-dimensionally arranged in the display area of the pixel array substrate 10. A plurality of data lines Ld are arranged in the column direction (left-right direction in the drawing). For example, the scanning line Ls becomes an anode electrode of the organic EL element of each display pixel PIX, and the data line Ld becomes a cathode electrode of the organic EL element. At each intersection of the scanning line Ls and the data line Ld, an organic EL layer (not shown) serving as a light emitting layer is interposed.

  As shown in FIG. 11, for example, in the region on the left side of the display region 12 in the drawing, the scanning line Ls is arranged so that the end on one end side extends to the peripheral portion on the upper side of the insulating substrate 11. In the region on the right side of the display region 12 in the drawing, the end portion on one end side thereof is disposed so as to extend to the peripheral portion below the drawing of the insulating substrate 11. As shown in FIG. 11, the data line Ld is arranged so that, for example, the end on one end side thereof extends to the peripheral edge on the left side of the insulating substrate 11 as shown in FIG. ing. These scanning lines Ls and data lines Ld are formed on one surface side of the insulating substrate 21 of the counter substrate 20 via a sealing material BND provided on the peripheral edge of the insulating substrate 11 as shown in FIGS. The pixel array connection pads 22s and 22d provided are electrically connected. On the other surface side of the insulating substrate 21 of the counter substrate 20, an IC chip 26 is mounted inside a region corresponding to the bonding region of the pixel array substrate 10 as shown in FIGS. 10A and 12. . The pixel array connection pads 22s and 22d are connected to connection terminals (not shown) of the IC chip 26 through individual through holes 27 and lead wirings 23s and 23d, respectively.

  Thereby, also in this embodiment, the effect similar to the 1st thru | or 3rd embodiment mentioned above can be acquired. In particular, in the case of a light-emitting device that supports a passive matrix driving method, the types and number of signal lines provided in the display region 12 can be reduced as compared with an active matrix type. Accordingly, the degree of freedom with respect to the wiring pattern, the pitch between the wirings, the wiring structure, and the like of the routing wirings 23s, 23d, and 25 disposed on the counter substrate 20 can be improved, thereby simplifying the manufacturing process and improving the manufacturing yield. Can be planned.

  In the present embodiment, as shown in FIG. 11, the display area 12 is divided into left and right areas, and a scanning line in which an end portion on one end side extends to the peripheral edge of the insulating substrate 11 above the drawing. A configuration is shown in which a group of Ls and a group of scanning lines Ls extending at one end on the peripheral edge below the drawing are provided. In this case, no wiring layer is formed in the left side region DLa of the peripheral portion below the drawing and the right region DLb of the peripheral portion above the drawing. In addition, as shown in FIG. 12, regions DPa and DPb in which the pixel array connection pads 22s are not formed also occur in the peripheral portion of the counter substrate 20 (insulating substrate 21) facing these regions DLa and DLb. When such a pixel array substrate 10 and the counter substrate 20 are bonded using the sealing material BND, the scanning line Ls and the pixel array connection pad 22s are bonded via the conductive filler CFL, the scanning line Ls, In the regions DLa, DLb and DPa, DPb in which the pixel array connection pads 22s are not formed, there is a possibility that a difference or deviation occurs in the distance between the substrates (inter-substrate gap G). Therefore, for example, in the insulating substrate 11 of the pixel array substrate 10, pseudo (dummy) wiring layers are formed in the regions DLa and DLb where the scanning lines Ls are not formed, and the insulating substrate of the counter substrate 20 is formed. In FIG. 21, pseudo (dummy) connection pads may be formed in the regions DPa and DPb where the pixel array connection pads 22s are not formed. As a result, the separation distance between the substrates (inter-substrate gap) can be made uniform, so that the pixel array substrate 10 and the counter substrate 20 can be uniformly sealed to realize a good sealing state. .

In the present embodiment, the case where the pixel array substrate corresponding to the passive matrix driving method is bonded to the counter substrate 20 according to the first embodiment has been described. However, the present invention is not limited to this. Instead, it may be bonded to the counter substrate according to the second to fourth embodiments.
Further, the light emitting device in the present embodiment is a display panel. However, the present invention is not limited to this, and the light emitting device may be applied as an exposure device of a printing apparatus.

10 pixel array substrate 11 insulating substrate 12 display area 20 counter substrate 21 insulating substrate 22s, 22a, 22d pixel array connection pad 23s, 23a, 23d, 25 lead-out wiring 24 external circuit connection pad 26, 28 IC chip 27 through hole BND Seal material PIX Display pixel Ls Scan line La Power supply voltage line Ld Data line DC Pixel drive circuit OEL Organic EL element

Claims (10)

A first substrate having, on one side, a display area in which a plurality of display pixels are arrayed, and a peripheral edge where ends of a plurality of signal lines connected to each of the display pixels are exposed;
A plurality of connection pads arranged on one surface side so as to correspond to the end portions of the signal lines, and a control circuit that is provided on the other surface side and supplies a control signal for driving the display pixels to the signal lines And a second substrate having a plurality of connection wirings for individually connecting the plurality of connection pads and the control circuit,
Joining the one surface side of the first substrate and the one surface side of the second substrate, and electrically connecting the end portions of the plurality of signal lines and the plurality of connection pads individually. A member,
A light emitting device comprising:   2. The separation distance between the first substrate and the second substrate is set to be smaller than the separation distance between the plurality of connection pads on the second substrate. Light emitting device.   3. The light emitting device according to claim 1, wherein a separation distance between the first substrate and the second substrate is set to be smaller than a height of the control circuit.   4. The light emitting device according to claim 1, wherein the control circuit is disposed inside a region of the second substrate corresponding to a region to which the first substrate is bonded. apparatus.   The first substrate and the second substrate have the same outer shape and outer dimensions, and end portions of the entire circumference of the first substrate and the second substrate are aligned with each other. The light emitting device according to claim 1, wherein the light emitting device is bonded.   The plurality of signal lines are supplied with at least a plurality of scanning lines to which a selection signal for setting the display pixel in a selected state is applied and display data for driving the display pixel in a predetermined display state. The light emitting device according to claim 1, comprising a plurality of data lines.   The second substrate individually connects a plurality of external connection pads for electrically connecting to the outside of the second substrate, the plurality of external connection pads, and the control circuit on the other surface side. The light emitting device according to claim 1, further comprising a plurality of external connection wirings. A second substrate for opposing a first substrate in which a plurality of display pixels are arranged in the display region and ends of a plurality of signal lines connected to each of the display pixels are exposed on an outer periphery of the display region; Forming a plurality of connection pads arranged on one side so as to correspond to ends of the plurality of signal lines;
Forming a plurality of through holes penetrating from the one surface side to the other surface side of the second substrate;
Forming a plurality of connection wirings having one end connected to each of the plurality of connection pads on the other surface side of the second substrate via the plurality of through holes;
Connecting a control circuit to the other end of the plurality of connection wires;
Bonding the first substrate and the second substrate using a bonding member, and electrically connecting the ends of the plurality of signal lines and the plurality of connection pads individually;
A method for manufacturing a light-emitting device, comprising:   The distance between the first substrate and the second substrate when the first substrate and the second substrate are bonded is greater than the distance between the plurality of connection pads on the second substrate. The method for manufacturing a light emitting device according to claim 8, wherein the value is set to be smaller.   10. The method for manufacturing a light emitting device according to claim 8, wherein a distance between the first substrate and the second substrate is set smaller than a height of the control circuit.

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