JP5675245B2 - Load drive device - Google Patents

Description

  The present invention relates to a load driving device that controls driving and stopping of a load by arranging a plurality of semiconductor switches in parallel on a wiring connecting a power source and a load and operating each semiconductor switch in conjunction with an on / off operation. In particular, the present invention relates to a technique for immediately shutting off a semiconductor switch when an excessive current flows during the OFF operation of the semiconductor switch.

  Loads such as lamps and motors mounted on the vehicle are provided with a MOSFET (hereinafter abbreviated as “FET”) between the battery and the load, and the FET is turned on and off to drive and stop the load. I have control. In such a load driving device, when the FET is switched from on to off, noise may occur if the gate voltage is cut off instantaneously. Therefore, a technique for suppressing the generation of noise by suppressing the speed at which the gate of the FET is closed has been proposed (see, for example, Patent Document 1).

  However, when this method is used, it takes a long time (this is called “off operation time”) until the FET gate is completely closed after turning off the FET, and a short circuit failure occurs in the load circuit during the off operation time. When this occurs, since the overcurrent protection circuit does not function, the drive circuit including the FET overheats.

  On the other hand, for example, a load in which a large current flows during driving, such as a rear defogger, may not be able to withstand the steady current of the load with one semiconductor switch. In such a case, two semiconductor switches Are connected in parallel, and the semiconductor switches are operated in conjunction with each other, thereby distributing the load current to the two semiconductor switches.

  In such a drive circuit, when a plurality of semiconductor switches are switched from on to off, there is a problem that current is concentrated on one semiconductor switch and the semiconductor switch on which current is concentrated is overheated. Therefore, in order to eliminate the time lag between the on and off operations of the two semiconductor switches, for example, as described in Patent Document 2, the gates of the two FETs are shared to operate each FET simultaneously. It has been proposed to let

  However, even in this case, as described above, when the off operation time is set to be long, if a short circuit failure occurs during the off operation time, the overcurrent protection function does not operate and the drive circuit operates. The problem of overheating occurs.

JP 2009-194514 A JP 2002-369497 A

  As described above, in the conventional load control device, when the OFF operation time of the semiconductor switch (FET) is set to be long in order to reduce noise, the short-circuit failure occurs during the OFF operation time. In addition, when a plurality of semiconductor switches are connected in parallel to control ON / OFF, similarly, if the semiconductor switch OFF operation time is set to be long, the semiconductor switch is immediately connected when a short circuit failure occurs. There was a problem that could not be shut off.

  The present invention has been made to solve such a conventional problem, and the object of the present invention is to connect a plurality of semiconductor switches in parallel to control driving and stopping of a load. An object of the present invention is to provide a load driving device capable of protecting a circuit by quickly shutting off a semiconductor switch when an overcurrent occurs during an OFF operation time of the semiconductor switch.

In order to achieve the above object, the invention according to claim 1 of the present application is a relay in which a plurality of relay circuits (11, 11a) including a semiconductor switch and a control circuit for controlling on / off of the semiconductor switch are connected in parallel. In the load driving device which has a circuit group, arranges the relay circuit group in an electric circuit connecting a power source and a load, operates the semiconductor switches in conjunction with each other, and controls driving and stopping of the load. The relay circuit outputs a drive signal to the control input of the semiconductor switch when a drive command is input, and gradually reduces the drive signal output to the control input at a predetermined OFF operation time when stopped. A drive control means for turning off the drive signal; a current detection means for detecting a current flowing through the semiconductor switch; and a current detected by the current detection means exceeds a preset threshold current. A fall section and a current determination means for outputting an overcurrent detection signal, when the overcurrent detection signal from the current determination means is output, to reduce the potential of the control input of the semiconductor switch when the said drive command Input determination means for determining whether the drive command is switched from on to off, and the current determination means determines the threshold current when the input determination means determines that the drive command has been switched from on to off. It is characterized by changing to another threshold current lower than the threshold current .

The invention according to claim 5 includes a relay circuit group in which a plurality of relay circuits including a semiconductor switch and a control circuit for controlling on / off of the semiconductor switch are connected in parallel, and an electric circuit for connecting a power source and a load. In the load driving device that controls the driving and stopping of the load by operating the semiconductor switches in conjunction with each other, the relay circuits, when a driving command is input, Drive control means for outputting a drive signal to the control input of the semiconductor switch, and gradually lowering the drive signal output to the control input at a predetermined off operation time when stopped to turn off the drive signal; and the semiconductor Current detection means for detecting a current flowing through the switch, and a current determination means for outputting an overcurrent detection signal when the current detected by the current detection means exceeds a preset threshold current. If, when the overcurrent detection signal from the current determination means is output, and a fall means lowering the potential of the control input of the semiconductor switch, the falling section, the control input of the semiconductor switch After the potential is lowered, the potential of the control input is restored after a predetermined time has elapsed.

  The load driving device according to the present invention includes current detecting means for detecting a current flowing through the semiconductor switch even during the OFF operation time of the semiconductor switch, and the current detected by the current detecting means exceeds a preset threshold current. In this case, the potential of the control input of the semiconductor switch is lowered by the falling means. For this reason, even when a long OFF operation time of the semiconductor switch is set and a short circuit failure occurs during this OFF operation time, the semiconductor switch is immediately shut off to protect the entire load circuit from overcurrent. be able to.

  Also, when driving a load using multiple systems of relay circuits, even if the current concentrates on one relay circuit and excessive current flows when the relay circuit is off, the semiconductor switch is immediately shut off can do.

It is a block diagram which shows the structure of the load drive device which concerns on 1st Embodiment of this invention. It is a block diagram which shows the detailed structure of the relay circuit provided in the load drive device which concerns on 1st Embodiment of this invention. It is a timing chart which shows operation | movement when an overcurrent generate | occur | produces in the relay circuit provided in the load drive device which concerns on 1st Embodiment of this invention. It is a timing chart which shows operation | movement when an electric current concentrates on one relay circuit provided in the load drive device which concerns on 1st Embodiment of this invention. It is a timing chart which shows the operation | movement at the time of a short fault having generate | occur | produced when the electric current is concentrated on one relay circuit among two relay circuits in the past. It is a timing chart which shows the operation | movement when a short circuit failure generate | occur | produces when an electric current concentrates on one relay circuit provided in the load drive device which concerns on 1st Embodiment of this invention. It is a block diagram which shows the detailed structure of the relay circuit provided in the load drive device which concerns on 2nd Embodiment of this invention. It is explanatory drawing which shows the structure of the current determination circuit of the load drive device which concerns on 2nd Embodiment of this invention. It is a timing chart which shows operation | movement when an overcurrent generate | occur | produces in the relay circuit provided in the load drive device which concerns on 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing the configuration of the load driving device according to the first embodiment of the present invention, and FIG. 2 is a block diagram showing the detailed configuration of the relay circuit 11 shown in FIG.

  As shown in FIG. 1, in this load driving device, relay circuits 11, 11a connected in parallel to each other are provided between a power source VB and a load RL, and FETs provided in the relay circuits 11, 11a ( The driving and stopping of the load RL are controlled by operating T1) and (T1a) in an on / off manner. That is, the power supply VB (the output voltage is also indicated by the same reference symbol VB) is connected to the power supply terminals TB2 and TB2a of the relay circuits 11 and 11a, respectively, and the output terminals TB3 and TB3a are connected to one end of the load RL. The other end of the load RL is grounded. The switch terminals TB1 and TB1a of the relay circuits 11 and 11a are connected to the power source VB through resistors and grounded through the switch SW1. Therefore, when the switch SW1 is off, an H level signal is supplied to each of the switch terminals TB1 and TB1a, and when the switch SW1 is turned on, this signal is switched to the L level.

  Further, as shown in FIG. 2, between the power supply terminal TB2 and the output terminal TB3, there is an N-type MOSFET (T1) (semiconductor switch, hereinafter abbreviated as “FET”) and a current flowing through the FET (T1). A current sensor (current detection means) 17 is provided for detecting. Further, the switch terminal TB1 is connected to an input determination circuit (input determination means) 14 that detects the on / off switching state of the switch SW1 shown in FIG.

  The current sensor 17 is, for example, a shunt resistor, and the current flowing through the FET (T1) (the current flowing from the power supply terminal TB2 to the output terminal TB3) is not affected even during the OFF operation of the FET (T1). This is the type of sensor to be measured.

  Further, the relay circuit 11 is detected by a drive circuit (drive control means) 12 that outputs a drive signal to the gate of the FET (T1), a charge pump 13 that supplies a drive voltage to the drive circuit 12, and a current sensor 17. A current determination circuit (current determination means) 15 for determining whether or not the current Id flowing through the FET (T1) has reached a preset threshold current Ith based on the current value, and the current determination circuit 15 When it is determined that Id has reached the threshold current Ith, a falling circuit (falling means) 16 that lowers the gate voltage of the FET (T1), a negative circuit NOT1, and an AND circuit AND1 are provided. .

  Since the relay circuit 11a has the same configuration as the relay circuit 11, the description of the configuration is omitted. At this time, the suffix “a” is attached to each component of the relay circuit 11a.

  Next, the operation of the load driving device according to the first embodiment will be described.

[Basic operation]
When the switch SW1 shown in FIG. 1 is turned on, signals supplied to the two switch terminals TB1 and TB1a are switched from the H level to the L level. Since the two relay circuits 11 and 11a operate in the same manner, only the operation of the relay circuit 11 will be described below.

  When an L level signal is supplied to the switch terminal TB1, the input determination circuit 14 shown in FIG. 2 outputs an H level signal for turning on the FET (T1). At this time, the output signal of the current determination circuit 15 is L level, the output signal of the NOT circuit NOT1 is H level, and the output signal of the AND circuit AND1 is H level.

  Therefore, since the H level signal output from the AND circuit AND1 is supplied to the drive circuit 12, the drive circuit 12 outputs the voltage output from the charge pump 13 to the gate of the FET (T1). (T1) is turned on.

  At the same time, since the FET (T1a) of the relay circuit 11a is turned on, the output voltage VB of the power supply VB shown in FIG. 1 is applied to the load RL via the two systems of relay circuits 11 and 11a, and the load RL Drive.

  Thereafter, when the switch SW1 is turned off, an H level signal is supplied to each of the switch terminals TB1 and TB1a, so that the output signal of the input determination circuit 14 becomes an L level. When an L level signal is supplied from the input determination circuit 14, the drive circuit 12 gradually decreases the voltage supplied to the gate of the FET (T1), and after the preset off operation time has elapsed, the FET (T1) Control the gate voltage to zero. As a result, the FETs (T1) and (T1a) are both turned off, and the load RL is stopped.

[Operation when a short circuit failure occurs during the OFF operation time]
Next, an operation when a short circuit fault occurs in the load circuit when the FET (T1) is turned off will be described with reference to a timing chart shown in FIG.

  When the switch SW1 is turned on at time t0 shown in FIG. 3, as shown in FIG. 3B, the gate voltage VG of the FET (T1) rises to reach “VS + 10V” (VS is the source voltage), and the FET ( The current Id flowing in T1) rises and stabilizes at a steady current. Thereafter, when the switch SW1 is turned off at time t1, the gate voltage VG gradually decreases at time t2 after the lapse of Δt, and accordingly, the current Id flowing through the FET (T1) gradually decreases.

When a short circuit fault occurs in the load circuit at time t3 during the OFF operation time of the FET (T1), the current Id increases rapidly, and this current is detected by the current sensor 17 shown in FIG. Is done. At this time, as described above, the current sensor 17 is a shunt resistor or the like and is not affected by the operation of the FET (T1), so that the current Id can be accurately detected.

  Thereafter, when the current Id detected by the current sensor 17 reaches a preset threshold current Ith (time t4 in FIG. 3), the current determination circuit 15 switches the output signal from the L level to the H level. As a result, the falling circuit 16 is turned on to connect the gate of the FET (T1) to the output terminal TB3. As a result, the gate voltage VG of the FET (T1) is lowered to the source voltage, so that the FET (T1) is instantaneously turned off.

  For this reason, the current Id flowing through the FET (T1) is cut off, and the load circuit can be protected from overcurrent. Thereafter, when the predetermined time elapses and time t5 is reached, the fall circuit 16 switches from on to off, the connection state between the gate of the FET (T1) and the terminal TB3 is released, and the initial state is restored. That is, the fall circuit 16 lowers the gate potential of the FET (T1), and then restores the gate potential after a predetermined time has elapsed.

[Operation when current concentrates on one relay circuit during parallel drive]
Next, an operation when current is concentrated on one FET (T1) when two FETs (T1) and (T1a) are driven in parallel will be described with reference to a timing chart shown in FIG. .

  When the switch SW1 is turned on at time t10 shown in FIG. 4, both the gate voltage VG of the FET (T1) and the gate voltage VGa of the FET (T1a) increase as shown in FIGS. The current Id flowing through the FET (T1) and the current Ida flowing through the FET (T1a) both rise.

  Here, when the current is concentrated on the relay circuit 11 side and a large part of the entire load current is biased to the FET (T1) side, if the switch SW1 is turned off at time t11, the current at time t12. When the current Id flowing through the FET (T1) reaches the threshold current Ith, the fall circuit 16 of the relay circuit 11 operates to turn off the FET (T1) and immediately cut off the current Id. Thereafter, the gate voltage VG of the FET (T1) becomes zero at time t13.

  Further, since the current Id flowing through the FET (T1a) increases due to the interruption of the current Id flowing through the FET (T1), when the current Ida reaches the threshold current Ith at time t14, the FET (T1a) Is turned off, so that the current Ida is cut off. Therefore, both the relay circuit 11 and the relay circuit 11a can be protected from overcurrent. In this way, even when a current bias occurs in the two FETs (T1) and (T1a) arranged in parallel and the current value increases during the off-operation period of each FET (T1) and (T1a), it is ensured. The load circuit can be protected from overcurrent.

[When a short circuit failure occurs during the OFF operation in which current is concentrated in one relay circuit]
Next, FIG. 5 and FIG. 6 show the operations when current concentrates on one FET (T1a) and a short circuit fault occurs in the load circuit when each relay circuit 11, 11a is turned off. The description will be given with reference. FIG. 5 is a timing chart showing the operation when the overcurrent protection function of the present invention is not provided (conventional case), and FIG. 6 is a timing chart showing the operation when the overcurrent protection function of the present invention is provided. It is.

  First, the operation when the overcurrent protection function is not provided will be described with reference to FIG. When the switch SW1 is turned on at time t20, the gate voltage VG of the FET (T1) and the gate voltage VGa of the FET (T1a) gradually increase, and accordingly, the currents Id and Ida, and the load current obtained by adding them. IL gradually increases. When the switch SW1 is turned off at time t21, the gate voltage VG of the FET (T1) gradually decreases, and the current Id starts to decrease from time t22 and becomes almost zero at time t23.

  Further, the timing at which the gate voltage VGa of the FET (T1a) decreases from the gate voltage VG of the FET (T1) is delayed, and the current concentrates on the FET (T1a), so the current Ida increases after the time t22. And convergence is delayed. When a short circuit fault occurs in the load circuit at time t23, the current Ida increases greatly after that because the FET (T1a) is not completely turned off. As a result, a large current flows through the load RL, and the elements and wirings constituting the circuit are overheated.

  Next, the operation when the overcurrent protection function of the present invention is provided will be described with reference to FIG. When the switch SW1 is turned on at time t30, the gate voltage VG of the FET (T1) and the gate voltage of the FET (T1a) gradually increase, and accordingly, the currents Id and Ida, and the load current IL obtained by adding these currents. Gradually increases. When the switch SW1 is turned off at time t31, the gate voltage VG of the FET (T1) gradually decreases, and the current Id starts decreasing from time t31 and converges to zero after time t33.

  Further, since the current is concentrated in the relay circuit 11a, the rate at which the gate voltage VGa of the FET (T1a) is lower than the gate voltage VG of the FET (T1) becomes slower. When a short circuit fault occurs in the load circuit at time t32, the current Ida increases rapidly. Thereafter, when the threshold current Ith is reached at time t33, the FET (T1a) is turned off and the current Ida is cut off. Thus, even if a short circuit failure occurs in the load circuit during the off operation period of the two FETs (T1) and (T1a) arranged in parallel, the FET (T1) and (T1a) are surely cut off to load The circuit can be protected.

  In other words, in the conventional load driving circuit, when the switch SW1 is turned off, the overcurrent detection function does not operate and the overcurrent during the off operation period cannot be detected. Since a shunt resistor is used as the current sensor 17, even when the switch SW1 is turned off, the currents flowing through the FETs (T1) and (T1a) are detected, and when the occurrence of overcurrent is detected, each FET (T1 ), (T1a) can be reliably cut off to protect the entire load circuit from overheating.

  Thus, in the load driving device according to the first embodiment, when the load RL is driven using the two systems of relay circuits 11 and 11a, the current sensor 17 that detects the current of the FET (T1) is provided, When it is detected that the current value detected by the current sensor 17 has reached the threshold current Ith, the FET (T1) is configured to be cut off, so that a short-circuit failure occurs during the OFF operation period of the FET (T1). Even if it occurs, the overcurrent can be detected reliably and the FET (T1) can be shut off. Even when current concentrates on one FET and only one FET becomes overcurrent, the FET (T1) is cut off when the current value detected by the current sensor 17 reaches the threshold current Ith. Thus, the load circuit can be protected from overheating.

  Further, unlike the prior art, since it is not necessary to provide a wiring for sharing the gates of the FETs (T1) and (T1a), the device configuration can be simplified. Furthermore, even if the FETs (T1) and (T1a) vary and the current is biased, if the biased current increases, the circuit can be reliably cut off and protected from overheating.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. The overall configuration diagram is the same as the block diagram shown in FIG. FIG. 7 is a block diagram showing a configuration of the relay circuit 11 ′ according to the second embodiment. As shown in the figure, the relay circuit 11 ′ is different from the relay circuit 11 shown in FIG. 2 only in that the output signal of the input determination circuit 14 is supplied to the current determination circuit 15.

  In the second embodiment, as shown in FIG. 8A, the current determination circuit 15 includes a power supply E1 capable of changing a voltage corresponding to the threshold current Ith and a comparator CMP1. . The comparator CMP1 compares the current Id detected by the current sensor 17 with the threshold current Ith output from the power source E1, and outputs an overcurrent determination signal when Id> Ith.

  Further, the current determination circuit 15 sets the threshold current to Ith2 (another threshold current) during the time period when the drive command is switched from on to off from the input determination circuit 14. That is, as shown in FIG. 8B, by changing the output voltage of the power supply E1, the threshold current is set to Ith1 in the normal state, and the threshold current is set to Ith1 during the time period when the FET (T1) is switched from on to off. Smaller than Ith2.

  Hereinafter, the operation of the relay circuit 11 ′ in the load driving device according to the second embodiment will be described with reference to the timing chart shown in FIG. 9. As shown in FIG. 9 (a), when the switch SW1 is turned on at time t40, as shown in FIG. 9 (b), the gate voltage VG of the FET (T1) starts to rise. The current Id increases. At this time, as indicated by reference numeral S41, the threshold current set by the current determination circuit 15 is Ith1.

  Thereafter, when the switch SW1 is turned off at time t41, the gate voltage VG of the FET (T1) gradually decreases, and the current Id also gradually decreases accordingly. Further, since the input determination circuit 14 supplies a command signal indicating that the FET (T1) has been switched from on to off to the current determination circuit 15, the current determination circuit 15 changes the threshold current from Ith1 to Ith2. .

  When a short circuit fault occurs in the load circuit at time t42, the current Id increases rapidly. When the threshold current Ith2 is reached at time t43, an overcurrent detection signal is output from the current determination circuit 15, and the fall circuit 16 By supplying this overcurrent detection signal, the gate of the FET (T1) and the output terminal TB3 are connected. For this reason, since the gate voltage of the FET (T1) becomes substantially equal to the source voltage, the FET (T1) is cut off. As a result, the current flowing through the FET (T1) immediately converges to zero as indicated by Id1. Thereafter, the fall circuit 16 is turned off at time t45.

  By setting in this way, when the off operation time is set to be long, and an overcurrent occurs in a time zone in which the FET (T1) is switched from on to off, a lower threshold current is set with reference to Ith2. Since the FET (T1) is cut off, it is possible to protect the load circuit by cutting off the FET (T1) at an earlier time when an overcurrent occurs.

  If the threshold current is not changed to Ith2 and Ith1 is continued, the threshold current Ith is reached at time t44 as shown by current Id2, and the timing at which the FET (T1) is cut off is delayed.

  Besides, the threshold current is set to Ith1, which is a large value, except during the time period in which the FET (T1) is switched from on to off. For example, when the rush current flows when the FET (T1) is on, Can be prevented from being erroneously determined as a short circuit fault, and the accuracy of overcurrent detection can be improved.

  In the second embodiment, the example in which the threshold current is changed to two stages of Ith1 and Ith2 has been described. However, it is possible to set the condition and change the threshold current to three or more stages.

  The load driving device of the present invention has been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each part is replaced with an arbitrary configuration having the same function. Can do.

  For example, in each of the above-described embodiments, an example in which two relay circuits are arranged has been described. However, the present invention is not limited to this, and a configuration in which three or more relay circuits are provided may be employed. In this case, it can be achieved by providing three or more relay circuits shown in FIG. 2 or 7 in parallel.

  Further, in each of the above-described embodiments, the example of controlling the load mounted on the vehicle has been described. However, the present invention is not limited to this and is used for controlling a DC power supply and other circuits having a load. Can do.

  In each of the above-described embodiments, the MOSFET is described as an example of the semiconductor switch. However, the present invention is not limited to this, and other semiconductor switches such as an IGBT can be used.

  The present invention can be used when a load is driven by connecting a plurality of semiconductor switches in parallel.

11, 11a, 11 ′ Relay circuit 12 Drive circuit 13 Charge pump 14 Input determination circuit 15 Current determination circuit 16 Falling circuit 17 Current sensor VB power supply TB1, TB1a Switch terminal TB2, TB2a Power supply terminal TB3, TB3a Output terminal RL Load T1, T1a MOSFET (semiconductor switch)
AND1 AND circuit NOT1 Negative circuit CMP1 Comparator

Claims (2)

A relay circuit group having a plurality of relay circuits connected in parallel with a semiconductor switch and a control circuit for controlling on / off of the semiconductor switch, and arranging the relay circuit group in an electric circuit connecting a power source and a load, In the load driving device that operates the semiconductor switches in conjunction with each other to control the driving and stopping of the load,
Each of the relay circuits is
When a drive command is input, a drive signal is output to the control input of the semiconductor switch. When the drive command is stopped, the drive signal output to the control input is gradually reduced over a predetermined OFF operation time to turn off the drive signal. Drive control means, and
Current detection means for detecting a current flowing through the semiconductor switch;
Current determination means for outputting an overcurrent detection signal when the current detected by the current detection means exceeds a preset threshold current;
When an overcurrent detection signal is output from the current determination unit, a falling unit that reduces the potential of the control input of the semiconductor switch;
Input determination means for determining ON / OFF of the drive command,
The current determination unit changes the threshold current to another threshold current lower than the threshold current when the input determination unit determines that the drive command has been switched from on to off. A load driving device. A relay circuit group having a plurality of relay circuits connected in parallel with a semiconductor switch and a control circuit for controlling on / off of the semiconductor switch, and arranging the relay circuit group in an electric circuit connecting a power source and a load, In the load driving device that operates the semiconductor switches in conjunction with each other to control the driving and stopping of the load,
Each of the relay circuits is
When a drive command is input, a drive signal is output to the control input of the semiconductor switch. When the drive command is stopped, the drive signal output to the control input is gradually reduced over a predetermined OFF operation time to turn off the drive signal. Drive control means, and
Current detection means for detecting a current flowing through the semiconductor switch;
Current determination means for outputting an overcurrent detection signal when the current detected by the current detection means exceeds a preset threshold current;
A falling means for lowering the potential of the control input of the semiconductor switch when an overcurrent detection signal is output from the current determination means ,
The load driving device according to claim 1, wherein the falling means lowers the potential of the control input of the semiconductor switch and then returns the potential of the control input to the original after a predetermined time has elapsed .

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