JP5866229B2 - Overcurrent protection circuit and overcurrent protection method - Google Patents

Description

  The present invention relates to an overcurrent protection circuit and an overcurrent protection method.

  In order to prevent the current supplied to the load from becoming an overcurrent, an overcurrent protection circuit may be provided in the power line to the load. Such an overcurrent protection circuit cuts off the current supply to the load when an overcurrent state occurs.

  In order to cut off the current to the load or the like, a field effect transistor (FET) may be used as a switch. In such an overcurrent protection circuit, it is necessary to reduce the resistance component as much as possible by connecting FETs having a small on-resistance in parallel in order to reduce power loss generated in the FET in a normal state.

  However, for example, in a small package FET, there is a small on-resistance and allowable loss. Also, even with FETs of the same model number, the threshold voltage and the like are different due to individual differences, so that the operation timing does not completely match, and current may concentrate on one FET. In such a case, the FET may be damaged by burning or the like.

  In Japanese Patent Application Laid-Open No. 2007-288356, two semiconductor switch devices are connected in parallel in a current path between a power source and a load, and a combined sense current of sense currents output from each semiconductor switch device is shared by a common RC parallel circuit. A power supply control device is disclosed in which each semiconductor switch device detects a current abnormality by comparing the terminal voltage of its RC parallel circuit with a divided voltage as a threshold voltage.

JP 2007-288356 A

  However, in the power supply control device in the above-mentioned patent document, if the allowable loss of the two semiconductor switch devices is large or small, current may be concentrated on the semiconductor switch device with small allowable loss, and the semiconductor switch device in which current is concentrated It may have been damaged.

  Accordingly, a main object of the present invention is to provide an overcurrent protection circuit and an overcurrent protection method capable of controlling power supply to a load without being damaged even if the switches have different allowable losses.

  In order to solve the above problem, an overcurrent protection circuit provided in a power line to a load is provided in the power line, and includes a first switch having a large allowable loss and a second switch having a smaller allowable loss than the first switch. Switches connected in parallel, a current detection circuit that detects a current to the load and outputs a current detection signal, and whether or not the current to the load is in an overcurrent state based on the current detection signal And a control drive unit that turns off the first switch prior to the second switch when it is in an overcurrent state.

  Further, the overcurrent protection method provided in the power line to the load includes a switch unit in which a first switch having a large allowable loss and a second switch having a small allowable loss than the first switch are connected in parallel. A current detection procedure for detecting the current flowing in the power line to the load and outputting a current detection signal; and an overcurrent determination procedure for determining whether the current to the load is in an overcurrent state based on the current detection signal; And a delay procedure for making the first switch off operation slower than the second switch off operation when the current to the load is in an overcurrent state.

  According to the present invention, since the operation timings of the first switch and the second switch are adjusted, even when the power loss between the first switch and the second switch is different, the power supply to the load is not damaged. Can be controlled.

It is a block diagram of the overcurrent protection circuit concerning this invention. It is a block diagram of a control drive part. FIG. 6 is a diagram illustrating operation timing of the overcurrent protection circuit, where (a) is a timing chart of an overcurrent state signal, (b) is a timing chart of a first drive signal, (c) is a timing chart of a second drive signal, and (d) ) Is a timing chart of the current flowing through the load.

  An embodiment of the present invention will be described. FIG. 1 is a block diagram of an overcurrent protection circuit 2 according to the present embodiment. The overcurrent protection circuit 2 is inserted into a power line 6 that connects the power source 4 and the load 5 and operates.

  The overcurrent protection circuit 2 includes a switch unit 10, a current detection circuit 11, and a control drive unit 12. The current detection circuit 11 detects a current flowing through the load 5 and outputs it to the control drive unit 12 as a current detection signal G1. The switch unit 10 is formed by connecting in parallel a first switch 10a having a large allowable loss and a second switch 10b having a small allowable loss and on-resistance. For example, the first switch 10a and the second switch 10b may be FET (Field Effect Transistor). Note that the expression “large or small” of the allowable loss means that the allowable loss is not the same between the first switch 10a and the second switch 10b, but has a relatively large relationship. The same applies to the “on / off” of the on-resistance.

  The control drive unit 12 includes an overcurrent determination unit 12a, a first drive signal generation unit 12b, and a second drive signal generation unit 12c. Then, when the current detection signal G1 from the current detection circuit 11 is larger than a preset value, the overcurrent determination unit 12a determines that the overcurrent state occurs and generates the overcurrent state signal G2 as the first drive signal. To the unit 12b and the second drive signal generator 12c. The first drive signal generator 12b generates a first drive signal G3 based on the overcurrent state signal G2 and outputs the first drive signal G3 to the first switch 10a. The second drive signal generation unit 12c generates a second drive signal G4 based on the overcurrent state signal G2 and outputs the second drive signal G4 to the second switch 10b. The first switch 10a and the second switch 10b are operated by the first drive signal G3 and the second drive signal G4.

  FIG. 2 is a detailed block diagram of the control drive unit 12. As described above, the control drive unit 12 includes the overcurrent determination unit 12a, the first drive signal generation unit 12b, and the second drive signal generation unit 12c. The first and second drive signal generation units 12b and 12c include timing adjustment circuits 21a and 22a and drive circuits 21b and 22b, respectively.

  When the current detection signal G1 is greater than a preset value, the overcurrent determination unit 12a determines that the overcurrent state is present and outputs the overcurrent state signal G2 to the timing adjustment circuits 21a and 22a. In the following description, when the normal current state (in-rated current state) changes to the overcurrent state, the signal level of the overcurrent state signal G2 changes from the “H” level to the “L” level. The timing adjustment circuits 21a and 22a may be configured to cause a delay in a signal by forming a wiring using a parasitic capacitance or the like, for example.

  The drive circuits 21b and 22b amplify the signals from the timing adjustment circuits 21a and 22a and output the amplified signals to the switch unit 10. When the switch unit 10 can be directly driven by signals from the timing adjustment circuits 21a and 22a, the drive circuits 21b and 22b are not necessary. That is, the drive circuits 21 b and 22 b form an interface between the control drive unit 12 and the switch unit 10.

  Next, adjustment of the output timing of the first drive signal G3 and the second drive signal G4 by the timing adjustment circuits 21a and 22a will be described with reference to FIG. 3 is a diagram showing the operation timing of the overcurrent protection circuit 2. FIG. 3A is a timing chart of the overcurrent state signal G2, FIG. 3B is a timing chart of the first drive signal G3, and FIG. ) Is a timing chart of the second drive signal G 4, and FIG. 3D is a timing chart of the current flowing through the load 5.

  When the power line 6 is turned on, the first drive signal G3 is output at an earlier timing than the second drive signal G4 (see FIG. 3B). In FIG. 3B, this timing difference is shown as δ2. When the first drive signal G3 reaches the level P2, the first switch 10a having a large allowable loss is turned on first to make the power line 6 conductive. Thereafter, the second switch 10b having a small allowable loss is turned on. Therefore, it is possible to supply a current to the load 5 while preventing damage to the second switch 10b having a small allowable loss (see FIG. 3D).

  On the other hand, when the power line 6 is cut off, the first drive signal G3 is output at a timing later than the second drive signal G4 (see FIG. 3C). In FIG. 3C, this timing difference is shown as δ1. When the second drive signal G4 reaches the level P1, the second switch 10b having a small allowable loss is turned off. Since this state is a state in which the first switch 10a is turned on, the power line 6 remains in a conductive state. Thereafter, after the second switch 10b is turned off, the first switch 10a having a large allowable loss is turned off. In this state, the power line 6 is cut off. Therefore, current supply to the load 5 can be cut off while preventing damage to the second switch 10b having a small allowable loss (see FIG. 3D).

  As a result, when the current to the load 5 is cut off, the first switch with a large allowable loss is turned off last, so that the current to the load 5 is exhibited while preventing damage to the second switch with a small allowable loss. In addition, when supplying current to the load 5, the first switch having a large allowable loss is turned on first, so that the current to the load 5 is prevented while preventing damage to the second switch having a small allowable loss. Can be supplied.

  In the above description, the overcurrent state is avoided by opening and closing the power line, but the present invention is not limited to this description. That is, an overcurrent state may be avoided from the viewpoint of load protection. In general, in a transistor such as an FET, the resistance between the source and the drain (referred to as SD resistance) varies depending on the gate voltage. Therefore, in the overcurrent state, by increasing the SD resistance, it is possible to increase the impedance viewed from the power source 4 and suppress the current flowing through the load.

  For example, in FIG. 2C, when the second drive signal G4 reaches the threshold value of the second switch 10b, the second switch 10b is turned off. In this state, the current flowing through the power supply line 6 is supplied via the first switch 10a. And if the signal level of the 1st drive signal G3 becomes small, the resistance between SD of the 1st switch 10a will increase. As a result, since the impedance viewed from the power source 4 increases, the current value supplied from the power source 6 decreases. That is, an overcurrent state is avoided. This means that an overcurrent state can be avoided without interrupting the current supply to the load 5. In order to achieve this function, the first drive signal G3 and the second drive signal G4 are required to be signals that do not change in a pulse but change in a sweep with a predetermined inclination.

  In the above description, the current detection circuit is provided at the rear stage of the switch unit, but may be provided at the front stage of the switch unit. The control drive unit may use a functional element such as a microcomputer.

DESCRIPTION OF SYMBOLS 2 Overcurrent protection circuit 4 Power supply 5 Load 6 Power line 10 Switch part 10a 1st switch 10b 2nd switch 11 Current detection circuit 12 Control drive part 12a Overcurrent judgment part 12b 1st drive signal generation part 12c 2nd drive signal generation part 21a, 22a Timing adjustment circuit 21b, 22b Drive circuit

Claims (7)

An overcurrent protection circuit provided in the power line to the load,
A switch unit provided in the power line and formed by connecting in parallel a first switch having a large allowable loss and a second switch having a smaller allowable loss than the first switch;
A current detection circuit that detects a current to the load and outputs a current detection signal;
A control drive unit that determines whether or not the current to the load is in an overcurrent state based on the current detection signal, and turns off the second switch before the first switch if the current is in an overcurrent state. And an overcurrent protection circuit. The overcurrent protection circuit according to claim 1,
The overcurrent protection circuit, wherein the control drive unit turns on the first switch before the second switch when supplying current to the load. The overcurrent protection circuit according to claim 1 or 2,
The overcurrent protection circuit, wherein the second switch has a smaller on-resistance than the first switch. The overcurrent protection circuit according to any one of claims 1 to 3,
A first timing adjustment circuit for delaying an output of a first drive signal for driving the first switch by a predetermined time from an output of a second drive signal for driving the second switch when stopping the current supply to the load; Prepared,
An overcurrent protection circuit comprising a second timing adjustment circuit that delays the output of the second drive signal by a predetermined time from the output of the first drive signal when starting to supply current to a load. The overcurrent protection circuit according to any one of claims 1 to 4,
An overcurrent protection circuit comprising a drive circuit that interfaces between the switch unit and the control drive. An overcurrent protection method provided in a power line to a load,
A current detection signal is obtained by detecting a current flowing in a power line to a load provided with a switch unit in which a first switch having a large allowable loss and a second switch having a smaller allowable loss than the first switch are connected in parallel. Current detection procedure to output;
An overcurrent determination procedure for determining whether or not the current to the load is in an overcurrent state based on the current detection signal;
A delay procedure for delaying the off operation of the first switch from the off operation of the second switch when the current to the load is in an overcurrent state. The overcurrent protection method according to claim 6,
The delay procedure is:
An overcurrent protection method comprising a step of turning on the first switch earlier than the turning on of the second switch when starting to supply current to the load.

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