TWI476559B - Over current protection circuit and operation method thereof - Google Patents
Over current protection circuit and operation method thereof Download PDFInfo
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本發明係關於過電流保護電路，且特別是有關於利用電流比較之過電流保護電路和其操作方法。The present invention relates to overcurrent protection circuits, and more particularly to overcurrent protection circuits that utilize current comparisons and methods of operation thereof.
電流驅動電路係依據一輸入電壓來產生一個大電流，然而，為了承受這個大電流，該電流驅動電路之一輸出級會被設計成具有極大的面積，換句話說，該輸出級的驅動電晶體會具有極高的長寬比(aspect ratio)。然而，若因電子裝置於啟動、或負載電路變動，而在動態之過程中，造成瞬間之大電流，不僅會影響整個電子裝置之正常工作，甚至導致整個系統的損害。因此，需於電子裝置中設計適當之過電流保護電路。The current driving circuit generates a large current according to an input voltage. However, in order to withstand this large current, one of the output stages of the current driving circuit is designed to have a large area, in other words, the driving transistor of the output stage. Will have a very high aspect ratio. However, if the electronic device is activated, or the load circuit changes, in the process of dynamic, causing a large instantaneous current, not only affects the normal operation of the entire electronic device, but even causes damage to the entire system. Therefore, it is necessary to design an appropriate overcurrent protection circuit in the electronic device.
傳統上，係利用設定一限制電流來防止過電流損壞整個系統達成過電流保護之目的，依此設計，最大之輸出驅動電流為此限制電流，因此，即便負載只有在短暫之瞬間需要大於此限制電流之驅動電流時，因為限制電流之設定，將會導致輸出之瞬間無法穩定在預期之電壓。Traditionally, it has been used to set a limiting current to prevent overcurrent from damaging the entire system to achieve overcurrent protection. According to this design, the maximum output driving current limits the current, so even if the load needs to be greater than this limit only for a short period of time. When the current is driven by the current, the setting of the current limit will cause the output to be unstable at the expected voltage.
是故，如何對一電流驅動電路提供一種有效而穩定的過電流保護電路即成為需考量的課題。Therefore, how to provide an effective and stable overcurrent protection circuit for a current drive circuit has become a subject to be considered.
本發明之一目的在於提供一種有效而穩定的過電流保 護電路。One of the objects of the present invention is to provide an effective and stable overcurrent protection. Protection circuit.
根據本發明之一態樣，一種過電流保護電路，具有一感應電路、一比較電路以及一電流限制電路。感應電路，與一電流路徑之一控制開關耦接，用以輸出一感應電流，其中該感應電流對應於流經該電流路徑之電流。比較電路耦接該感應電路，用以將該感應電流與一參考電流比較，以輸出一控制信號。電流限制電路，耦接該比較電路以及該控制開關，根據該控制信號，產生一切換信號切換該控制開關以中斷或開啟流經該電流路徑之電流。According to one aspect of the invention, an overcurrent protection circuit has an inductive circuit, a comparison circuit, and a current limiting circuit. The sensing circuit is coupled to a control switch of a current path for outputting an induced current, wherein the induced current corresponds to a current flowing through the current path. The comparison circuit is coupled to the sensing circuit for comparing the induced current with a reference current to output a control signal. The current limiting circuit is coupled to the comparison circuit and the control switch, and generates a switching signal according to the control signal to switch the control switch to interrupt or turn on a current flowing through the current path.
在一實施例中，控制開關更包括一第一電晶體。感應電路更包括一第二電晶體具有一閘極與該第一電晶體之閘極耦接。比較電路更包括：由一第三電晶體以及一第四電晶體組成之一第一電流鏡，具有一第一輸入端以及一第一輸出端，其中該第一輸入端接收該感應電流以於該第一輸出端產生一第一輸出電流；由一第五電晶體以及一第六電晶體所組成一第二電流鏡，具有一第二輸入端以及一第二輸出端，該第二輸出端與該第一輸出端共同耦接於一共接點上，其中該第二輸入端接收該參考電壓以於該第二輸出端產生一第二輸出電流。電流限制電路更包括：一第七電晶體，具有一閘極端與該共接點耦接，一輸出端產生該切換信號切換該第一電晶體。In an embodiment, the control switch further includes a first transistor. The sensing circuit further includes a second transistor having a gate coupled to the gate of the first transistor. The comparison circuit further includes: a first current mirror composed of a third transistor and a fourth transistor, having a first input end and a first output end, wherein the first input end receives the induced current to The first output end generates a first output current; a second current mirror is formed by a fifth transistor and a sixth transistor, and has a second input end and a second output end, the second output end The second output terminal is coupled to the common input terminal, wherein the second input terminal receives the reference voltage to generate a second output current at the second output terminal. The current limiting circuit further includes: a seventh transistor having a gate terminal coupled to the common junction, and an output terminal generating the switching signal to switch the first transistor.
在一實施例中，該第一電晶體、該第二電晶體、該第五電晶體、該第六電晶體以及該第七電晶體為P型電晶體，該第三電晶體以及該第四電晶體為N型電晶體，其中，當該第一輸出電流大於該第二輸出電流時，該控制信號為 一第一控制信號，控制該第七電晶體導通，以切換該第一電晶體截止，中斷流經該電流路徑之電流，以及當該第一輸出電流小於該第二輸出電流時，該控制信號為一第二控制信號，控制該第七電晶體截止，以切換該第一電晶體導通，開啟流經該電流路徑之電流。In one embodiment, the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors, the third transistor, and the fourth The transistor is an N-type transistor, wherein when the first output current is greater than the second output current, the control signal is a first control signal, controlling the seventh transistor to be turned on to switch the first transistor off, interrupting a current flowing through the current path, and when the first output current is less than the second output current, the control signal For a second control signal, the seventh transistor is controlled to be turned off to switch the first transistor to conduct, and to turn on a current flowing through the current path.
在一實施例中，該第一電晶體、該第二電晶體、該第五電晶體、該第六電晶體以及該第七電晶體為N型電晶體，該第三電晶體以及該第四電晶體為P型電晶體，其中，當該第一輸出電流大於該第二輸出電流時，該控制信號為一第一控制信號，控制該第七電晶體導通，以切換該第一電晶體截止，中斷流經該電流路徑之電流，以及當該第一輸出電流小於該第二輸出電流時，該控制信號為一第二控制信號，控制該第七電晶體截止，以切換該第一電晶體導通，開啟流經該電流路徑之電流。In one embodiment, the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor are N-type transistors, the third transistor, and the fourth The transistor is a P-type transistor, wherein when the first output current is greater than the second output current, the control signal is a first control signal, and the seventh transistor is controlled to be turned on to switch the first transistor to be turned off. Interrupting a current flowing through the current path, and when the first output current is less than the second output current, the control signal is a second control signal, controlling the seventh transistor to be turned off to switch the first transistor Turns on, turning on the current flowing through the current path.
根據本發明之另一態樣，一種過電流保護方法，包括：感應流經一電流路徑之電流，並對應產生一感應電流；將該感應電流與一參考電流比較，以產生一控制信號；以及根據該控制信號，產生一切換信號切換該電流路徑之一控制開關以中斷或開啟流經該電流路徑之電流。According to another aspect of the present invention, an overcurrent protection method includes: sensing a current flowing through a current path and correspondingly generating an induced current; comparing the induced current with a reference current to generate a control signal; According to the control signal, a switching signal is generated to switch one of the current paths to control the switch to interrupt or turn on the current flowing through the current path.
綜合上述所言，本案藉由控制開關在流經電流路徑之電流發生一過電流之情況，即時中斷電流，因此輸出電流會逐漸降低，直至控制開再次開啟輸出電流，因此其輸出方式類似脈衝輸出。且藉由如此之電路設計，可適度放大瞬間可容許之輸出電流額定值，來滿足瞬間穩定在預期電壓之需求。In summary, the present case interrupts the current by instantaneously controlling the current flowing through the current path, so the output current will gradually decrease until the control is turned on and the output current is turned on again, so the output mode is similar to the pulse output. . And with such a circuit design, the instantaneous allowable output current rating can be appropriately amplified to meet the need for instantaneous stability at the expected voltage.
以下為本發明較佳具體實施例以所附圖示加以詳細說明，下列之說明及圖示使用相同之參考數字以表示相同或類似元件，並且在重複描述相同或類似元件時則予省略。The following description of the preferred embodiments of the invention is in the
第1圖係繪示根據本發明一較佳實施例之過電流保護電路100方塊圖。過電流保護電路100包括：一感應電路101、一比較電路102以及一電流限制電路103。感應電路101與一電流路徑之一控制開關105耦接，用以輸出一感應電流IS ，其中該感應電流IS 對應於流經該電流路徑106之電流Io 。比較電路102，耦接該感應電路101，用以將該感應電流IS 與一參考電流Iref 比較，以輸出一控制信號C1 。一電流限制電路103，耦接該比較電路102，根據該控制信號C1 ，產生一切換信號S1 切換該控制開關105以中斷或開啟流經該電流路徑之電流。相關之工作原理將進一步說明如下。1 is a block diagram of an overcurrent protection circuit 100 in accordance with a preferred embodiment of the present invention. The overcurrent protection circuit 100 includes an induction circuit 101, a comparison circuit 102, and a current limiting circuit 103. The sensing circuit 101 is coupled to a control circuit 105 of a current path for outputting an induced current I S , wherein the induced current I S corresponds to a current I o flowing through the current path 106 . The comparison circuit 102 is coupled to the sensing circuit 101 for comparing the induced current I S with a reference current I ref to output a control signal C 1 . A current limiting circuit 103, coupled to the comparison circuit 102, according to the control signal C 1, generating a switching control signals S 1 switches the switch 105 to interrupt or open the current path of the current flowing through. The related working principle will be further explained as follows.
第2圖係繪示根據本發明一較佳實施例之過電流保護電路100之詳細電路圖方塊圖。控制開關105包括一P型電晶體111，用以控制流經電流路徑106之電流Io 。而感應電路101亦包括一P型電晶體112，其中，電晶體112之閘極與電晶體111之閘極耦接在一起，且電晶體112之源極與電晶體111之源極共同耦接至同一電壓源，因此當電晶體111與電晶體112同時被開啟後，電晶體112之汲極端可對應於電流Io ，對應產生一感應電流IS 。在一實施例中，電晶體112與電晶體111之通道區域寬長比(W/L)為1： C，因此，感應電流IS 之大小為電流Io 大小之1/C，亦即IS =Io /C。2 is a block diagram showing a detailed circuit diagram of an overcurrent protection circuit 100 in accordance with a preferred embodiment of the present invention. Control switch 105 includes a P-type transistor 111, for controlling the current flowing through the current path 106. I o. The sensing circuit 101 also includes a P-type transistor 112, wherein the gate of the transistor 112 is coupled to the gate of the transistor 111, and the source of the transistor 112 is coupled to the source of the transistor 111. To the same voltage source, when the transistor 111 and the transistor 112 are simultaneously turned on, the 汲 terminal of the transistor 112 can correspond to the current I o , correspondingly generating an induced current I S . In one embodiment, the channel area width to length ratio (W/L) of the transistor 112 and the transistor 111 is 1:C. Therefore, the magnitude of the induced current I S is 1/C of the current I o , that is, I. S = I o /C.
而比較電路102更包括：一第一電流鏡1021、一第二電流鏡1022，以及一緩衝器1023。其中，第一電流鏡1021是由一N型電晶體113以及一N型電晶體114所組成。第一電流鏡1021更具有一輸入端耦接於節點N1，以及一輸出端耦接於節點N2，該輸入端用以接收感應電流IS 以於輸出端產生第一輸出電流I1 。在一實施例中，電晶體114與電晶體113之通道區域寬長比(W/L)為1：B，因此，第一輸出電流I1 之大小為感應電流IS 大小之1/B，亦即I1 =IS /B=Io /C×B。The comparison circuit 102 further includes a first current mirror 1021, a second current mirror 1022, and a buffer 1023. The first current mirror 1021 is composed of an N-type transistor 113 and an N-type transistor 114. The first current mirror 1021 has an input coupled to the node N1, and an output coupled to the node N2 for receiving the induced current I S to generate a first output current I 1 at the output. In one embodiment, the channel area width to length ratio (W/L) of the transistor 114 and the transistor 113 is 1:B. Therefore, the magnitude of the first output current I 1 is 1/B of the magnitude of the induced current I S . That is, I 1 =I S /B=I o /C×B.
第二電流鏡1022是由一P型電晶體115以及一P型電晶體116所組成。第二電流鏡1022亦具有一輸入端以及一輸出端，其中輸入端接收參考電流Iref ，而輸出端耦接於節點N2，換言之，第一電流鏡1021之輸出端與第二電流鏡1022之輸出端共同耦接於節點N2。其中第二電流鏡1022之輸出端會根據輸入端接收之參考電流Iref 而於該輸出端產生一第二輸出電流I2 。在一實施例中，電晶體116與電晶體115之通道區域寬長比(W/L)為1：A，因此，第二輸出電流I2 之大小為參考電流Iref 大小之1/A，亦即I2 =Iref ×A。此外，緩衝器1023亦耦接於節點N2，根據第一輸出電流I1 與第二輸出電流I2 之比較結果產生一控制信號C1 輸出給電流限制電路103。The second current mirror 1022 is composed of a P-type transistor 115 and a P-type transistor 116. The second current mirror 1022 also has an input end and an output end, wherein the input end receives the reference current I ref , and the output end is coupled to the node N2 , in other words, the output end of the first current mirror 1021 and the second current mirror 1022 The output ends are coupled to the node N2. The output of the second current mirror 1022 generates a second output current I 2 at the output according to the reference current I ref received by the input terminal. In one embodiment, the channel area width to length ratio (W/L) of the transistor 116 and the transistor 115 is 1:A. Therefore, the magnitude of the second output current I 2 is 1/A of the reference current I ref . That is, I 2 =I ref ×A. Further, the buffer 1023 is also coupled to the node N2, to produce an output current limiting circuit 103 according to a first control signal C 1 output current I 1 and the second output current I 2 of the comparison result.
電流限制電路103包括一P型電晶體117，此電晶體117具有一閘極端以及一輸出端，其中閘極端耦接於節點 N2，控制信號C1 會切換電晶體117，以於電晶體117之輸出端產生切換信號S1 ，此切換信號S1 會切換控制開關105，以中斷或開啟流經電流路徑106之電流。電流限制電路103是為了避免流經電流路徑106之電流Io 持續維持在一過電流之情況，造成輸出電路之毀損，因此需要透過電流限制電路103，在流經電流路徑106之電流Io 發生一過電流之情況，即時關閉控制開關105中斷電流Io 。The current limiting circuit 103 includes a P-type transistor 117 having a gate terminal and an output terminal, wherein the gate terminal is coupled to the node N2, and the control signal C 1 switches the transistor 117 for the transistor 117. an output terminal for generating the switching signals S 1, this switching control signals S 1 switches the switch 105 to open or interrupt a current flowing through the current path 106. The current limiting circuit 103 is to prevent the current flowing through the current path of I o 106 continuously maintained in the case of an over-current, resulting in damage to the output circuits, it is necessary to limit the current through the circuit 103, flows through the current path occurs in the I o 106 of an over-current situation, the instant the control switch 105 off to interrupt the current I o.
當第二輸出電流I2 大於第一輸出電流I1 ，亦即，Iref ×A大於Io /C×B，Iref ×A×B×C大於Io ，代表流經電流路徑106電流Io 無過電流情況發生，此時，節點N2被拉高而具有一高電位準位，並透過緩衝器1023產生一高準位之控制信號C1 輸出給電流限制電路103。高準位之控制信號C1 會切換電晶體117關閉，而於電晶體117之輸出端產生一低位準之切換信號S1 ，此切換信號S1 會讓控制開關105維持在導通之狀態，讓電流Io 持續流經電流路徑106。When the second output current I 2 is greater than the first output current I 1 , that is, I ref × A is greater than I o /C×B, I ref ×A×B×C is greater than I o , representing current flowing through current path 106 I o no over-current condition has occurred and the node N2 is pulled high to have a high potential level, and 1023 to generate an output current limiting circuit 103 of a high-level control signal C 1 through the buffer. The high level control signal C 1 switches the transistor 117 to turn off, and a low level switching signal S 1 is generated at the output of the transistor 117. The switching signal S 1 maintains the control switch 105 in the on state. I o current continues to flow through a current path 106.
隨著流經電流路徑106之電流Io 逐漸增加，流經感應電路101之感應電流IS 亦逐漸增加，導致第一電流鏡1021耦接節點N2輸出端處之第一輸出電流I1 亦逐漸增加。因為參考電流Iref 之大小不變，因此第二電流鏡1022耦接節點N2輸出端處之第二輸出電流I2 大小維持不變。當第一輸出電流I1 持續增加，致造成第一輸出電流I1 大於第二輸出電流I2 時，代表流經電流路徑106電流Io 發生過電流情況，此時，節點N2被拉低而具有一低電位準位，並透過緩衝器1023產生一低準位之控制信號C1 輸出給電流限制電路103。此低準位之控制信號C1 會切換電晶體117導通， 而於電晶體117之輸出端產生一高位準之切換信號S1 ，此切換信號S1 會關閉控制開關105，中斷電流Io 流經電流路徑106。As the current flowing through the current path 106. I o gradually increases, the induced current I S flowing through the sensing circuit 101 also increases gradually, resulting in a first output current I of the first current mirror 1021 is coupled to the output of the node N2 gradually also 1 increase. Because the magnitude of the reference current I ref is constant, the magnitude of the second output current I 2 coupled to the output of the node N2 of the second current mirror 1022 remains unchanged. When the first output current I 1 continues to increase, causing the first output current I 1 to be greater than the second output current I 2 , an overcurrent condition occurs in the current I o flowing through the current path 106. At this time, the node N2 is pulled low. having a low voltage level, and 1023 to generate an output current limiting circuit 103 is a low level of the control signal C 1 through the buffer. The low level control signal C 1 switches the transistor 117 to be turned on, and generates a high level switching signal S 1 at the output of the transistor 117. The switching signal S 1 turns off the control switch 105 to interrupt the current I o flow. Via current path 106.
第3圖係繪示根據本發明另一較佳實施例之過電流保護電路100之詳細電路圖方塊圖。控制開關105包括一N型電晶體211，用以控制流經電流路徑206之電流Io 。而感應電路101亦包括一N型電晶體212，其中電晶體212可對應於電流Io ，產生一感應電流IS 。3 is a block diagram showing a detailed circuit diagram of an overcurrent protection circuit 100 in accordance with another preferred embodiment of the present invention. Control switch 105 includes an N-type transistor 211, for controlling the current flowing through the current path 206. I o. The sensing circuit 101 also includes an N-type transistor 212, wherein the transistor 212 can generate an induced current I S corresponding to the current I o .
此外，比較電路102更包括：一第一電流鏡2021、一第二電流鏡2022，以及一緩衝器2023。其中，第一電流鏡2021是由一P型電晶體213以及一P型電晶體214所組成，其輸入端耦接於節點N1，輸出端耦接於節點N2，輸入端用以接收感應電流IS 以於輸出端產生第一輸出電流I1 。第二電流鏡2022是由一N型電晶體215以及一N型電晶體216所組成，其輸入端接收參考電流Iref ，而輸出端耦接於節點N2，並根據輸入端接收之參考電流Iref 於輸出端產生一第二輸出電流I2 。緩衝器2023亦耦接於節點N2，根據第一輸出電流I1 與第二輸出電流I2 之比較結果產生一控制信號C1 輸出給電流限制電路103。In addition, the comparison circuit 102 further includes a first current mirror 2021, a second current mirror 2022, and a buffer 2023. The first current mirror 2021 is composed of a P-type transistor 213 and a P-type transistor 214. The input end is coupled to the node N1, the output end is coupled to the node N2, and the input end is configured to receive the induced current I. S generates a first output current I 1 at the output. The second current mirror 2022 is composed of an N-type transistor 215 and an N-type transistor 216. The input terminal receives the reference current I ref , and the output terminal is coupled to the node N2 and receives the reference current I according to the input terminal. Ref produces a second output current I 2 at the output. Buffer 2023 is also coupled to the node N2, to produce an output current limiting circuit 103 according to a first control signal C 1 output current I 1 and the second output current I 2 of the comparison result.
電流限制電路103包括一N型電晶體217，此電晶體217具有一閘極端以及一輸出端，其中閘極端耦接於節點N2，控制信號C1 會切換電晶體217，以於電晶體217之輸出端產生切換信號S1 ，此切換信號S1 會切換控制開關105，以中斷或開啟流經電流路徑206之電流。The current limiting circuit 103 includes an N-type transistor 217. The transistor 217 has a gate terminal and an output terminal. The gate terminal is coupled to the node N2. The control signal C 1 switches the transistor 217 to the transistor 217. an output terminal for generating the switching signals S 1, this switching control signals S 1 switches the switch 105 to open or interrupt a current flowing through a current path 206.
當第二輸出電流I2 大於第一輸出電流I1 ，代表流經電 流路徑206電流Io 無過電流情況發生，此時，節點N2被拉低而具有一低電位準位，並透過緩衝器1023產生一低準位之控制信號C1 輸出給電流限制電路103。低準位之控制信號C1 會切換電晶體217關閉，而於電晶體217之輸出端產生一高位準之切換信號S1 ，此切換信號S1 會讓控制開關105維持在導通之狀態，讓電流Io 持續流經電流路徑206。When the second output current I 2 is greater than the first output current I 1, the current flowing through the path 206 representative of the current I o no over-current occurs, this time, the node N2 is pulled down to have a low voltage level, and through the buffer The control signal C 1 that generates a low level is output to the current limiting circuit 103. Controlling the low level of the signal C 1 switches the transistor 217 off, the output terminal of the transistor 217 of generating a high level of the switching signals S 1, this switching signals S 1 will control switch 105 is maintained in the turn-on state, let I o current continues to flow through a current path 206.
隨著流經電流路徑206之電流Io 逐漸增加，流經感應電路101之感應電流IS 亦逐漸增加，導致第一電流鏡2021耦接節點N2輸出端處之第一輸出電流I1 亦逐漸增加，當第一輸出電流I1 大於第二輸出電流I2 時，代表流經電流路徑106電流Io 發生過電流情況，此時，節點N2被拉高而具有一高電位準位，並透過緩衝器1023產生一高準位之控制信號C1 輸出給電流限制電路103。此高準位之控制信號C1 會切換電晶體117導通，而於電晶體117之輸出端產生一低位準之切換信號S1 ，此切換信號S1 會關閉控制開關105，中斷電流Io 流經電流路徑206。As the current flowing through the current path 206 I o gradually increases, the induced current I S flowing through the sensing circuit 101 also increases gradually, resulting in a first output current I N2 at the output of the first current mirror coupled to the node 2021 are gradually 1 Increasing, when the first output current I 1 is greater than the second output current I 2 , it represents an overcurrent condition flowing through the current path 106 current I o , at this time, the node N2 is pulled high to have a high potential level, and is transmitted through buffer 1023 to generate an output current limiting circuit 103 of a high-level control signal C 1. The high-level control signal C 1 switches the transistor 117 to be turned on, and generates a low-level switching signal S 1 at the output of the transistor 117. The switching signal S 1 turns off the control switch 105, interrupting the current I o flow. Via current path 206.
依此，本案藉由控制開關105在流經電流路徑106或206之電流Io 發生一過電流之情況，即時中斷電流Io ，因此可避免過電流之情況持續發生在輸出電路。且藉由如此之電路設計，可適度放大瞬間可容許之輸出電流額定值，來滿足瞬間穩定在預期電壓之需求。因此，本案之輸出電流如第4圖所示，當輸出電流Io 在達到第一限制電流之後，控制開關105控制電流Io 停止輸出，因此輸出電流會逐漸降低，直至控制開關105再次開啟輸出電流Io ，因此其輸出方式類似脈衝輸出。而傳統利用設定一限制電流來防止 過電流之方式，其係讓大於第二限制電流之輸出電流Io 保持在第二限制電流大小持續輸出，因此與傳統之方法相較，本案由於是瞬間輸出，因此可設定一遠大於第二限制電流之第一限制電流，來充分滿足瞬間穩定在預期電壓之需求。So, the occurrence of the case 105 by controlling the switching current flowing through the current path I o 106 or 206 of a case of an overcurrent, interrupting the current instant I o, thereby avoiding the overcurrent persists in the output circuit. And with such a circuit design, the instantaneous allowable output current rating can be appropriately amplified to meet the need for instantaneous stability at the expected voltage. Accordingly, the case that the output current as shown in FIG. 4, the output current I o when the first current limit is reached, the control switch 105 controls the output current I o is stopped, the output current will gradually decrease until the output control switch 105 is turned on again The current I o is therefore output in a manner similar to a pulse output. The traditional use of a current limit is set to prevent an overcurrent of the embodiment, which is greater than the second limit current system so that the output current I o is maintained at the second continuous output current limit magnitude, and therefore as compared with the conventional methods, since the present case is the instantaneous output Therefore, a first limiting current that is much larger than the second limiting current can be set to fully satisfy the requirement of instantaneously stabilizing at the expected voltage.
參閱第5圖所示為根據本發明一較佳實施例之過電流保護之流程圖。其中包括，首先於步驟501，感應流經一電流路徑之電流，並對應產生一感應電流。接著於步驟502，將該感應電流與一參考電流比較，以產生一控制信號。在一實施例中，當該感應電流大於一參考電流時，會產生一第一控制信號，而當該感應電流小於一參考電流時，會產生一第二控制信號。其中，係使用一第一電流鏡，根據該感應電流對應輸出一第一輸出電流，以及一第二電流鏡，根據該參考電流對應輸出一第二輸出電流。當該第一輸出電流大於該第二輸出電流時，產生一第一控制信號，以及當第一輸出電流小於該第二輸出電流時，產生一第二控制信號。最後於步驟503，根據該控制信號，產生一切換信號切換該電流路徑之一控制開關以中斷或開啟流經該電流路徑之電流。在一實施例中，更包括根據該第一控制信號產生一第一切換信號切換該控制開關截止，以中斷流經該電流路徑之電流，以及根據該第二控制信號產生一第二切換信號切換該控制開關導通，以開啟流經該電流路徑之電流。Referring to Figure 5, there is shown a flow chart of overcurrent protection in accordance with a preferred embodiment of the present invention. The method includes, firstly, in step 501, inducing a current flowing through a current path, and correspondingly generating an induced current. Next, in step 502, the induced current is compared with a reference current to generate a control signal. In an embodiment, when the induced current is greater than a reference current, a first control signal is generated, and when the induced current is less than a reference current, a second control signal is generated. The first current mirror is used to output a first output current according to the induced current, and a second current mirror is configured to output a second output current according to the reference current. When the first output current is greater than the second output current, a first control signal is generated, and when the first output current is less than the second output current, a second control signal is generated. Finally, in step 503, a switching signal is generated according to the control signal to switch one of the current paths to control the switch to interrupt or turn on the current flowing through the current path. In an embodiment, the method further includes: generating a first switching signal according to the first control signal, switching the control switch to turn off, interrupting a current flowing through the current path, and generating a second switching signal according to the second control signal. The control switch is turned on to turn on current flowing through the current path.
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and those skilled in the art, without departing from the spirit of the invention, In the scope of the invention, the scope of the invention is defined by the scope of the appended claims.
100‧‧‧過電流保護電路100‧‧‧Overcurrent protection circuit
101‧‧‧感應電路101‧‧‧Induction circuit
102‧‧‧比較電路102‧‧‧Comparative circuit
103‧‧‧電流限制電路103‧‧‧ Current limiting circuit
105‧‧‧控制開關105‧‧‧Control switch
106,206‧‧‧電流路徑106,206‧‧‧ Current path
111,112,113,114,115,116,117,211,212,213,214, 215,216,217‧‧‧電晶體111, 112, 113, 114, 115, 116, 117, 211, 212, 213, 214, 215,216,217‧‧‧Optoelectronics
1021,2021‧‧‧第一電流鏡1021, 2021‧‧‧ first current mirror
1022,2022‧‧‧第二電流鏡1022, 2022‧‧‧second current mirror
1023,2023‧‧‧緩衝器1023, 2023‧‧‧ buffer
501~503‧‧‧步驟501~503‧‧‧Steps
N1,N2‧‧‧節點N1, N2‧‧‧ nodes
I1 ‧‧‧第一輸出電流I 1 ‧‧‧first output current
I2 ‧‧‧第二輸出電流I 2 ‧‧‧second output current
IS ‧‧‧感應電流I S ‧‧‧Induction current
Io ‧‧‧電流I o ‧‧‧current
Iref ‧‧‧參考電流I ref ‧‧‧reference current
C1 ‧‧‧控制信號C 1 ‧‧‧ control signal
S1 ‧‧‧切換信號S 1 ‧‧‧Switching signal
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.
第1圖係繪示根據本發明一較佳實施例之過電流保護電路方塊圖。1 is a block diagram of an overcurrent protection circuit in accordance with a preferred embodiment of the present invention.
第2圖係繪示根據本發明一較佳實施例之過電流保護電路之詳細電路圖方塊圖。2 is a block diagram showing a detailed circuit diagram of an overcurrent protection circuit in accordance with a preferred embodiment of the present invention.
第3圖係繪示根據本發明另一較佳實施例之過電流保護電路之詳細電路圖方塊圖。3 is a block diagram showing a detailed circuit diagram of an overcurrent protection circuit in accordance with another preferred embodiment of the present invention.
第4圖所示為根據本發明一較佳實施例之輸出電流波形圖。Figure 4 is a diagram showing the waveform of the output current in accordance with a preferred embodiment of the present invention.
第5圖所示為根據本發明一較佳實施例之過電流保護之流程圖。Figure 5 is a flow chart showing overcurrent protection in accordance with a preferred embodiment of the present invention.
100‧‧‧過電流保護電路100‧‧‧Overcurrent protection circuit
101‧‧‧感應電路101‧‧‧Induction circuit
102‧‧‧比較電路102‧‧‧Comparative circuit
103‧‧‧電流限制電路103‧‧‧ Current limiting circuit
105‧‧‧控制開關105‧‧‧Control switch
IS ‧‧‧感應電流I S ‧‧‧Induction current
Io ‧‧‧電流I o ‧‧‧current
C1 ‧‧‧控制信號C 1 ‧‧‧ control signal
S1 ‧‧‧切換信號S 1 ‧‧‧Switching signal
Claims (12)
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|---|---|---|---|---|
| TW200828715A (en) * | 2006-12-25 | 2008-07-01 | Winbond Electronics Corp | Over-current protection circuit |
| JP2010279188A (en) * | 2009-05-29 | 2010-12-09 | Sanyo Electric Co Ltd | Overcurrent protection circuit |
| TW201108540A (en) * | 2009-08-19 | 2011-03-01 | Himax Analogic Inc | Driver and over-current protection circuit therein |
| TWM420923U (en) * | 2011-08-29 | 2012-01-11 | Hiwin Mikrosystem Corp | Protection device for over-current |
| US20120039007A1 (en) * | 2009-04-28 | 2012-02-16 | Joel Turchi | Method for providing over current protection and circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200828715A (en) * | 2006-12-25 | 2008-07-01 | Winbond Electronics Corp | Over-current protection circuit |
| US20120039007A1 (en) * | 2009-04-28 | 2012-02-16 | Joel Turchi | Method for providing over current protection and circuit |
| JP2010279188A (en) * | 2009-05-29 | 2010-12-09 | Sanyo Electric Co Ltd | Overcurrent protection circuit |
| TW201108540A (en) * | 2009-08-19 | 2011-03-01 | Himax Analogic Inc | Driver and over-current protection circuit therein |
| TWM420923U (en) * | 2011-08-29 | 2012-01-11 | Hiwin Mikrosystem Corp | Protection device for over-current |
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