JP4475257B2 - Current limit circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a current limiting circuit suitable as an overcurrent protection circuit for a circuit including a switching element that performs switching of a relatively large current, such as a class D amplifier.

As is well known, in a class D amplifier, a transistor as a switching element is switched on / off by a pulsed control signal modulated in accordance with an input signal, and a load such as a speaker is driven through this transistor. Here, in order to appropriately drive a load such as a speaker, it is necessary to reduce the ON resistance of the transistor. However, if the ON resistance of the transistor is lowered, if there is a ground fault or ground fault at one end of the load, or a short circuit occurs at both ends of the load, an overcurrent exceeding the allowable range flows in the transistor, and in the worst case, the transistor May lead to destruction. As a technique for solving this problem, Patent Document 1 proposes a technique for monitoring a current flowing through a load driving transistor and turning off the transistor when an overcurrent is detected in the transistor. Yes.
JP 2002-171140 A

  By the way, since the class D amplifier drives the load by switching the output stage transistor, a transient large switching current flows through the transistor even in normal operation. Therefore, if the transistor is switched to the OFF state in response to the overcurrent flowing through the transistor, the operation of the class D amplifier becomes extremely unstable. Therefore, under the prior art, a circuit that detects overcurrent is configured so as not to react to overcurrent for a relatively short time, and when an overcurrent is detected for a predetermined time or longer, the output stage The coping method of switching the transistor to the OFF state has been adopted (see, for example, claim 7 of FIG. 1 and FIG. 12). However, when such a countermeasure is adopted, an overcurrent is caused to flow for a predetermined time to a transistor in which an overcurrent is detected, and damage due to the energization of the overcurrent is given to the transistor. In addition, when such a countermeasure is adopted, a time delay occurs between the time when the overcurrent starts to be detected and the time when the transistor is turned off. The value of the overcurrent that flows is a large value. Therefore, when the transistor is turned off, a large voltage is generated at both ends of the load in an attempt to maintain the current that the inductance of the inductive load such as a speaker connected to the class D amplifier has been flowing. For this reason, a large voltage exceeding the level of the power supply voltage is generated at some output nodes of the output buffer circuit, causing a problem that the related transistors are damaged. This problem is not limited to a circuit that drives an external load by a switching element such as a class D amplifier, but is a problem that occurs in all circuits that perform switching of a relatively large current, such as a switching regulator.

  The present invention has been made in view of the circumstances described above, and in a circuit having a switching element that performs switching of a large current, the switching element is protected from overcurrent so that the switching element is not greatly damaged. It is an object of the present invention to provide a current limiting circuit that can be used.

The present invention relates to a switching element that passes a current according to a level of a control signal, a current detection unit that detects a current flowing through the switching element, and a current that exceeds an allowable value is detected by the current detection unit. A current limiting unit including a current control unit configured to control a level of a control signal applied to the switching element so that a current flowing through the switching element is limited to a predetermined current limit target value; Provide a circuit.
According to this invention, when an overcurrent exceeding the allowable value flows through the switching element, the current flowing through the switching element is immediately limited to the current limit target value by the current limiting unit. Therefore, damage given to the switching element can be reduced.

Embodiments of the present invention will be described below with reference to the drawings.
<Overall configuration>
FIG. 1 is a circuit diagram showing a configuration of a class D amplifier having an overcurrent protection circuit which is an embodiment of a current limiting circuit according to the present invention. Each circuit constituting the class D amplifier is configured by a field effect transistor (hereinafter simply referred to as a transistor) or the like, and a power supply voltage VDD is applied to each circuit from a power source (not shown).

  The output buffer circuit 10 forms the final output stage of the class D amplifier, and includes a P-channel transistor PP, an N-channel transistor NP, a P-channel transistor PM, and an N-channel transistor NM. Here, the sources of P-channel transistors PP and PM are connected to a power supply line, and the sources of N-channel transistors NP and NM are connected to a ground line. The drains of the P channel transistor PP and the N channel transistor NP are connected to each other, and this connection point is connected to one end of the load L. Similarly, the drains of the P channel transistor PM and the N channel transistor NM are connected to each other. This connection point is connected to the other end of the load L.

  This load L is, for example, a speaker. When this class D amplifier is in operation, a fault or a ground fault occurs at one end of the load L, or an accident occurs in which both ends of the load L are short-circuited, and the transistors PP, NP, and PM constituting the output buffer circuit 10 Alternatively, an overcurrent having a current value exceeding the allowable range may flow through either NM. The feature of this embodiment is an overcurrent protection circuit that protects the transistors PP, NP, PM, and NM from such overcurrent. The details of this overcurrent protection circuit will be described later.

  A PWM (Pulse Width Modulation) modulation unit 20 outputs four-phase pulses PWMPP, PWMPM, PWMNP, and PWMNM that are pulse width modulated in accordance with the level of an input signal IN given from the outside. When no overcurrent flows in any of the transistors PP, NP, PM, and NM, and the class D amplifier is operating normally, the pulses PWMPP, PWMPM, PWMNP, and PWMNM output from the PWM modulator 20 are , AND gate 31, AND gate 32, OR gate 33 and OR gate 34, respectively. The output signals CPP, CPM, CNP and CNM (in this case, pulses PWMPP, PWMPM, PWMNP and PWMNM) of the AND gate 31, AND gate 32, OR gate 33 and OR gate 34 are pre-drivers 51, 52, 53 and 54. Given to each.

  Here, each of the pre-drivers 51 to 54 is an inverter driver that drives the transistors PP, PM, NP, and NM of the output buffer circuit 10, and the pre-driver 51 includes a P-channel transistor 51P and an N-channel transistor 51N. The pre-driver 52 is composed of a P-channel transistor 52P and an N-channel transistor 52N, the pre-driver 53 is composed of a P-channel transistor 53P and an N-channel transistor 53N, and the pre-driver 54 is composed of a P-channel transistor 54P and an N-channel transistor 54N. ing. These pre-drivers 51, 52, 53 and 54 generate control signals GPP, GPM, GNP and GNM for driving based on signals CPP, CPM, CNP and CNM, respectively, and transistors PP, PM, NP and Output to each gate of NM.

  FIG. 2 shows waveforms of control signals GPP, GPM, GNP and GNM applied to the gates of the transistors PP, PM, NP and NM in a normal state. In FIG. 2, in the period TA, the control signals GPP, GPM, GNP, and GNM are set to the L level, the H level, the L level, and the H level, respectively, the set of the transistors PP and NM is in the ON state, and the set of the transistors PM and NP is set. It is turned off. Therefore, in the period TA, a current from the power source flows through the path of the transistor PP, the load L, and the transistor NM. In the period TB, the control signals GPP, GPM, GNP, and GNM are set to the H level, the L level, the H level, and the L level, respectively, the pair of the transistors PM and NP is in the ON state, and the pair of the transistors PP and NM is in the OFF state. It is said. Therefore, in the period TB, a current from the power source flows through the path of the transistor PM, the load L, and the transistor NP.

  A dead time TD is interposed between the period TA and the subsequent period TB and between the period TB and the subsequent period TA. In the dead time TD, all of the transistors PP, NP, PM, and NM are turned off. During normal operation, the periods TA and TB are alternately repeated with a dead time TD interposed therebetween as shown in the figure, and the output buffer circuit 10 performs push-pull driving of the load L. The reason for providing the dead time TD between the periods TA and TB is to prevent the occurrence of a through current.

  Next, the overcurrent protection circuit according to the present embodiment will be described. The overcurrent protection circuit according to the present embodiment includes the current interrupting unit 30 shown in FIG. 1 and current limiting units 60PP, 60PM, 60NP, and 60NM.

  Here, the current interrupting unit 30 monitors the current flowing through the transistors PP, PM, NP and NM in the output buffer circuit 10, and forcibly turns off the transistors PP, PM, NP and NM based on the monitoring result. It is a circuit that controls whether or not to do.

  More specifically, when it is recognized that no overcurrent exceeding the reference value th1 flows in any of the transistors PP, PM, NP, and NM, the current interrupting unit 30 detects the error signal Err1 of the inactive level (H level). Is supplied to AND gates 31 and 32 and an inactive level (L level) error signal Err2 is supplied to OR gates 33 and 34. As a result, the pulses PWMPP, PWMPM, PWMNP, and PWMNM output from the PWM modulation unit 20 pass through the AND gates 31 and 32 and the OR gates 33 and 34, respectively, and are then leveled by the pre-drivers 51, 52, 53, and 54, respectively. Inverted and supplied as control signals GPP, GPM, GNP, and GNM to the gates of the transistors PP, PM, NP, and NM.

  On the other hand, when it is detected that an overcurrent exceeding the reference value th1 continuously flows in any of the transistors PP, PM, NP, or NM in the output buffer circuit 10 for a predetermined time or more, the current interrupting unit 30 is set to the active level ( L level error signal Err1 is supplied to AND gates 31 and 32, and active level (H level) error signal Err2 is supplied to OR gates 33 and 34. Thus, control signals GPP and GPM for P channel transistors PP and PM of output buffer circuit 10 are forcibly set to H level, and control signals GNP and GNM for N channel transistors NP and NM are forcibly set to L level. As a result, the transistors PP, PM, NP and NM of the output buffer circuit 10 are all turned off and protected from overcurrent.

  The current limiters 60PP, 60PM, 60NP and 60NM are arranged so that when the magnitude of the drain current flowing through any of the transistors PP, PM, NP or NM exceeds a predetermined allowable value UL, the drain current is set to a predetermined current limit target. This is a circuit that performs control for limiting to the value LMT. In a preferred embodiment, the allowable value UL used for the current limiting units 60PP, 60PM, 60NP and 60NM is a value slightly larger than the reference value th1 used for the current interrupting unit 30 described above.

  The current limiter 60PP includes a current detector 61PP that detects a drain current flowing through the transistor PP, and the drain current of the transistor PP when the magnitude of the drain current detected by the current detector 61PP exceeds an allowable value UL. The current control unit 62PP controls the control signal GPP supplied to the gate of the transistor PP so as to be limited to the current limit target value LMT having the same size as or smaller than the allowable value UL. The same applies to the other current limiting units 60PM, 60NP, and 60NM. The current limiting unit 60PM includes a current detection unit 61PM and a current control unit 62PM, and the current limiting unit 60NP includes a current detection unit 61NP and a current control unit 62NP. The limiting unit 60NM includes a current detection unit 61NM and a current control unit 62NM.

  The overcurrent protection circuit according to the present embodiment is characterized in that the current interrupting unit 30 and the current limiting units 60PP, 60PM, 60NP, and 60NM are used in combination.

  As described above, in the conventional class D amplifier, the transistors PP, PM, NP, and NM of the output buffer circuit 10 are protected from overcurrent only by the one corresponding to the current cutoff unit 30 in the present embodiment. Here, if the conditions for turning off the transistors PP, PM, NP, or NM in the current interrupting unit 30 are moderate, the transistors PP, PM, NP, or NM are operated during normal operation of the class D amplifier. Even when a temporary excessive switching current flows, the current interrupting unit 30 reacts to this, and a large overcurrent with a large energy that may cause the transistor PP, PM, NP or NM to break is not flowing. Nevertheless, the transistors PP, PM, NP and NM may be turned off by the current interrupting unit 30. Under the prior art, in order to prevent such an unstable operation from occurring, any one of the transistors PP, PM, NP, or NM is not less than a predetermined time as in the current interrupt unit 30 in the present embodiment. On the other hand, when an overcurrent exceeding the reference value th1 flows, the transistor PP, PM, NP or NM is turned off.

  However, in such a countermeasure, an overcurrent is applied to a transistor PP, PM, NP, and NM until the transistors PP, PM, NP, and NM are turned off. This causes a disadvantage that the transistor is damaged by overcurrent.

  Further, when overcurrent protection is performed only by the current interrupting unit 30, a time delay occurs between the time when the overcurrent starts to be detected and the time when the transistors PP, PM, NP, and NM are turned off, so that the transistors PP, PM, When the current value of the overcurrent flowing through NP and NM becomes a large value, the transistors PP, PM, NP and NM are turned off. For this reason, an excessive voltage is induced at both ends of the load L, and the application of this voltage causes a disadvantage that the transistor PP, PM, NP or NM is damaged.

  The overcurrent protection circuit according to the present embodiment is provided with the current limiting units 60PP, 60PM, 60NP, and 60NM in addition to the current interrupting unit 30, so that the above inconveniences are corrected. Hereinafter, an operation of overcurrent protection performed in the present embodiment will be described with a specific example.

  FIG. 3 is a time chart showing an operation example of overcurrent protection when there is a power supply at the connection point between the drains of the transistors PP and NP in FIG. 1 and an overcurrent flows through the transistor NP.

  As shown in FIG. 3, when the pulse PWMNP becomes L level, the control signal GNP for the gate of the transistor NP becomes H level, and the transistor NP is turned on. At this time, the drain current INP of the transistor NP starts to increase due to the power fault. When the current detection unit 61NP detects that the drain current INP exceeds the reference value th1 and further exceeds the allowable value UL higher than the reference value th1, the current control unit 62NP determines that the drain current INP has the allowable value UL. The control signal GNP for the gate of the transistor NP is controlled so as to be limited to the current limit target value LMT having the same magnitude as or lower than. Therefore, thereafter, the drain current INP of the transistor NP maintains the current limit target value LMT.

  In FIG. 3, when the drain current INP exceeds the allowable value UL, the level of the control signal GNP with respect to the gate of the transistor NP is lowered, so that the drain current INP is smaller than the allowable value UL and from the reference value th1. An example in which the current limit target value LMT is limited to a higher value is shown.

  When the elapsed time after the drain current INP of the transistor NP exceeds the reference value th1 reaches a predetermined time T, the control signal GNP is forcibly set to the L level by the current cutoff unit 30, and the transistor NP is turned off. Is done.

  As described above, according to the present embodiment, when the overcurrent of the transistor NP exceeds the allowable value UL, the current limiting unit 60NP immediately controls to limit the drain current INP of the transistor NP to the current limit target value LMT. . Therefore, even when the operation of the current interrupting unit 30 that switches the transistors PP, PM, NP, and NM to the OFF state in response to the detection of the overcurrent is delayed, the overcurrent flowing through the transistor NP is limited to a low level and the damage given to the transistor NP. Can be reduced. If current limiting by the current limiting unit 60NP is not performed, the drain current INP flowing through the transistor NP increases as illustrated by a broken line in FIG. 3, and when the transistor NP is switched to the OFF state, the drain current INP Is a very large value (INPmax in the illustrated example). For this reason, when the transistor NP is turned off, an excessive voltage is induced at both ends of the load L, and this voltage may damage any of the transistors in the output buffer circuit 10. However, in the present embodiment, the drain current INP of the transistor NP is limited to the current limit target value LMT by the current limiter 60NP. For this reason, when the transistor NP is turned off by the action of the current interrupting unit 30, the voltage induced across the load L can be lowered to reduce the damage given to each transistor of the output buffer circuit 10. it can.

  Although the overcurrent protection operation when an overcurrent flows through the transistor NP has been described above, the same overcurrent protection operation as described above is performed when an overcurrent flows through the other transistors NM, PP, and PM. .

  Next, specific examples of the current interrupting unit 30 and the current limiting units 60PP, 60PM, 60NP, and 60NM will be described in order.

<Specific example of current interrupting unit>
FIG. 4 is a circuit diagram illustrating a configuration example of the current interrupting unit 30. Reference levels REFP and REFN are applied to the current interrupting unit 30, and the signal OUTP at the connection point between the drains of the transistors PP and NP in the output buffer circuit 10 and the signal at the connection point between the drains of the transistors PM and NM. OUTM and pulses PWMPP, PWMPM, PWMNP, and PWMNM output from the PWM modulator 20 are given.

  As shown in the figure, the current interrupting unit 30 includes comparators 301 to 304, inverters 311 to 314, low active AND gates 321 and 322, AND gates 323 and 324, timers 331 to 334, an OR gate 341, and a set / reset flip-flop 342. Connected. Here, the reference level REFP given to the comparators 301 and 302 is set in accordance with the drain voltage of the transistor when the drain current corresponding to the reference value th1 flows through the transistor PP or PM. The reference level REFN given to the comparators 303 and 304 is set according to the drain voltage of the transistor when the drain current corresponding to the reference value th1 flows through the transistor NP or NM.

  In this configuration, the low active AND gate 321 is connected to the transistor PP when the pulse PWMPP is at the H level and the output signal of the comparator 301 is at the L level (the level of the signal OUTP is lower than the reference level REFP). An overcurrent detection signal IN-PCHP indicating that an overcurrent exceeding the value th1 is flowing is set to an active level (H level). Further, the low active AND gate 322 applies the reference value th1 to the transistor PM when the pulse PWMPM is at the H level and the output signal of the comparator 302 is at the L level (the level of the signal OUTM is lower than the reference level REFP). An overcurrent detection signal IN-PCHM indicating that an overcurrent exceeding 1 is flowing is set to an active level (H level). Further, the AND gate 323 exceeds the reference value th1 in the transistor NP when the pulse PWMNP is at L level and the output signal of the comparator 303 is at H level (the level of the signal OUTP is higher than the reference level REFN). An overcurrent detection signal IN-NCHP indicating that an overcurrent is flowing is set to an active level (H level). The AND gate 324 exceeds the reference value th1 in the transistor NM when the pulse PWMNM is at L level and the output signal of the comparator 304 is at H level (the level of the signal OUTM is higher than the reference level REFN). An overcurrent detection signal IN-NCHM indicating that an overcurrent is flowing is set to an active level (H level).

The timer 331 outputs a pulse when the overcurrent detection signal IN-PCHP continues the active level for a predetermined time T or longer. Similarly, when the overcurrent detection signal IN-PCHM continues the active level for the predetermined time T or more, the timer 333 detects that the overcurrent detection signal IN-NCHP has the active level for the predetermined time T or more. The timer 334 outputs a pulse when the overcurrent detection signal IN-NCHM continues the active level for a predetermined time T or more. When a pulse is output from any of the timers 331 to 334, the OR gate 341 applies the pulse to the set terminal of the set / reset flip-flop 342. The output signal at the high active output terminal of the set / reset flip-flop 342 is supplied to the OR gates 33 and 34 as the error signal Err2, and the output signal at the low active output terminal is the AND gates 31 and 32 as the error signal Err1. (See FIG. 1). The set / reset flip-flop 342 is reset when the class D amplifier is powered on.
The configuration example of the current interrupting unit 30 has been described above.

<First Specific Example of Current Limiting Unit>
FIG. 5 is a circuit diagram showing a first specific example of the current limiting unit 60NP in the present embodiment. The current limiting unit 60NM has the same configuration as that shown in FIG.

  In this specific example, a resistor 607 is interposed between the drains of the transistors 53P and 53N in the pre-driver 53. A connection point between the resistor 607 and the drain of the transistor 53N is connected to the gate of the transistor NP via the signal line 600, and the control signal GNP, which is an output signal of the predriver 53, is connected to the transistor via the signal line 600. It is given to the gate of NP. The source and drain of the P-channel transistor 608 are connected to both ends of the resistor 607.

  Further, N-channel transistors 601 to 603 are interposed in series between the signal line 600 and the ground line. Here, the drain of the transistor 601 is connected to the signal line 600, the gate of the transistor 601 is connected to the connection point of each drain of the transistors PP and NP, and the source of the transistor 601 is connected to the drain and gate of the transistor 602. ing. The source of the transistor 602 is connected to the drain and gate of the transistor 603, and the source of the transistor 603 is grounded. The N-channel transistor 609 has a gate connected to the power supply, a drain connected to the gate and drain of the transistor 603, and a source grounded. The transistor 609 is provided to keep the gate and drain levels of the transistor 603 at the ground level when the transistors 601 to 603 are in the OFF state.

  The transistors 601 to 603, the resistor 607, and the transistors 608 and 609 described above constitute the current control unit 62NP in FIG.

  In this specific example, a constant current source 605 and an N-channel transistor 604 are interposed in series between the power supply line and the ground line. Here, a gate voltage common to the transistor 603 is supplied to the transistor 604. Then, the inverter 606 inverts the level of the connection point between the drain of the transistor 604 and the constant current source 605 and supplies it to the gate of the transistor 608 as the current limit command signal CURLMT. The transistor 604, the constant current source 605, the inverter 606, and the transistors 601 to 603 and 609 described above constitute the current detection unit 61NP in FIG.

  In this specific example, when the gate threshold value of the N-channel transistors 601 to 603 is VT, the drain current INP that can flow through the transistor NP when the gate voltage 2VT and the drain voltage 3VT are applied to the transistor NP is the allowable value UL. It is said that. Further, the saturation current value of the drain current of the transistor NP when the gate voltage is 2VT is the current limit target value LMT.

  FIG. 6 is a waveform diagram showing the waveforms of the respective parts in the present specific example when there is no power supply at the connection point between the drains of the transistors PP and NP and normal operation is performed. FIG. 7 is a waveform diagram showing waveforms at various parts when there is a power fault at the connection point between the drains of the transistors PP and NP. Hereinafter, the operation of this example will be described with reference to these drawings.

  As shown in FIGS. 6 and 7, when the input signal CNP to the pre-driver 53 falls, the control signal GNP rises from 0V toward VDD. When there is no power supply at the connection point between the drains of the transistors PP and NP, as shown in FIG. 6, when the level of the control signal GNP reaches 2VT, the signal OUTP becomes lower than 3VT. For this reason, the transistors 601 to 603 are maintained in the OFF state, the current limit command signal CURLMT output from the inverter 606 is maintained at the inactive level (L level), and the control signal GNP rises to the level of the power supply voltage VDD.

  On the other hand, if there is a power fault at the connection point between the drains of the transistors PP and NP, the drain current flowing through the transistor NP increases as the control signal GNP increases, and the level of the signal OUTP rises. When the level of the control signal GNP reaches 2VT and the drain current INP exceeding the allowable value UL flows to the transistor NP, as shown in FIG. 7, the level of the signal OUTP becomes higher than 3VT, and the transistors 601 to 603 Is turned on, and the current limiting command signal CURLMT output from the inverter 606 becomes active level (H level). As a result, the transistor 608 is turned off, a current flows through the path of the transistor 53P, the resistor 607, and the transistors 601 to 603, and a voltage drop occurs due to the resistor 607. Therefore, the level of the control signal GNP becomes 2VT. As a result, the drain current INP flowing through the transistor NP is limited to the current limit target value LMT.

  FIG. 8 is a circuit diagram showing a first specific example of the current limiting unit 60PP in the present embodiment. The current limiting unit 60PM has the same configuration as that shown in FIG.

  In the current limiting unit 60PP shown in FIG. 8, the P channel transistors 621 to 624, the constant current source 625, the inverter 626, the resistor 627, the N channel transistor 628, and the P channel transistor 629 are the same as the N channel in the current limiting unit 60NP of FIG. The transistors 601 to 604, the constant current source 605, the inverter 606, the resistor 607, the P-channel transistor 608 and the N-channel transistor 609 play corresponding roles.

  In this current limiting unit 60PP, when the gate threshold values of the P-channel transistors 621 to 623 are VT, the drain current that can flow through the transistor PP when the gate voltage 2VT and the drain voltage 3VT are applied to the transistor PP is an allowable value UL. It has become. Further, the saturation current value of the drain current of the transistor PP when the gate voltage 2VT is applied to the transistor PP is the current limit target value LMT. In the current limiting unit 60PP, similarly to the current limiting unit 60NP of FIG. 5, the gate voltage applied to the transistor PP is controlled to 2 VT when a drain current exceeding the allowable value UL flows to the transistor PP. The level of the signal GPP is fixed, and the drain current of the transistor PP is limited to the current limit target value LMT.

<Second Specific Example of Current Limiting Unit>
FIG. 9 is a circuit diagram showing a second specific example of the current limiting unit 60NP in the present embodiment. The current limiting unit 60NM has the same configuration as that shown in FIG.

  First, the current control unit 62NP among the circuits constituting the current limiting unit 60NP will be described. A resistor 711 is interposed between the drains of the transistors 53P and 53N in the pre-driver 53. The source and drain of a P-channel transistor 712 are connected to both ends of the resistor 711, respectively. The connection point between the resistor 711 and the drain of the transistor 53N is connected to the gate of the transistor NP through the signal line 700, and the control signal GNP, which is an output signal of the predriver 53, is connected to the transistor through the signal line 700. It is given to the gate of NP. Further, N-channel transistors 713 and 714 are interposed in series between the signal line 700 and the ground line. Here, the drain and gate of the transistor 713 are connected to the signal line 700. The source of the transistor 713 is connected to the drain of the transistor 714, and the source of the transistor 714 is grounded. Each gate of transistors 712 and 714 is supplied with current limit command signal CURLMT output from current detection unit 61NP.

The resistance value of the resistor 711 is determined as follows.
a. The gate voltage value when the saturation current value of the transistor NP becomes the current limit target value LMT is determined as the current limit gate voltage value.
b. When the input signal CNP to the pre-driver 53 is L level, the current limit command signal CURLMT is H level (active level), and the current flows through the path of the transistor 53P, the resistor 711, the transistor 713, and the transistor 714, the level of the control signal GNP The resistance value of the resistor 711 is determined so that becomes the current limiting gate voltage value.

  Next, the current detection unit 61NP will be described. This current detection unit 61NP compares the drain current INP of the transistor NP with the allowable value UL, and when the drain current INP becomes larger than the allowable value UL, the overcurrent detection signal OVERCURN is set to L level (active level), and the current is detected. This is a circuit for setting the limit command signal CURLMT to the H level (active level). The detailed configuration of the current detection unit 61NP is as follows.

  The N-channel transistor 701 has a 1 / N channel width of the transistor NP, the source is grounded, and the gate is connected to the signal line 700. A constant current source 702 having a current value I1 is interposed between the drain of the transistor 701 and the power supply line. Further, a constant current source 703 having a current value I2 and a P-channel transistor 704 are interposed between the drain of the transistor 701 and the power supply line. These constant current sources 702 and 703 and the transistor 704 serve as a constant current generating circuit that supplies a constant current to the transistor 701.

  Since the transistor 701 is supplied with a gate voltage (= GNP) common to the transistor NP, if the drain voltages of the transistors 701 and NP are the same, the drain current INP flowing in the transistor NP is equal to the drain current flowing in the transistor 701. Should be N times. Therefore, in this specific example, the transistor 701 is a switching element for comparison with the transistor NP, and the comparator 705 receives the comparison signal OUTPref generated at the drain of the transistor 701 as the comparison switching element and the signal OUTP generated at the drain of the transistor NP. Thus, it is determined whether or not the drain current INP flowing through the transistor NP is larger than N times the drain current flowing through the transistor 701.

  The comparator 705 includes constant current sources 731 and 732 and N channel transistors 733 and 734. A connection point between the constant current source 732 and the drain of the transistor 734 is an output terminal of the comparator 705, and an input terminal of the inverter 706 is connected to this output terminal. As a result of the level comparison between the signals OUTP and OUTPref by the comparator 705, when OUTP <OUTPref, the inverter 706 has an H level (non-level) indicating that the drain current INP of the transistor NP is smaller than N times the drain current of the transistor 701. Active level) overcurrent detection signal OVERCURN is output, and when OUTP> OUTPref, L level (active level) overcurrent detection indicating that the drain current INP of the transistor NP is larger than N times the drain current of the transistor 701 The signal OVERCURN is output.

  The low active AND gate 707 receives the comparison signal OUTPref and the overcurrent detection signal OVERCURN. The output signal of the low active AND gate 707 is supplied to the gates of the transistors 712 and 714 as the current limit command signal CURLMT and to the gate of the transistor 704.

The above-described transistor 704 is used as switching means for switching whether the constant current supplied to the transistor 701 is I1 + I2 or I1. Here, the current values I1 and I2 of the constant current sources 702 and 703 are set to values that satisfy the following equation.
N · (I1 + I2)> LMT (1)
N · I1 <LMT (2)

  In an initial state where the current limit command signal CURLMT is at an inactive level (L level), the transistor 704 is turned on, so that the current value of the constant current supplied to the transistor 704 is I1 + I2. Therefore, the allowable value UL is N · (I1 + I2), and when the drain current INP exceeding the allowable value UL flows to the transistor NP, the current detection unit 61NP receives an overcurrent detection signal of an active level (L level) from the inverter 706. OVERCURN is output, and an active level (H level) current limit command signal CURLMT is output from the low active AND gate 707.

  When the current limit command signal CURLMT becomes active level (H level), the transistor 704 is turned off, so that the current value of the constant current supplied to the transistor 704 is I1, and the allowable value UL is the current limit target value LMT. Lower value N · I1. This is because in the current detection unit 61NP, the response characteristics of the overcurrent detection signal OVERCURN and the current limit command signal CURLMT with respect to the change of the drain current INP have hysteresis characteristics, and the overcurrent detection signal OVERCURN and the current limit command signal CURLMT are vibrated. This is to obtain a stable operation.

  FIG. 10 is a waveform diagram showing the waveforms of the respective parts when a normal operation is performed at the connection point between the drains of the transistors PP and NP in the specific example without a power supply fault. FIG. 11 is a waveform diagram showing waveforms at various parts when there is a power fault at the connection point between the drains of the transistors PP and NP. Hereinafter, the operation of this example will be described with reference to these drawings.

  During the period when the input signal CNP to the pre-driver 53 is at H level, the transistor 53P is OFF and the transistor 53N is ON, so that the control signal GNP is L level (= 0V), the transistor NP is OFF, and the signal OUTP Becomes H level (= VDD). Since the level of the control signal GNP is 0V, the transistor 701 is turned off, and the level of the comparison signal OUTPref appearing at the drain of the transistor 701 is VDD. For this reason, the current limit command signal CURLMT output from the low active AND gate 707 becomes L level (inactive level), the transistor 712 is turned on, and the transistor 714 is turned off. Further, since the signal OUTP is at H level (= VDD), the output signal of the comparator 705 becomes H level, and the overcurrent detection signal OVERCURN output from the inverter 706 becomes L level.

  Next, as shown in FIGS. 10 and 11, when the input signal CNP to the pre-driver 53 falls, the transistor 53P is turned on, the transistor 53N is turned off, and the level of the control signal GNP appearing on the signal line 700 increases. Begin to. When the level of the control signal GNP exceeds the gate threshold value VT of the N-channel transistor, current starts to flow through the transistors NP and 701.

  When the level of the control signal GNP further increases and the saturation current of the transistor 701 exceeds the sum I1 + I2 of the current values of the constant current sources 702 and 703, the operating point of the transistor 701 moves from the saturation region to the non-saturation region. The signal OUTPref falls below the logical threshold value of the low active AND gate 707 (the boundary value between the input level range determined as the L level and the input level range determined as the H level, which is about VDD / 2 level).

  Here, when there is no power supply at the connection point between the drains of the transistors PP and NP, the drain current INP of the transistor NP becomes smaller than the allowable value UL = N (I1 + I2), and as shown in FIG. Since the level of OUTP is lower than that of the comparison signal OUTPref, the overcurrent detection signal OVERCURN becomes H level (inactive level). In this case, current limit command signal CURLMT maintains L level (inactive level), and control signal GNP rises to the level of power supply voltage VDD.

  On the other hand, when there is a power supply at the connection point between the drains of the transistors PP and NP and the drain current INP of the transistor NP becomes larger than the allowable value UL = N (I1 + I2), the level of the signal OUTP is as shown in FIG. Since it becomes higher than the comparison signal OUTPref, the overcurrent detection signal OVERCURN becomes L level (active level), and the current limit command signal CURLMT becomes H level (active level). As a result, the transistor 712 is turned off and the transistor 714 is turned on, the level of the control signal GNP is lowered to the current limiting gate voltage value, and the drain current INP of the transistor NP is limited to the current limiting target value LMT.

  Further, when the current limit command signal CURLMT becomes H level, the transistor 704 is turned off, and the allowable value UL that is a threshold for changing the current limit command signal CURLMT from H level to L level is changed from N · (I1 + I2) to N · I1. To drop. Therefore, even if the current limit command signal CURLMT becomes H level (active level), the level of the control signal GNP decreases, and the drain current INP decreases to the current limit target value LMT lower than N · (I1 + I2). Since the drain current INP (= LMT) at this time is higher than the allowable value UL (= N · I1), the current limit command signal CURLMT maintains the H level (active level).

This example has the following advantages over the first example.
a. In the first specific example, since the allowable value UL depends on the VT of the transistor, it varies depending on the manufacturing state of the class D amplifier. However, in this specific example, the allowable value UL is determined by the value of the constant current flowing through the transistor 701. Less affected by manufacturing variations.
b. In this specific example, since the response characteristics of the overcurrent detection signal OVERCURN and the current limit command signal CURLMT with respect to the change of the drain current INP have hysteresis characteristics, the overcurrent detection signal OVERCURN and the current limit command signal CURLMT do not vibrate. , Stable operation can be obtained.

  FIG. 12 is a circuit diagram showing a second specific example of the current limiting unit 60PP in the present embodiment. The current limiting unit 60PM has the same configuration as that shown in FIG.

  In the current limiting unit 60PP shown in FIG. 12, a P-channel transistor 741, constant current sources 742 and 743, an N-channel transistor 744, a comparator 745, an inverter 746, a NAND gate 747, a resistor 751, an N-channel transistor 752, a P-channel transistor 753 and 754 is an N channel transistor 701, constant current sources 702 and 703, P channel transistor 704, comparator 705, inverter 706, low active AND gate 707, resistor 711, P channel transistor 712, N in the current limiting unit 60NP of FIG. It plays a role corresponding to each of the channel transistors 713 and 714.

  The operation of the current limiting unit 60PP is basically the same as that of the current limiting unit 60NP of FIG. That is, the current detection unit 61PP compares the drain current IPP of the transistor PP with the allowable value UL = N · (I1 + I2). When the drain current IPP becomes larger than the allowable value UL, the overcurrent detection signal OVERCURN output from the inverter 746 is set to H level (active level), and the current limit command signal CURLMT output from the NAND gate 747 is L level (active level). As a result, the current control unit 62PP limits the drain current IPP of the transistor PP to the current limit target value LMT.

<Other embodiments>
As mentioned above, although one Embodiment of this invention was described, this invention can have other embodiment besides this. For example:

(1) In the above embodiment, the present invention is applied to a class D amplifier having a bridge-type output buffer circuit composed of two P-channel transistors and two N-channel transistors. The present invention may be applied to a class D amplifier having an output buffer circuit having an inverter configuration including a P channel transistor and an N channel transistor.

(2) In the above embodiment, the current limiter is provided corresponding to all the transistors constituting the output buffer circuit. However, in the case where there is a difference in the magnitude of overcurrent that can flow through each transistor, protection is provided. However, the current limiting unit may be provided only for some of the transistors that require the above.

(3) In the above embodiment, in addition to the current limiting unit, the current interrupting unit is provided in the overcurrent protection circuit, but the transistor of the output buffer circuit can be protected from the overcurrent only by the current limiting unit. The current interrupting unit may be omitted.

(4) Instead of providing a current cut-off unit, a warning signal is output to the outside of the D-class amplifier when the drain current is limited by the current limiter for the transistor of the output buffer circuit. May be. In this case, for example, an external device that has received the warning signal may take measures such as shutting off the power supply to the class D amplifier.

(5) In each of the above embodiments, each switching element of the output buffer circuit is configured by a field effect transistor, but each switching element may be configured by a bipolar transistor.

(6) In each of the above embodiments, the current limiting circuit according to the present invention is used as an overcurrent protection circuit for a class D amplifier. However, the current limiting circuit according to the present invention is a switching element that handles a relatively large current, such as a switching regulator, for example. In a circuit having the above, it may be used as a circuit for protecting the switching element from an overcurrent.

(7) In each of the above embodiments, the current limiting circuit according to the present invention is used as an overcurrent protection circuit. However, the current limiting circuit according to the present invention is not limited to such protection from overcurrent, and no overcurrent flows. During normal operation, it may be used to limit the current flowing through the switching element within a current limit target value.

It is a circuit diagram which shows the structure of the class D amplifier provided with the overcurrent protection circuit which is one Embodiment of the current limiting circuit by this invention. FIG. 3 is a waveform diagram showing waveforms of control signals applied to the gates of the transistors of the output buffer circuit 10 in the same embodiment in a normal state. 5 is a time chart showing an operation example of overcurrent protection when a connection between the drains of the transistors NP and PP of the output buffer circuit 10 in the embodiment has a power fault and an overcurrent flows through the transistor NP. It is a circuit diagram which shows the structural example of the electric current interruption part 30 in the same embodiment. 3 is a circuit diagram showing a first specific example of a current limiting unit 60NP in the same embodiment. FIG. In the same specific example, it is a wave form diagram which shows the waveform of each part in case there is no power supply at the connection point of the drains of transistor PP and NP, and normal operation is performed. In the same specific example, it is a wave form diagram which shows the waveform of each part when there is a power fault in the connection point of the drains of transistors PP and NP. FIG. 4 is a circuit diagram showing a first specific example of a current limiting unit 60PP in the same embodiment. It is a circuit diagram showing the 2nd example of current limiting part 60NP in the embodiment. In the same specific example, it is a wave form diagram which shows the waveform of each part in case there is no power supply at the connection point of the drains of transistors PP and NP and normal operation is performed. In the same specific example, it is a wave form diagram which shows the waveform of each part when there is a power fault in the connection point of the drains of transistors PP and NP. It is a circuit diagram showing the 2nd example of current limiting part 60PP in the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Output buffer circuit, PP, PM ... P channel transistor, NP, NM ... N channel transistor, L ... Load, 20 ... PWM modulation part, 30 ... Current interruption part, 60PP, 60PM, 60NP, 60NM: current limiting unit, 61PP, 61PM, 61NP, 61NM ... current detecting unit, 62PP, 62PM, 62NP, 62NM ... current control unit.

Claims (4)

For the controlled object field effect transistor for passing a current corresponding to the level of the control signal applied to the gate, a current detection unit for detecting a current flowing through the controlled object field effect transistor,
When a current exceeding an allowable value is detected by the current detection unit, control is given to the gate of the control target field effect transistor so that the current flowing through the control target field effect transistor is limited to a predetermined current limit target value. A current control unit having a current control unit for controlling a signal level ;
The current detector is
A comparative field effect transistor in which a control signal common to the control target field effect transistor is applied to a gate;
A constant current generating circuit for supplying a constant current having a current value determined in accordance with the allowable value to the drain of the comparative field effect transistor;
Compares the voltage applied to the drain of the comparative field effect transistor with the voltage applied to the drain of the controlled field effect transistor, and whether a current exceeding the allowable value flows through the controlled field effect transistor. And a comparator for determining whether or not . When the current flowing through the control target field effect transistor is monitored and it is detected that a current exceeding a reference value smaller than the allowable value has continuously flowed through the control target field effect transistor for a predetermined time or more, the control target electric field 2. The current limiting circuit according to claim 1, further comprising a current cutoff unit that controls a level of a control signal applied to a gate of the control target field effect transistor so that the effect transistor is turned off. 3. The current control unit is configured to fix the control signal at a predetermined level when the current detection unit detects a current exceeding the allowable value, thereby to control the current flowing through the control target field effect transistor to the current limit target value. The current limiting circuit according to claim 1, wherein the current limiting circuit is limited to The current detection unit controls the control signal to limit the current flowing through the control target field effect transistor to the current limit target value when the current flowing through the control target field effect transistor exceeds the allowable value. The current controller to reduce the current value of the constant current supplied from the constant current generation circuit to the drain of the comparative field effect transistor to a current value corresponding to an allowable value lower than the allowable value. The current limiting circuit according to any one of claims 1 to 3, characterized in that

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