JP4535028B2 - Class D amplifier and overcurrent protection method thereof - Google Patents

Description

  The present invention relates to a class D amplifier suitable for audio equipment and the like, and particularly to a class D amplifier having an overcurrent protection function.

As a class D amplifier, one having a bridge circuit composed of four transistors as an output buffer circuit is generally known. In this class D amplifier, the first and second transistors inserted in series between the high-level power supply line and the low-level power supply line and the series connection between the high-level power supply line and the low-level power supply line are also provided. A bridge circuit as an output buffer circuit is configured by the inserted third and fourth transistors. The first and fourth transistor sets and the second and third transistor sets are alternately turned on by the pulse modulated according to the input signal, and the connection point between the first and second transistors. And a load such as a speaker inserted between the connection point of the third transistor and the fourth transistor is driven. Here, in order to appropriately drive a load such as a speaker, it is necessary to reduce the ON resistances of the first to fourth transistors. However, when the ON resistances of the first to fourth transistors are lowered, if some of the loads have a ground fault or a ground fault, or if both ends of the load are short-circuited, some transistors may exceed the allowable range. Current flows, and in the worst case, the transistor can be destroyed. As a technique for solving this problem, Patent Document 1 proposes a technique for monitoring the current flowing through each transistor and immediately turning off all the transistors when an overcurrent is detected in a certain transistor. ing.
JP 2002-171140 A

  However, when the load of the class D amplifier is an inductive load such as a speaker, when all the transistors are turned off by detecting the overcurrent, the load inductance tries to maintain the current that has been flowing so far, A large voltage is generated at both ends. For this reason, a large voltage exceeding the level of the power supply voltage is generated at some output nodes of the output buffer circuit, causing a problem of damaging related transistors and loads.

  The present invention has been made in view of the circumstances described above, and when an overcurrent occurs in the switching element of the output buffer circuit, each switching element without causing any significant damage to each switching element or load of the output buffer circuit. An object of the present invention is to provide a class D amplifier capable of transitioning an element to an OFF state and an overcurrent protection method thereof.

In the present invention, the first and second switching elements inserted in series between the high level power supply line and the low level power supply line and the high level power supply line and the low level power supply line are inserted in series. The third switching element and the fourth switching element, and the first and fourth switching elements and the second and third switching elements are alternately switched by a pulse modulated according to an input signal. In a class D amplifier that drives a load interposed between the connection point of the first and second switching elements and the connection point of the third and fourth switching elements by turning on An overcurrent detection unit that detects an overcurrent in each of the first to fourth switching elements, and an overcurrent in any of the first to fourth switching elements is detected by the overcurrent detection unit. At least one switching element other than the switching element in which an overcurrent is detected among the first to fourth switching elements is used as a discharging switching element, and the first to fourth switching elements are discharged. A switching circuit that is not a switching element is turned off, and the switching element that is the discharging switching element is provided with a protection circuit that is turned on after being turned on for a predetermined time. .
According to this invention, when an overcurrent is detected in a certain switching element, at least one switching element other than the switching element in which the overcurrent is detected is used as a discharge switching element, and the first to fourth switching elements Among them, switching elements that are not discharging switching elements are turned off, and switching elements that are discharging switching elements are turned on for a predetermined time and then turned off. Therefore, when detecting an overcurrent, the electric energy accumulated in the load can be discharged through the discharge switching element, and an excessive voltage can be prevented from being applied to each switching element.

Embodiments of the present invention will be described below with reference to the drawings.
<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a class D amplifier 100 according to the first embodiment of the present invention. In FIG. 1, a high level power supply line 1 is connected to a positive electrode of a power supply (not shown), and a low level power supply line 2 is connected to a negative electrode of the same power supply and grounded. Each circuit constituting the class D amplifier 100 is configured by a field effect transistor (hereinafter simply referred to as a transistor) or the like, and these circuits are connected to the power supply voltage VDD via the high level power line 1 and the low level power line 2. Is given.

  The output buffer circuit 10 forms the final output stage of the class D amplifier 100, and includes a P-channel transistor PP as a first switching element, an N-channel transistor NP as a second switching element, and a third switching element. P-channel transistor PM and an N-channel transistor NM which is a fourth switching element. Here, the sources of the P-channel transistors PP and PM are connected to the high-level power supply line 1, and the sources of the N-channel transistors NP and NM are connected to the low-level power supply line 2. The drains of the P channel transistor PP and the N channel transistor NP are connected to each other, and this connection point is connected to one end of the load L. Similarly, the drains of the P channel transistor PM and the N channel transistor NM are connected to each other. This connection point is connected to the other end of the load L.

  The load L is, for example, a speaker. When the class D amplifier 100 is in operation, a fault or a ground fault occurs at one end of the load L, or an accident occurs in which both ends of the load L are short-circuited, so that the transistors PP, NP, There is a case where an overcurrent having a current value exceeding the allowable range flows in either PM or NM. A feature of the present embodiment is that when such an overcurrent is detected, the states of the transistors PP, NP, PM, and NM are changed so that the transistors PP, NP, PM, and NM and the load L are not damaged. And has a protection function that quickly attenuates overcurrent. The circuit configuration for this protection function will be described later.

  The PWM modulation unit 20 outputs four-phase pulses PWMPP, PWMNP, PWMPM, and PWMNM that are pulse-width modulated in accordance with the level of the input signal IN given from the outside. During normal operation without overcurrent generation or the like, these pulses PWMPP, PWMNP, PWMPM, and PWMNM pass through the gate signal control unit 60 as they are, and as the gate signals CNTPP, CNTNP, CNTPM, and CNTNM, The transistors PP, NP, PM and NM are respectively supplied to the gates.

  FIG. 2 shows waveforms of the gate signals CNTPP, CNTPM, CNTNP, and CNTNM (pulses PWMPP, PWMPM, PWMNP, and PWMNM) during the normal operation. In FIG. 2, in the period TA, the gate signals CNTPP, CNTPM, CNTNP, and CNTNM are set to the L level, the H level, the L level, and the H level, respectively, and the set of the P channel transistor PP and the N channel transistor NM is in the ON state. A set of transistor PM and N-channel transistor NP is turned off. Therefore, in the period TA, a current from the power source flows through the path of the P channel transistor PP, the load L, and the N channel transistor NM.

  In the period TB, the gate signals CNTPP, CNTPM, CNTNP, and CNTNM are set to the H level, the L level, the H level, and the L level, respectively, and the pair of the P channel transistor PM and the N channel transistor NP is in the ON state. And the set of N channel transistors NM is turned off. Therefore, in the period TB, a current from the power source flows through the path of the P channel transistor PM, the load L, and the N channel transistor NP.

  A dead time TD is interposed between the period TA and the subsequent period TB and between the period TB and the subsequent period TA. In the dead time TD, all of the transistors PP, NP, PM, and NM are turned off. During normal operation, the periods TA and TB are alternately repeated with a dead time TD interposed therebetween as shown in the figure, and the output buffer circuit 10 performs push-pull driving of the load L. The reason for providing the dead time TD between the periods TA and TB is to prevent the occurrence of a through current.

  In FIG. 1, the reference level generator 30 includes a P-channel transistor 31 and a constant current source 32 that are inserted in series between the high-level power supply line 1 and the low-level power supply line 2. The level at the connection point between the drain of the P-channel transistor 31 and the constant current source 32 is output to the overcurrent detection unit 40 as the reference level REFP. Here, the ratio between the size of the P-channel transistor 31 and the size of the P-channel transistor PP or PM is the ratio between the current value of the constant current source 32 and the upper limit value of the allowable range of the drain current of the P-channel transistor PP or PM. Match. Therefore, the reference level REFP corresponds to the drain level of the transistor when a drain current corresponding to the upper limit value of the allowable range flows through the P-channel transistor PP or PM. Similarly, the reference level generator 30 includes an N-channel transistor 33 and a constant current source 34 that are inserted in series between the high-level power supply line 1 and the low-level power supply line 2. The level at the connection point between the drain of the N-channel transistor 33 and the constant current source 34 is output to the overcurrent detection unit 40 as the reference level REFN. Here, the ratio between the size of the N-channel transistor 33 and the size of the N-channel transistor NP or NM is the ratio between the current value of the constant current source 34 and the upper limit value of the allowable range of the drain current of the N-channel transistor NP or NM. Match. Therefore, the reference level REFN corresponds to the drain level of the N-channel transistor NP or NM when a drain current corresponding to the upper limit value of the allowable range flows.

  The overcurrent detection unit 40 is supplied with reference levels REFP and REFN, the signal OUTP at the connection point between the drain of the P-channel transistor PP and the drain of the N-channel transistor NP in the output buffer circuit 10, and the P-channel transistor PM. A signal OUTM at a connection point between the drain and the drain of the N-channel transistor NM and gate signals CNTPP, CNTNP, CNTPM, and CNTNM for each transistor of the output buffer circuit 10 are provided. Based on these input signals, the overcurrent detection unit 40 detects the occurrence of overcurrent in each transistor of the output buffer circuit 10, and detects overcurrent detection signals IN-PCHP, IN- PCHM, IN-NCHP and IN-NCHM are output.

  FIG. 3 is a circuit diagram showing a configuration example of the overcurrent detection unit 40. In FIG. 3, the comparator 41 outputs an L level signal CPP when the level of the signal OUTP is lower than the reference level REFP, and an H level signal CPP when it is higher. The low active AND gate 42 outputs a P channel transistor PP when the gate signal CNTPP is at L level (that is, the P channel transistor PP is in an ON state) and the output signal CPP of the comparator 41 is at L level. An overcurrent detection signal IN-PCHP indicating that an overcurrent is flowing is set to an H level which is an active level. Similarly, the comparator 43 outputs an L level signal CPM when the level of the signal OUTM is lower than the reference level REFP, and the low active AND gate 44 determines that the gate signal CNTPM is at the L level and the comparator 43 When the output signal CPM is at the L level, the overcurrent detection signal IN-PCHM indicating that an overcurrent flows through the P-channel transistor PM is set to the H level that is the active level.

  The comparator 45 outputs an H level signal CNP when the level of the signal OUTP is higher than the reference level REFN, and the AND gate 46 outputs the output signal CNP of the comparator 45 when the gate signal CNTNP is at the H level. Is at the H level, the overcurrent detection signal IN-NCHP indicating that an overcurrent flows through the N-channel transistor NP is set to the H level which is the active level. Further, the comparator 47 outputs an H level signal CNM when the level of the signal OUTM is higher than the reference level REFN, and the AND gate 48 has the gate signal CNTNM at the H level and the output signal CNM of the comparator 47. Is at the H level, the overcurrent detection signal IN-NCHM indicating that an overcurrent flows through the N-channel transistor NM is set to the H level, which is the active level.

  In FIG. 1, the timing signal generation unit 50 and the gate signal control unit 60 damage the transistors PP, NP, PM, and NM and the load L of the output buffer circuit 10 when an overcurrent is detected by the overcurrent detection unit 40. In order to prevent the overcurrent from flowing, the transistors PP, NP, PM and NM function as a protection circuit that quickly attenuates overcurrent. Here, the function as the protection circuit will be described with reference to FIGS.

  As shown in FIG. 4A, when the set of the P-channel transistor PP and the N-channel transistor NM is turned on, an overcurrent may flow through the P-channel transistor PP or the N-channel transistor NM. In the example shown in FIG. 4A, it is detected that an overcurrent flows through the P-channel transistor PP. In this case, in the present embodiment, another P-channel transistor PM on the high-level power supply line 1 side when viewed from the load L is used as a discharge switching element in the same manner as the P-channel transistor PP in which overcurrent is detected. Then, as shown in FIGS. 4B and 4C, the timing signal generation unit 50 and the gate signal control unit 60 in this embodiment immediately turn off the transistors that are not the discharge switching elements and use the discharge switching elements. A certain P-channel transistor PM is temporarily turned on and then transitioned to an off state.

  When the state of each transistor is changed in this way, when the P-channel transistor PP and the N-channel transistor NM are turned off, the electric energy accumulated in the inductance of the load L is changed to the drain and the substrate of the N-channel transistor NP. Are discharged through a discharge path including a parasitic diode D, a load L, and a P-channel transistor PM.

  Here, if the P-channel transistor PM is left in the OFF state when the P-channel transistor PP in which the overcurrent is detected is turned off, the electrical energy accumulated in the inductance of the load L is changed to the P-channel transistor PM. Level of the connection point between the drain of the P-channel transistor PM and the drain of the N-channel transistor NM in order to escape to the high-level power supply line 1 side via a parasitic diode (not shown) between the drain of the transistor and the substrate And the transistor (in this case, the transistor PM or NM) and the load L of the output buffer circuit 10 are easily damaged.

  However, in this embodiment, when the P-channel transistor PP in which an overcurrent is detected is turned off, the P-channel transistor PM is temporarily turned on and then turned off. The rise in the level of the connection point with the drain of the N-channel transistor NM can be suppressed low, and an excessive voltage can be suppressed from being applied to the transistor of the output buffer circuit 10 and the load L.

  The same applies when an overcurrent is detected in another transistor. FIG. 5 shows the state transition state of each transistor that is performed when an overcurrent is detected in this embodiment, according to the overcurrent detection location. As described with reference to FIGS. 4A to 4C, when an overcurrent is detected in the P-channel transistor PP, the P-channel transistor PM is used as a discharge switching element. As shown in FIG. In addition, when an overcurrent is detected in the P-channel transistor PM, the P-channel transistor PP is selected. When an overcurrent is detected in the N-channel transistor NP, the N-channel transistor NM is selected. If detected, each N-channel transistor NP is used as a discharge switching element.

  That is, in this embodiment, when an overcurrent is detected in a P-channel transistor interposed between one end of the load L and the high level power supply line 1, the other end of the load L and the high level power supply line 1 are detected. And another P-channel transistor inserted between the N-channel transistor interposed between one end of the load L and the low-level power supply line 2 is detected as another discharge channel switching element. The other N-channel transistor interposed between the other end of the load L and the low-level power supply line 2 is used as a discharge switching element. After the overcurrent is detected, the transistors that are not the discharge switching elements are immediately turned off, and the transistors that are the discharge switching elements are temporarily turned on and then turned off.

  Normally, only the overcurrent of one transistor is detected as described above. However, when both ends of the load L are short-circuited, the overcurrent is detected in both of the two transistors that are turned on simultaneously. May be detected. In this case, in this embodiment, priority is given to overcurrent detection for the P-channel transistor, and the discharge switching element is determined. That is, as shown in FIG. 5, when an overcurrent is detected in both the P-channel transistor PP and the N-channel transistor NM, the P-channel transistor PM is discharged giving priority to the overcurrent detection for the P-channel transistor PP. When an overcurrent is detected in both the P-channel transistor PM and the N-channel transistor NP, the over-current detection for the P-channel transistor PM is given priority to the P-channel transistor PP as the discharge switching element. To do.

  Next, specific examples of the timing signal generation unit 50 and the gate signal control unit 60 that function as the protection circuit described above will be described.

  FIG. 6 is a circuit diagram showing a configuration example of the timing signal generator 50. In FIG. 6, the timer 501 outputs a positive pulse OCPP1 having a predetermined pulse width when the overcurrent detection signal IN-PCHP is maintained at the H level for a predetermined time T1 or more as shown in FIG. Similarly, the timers 502 to 504 are timers having the same configuration as the timer 501, and the timer 502 outputs the pulse OCPM1 when the overcurrent detection signal IN-PCHM maintains the H level for a predetermined time T1 or more. The timer 503 gives a pulse OCNP1 when the overcurrent detection signal IN-NCHP remains at the H level for a predetermined time T1 or more, and the timer 504 gives a pulse OCNP1 when the overcurrent detection signal IN-NCHM stays at the predetermined time T1 or more. When the H level is maintained, the pulse OCNM1 is output.

  The timers 511 to 514, together with the timers 501 to 504, constitute means for generating a discharge command pulse associated with the transistor in which overcurrent is detected. More specifically, as shown in FIG. 8, the timer 511 outputs a discharge command pulse OCPP2 having a pulse width T2 associated with the P-channel transistor PP using the pulse OCPP1 as a trigger, and the discharge command pulse OCPP2 A narrow pulse OCPP2T is output from the trigger output terminal T at the fall. The timers 512 to 514 are timers having the same configuration as the timer 511. The timer 512 is triggered by the pulse OCPM1 and is synchronized with the discharge command pulse OCPM2 having the pulse width T2 associated with the P-channel transistor PM and its falling edge. The timer 513 generates a discharge command pulse OCNP2 having a pulse width T2 associated with the N-channel transistor NP and a pulse OCNP2T having a narrow width synchronized with the fall thereof, with the pulse OCNP1 as a trigger. The timer 514 uses the pulse OCNM1 as a trigger to output a discharge command pulse OCNM2 having a pulse width T2 associated with the N-channel transistor NM and a narrow pulse OCNM2T synchronized with the falling edge.

  The priority circuit 520 is a well-known circuit in which inverters 521 to 523 and AND gates 524 to 526 are connected as shown in the figure. When only one discharge command pulse is generated, the discharge command pulse is gate-controlled. When two or more discharge command pulses are generated simultaneously, the discharge command pulse having the highest priority is selected and supplied to the gate signal control unit 60.

  More specifically, when the discharge command pulse OCPP2 is generated, the priority circuit 520 outputs the discharge command pulse OCPP2 to the gate signal control unit 60 as it is as the discharge command pulse OCPP. When the discharge command pulse OCPM2 is generated when the discharge command pulse OCPP2 is not generated and the output signal of the inverter 521 is at the H level, the AND gate 524 of the priority circuit 520 discharges the discharge command pulse OCPM2. The command pulse OCPM is output to the gate signal control unit 60. When discharge command pulse OCNP2 is generated when neither discharge command pulse OCPP2 nor OCPM2 is generated and both output signals of inverters 521 and 522 are at the H level, AND gate 525 of priority circuit 520 Outputs the discharge command pulse OCNP2 to the gate signal control unit 60 as the discharge command pulse OCNP. When discharge command pulse OCNM2 is generated in a state where none of discharge command pulses OCPP2, OCPM2, and OCNP2 is generated and all output signals of inverters 521, 522, and 523 are at the H level, priority circuit 520 AND gate 526 outputs discharge command pulse OCNM2 to gate signal control unit 60 as discharge command pulse OCNM. As described above, the priority circuit 520 selects each discharge command pulse output from the timers 511 to 514 in accordance with the priority of OCPP2> OCPM2> OCNP2> OCNM2, and outputs it as a discharge command pulse OCPP, OCPM, OCNP or OCNM. To do.

  Here, discharge command pulses OCPP, OCPM, OCNP and OCNM are each pulses having a pulse width T2. This pulse width T2 determines the duration of the ON state when the above-described discharge switching element is temporarily turned on. Details thereof will be made clear in the description of the operation of the present embodiment.

  OR gate 530 outputs a pulse OC that is a logical sum of discharge command pulses OCPP2, OCPM2, OCNP2, and OCNM2. This pulse OC is used for system control such as alarm output and power-off.

  The OR gate 541 outputs a pulse OCT that is a logical sum of the pulses OCPP2T, OCPM2T, OCNP2T, and OCNM2T. As shown in FIG. 9, the timer 542 uses the pulse OCT as a trigger to output a cutoff command pulse PNchOFF having a pulse width T3. This shut-off command pulse PNchOFF is used as a shut-off command signal for commanding all the transistors PP, PM, NP and NM of the output buffer circuit 10 to be turned off. Here, the pulses OCPP2T, OCPM2T, OCNP2T, and OCNM2T are generated when the discharge command pulses OCPP2, OCPM2, OCNP2, and OCNM2 fall from the active level to the inactive level, respectively. Therefore, the cutoff command pulse PNchOFF rises to the active level when the discharge command pulse falls to the inactive level after the discharge command pulse OCPP2, OCPM2, OCNP2, or OCNM2 rises to the active level. This cut-off command pulse PNchOFF is an active level for turning off all the transistors of the output buffer circuit 10 after the above-described discharge switching element is turned on for a predetermined time (specifically, the above-described time T2). Pulse.

As shown in FIG. 10, the timer 542 is replaced with a set-reset type flip-flop 543 that is set by a pulse OCT and reset by a reset signal generated in response to a power-off or system reset. The output signal may be used as a cutoff command signal instead of the cutoff command pulse PNchOFF.
The details of the configuration of the timing signal generator 50 have been described above.

  FIG. 11 is a circuit diagram illustrating a configuration example of the gate signal control unit 60. In FIG. 11, pre-drivers 641, 642, 643, and 644 are circuits that output gate signals CNTPP, CNTNP, CNTPM, and CNTNM, respectively, to each transistor of the output buffer circuit 10. A low active NAND gate 631, an AND gate 632, a low active NAND gate 633, and an AND gate 634 are arranged in front of each of the pre-drivers 641, 642, 643, and 644. One input terminal of each of the low active NAND gate 631, the AND gate 632, the low active NAND gate 633, and the AND gate 634 has a low active NOR gate 601, an OR gate 602, a low active NOR gate 603, and an OR gate 604. Each output terminal is connected. The other input terminals of the low active NAND gate 631, the AND gate 632, the low active NAND gate 633, and the AND gate 634 are output terminals of the OR gate 621, the NOR gate 622, the OR gate 623, and the NOR gate 624, respectively. Are connected to each other.

  Pulses PWMPP, PWMNP, PWMPM, and PWMNM output from the PWM modulator 20 are input to one input terminal of each of the low active NOR gate 601, the OR gate 602, the low active NOR gate 603, and the OR gate 604. . The other input terminal of each of the low active NOR gate 601, the OR gate 602, the low active NOR gate 603, and the OR gate 604 has a signal obtained by inverting the discharge command pulse OCPM by the inverter 611, a discharge command pulse OCNM, and a discharge command. A signal obtained by inverting pulse OCPP by inverter 612 and discharge command pulse OCNP are input.

The OR gate 621 has a discharge command pulse OCPP, OCNP, OCNM and a cutoff command pulse PNchOFF, the NOR gate 622 has a discharge command pulse OCPP, OCPM, OCNP and a cutoff command pulse PNchOFF, and the OR gate 623 has a Discharge command pulses OCPM, OCNP, OCNM and cutoff command pulse PNchOFF are input to NOR gate 624, and discharge command pulses OCPP, OCPM, OCNM and cutoff command pulse PNchOFF are input to NOR gate 624, respectively.
The details of the configuration of the gate signal control unit 60 have been described above.

Next, the operation of this embodiment will be described.
First, when the output terminal of the output buffer circuit 10 does not have a power supply fault, a ground fault, or the like, and the current flowing through each transistor of the output buffer circuit 10 is within an allowable range, the overcurrent detection unit 40 generates an overcurrent detection signal. IN-PCHP, IN-PCHM, IN-NCHP, and IN-NCHM are all set to an inactive L level. In this case, the timing signal generator 50 does not output any of the discharge command pulses OCPP, OCPM, OCNP, OCNM, and the cutoff command pulse PNchOFF. Therefore, in the gate signal control unit 60, the output signals of the OR gates 621 and 623 are at the L level, and the output signals of the NOR gates 622 and 624 are at the H level. Therefore, in this state, the pulse PWMPP output from the PWM modulation unit 20 is supplied to the pre-driver 641 via the low active NOR gate 601 and the low active NAND gate 631, and the pulse PWMNP is supplied to the OR gate 602 and the AND gate 632. To the pre-driver 642. The pulse PWMPM is supplied to the pre-driver 643 through the low active NOR gate 603 and the low active NAND gate 633, and the pulse PWMNM is supplied to the pre-driver 644 through the OR gate 604 and the AND gate 634. These pulses are supplied to the transistors PP, NP, PM and NM of the output buffer circuit 10 as gate signals CNTPP, CNTNP, CNTPM and CNTNM from the respective pre-drivers 641 to 644.

  Next, the operation of overcurrent protection in the present embodiment will be described with a specific example. First, for example, it is assumed that a ground fault occurs at the connection point between the drains of the P-channel transistor PP and the N-channel transistor NP in the output buffer circuit 10. In this case, when the set of the P channel transistor PP and the N channel transistor NM is in the ON state, there is a high possibility that an overcurrent exceeding the allowable range flows in the P channel transistor PP. FIG. 12 illustrates the waveform of each part in that case.

  In the example shown in FIG. 12, the set of the P-channel transistor PM and the N-channel transistor NP is in the ON state while the gate signals CNTPP, CNTPM, CNTNP, and CNTNM are at the H level, L level, H level, and L level, respectively. The pair of the P channel transistor PP and the N channel transistor NM is in the OFF state. In the illustrated example, from this state, first, the gate signal CNTPM becomes H level and the gate signal CNTNP becomes L level, and all the transistors of the output buffer circuit 10 are turned off. Next, the gate signal CNTPP becomes L level and the gate signal CNTNM becomes H level, and the set of the P channel transistor PP and the N channel transistor NM is turned on.

  At this time, if a ground fault occurs at the connection point between the drains of the P-channel transistor PP and N-channel transistor NP, the signal OUTM at the connection point between the drains of the P-channel transistor PM and N-channel transistor NM is the power supply voltage VDD. However, the signal OUTP at the connection point between the drains of the P-channel transistor PP and the N-channel transistor NP does not reach the level of the power supply voltage VDD due to the ground fault, and the P-channel transistor PP A large current flows. When a ground fault with a low resistance occurs and an overcurrent exceeding the allowable range flows through the P-channel transistor PP, the signal OUTP becomes a level lower than the reference level REFP as shown in the figure. In the case of the illustrated example, OUTP <REFP, OUTM <REFP, OUTP> REFN, and OUTM <REFN, so that the output signals CPP of the comparators 41, 43, 45, and 47 of the overcurrent detection unit 40 (see FIG. 3). , CPM, CNP and CNM are at L level, L level, H level and L level, respectively.

  In the overcurrent detection unit 40, since the output signal CPP of the comparator 41 is at L level and the gate signal CNTPP is at L level, the low active AND gate 42 activates the overcurrent detection signal IN-PCHP. It is assumed that the level is the H level. When this overcurrent detection signal IN-PCHP is maintained at the H level for the time T1, in the timing signal generator 50 (see FIG. 6), the timer 501 outputs the pulse OCPP1.

  Note that when the output signal CPM of the comparator 43 becomes L level, the gate signal CNTPM is already at H level, so the overcurrent detection signal IN-PCHM output from the low active AND gate 44 maintains L level. When the output signal CNP of the comparator 45 becomes H level, since the gate signal CNTNP is already at L level, the overcurrent detection signal IN-NCHP output from the AND gate 46 maintains L level. The output signal CNM of the comparator 47 falls with a delay from the rise of the gate signal CNTNM. For this reason, a period in which both the signals CNM and CNTNM are simultaneously at the H level occurs, and a narrow pulse-like overcurrent detection signal IN-NCHM is output from the AND gate 48. However, since the pulse width of the overcurrent detection signal IN-NCHM is shorter than the time T1, the timer 504 does not output the pulse OCNM1. Therefore, only the pulse OCPP1 is generated in the illustrated example.

  When the pulse OCPP1 is generated, the timer 511 uses the pulse OCPP1 as a trigger, outputs a discharge command pulse OCPP2 having a pulse width T2, and outputs a pulse OCPP2T when the discharge command pulse OCPP2 falls. Here, the discharge command pulse OCPP2 is supplied to the gate signal control unit 60 as the discharge command pulse OCPP via the priority circuit 520. The pulse OCPP2T is supplied to the timer 542 as the pulse OCT via the OR gate 541. The timer 542 outputs the interruption command pulse PNchOFF having the pulse width T3 to the gate signal control unit 60 using the pulse OCT as a trigger.

  As described above, when an overcurrent of the P-channel transistor PP is detected, the discharge command pulse OCPP associated with the P-channel transistor PP and the subsequent cutoff command pulse PNchOFF are generated, and the gate signal control unit 60 To be supplied. The gate signal control unit 60 (see FIG. 11) performs the following operation.

  First, discharge command pulse OCPP is applied to OR gate 621, NOR gate 622, and NOR gate 624 in each drive system of P channel transistor PP, N channel transistors NP, and NM that are not discharge switching elements in relation to P channel transistor PP. Entered. For this reason, during the period in which the discharge command pulse OCPP (= OCPP2) is maintained at the active H level, the output signal of the OR gate 621 is H level, the output signal of the NOR gate 622 is L level, and the output signal of the NOR gate 624 is Since it is at the L level, the gate signal CNTPP is at the H level, the gate signal CNTNP is at the L level, the gate signal CNTNM is at the L level, and the P channel transistor PP and the N channel transistors NP and NM are turned off.

  Discharge command pulse OCPP is inverted by inverter 612 and input to one input terminal of low active NOR gate 603 in the drive system of P channel transistor PM which is a switching element for discharge in relation to P channel transistor PP. The The pulse PWMPM that is the source of the gate signal CNTPM is input to the other input terminal of the low active NOR gate 603. At this time, the pulse PWMPM is at the H level. Therefore, a pulse (negative pulse) obtained by inverting the discharge command pulse OCPP by the inverter 612 passes through the low active NOR gate 603 and is input to one input terminal of the low active NAND gate 633. Here, the output signal of the OR gate 623 is applied to the other input terminal of the low active NAND gate 633. Since the discharge command pulse OCPP is not applied to the OR gate 623, the output signal of the OR gate 623 is L Is a level. Therefore, a pulse (negative pulse) obtained by inverting the discharge command pulse OCPP by the inverter 612 passes through the low active NAND gate 633 and is output from the pre-driver 643 as the gate signal CNTPM. Therefore, during the period when the discharge command pulse OCPP is at the H level, the gate signal CNTPM is at the L level, and the P-channel transistor PM is turned on.

  As described above, when an overcurrent is detected in the P channel transistor PP and the discharge command pulse OCPP is output, the discharge switching is performed in relation to the P channel transistor PP while the discharge command pulse OCPP maintains the active level. The P channel transistor PM which is an element is turned on, and other transistors PP, NP and NM which are not switching elements for discharge are turned off.

  Here, when the P-channel transistor PP and the N-channel transistor NM are turned off due to the generation of the discharge command pulse OCPP, the inductance of the load L tries to maintain the current that has been flowing in the load L until then. A large voltage is generated across L. For this reason, as illustrated in FIG. 4B, the electrical energy accumulated in the inductance of the load L is referred to as a parasitic diode D between the drain of the N-channel transistor NP and the substrate, the load L, and the P-channel transistor PM. It is discharged to the high level power supply line 1 side through the discharge path. At this time, as shown in FIG. 12, the signal OUTM appearing at the drain of the P-channel transistor PM is raised beyond the level of the power supply voltage VDD. However, in this embodiment, since the P-channel transistor PM is turned on at this time and discharge is performed through this, the lift amount can be suppressed small.

  Thereafter, when the discharge command pulse OCPP falls to the inactive level and the cutoff command pulse PNchOFF rises to the active level, the output signal of the OR gate 621 is H level, the output signal of the NOR gate 622 is L level, and the output of the OR gate 623 Since the signal is H level and the output signal of the NOR gate 624 is L level, the gate signal CNTPP is H level, the gate signal CNTNP is L level, the gate signal CNTPM is H level, and the gate signal CNTNM is L level. For this reason, all the transistors PP, NP, PM, and NM of the output buffer circuit 10 are turned off. This state is maintained over a period of time T3 when the cutoff command pulse PNchOFF maintains the H level.

  As described above, when an overcurrent of the P-channel transistor PP is detected, the P-channel transistor PM on the high-level power supply line 1 side as seen from the load is used as a discharge switching element, The transistors PP, NP and NM which are not switching elements are immediately turned off, and the transistor PM which is a discharge switching element is turned on only for a period of time T2, and then is turned off.

  Although not shown, the operation in the case where an overcurrent of another transistor in the output buffer circuit 10 is detected is the same. First, when an overcurrent of the P-channel transistor PM is detected, the P-channel transistor PP becomes a discharge switching element. In this case, upon detection of the overcurrent of the P channel transistor PM, a discharge command pulse OCPM having a pulse width T2 associated with the P channel transistor PM and a subsequent cutoff command pulse PNchOFF having a pulse width T3 are generated. Here, the discharge command pulse OCPM is a NOR gate 622, an OR gate 623, and a NOR gate in each drive system of the transistors NP, PM, and NM that are not discharge switching elements in relation to the P channel transistor PM in which an overcurrent is detected. 624, respectively. On the other hand, discharge command pulse OCPM is inverted by inverter 611 and applied to low active NOR gate 601 in the drive system of P channel transistor PP, which is a discharge switching element, in relation to P channel transistor PM in which overcurrent is detected. It is done. Therefore, while the discharge command pulse OCPM is at the H level, the P-channel transistor PP that is the discharge switching element is turned on, and the other transistors NP, PM, and NM that are not the discharge switching elements are turned off, and thereafter In other words, all the transistors PP, NP, PM, and NM are turned off when the pulse PNchOFF rises.

  When an overcurrent of the N channel transistor NP is detected, the N channel transistor NM serves as a discharge switching element. In this case, a discharge command pulse OCNP having a pulse width T2 and a subsequent cut command pulse PNchOFF having a pulse width T3 are generated by detecting an overcurrent of the N-channel transistor NP. Here, pulse OCNP is applied to OR gate 621, NOR gate 622, and OR gate 623 in each drive system of transistors PP, NP, and PM that are not discharge switching elements in relation to N channel transistor NP. On the other hand, discharge command pulse OCNP is applied to OR gate 604 in the drive system of N channel transistor NM, which is a discharge switching element, in relation to N channel transistor NP. Therefore, while the discharge command pulse OCNP is at the H level, the N-channel transistor NM that is the discharge switching element is turned on, and the other transistors PP, NP, and PM that are not the discharge switching elements are turned off, and thereafter In other words, all the transistors PP, NP, PM and NM are turned off by the rising of the cutoff command pulse PNchOFF.

  When an overcurrent of the N channel transistor NM is detected, the N channel transistor NP becomes a discharging switching element. In this case, a discharge command pulse OCNM having a pulse width T2 and a subsequent cut command pulse PNchOFF having a pulse width T3 are generated by detecting an overcurrent of the N-channel transistor NM. Here, discharge command pulse OCNM is applied to OR gate 621, OR gate 623 and NOR gate 624 in the drive systems of transistors PP, PM and NM that are not switching elements for discharge in relation to N channel transistor NM. . On the other hand, discharge command pulse OCNM is applied to OR gate 602 in the drive system of N channel transistor NP which is a switching element for discharge in relation to N channel transistor NM. Therefore, while the discharge command pulse OCNM is at the H level, the N-channel transistor NP that is the discharge switching element is turned on, and the other transistors PP, PM, and NM that are not the discharge switching elements are turned off, and thereafter In other words, all the transistors PP, NP, PM, and NM are turned off when the pulse PNchOFF rises. When an overcurrent of both the P channel transistor PP and the N channel transistor NM is detected, or when an overcurrent of both the P channel transistor PM and the N channel transistor NP is detected, an overcurrent of the P channel transistor is detected. The detection is prioritized and the same operation as when an overcurrent of the P-channel transistor PP or PM is detected is performed.

  As described above, according to the present embodiment, in the output buffer circuit 10, when an overcurrent is detected in a P-channel transistor interposed between one end of the load L and the high-level power supply line 1, Another P-channel transistor inserted between the other end of the load L and the high level power supply line 1 is used as a discharge switching element, and is inserted between one end of the load L and the low level power supply line 2. When an overcurrent is detected in the N-channel transistor, another N-channel transistor interposed between the other end of the load L and the low-level power supply line 2 is used as a discharge switching element, and the discharge switching element The transistor that is not is immediately turned off, and the transistor that is the switching element for discharge is turned on after being turned on for a predetermined time T2. Therefore, the electric energy accumulated in the inductance of the load L can be discharged through the discharge switching element, and an excessive voltage is applied to the drain of each transistor when the transistors of the output buffer circuit 10 are shifted to the OFF state. Can be prevented, and damage to each transistor and the load L can be reduced.

<Second Embodiment>
In the class D amplifier in this embodiment, the timing signal generator 50 and the gate signal controller 60 of the class D amplifier 100 in the first embodiment are replaced with the timing signal generator 50A and the gate signal controller 60A shown in FIG. It has a configuration. The configurations of the output buffer circuit 10, the PWM modulation unit 20, the reference level generation unit 30, and the overcurrent detection unit 40 are the same as those in the first embodiment.

  In the timing signal generation unit 50A in FIG. 13, the OR gate 551 takes the logical sum of the overcurrent detection signals IN-PCHP and IN-PCHM output from the overcurrent detection unit 40, and any of these signals is at the H level. If it is, an H level signal is output. The OR gate 552 calculates the logical sum of the overcurrent detection signals IN-NCHP and IN-NCHM output from the overcurrent detection unit 40, and when any of these signals is at the H level, Is output.

  The timer 561 outputs a pulse OCP1 when the output signal of the OR gate 551 maintains the H level for the time T1 or more. The timer 562 outputs a pulse OCN1 when the output signal of the OR gate 552 maintains the H level over the time T1. The timer 571 outputs a discharge command pulse OCP2 having a pulse width T2 associated with the P-channel transistor PP or PM with the pulse OCP1 as a trigger, and outputs a pulse OCP2T when the discharge command pulse OCP2 falls. The timer 572 outputs a discharge command pulse OCN2 having a pulse width T2 associated with the N-channel transistor NP or NM using the pulse OCN1 as a trigger, and outputs a pulse OCN2T when the discharge command pulse OCN2 falls. .

  When the discharge command pulse OCP2 is generated, it is supplied as it is to the gate signal control unit 60A as the discharge command pulse OCPch. To AND gate 582, a signal obtained by inverting discharge command pulse OCP2 by inverter 581 and discharge command pulse OCN2 are input. Accordingly, the discharge command pulse OCN2 passes through the AND gate 582 and is supplied to the gate signal control unit 60A as the discharge command pulse OCNch only when the discharge command pulse OCP2 is not generated. OR gate 583 outputs a pulse OC which is a logical sum of discharge command pulses OCP2 and OCN2. Similar to the first embodiment, the pulse OC is used for system control such as output of an alarm and power-off.

  The pulses OCP2T and OCN2T are supplied to the timer 592 through the OR gate 591. The timer 592 uses the pulse OCP2T or OCN2T given through the OR gate 591 as a trigger, outputs a cutoff command pulse PNchOFF having a pulse width T3, and supplies it to the gate signal control unit 60A. Note that the timer 592 may be replaced with a set-reset flip-flop as shown in FIG.

  In the gate signal control unit 60A, the configurations of the pre-drivers 641 to 644 and the preceding low active NAND gate 631, AND gate 632, low active NAND gate 633, and AND gate 634 are the same as the gate signal control unit in the first embodiment. Same as 60.

  One input terminal of each of the low active NAND gate 631, the AND gate 632, the low active NAND gate 633, and the AND gate 634 has a low active NOR gate 651, an OR gate 652, a low active NOR gate 653, and an OR gate 654. Each output terminal is connected. The other input terminals of the low active NAND gate 631, the AND gate 632, the low active NAND gate 633, and the AND gate 634 are the output terminals of the OR gate 671, NOR gate 672, OR gate 673, and NOR gate 674, respectively. Are connected to each other.

  Pulses PWMPP, PWMNP, PWMPM, and PWMNM output from the PWM modulator 20 are input to one input terminal of each of the low active NOR gate 651, the OR gate 652, the low active NOR gate 653, and the OR gate 654. . The other input terminal of each of the low active NOR gate 651, the OR gate 652, the low active NOR gate 653, and the OR gate 654 has a signal obtained by inverting the discharge command pulse OCNch by the inverter 661, a discharge command pulse OCPch, and a discharge command. A signal obtained by inverting pulse OCNch by inverter 662 and discharge command pulse OCPch are input.

The OR gate 671 has a discharge command pulse OCPch and a cutoff command pulse PNchOFF, the NOR gate 672 has a discharge command pulse OCNch and a cutoff command pulse PNchOFF, and the OR gate 673 has a discharge command pulse OCPch and a cutoff command pulse. The discharge command pulse OCNch and the cutoff command PNchOFF are input to the NOR gate 674, respectively.
The above is the details of the configuration of the class D amplifier according to the present embodiment.

Next, the operation of this embodiment will be described.
First, when the output terminal of the output buffer circuit 10 does not have a power supply fault, a ground fault, or the like, and the current flowing through each transistor of the output buffer circuit 10 is within an allowable range, the overcurrent detection unit 40 generates an overcurrent detection signal. IN-PCHP, IN-PCHM, IN-NCHP, and IN-NCHM are all set to the L level. In this case, the timing signal generator 50A does not output any of the discharge command pulses OCPch, OCNch and the cutoff command pulse PNchOFF. Therefore, in gate signal control unit 60A, the output signals of OR gates 671 and 673 are at L level, and the output signals of NOR gates 672 and 674 are at H level. Therefore, in this state, the pulse PWMPP output from the PWM modulation unit 20 is supplied to the pre-driver 641 via the low active NOR gate 651 and the low active NAND gate 631, and the pulse PWMNP is supplied to the OR gate 652 and the AND gate 632. To the pre-driver 642. The pulse PWMPM is supplied to the pre-driver 643 through the low active NOR gate 653 and the low active NAND gate 633, and the pulse PWMNM is supplied to the pre-driver 644 through the OR gate 654 and the AND gate 634. These pulses are supplied to the transistors PP, NP, PM and NM of the output buffer circuit 10 as gate signals CNTPP, CNTNP, CNTPM and CNTNM from the respective pre-drivers 641 to 644.

  Now, as shown in FIG. 14A, it is assumed that an overcurrent flows through the P-channel transistor PP when the set of the P-channel transistor PP and the N-channel transistor NM is turned on. In this case, the overcurrent detection unit 40 sets the overcurrent detection signal IN-PCHP to the H level. When this overcurrent detection signal IN-PCHP maintains the H level for the time T1 or more, the timing signal generator 50A (see FIG. 13) causes the discharge command pulse having the pulse width T2 associated with the P channel transistor PP. OCPch is output, and then a pulse PNchOFF having a pulse width T3 is output at the falling edge of the pulse OCPch.

  In gate signal control unit 60A (see FIG. 13), discharge command pulse OCPch is applied to OR gates 671 and 673 in each drive system of P channel transistors PP and PM, which are not switching elements for discharge in relation to P channel transistor PP, respectively. Supplied. Therefore, while the discharge command pulse OCPch is at the H level, the output signals of the OR gates 671 and 673 are at the H level, so that the gate signals CNTPP and CNTPM are at the H level, and the P-channel transistors PP and PM are in the OFF state. It becomes.

  On the other hand, discharge command pulse OCPch is supplied to OR gates 652 and 654 in each drive system of N channel transistors NP and NM, which are discharge switching elements, in relation to P channel transistor PP. Therefore, while discharge command pulse OCPch is at the H level, the output signals of OR gates 652 and 654 are at the H level. Since discharge command pulse OCPch is not supplied to NOR gates 672 and 674, the output signals of NOR gates 672 and 674 are at the H level. Therefore, while the discharge command pulse OCPch is at the H level, the gate signals CNTNP and CNTNM are at the H level, and the N channel transistors NP and NM are in the ON state as shown in FIG.

  Thereafter, when discharge command pulse OCPch falls and shut-off command pulse PCchOFF rises, the output signals of OR gates 671 and 672 become H level, and the output signals of NOR gates 672 and 674 become L level. Therefore, the gate signals CNTPP, CNTNP, CNTPM, and CNTNM become H level, L level, H level, and L level, respectively, and as shown in FIG. 14C, all the transistors PP, NP, PM of the output buffer circuit 10 And NM will be in an OFF state.

  As described above, in the present embodiment, when an overcurrent is detected in the P channel transistor PP on the high level power supply line 1 side when viewed from the load L, the N channel transistors NP and NM on the low level power supply line 2 side are detected. Is a switching element for discharge. Then, the timing signal generator 50A and the gate signal controller 60A according to the present embodiment immediately turn off the transistors other than the discharge switching element as shown in FIGS. 14B and 14C, The N-channel transistors NP and NM are temporarily turned on and then turned off.

  When the state of each transistor is changed in this way, when the P-channel transistor PP in which an overcurrent has flowed is turned off, the N-channel transistors NP and NM are turned on, so that they are accumulated in the inductance of the load L. The electrical energy is discharged through a closed-loop discharge path including the N-channel transistor NP, the load L, and the N-channel transistor NM that does not include a power source. Therefore, it is possible to effectively suppress the occurrence of an excessive voltage at the drain of each transistor of the output buffer circuit 10.

  The same applies when an overcurrent is detected in another transistor. FIG. 15 shows the state transition state of each transistor that is performed when an overcurrent is detected for each overcurrent detection location. As shown in FIG. 15, the state transition of each transistor when an overcurrent is detected in the P-channel transistor PP is as described with reference to FIGS.

  Even when an overcurrent is detected in the P-channel transistor PM, the timing signal generator 50A outputs the discharge command pulse OCPch having the pulse width T2 as in the case where the overcurrent is detected in the P-channel transistor PP. In response to the fall of the discharge command pulse OCPch, a cutoff command pulse PNchOFF having a pulse width T3 is output. Therefore, N-channel transistors NP and NM are discharge switching elements. Then, the P-channel transistors PP and PM that are not the discharge switching elements are immediately turned off, and the N-channel transistors NP and NM that are the discharge switching elements are turned on for the time T2 and then turned off.

  When an overcurrent is detected in the N channel transistor NP, the timing signal generator 50A outputs a discharge command pulse OCNch having a pulse width T2 associated with the N channel transistor NP, and then the discharge command pulse OCNch. A cutoff command pulse PNchOFF having a pulse width T3 is output at the falling edge.

  In gate signal control unit 60A, discharge command pulse OCNch is supplied to NOR gates 672 and 674 in each drive system of N channel transistors NP and NM that are not switching elements for discharge in relation to N channel transistor NP, respectively. Therefore, while discharge command pulse OCNch is at the H level, the output signals of NOR gates 672 and 674 are at the L level, so that gate signals CNTNP and CNTNM are at the L level, and N channel transistors NP and NM are in the OFF state. It becomes.

  On the other hand, discharge command pulse OCNch is applied to inverters 661 and 662, and the output signals of these inverters are connected to the drive systems of P-channel transistors PP and PM which are discharge switching elements in relation to N-channel transistor NP. Are supplied to the low active NOR gates 651 and 653, respectively. Therefore, while discharge command pulse OCNch is at the H level, the output signals of low active NOR gates 651 and 653 are at the L level. Since discharge command pulse OCNch is not supplied to OR gates 671 and 673, each output signal of OR gates 671 and 673 is at L level. Therefore, while the discharge command pulse OCNch is at the H level, the gate signals CNTPP and CNTPM are at the L level, and the P channel transistors PP and PM are in the ON state.

  Thereafter, when discharge command pulse OCNch falls and shut-off command pulse PCchOFF rises, the output signals of OR gates 671 and 672 become H level, and the output signals of NOR gates 672 and 674 become L level. For this reason, the gate signals CNTPP, CNTNP, CNTPM, and CNTNM become H level, L level, H level, and L level, respectively, and all the transistors PP, NP, PM, and NM of the output buffer circuit 10 are turned off.

  As described above, when an overcurrent is detected in the N-channel transistor NP on the low-level power supply line 2 side as viewed from the load L, the P-channel transistors PP and PM on the high-level power supply line 1 side as viewed from the load L are The switching element for discharge is used.

  Even when an overcurrent is detected in the N-channel transistor NM, the timing signal generator 50A outputs a discharge command pulse OCNch having a pulse width T2, as in the case where an overcurrent is detected in the N-channel transistor NP. Then, a cutoff command pulse PNchOFF having a pulse width T3 is output at the falling edge of the discharge command pulse OCNch. Accordingly, the P-channel transistors PP and PM are each used as a discharge switching element. Then, N-channel transistors NP and NM that are not discharging switching elements are immediately turned off, and P-channel transistors PP and PM that are discharging switching elements are turned on only for time T2, and then are turned off.

  Further, when an overcurrent is detected in both the P channel transistor PP and the N channel transistor NM, the N channel transistors NP and NM are set as the discharge switching elements with priority given to the overcurrent detection for the P channel transistor PP. When an overcurrent is detected in both the P-channel transistor PM and the N-channel transistor NP, the N-channel transistors NP and NM are set as discharge switching elements with priority given to overcurrent detection for the P-channel transistor PM. .

  As described above, according to the present embodiment, when an overcurrent is detected in the P-channel transistor on the high level power supply line 1 side in the output buffer circuit 10, two N on the low level power supply line 2 side are detected. When the channel transistor is a discharge switching element and an overcurrent is detected in the N-channel transistor on the low-level power supply line 2 side, the two P-channel transistors on the high-level power supply line 1 side are the discharge switching elements. Is done. The transistors that are not the discharge switching elements are turned off, and the two transistors that are the discharge switching elements are temporarily turned on and then turned off. Therefore, the electrical energy accumulated in the inductance of the load L is discharged through a closed loop including two transistors, which are the load and a switching element for discharging, and an excessive voltage is applied to the drain of each transistor of the output buffer circuit 10. Can be effectively suppressed.

<Third Embodiment>
This embodiment is a modification of the first embodiment. FIG. 16 shows the state transition of each transistor that is performed when an overcurrent of the P-channel transistor PP is detected in the present embodiment. FIG. 17 shows the state transition state of each transistor performed when an overcurrent is detected in this embodiment, according to the overcurrent detection location. In order to obtain such a state transition, it is necessary to change the circuit configuration of the gate signal control unit 60 in the first embodiment, but such a change can be easily made by those skilled in the art. Therefore, explanation is omitted.

  As shown in FIG. 16A, when an overcurrent is detected in the P-channel transistor PP, in this embodiment, the P-channel transistor PM and the N-channel transistor NP are used as discharge switching elements. Then, as shown in FIGS. 16B and 16C, the transistors PP and NM that are not the discharge switching elements are immediately turned off, and the transistors PM and NP that are the discharge switching elements are temporarily turned on. After that, it is turned off. When the state of each transistor is changed in this way, the electric energy accumulated in the load L can be discharged through the path of the transistor NP, the load L, and the transistor PM, and the voltage applied to each transistor of the output buffer circuit 10 Can be prevented from becoming excessive.

  The same applies to the case where an overcurrent is detected at another location. In the present embodiment, as shown in FIG. 17, a P-channel transistor interposed between one end of the load L and the high-level power supply line 1 ( For example, when an overcurrent is detected in the transistor PM), an N-channel transistor (for example, the transistor NM) interposed between one end of the load L and the low-level power supply line 2 and the other end of the load L and the high level A P-channel transistor (for example, a transistor PP) inserted between the power supply line 1 is used as a discharge switching element. When an overcurrent is detected in an N-channel transistor (for example, a transistor NP) inserted between one end of the load L and the low level power supply line 2, one end of the load L and the high level power supply line 1 A P-channel transistor (for example, transistor PP) interposed between the other end of the load L and an N-channel transistor (for example, transistor NM) interposed between the low-level power supply line 2 and the discharge switching element. To do. If overcurrent is detected in both the P-channel transistor and the N-channel transistor that are turned on simultaneously, priority is given to overcurrent detection for the P-channel transistor. Then, the transistor that is not the discharging switching element is immediately turned off, and the transistor that is the discharging switching element is temporarily turned on and then turned off.

  According to this embodiment, when each transistor of the output buffer circuit 10 is shifted to the OFF state by overcurrent detection, the high-level power supply line 1 and the low-level power supply line 2 among the transistors other than the transistor in which the overcurrent is detected. A P-channel transistor and an N-channel transistor connected in series with the load L interposed therebetween are used as a discharge switching element, and the electric energy accumulated in the load L is discharged through the discharge switching element. Therefore, also in this embodiment, it is possible to suppress an excessive voltage from being applied to each transistor of the output buffer circuit 10.

<Other embodiments>
Although the first to third embodiments of the present invention have been described above, there may be other embodiments besides this. For example:
(1) In the above embodiments, when overcurrent is detected in both the P-channel transistor and the N-channel transistor that are turned on simultaneously, priority is given to overcurrent detection for the P-channel transistor. Priority may be given to overcurrent detection.
(2) In each of the above embodiments, each switching element of the output buffer circuit is configured by a field effect transistor, but each switching element may be configured by a bipolar transistor.
(3) In each of the above embodiments, the processor performs the processing performed by the PWM modulation unit 20, the overcurrent detection unit 40, the timing signal generation unit 50 (50A), and the gate signal control unit 60 (60A). The output buffer circuit 10 may be driven and overcurrent protected.

1 is a circuit diagram showing a configuration of a class D amplifier according to a first embodiment of the present invention. FIG. It is a wave form diagram which shows the waveform of the gate signal at the time of normal operation | movement given to the output buffer circuit in the class D amplifier. It is a circuit diagram which shows the structure of the overcurrent detection part in the same class D amplifier. It is a figure which shows the operation | movement of the overcurrent protection in the same embodiment. 4 is a table showing the state transition of each transistor when an overcurrent is detected in the same embodiment, for each overcurrent detection location. It is a circuit diagram which shows the structure of the timing signal generation part in the same class D amplifier. It is a wave form diagram which shows the pulse generate | occur | produced in the same timing signal generation part. It is a wave form diagram which shows the pulse generate | occur | produced in the same timing signal generation part. It is a wave form diagram which shows the pulse generate | occur | produced in the same timing signal generation part. It is a circuit diagram which shows the other structural example of the timing signal generation part. It is a circuit diagram which shows the structure of the gate signal control part in the same class D amplifier. It is a wave form diagram which shows the waveform of each part when overcurrent protection operation is performed in the same embodiment. It is a circuit diagram which shows the structure of the timing signal generation part of the class D amplifier which is 2nd Embodiment of this invention, and a gate signal control part. It is a figure which shows the operation | movement of the overcurrent protection in the same embodiment. 4 is a table showing the state transition of each transistor when an overcurrent is detected in the same embodiment, for each overcurrent detection location. It is a figure which shows the operation | movement of the overcurrent protection in the class D amplifier which is 3rd Embodiment of this invention. 4 is a table showing the state transition of each transistor when an overcurrent is detected in the same embodiment, for each overcurrent detection location.

Explanation of symbols

100 ... Class D amplifier, 1 ... High level power line, 2 ... Low level power line, 10 ... Output buffer circuit, PP, PM ... P channel transistor, NP, NM ... N channel transistor, 20 ... ... PWM modulation unit, 40 ... overcurrent detection unit, 50, 50A ... timing signal generation unit, 60, 60A ... gate signal control unit.

Claims (9)

First and second switching elements interposed in series between a high level power line and a low level power line, and a third and a second switching element interposed in series between the high level power line and the low level power line A fourth switching element, and a set of the first and fourth switching elements and a set of the second and third switching elements are alternately turned on by a pulse modulated in accordance with an input signal. In the class D amplifier that drives a load interposed between the connection point of the first and second switching elements and the connection point of the third and fourth switching elements,
An overcurrent detector for detecting an overcurrent in each of the first to fourth switching elements;
When an overcurrent in a switching element interposed between one end of the load and the high-level power supply line is detected by the overcurrent detection unit, between the other end of the load and the high-level power supply line When the overcurrent detection unit detects an overcurrent in the switching element inserted between the one end of the load and the low-level power supply line, the inserted switching element is a discharge switching element. A switching element interposed between the other end of the first power supply line and the low-level power supply line is a discharging switching element, and among the first to fourth switching elements, a switching element that is not a discharging switching element is turned off, A switching element, which is a switching element for discharging, has a protection circuit that is turned on after being turned on for a predetermined time. Class D amplifier. First and second switching elements interposed in series between a high level power line and a low level power line, and a third and a second switching element interposed in series between the high level power line and the low level power line A fourth switching element, and a set of the first and fourth switching elements and a set of the second and third switching elements are alternately turned on by a pulse modulated in accordance with an input signal. In the class D amplifier that drives a load interposed between the connection point of the first and second switching elements and the connection point of the third and fourth switching elements,
An overcurrent detector for detecting an overcurrent in each of the first to fourth switching elements;
When an overcurrent in a switching element interposed between one end of the load and the high-level power supply line is detected by the overcurrent detection unit, each between the both ends of the load and the low-level power supply line When the two switching elements inserted are used as discharge switching elements, and an overcurrent in the switching element inserted between one end of the load and the low-level power supply line is detected by the overcurrent detection unit Two switching elements interposed between both ends of the load and the high-level power supply line are used as discharge switching elements, and the switching elements that are not discharge switching elements among the first to fourth switching elements And a protection circuit that turns off the switching element, which is the discharging switching element, after being turned on for a predetermined time;
A class-D amplifier comprising: First and second switching elements interposed in series between a high level power line and a low level power line, and a third and a second switching element interposed in series between the high level power line and the low level power line A fourth switching element, and a set of the first and fourth switching elements and a set of the second and third switching elements are alternately turned on by a pulse modulated in accordance with an input signal. In the class D amplifier that drives a load interposed between the connection point of the first and second switching elements and the connection point of the third and fourth switching elements,
An overcurrent detector for detecting an overcurrent in each of the first to fourth switching elements;
When an overcurrent in a switching element interposed between one end of the load and the high-level power supply line is detected by the overcurrent detection unit, the load is interposed between the one end of the load and the low-level power supply line. The inserted switching element and the switching element inserted between the other end of the load and the high-level power supply line serve as a discharge switching element, and are interposed between one end of the load and the low-level power supply line. When an overcurrent in the inserted switching element is detected by the overcurrent detector, the switching element inserted between one end of the load and the high-level power supply line, the other end of the load, and the low level A switching element that is interposed between the power line and the switching element is a discharging switching element, and is a switching element that is not a discharging switching element among the first to fourth switching elements. And the OFF state, the switching element and said a discharge switching element and the protection circuit to the OFF state after only ON state for a predetermined time
A class-D amplifier comprising: The protection circuit is
A discharge command pulse associated with a switching element in which an overcurrent is detected, and a timing signal generating unit that outputs a cutoff command signal that rises to an active level when the discharge command pulse falls from an active level to an inactive level;
A discharge command pulse associated with the switching element in which the overcurrent is detected is output, and the discharge switching element in relation to the switching element in which the overcurrent is detected while the discharge command pulse maintains an active level. A gate signal that turns on a switching element that is a switching element that is not a discharging switching element and that turns off all the first to fourth switching elements while the cutoff command signal is at an active level. With control
The class D amplifier according to any one of claims 1 to 3, further comprising: The timing signal generation unit outputs a discharge command pulse associated with the switching element when an overcurrent is detected continuously for a predetermined time or more in one switching element. Class D amplifier as described. The timing signal generation unit supplies the discharge command pulse to the gate signal control unit when only one discharge command pulse is generated, and has the highest priority when a plurality of discharge command pulses are generated simultaneously. 6. The class D amplifier according to claim 4, further comprising a priority circuit that selects and supplies one discharge command pulse to the gate signal control unit. First and second switching elements interposed in series between a high level power line and a low level power line, and a third and a second switching element interposed in series between the high level power line and the low level power line A fourth switching element, and a set of the first and fourth switching elements and a set of the second and third switching elements are alternately turned on by a pulse modulated in accordance with an input signal. In the method for overcurrent protection of the class D amplifier for driving a load interposed between the connection point of the first and second switching elements and the connection point of the third and fourth switching elements. ,
An overcurrent detection process for detecting an overcurrent in each of the first to fourth switching elements;
When an overcurrent in a switching element interposed between one end of the load and the high level power supply line is detected by the overcurrent detection process, between the other end of the load and the high level power supply line When the overcurrent in the switching element inserted between the one end of the load and the low-level power line is detected by the overcurrent detection process, the inserted switching element is a discharge switching element. A switching element interposed between the other end of the first power supply line and the low-level power supply line is a discharging switching element, and among the first to fourth switching elements, a switching element that is not a discharging switching element is turned off, The switching process, which is a switching element for discharging, is a protection process in which the switching element is turned on after being turned on for a predetermined time.
An overcurrent protection method for a class D amplifier, comprising: First and second switching elements interposed in series between a high level power line and a low level power line, and a third and a second switching element interposed in series between the high level power line and the low level power line A fourth switching element, and a set of the first and fourth switching elements and a set of the second and third switching elements are alternately turned on by a pulse modulated in accordance with an input signal. In the method for overcurrent protection of the class D amplifier for driving a load interposed between the connection point of the first and second switching elements and the connection point of the third and fourth switching elements. ,
An overcurrent detection process for detecting an overcurrent in each of the first to fourth switching elements;
When an overcurrent in a switching element interposed between one end of the load and the high level power supply line is detected by the overcurrent detection process, each between the both ends of the load and the low level power supply line When the two switching elements inserted are used as switching elements for discharge, and an overcurrent in the switching element inserted between one end of the load and the low-level power supply line is detected by the overcurrent detection process Two switching elements interposed between both ends of the load and the high-level power supply line are used as discharge switching elements, and the switching elements that are not discharge switching elements among the first to fourth switching elements Is turned off, and the switching element that is the discharge switching element is turned on after a predetermined time. And
An overcurrent protection method for a class D amplifier, comprising: First and second switching elements interposed in series between a high level power line and a low level power line, and a third and a second switching element interposed in series between the high level power line and the low level power line A fourth switching element, and a set of the first and fourth switching elements and a set of the second and third switching elements are alternately turned on by a pulse modulated in accordance with an input signal. In the method for overcurrent protection of the class D amplifier for driving a load interposed between the connection point of the first and second switching elements and the connection point of the third and fourth switching elements. ,
An overcurrent detection process for detecting an overcurrent in each of the first to fourth switching elements;
When an overcurrent in a switching element inserted between one end of the load and the high level power supply line is detected by the overcurrent detection process, the switch is interposed between the one end of the load and the low level power supply line. The inserted switching element and the switching element inserted between the other end of the load and the high-level power supply line serve as a discharge switching element, and are interposed between one end of the load and the low-level power supply line. When an overcurrent in the inserted switching element is detected by the overcurrent detection process, the switching element inserted between one end of the load and the high level power line, the other end of the load, and the low level A switching element interposed between the power line and the switching element for discharging is a switching element that is not a discharging switching element among the first to fourth switching elements. A child in the OFF state, the switching element and said a discharge switching element and the protection process of the OFF state after the ON state for a predetermined time
An overcurrent protection method for a class D amplifier, comprising:

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