JP5664012B2 - Light emitting element array chip, light emitting element head, and image forming apparatus - Google Patents

Description

  The present invention relates to a light emitting element array chip, a light emitting element head, and an image forming apparatus.

  In image forming apparatuses such as printers, copiers, and facsimiles that employ an electrophotographic method, after obtaining an electrostatic latent image by irradiating image information onto a uniformly charged photoreceptor by optical recording means The electrostatic latent image is visualized by adding toner, and the image is formed by transferring and fixing on the recording paper. As such an optical recording means, in addition to an optical scanning method in which a laser beam is scanned in a main scanning direction using a laser for exposure, in recent years, a large number of LED (Light Emitting Diode) array light sources are arranged in the main scanning direction. An optical recording means using an LED head is employed.

In Patent Document 1, a p-type semiconductor layer, an n-type semiconductor layer, a p-type semiconductor layer, and an n-type semiconductor layer are stacked on a p-type substrate to form a PNPN structure, and the cathode layer constitutes a cathode island. However, a light-emitting thyristor is disclosed in which the active layer and the anode layer are separated by the same mesa surface and the peripheral portion is etched to form a thin portion.
In Patent Document 2, the circuit is divided into a left side circuit and a right side circuit. For each of the left and right circuits, the clock pulses φ1, φ2, the start pulse φ _S , and the write signal φ _I are separated from each other, and only the power source V _GK is shared. A self-scanning light emitting element array chip is disclosed.

JP 2004-179368 A JP 2002-111063 A

  Here, disturbances such as noise and surge may be mixed in the signal for driving the light emitting element array chip. In this case, it is desirable to suppress damage to the light emitting element array chip that may be caused by disturbance by the single chip.

According to a first aspect of the present invention, there is provided a light emitting element array having a plurality of light emitting elements arranged in a line in the main scanning direction, an electrode portion for inputting / outputting a signal for driving the light emitting element array, and the light emission A wiring portion connecting the element array and the electrode portion; and a wiring portion formed between the light emitting element array and the electrode portion and connected to the wiring portion; A protective element for protecting the light emitting element array , wherein the light emitting element is formed of four layers having a pnpn structure formed on a substrate, and the protective element is formed on the substrate side of the pnpn structure. The light emitting element array chip is formed of a layer, and the wiring portion is electrically connected to a third layer from the substrate side, which is the uppermost layer of the protection element, at one point .

The invention according to claim 2, wherein the protective element is a light-emitting element array chip according to claim 1, characterized in that connected to the wiring portion for transmitting a lighting signal for lighting the light emitting element.

According to a third aspect of the present invention, there is provided a light emitting element array having a plurality of light emitting elements arranged in a line in the main scanning direction, an electrode portion for inputting / outputting a signal for driving the light emitting element array, and the light emission A wiring portion that connects the element array and the electrode portion; a wiring portion that is formed between the light emitting element array and the electrode portion and connected to the wiring portion; A light-emitting element array chip comprising a protective element for protecting the light-emitting element array, an optical element for forming an electrostatic latent image by exposing the photosensitive member by imaging the light output of the light-emitting element array, and The light emitting element is formed of four layers of a pnpn structure formed on a substrate, the protection element is formed of the substrate side three layers of the pnpn structure, and the wiring portion is formed of the protection On the top layer of the device Electrically with the third layer of the layer from the substrate side is a light-emitting element head, characterized in that it is connected at one point.

The invention described in claim 4 includes a toner image forming unit that forms a toner image, a transfer unit that transfers the toner image to a recording medium, and a fixing unit that fixes the toner image to the recording medium. The toner image forming means includes a light emitting element array having a plurality of light emitting elements arranged in a row in the main scanning direction, an electrode unit for inputting and outputting a signal for driving the light emitting element array, and the light emitting element array And a wiring part that connects the electrode part to the wiring part, and is formed between the light emitting element array and the electrode part and connected to the wiring part, and from the disturbance that is input to the wiring part, the wiring part and the light emitting element A light-emitting element array chip including a protection element for protecting the array; and an optical element for forming an electrostatic latent image by exposing the photosensitive member by imaging the light output of the light-emitting element array. Light emitting element Comprising a head, said light emitting element is formed by four layers of pnpn structure formed on a substrate, wherein the protective element is formed by the substrate-side three layers of the pnpn structure, the wiring portion, The image forming apparatus is electrically connected to the third layer from the substrate side, which is the uppermost layer of the protection element, at one point .

According to the first aspect of the present invention, it is possible to provide a light emitting element array chip that is less likely to be damaged even when a disturbance is mixed in a signal for driving the light emitting element array chip as compared with the case where this configuration is not adopted. In addition, the protective element can be manufactured together with the light-emitting element as compared with the case where this configuration is not employed.
According to the second aspect of the present invention, it is possible to protect the light emitting element from disturbance as compared with the case where this configuration is not adopted.
According to the invention of claim 3 , it is possible to provide a light emitting element head that operates more stably as compared with the case where this configuration is not adopted.
According to the invention of claim 4 , it is possible to provide an image forming apparatus with less image disturbance as compared with the case where this configuration is not adopted.

1 is a diagram illustrating an example of an overall configuration of an image forming apparatus to which the exemplary embodiment is applied. It is the figure which showed the structure of the light emitting element head to which this Embodiment is applied. It is a top view of the circuit board and the light emission part in a light emitting element head. (A)-(b) is the figure explaining the structure of the light emitting chip to which this Embodiment is applied. It is the figure which showed the wiring diagram formed on a circuit board when the self-scanning light emitting element array chip is employ | adopted as a light emitting chip. It is a figure for demonstrating the circuit structure at the time of employ | adopting a self-scanning light emitting element array chip as a light emitting chip. It is a timing chart of the signal which drives a light emitting chip. It is the figure explaining the flow of the electric current in the drive device which drives a light emitting chip. It is the figure explaining the flow of the electric current in the drive device which drives a light emitting chip. It is the figure explaining the flow of the electric current in the drive device which drives a light emitting chip. It is the figure explaining the flow of the electric current in the drive device which drives a light emitting chip. It is a figure explaining the 1st form of the protection element. It is a figure explaining the 2nd form of the protection element. It is a figure explaining the 3rd form of a protection element.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
<Description of Image Forming Apparatus>
FIG. 1 is a diagram illustrating an example of the overall configuration of an image forming apparatus to which the exemplary embodiment is applied.
An image forming apparatus 1 shown in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process unit 10 that forms an image corresponding to image data of each color, an image output control unit 30 that controls the image forming process unit 10, such as a personal computer (PC) 2 or an image reading device. 3 and an image processing unit 40 that performs predetermined image processing on image data received from these.

The image forming process unit 10 includes an image forming unit 11 composed of a plurality of engines arranged in parallel at regular intervals. The image forming unit 11 includes four image forming units 11Y, 11M, 11C, and 11K that are examples of toner image forming units. The image forming units 11Y, 11M, 11C, and 11K respectively form a photosensitive drum 12 as an example of an image carrier that forms an electrostatic latent image and holds a toner image, and a photosensitive material applied to the surface of the photosensitive drum 12. A charger 13 that uniformly charges the body at a predetermined potential, a light-emitting element head 14 that exposes a photosensitive member charged by the charger 13 to form an electrostatic latent image, and a static formed by the light-emitting element head 14. A developing device 15 is provided as an example of developing means for developing the electrostatic latent image. Here, the image forming units 11 </ b> Y, 11 </ b> M, 11 </ b> C, and 11 </ b> K have no difference in configuration except for the toner stored in the developing device 15. The image forming units 11Y, 11M, 11C, and 11K form toner images of yellow (Y), magenta (M), cyan (C), and black (K), respectively.
Further, the image forming process unit 10 multiplex-transfers each color toner image formed on the photosensitive drum 12 of each image forming unit 11Y, 11M, 11C, and 11K onto a recording sheet as an example of a recording medium. A sheet conveying belt 21 that conveys the recording sheet, a driving roll 22 that is a roll for driving the sheet conveying belt 21, and a transfer roll 23 as an example of a transfer unit that transfers the toner image on the photosensitive drum 12 to the recording sheet. And a fixing device 24 as an example of fixing means for fixing the toner image on the recording paper.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the image output control unit 30. The image data received from the personal computer (PC) 2 or the image reading device 3 under the control of the image output control unit 30 is subjected to image processing by the image processing unit 40 and supplied to the image forming unit 11. The For example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged in a predetermined potential by the charger 13 while rotating in the direction of arrow A, and the image supplied from the image processing unit 40 is supplied. Exposure is performed by the light emitting element head 14 that emits light based on the data. As a result, an electrostatic latent image related to a black (K) color image is formed on the photosensitive drum 12. The electrostatic latent image formed on the photosensitive drum 12 is developed by the developing device 15, and a black (K) toner image is formed on the photosensitive drum 12. Similarly, yellow (Y), magenta (M), and cyan (C) toner images are formed in the image forming units 11Y, 11M, and 11C, respectively.

The toner images of the respective colors on the photosensitive drums 12 formed by the image forming units 11 are transferred to the recording paper supplied along with the movement of the paper conveying belt 21 moving in the arrow B direction. An electrostatic field is sequentially transferred by the electric field, and a composite toner image is formed in which toner of each color is superimposed on the recording paper.
Thereafter, the recording paper on which the synthetic toner image is electrostatically transferred is conveyed to the fixing device 24. The synthesized toner image on the recording paper conveyed to the fixing device 24 is fixed on the recording paper by the fixing device 24 by heat and pressure and discharged from the image forming apparatus 1.

<Description of light emitting element head>
FIG. 2 is a diagram illustrating a configuration of the light emitting element head 14 to which the exemplary embodiment is applied. The light-emitting element head 14 includes a housing 61, a light-emitting unit 63 including a plurality of LEDs as light-emitting elements, a circuit board 62 on which the light-emitting unit 63, the signal generation circuit 100 (see FIG. 3 described later), and the like are mounted. A rod lens (radial refractive index distribution type lens) array 64 as an example of an optical element for forming an electrostatic latent image by forming an image of the light output emitted from the unit 63 to expose the photosensitive member. Yes.

  The housing 61 is made of, for example, metal, supports the circuit board 62 and the rod lens array 64, and is set so that the light emitting point of the light emitting unit 63 and the focal plane of the rod lens array 64 coincide. Further, the rod lens array 64 is arranged along the axial direction (main scanning direction) of the photosensitive drum 12.

<Description of light emitting unit>
FIG. 3 is a top view of the circuit board 62 and the light emitting unit 63 in the light emitting element head 14.
As shown in FIG. 3, the light emitting unit 63 has a light emitting chip C (C1 to C60) as an example of 60 light emitting element array chips on a circuit board 62 facing each other in two rows in the main scanning direction. Arranged in a shape. Further, the circuit board 62 is mounted with a signal generation circuit 100 that generates a signal for driving a light emitting element array (see FIG. 4 described later) of the light emitting chip C.

<Description of Light Emitting Element Array Chip>
FIGS. 4A to 4B are diagrams illustrating the structure of a light-emitting chip C to which the present embodiment is applied.
FIG. 4A is a view of the light emitting chip C as seen from the direction in which the LED light is emitted. FIG. 4B is a cross-sectional view taken along line IVb-IVb in FIG.
In the light emitting chip C, as an example of the light emitting element array, a plurality of LEDs 81 arranged in a line in the main scanning direction are arranged in a straight line at equal intervals. Bonding pads 82 as an example of electrode portions for inputting and outputting signals for driving the light emitting element array are arranged on both sides of the substrate 80 so as to sandwich the light emitting element array. Each LED 81 is formed with a microlens 83 on the light emitting side. The light emitted from the LED 81 is collected by the microlens 83, and the light can be efficiently incident on the photosensitive drum 12 (see FIG. 2).
The microlens 83 is made of a transparent resin such as a photocurable resin, and the surface thereof preferably has an aspherical shape in order to collect light more efficiently. Further, the size, thickness, focal length, and the like of the microlens 83 are determined by the wavelength of the LED 81 used, the refractive index of the photocurable resin used, and the like.

<Description of Self-Scanning Light Emitting Element Array Chip>
In the present embodiment, it is preferable to use a self-scanning light emitting device (SLED) chip as the light emitting element array chip exemplified as the light emitting chip C. The self-scanning light-emitting element array chip uses a light-emitting thyristor having a pnpn structure as a constituent element of the light-emitting element array chip, and is configured to realize self-scanning of the light-emitting elements.

FIG. 5 is a diagram showing a wiring diagram formed on the circuit board 62 when a self-scanning light emitting element array chip is adopted as the light emitting chip C. FIG.
As shown in FIG. 5, on the circuit board 62, the signal lines 101 (101_1 to 101_60) for transmitting the lighting signals φI (φI1 to φI60) from the signal generating circuit 100 to the light emitting chip C, the transfer signal CK1 ( Signal lines 102 (102_1 to 102_6) for transmitting CK1_1 to 1_6), signal lines 103 (103_1 to 103_6) for transmitting transfer signals CK2 (CK2_1 to 2_6), and signal lines 104 for transmitting transfer signals CKS (CKS_1 to S_6). (104_1 to 104_6) are wired. On the circuit board 62, a + 3.3V power supply line 105 for supplying power to the light emitting chips C (C1 to C60) and a grounded (GND) power supply line 106 are wired.
That is, the lighting signal φI for each light emitting chip C is input to each light emitting chip C via the signal line 101. Further, the transfer signal CK1 (CK1_1 to 1_6) via the signal line 102, the transfer signal CK2 (CK2_1 to 2_6) via the signal line 103, and the transfer signal CKS (CKS_1 to S_6) via the signal line 104, respectively. Input to each light emitting chip C. Since each of the transfer signal CK1, the transfer signal CK2, and the transfer signal CKS can drive ten light emitting chips C, six sets of the signal lines 102, 103, and 104 are sufficient.

  FIG. 6 is a diagram for explaining a circuit configuration when a self-scanning light emitting element array chip is employed as the light emitting chip. Here, the light emitting chip C1 is described as an example, but the other light emitting chips C2 to C60 are not different from the light emitting chip C1 in configuration.

  As shown in FIG. 6, the light emitting chip C1 includes 60 transfer thyristors S1 to S60, 60 light emitting thyristors L1 to L60, and 61 diodes CR0 to CR60. In addition, the light emitting chip C1 includes resistors RS, R1B, R2B, and RID, and capacitors C1 and C2 as the driving device 110. The light-emitting chip C1 further includes a protection element 113 for protecting the transfer thyristors S1 to S60, the light-emitting thyristors (LEDs) L1 to L60, and the diodes CR0 to CR60 from disturbances such as noise and surge. Here, the light-emitting thyristors L1 to L60 correspond to the LED 81 described in FIG.

Here, the anode terminals A1 to A60 of the transfer thyristors S1 to S60 are connected to the power supply line 105. A power supply voltage VDD (VDD = + 3.3 V) is supplied to the power supply line 105.
The cathode terminals K1, K3,..., K59 of the odd-numbered transfer thyristors S1, S3,..., S59 are connected to the signal generating circuit 100 via the resistor R1A. A level shift circuit 111 is arranged in which a signal line connected to the resistor R1B and a signal line connected to the capacitor C1 are branched in parallel.
Further, the cathode terminals K2, K4,..., K60 of the even-numbered transfer thyristors are connected to the signal generating circuit 100 via the resistor R2A, but the resistor R2B is connected between the resistor R2A and the signal generating circuit 100. A level shift circuit 112 is arranged in which the signal line and the signal line to which the capacitor C2 is connected are branched in parallel.

On the other hand, the gate terminals G1 to G60 of the transfer thyristors S1 to S60 are respectively connected to the power supply line 106 via resistors R1 to R60 provided corresponding to the transfer thyristors. The power supply line 106 is grounded (GND).
The gate terminals G1 to G60 of the transfer thyristors S1 to S60 are connected to the gate terminals of the light emitting thyristors L1 to L60 provided corresponding to the transfer thyristors S1 to S60, respectively. Furthermore, the anode terminals of the diodes CR1 to CR60 are connected to the gate terminals G1 to G60 of the transfer thyristors S1 to S60. The cathode terminals of the diodes CR1 to CR60 are connected to the gate terminals of the next stage. That is, the diodes CR1 to CR60 are connected in series.

  The anode terminal of the diode CR1 is connected to the cathode terminal of the diode CR0, and the anode terminal of the diode CR0 is connected to the signal generating circuit 100 via a resistor RS which is a current limiting resistor. Further, the cathode terminals of the light emitting thyristors L1 to L60 are connected to the signal generating circuit 100 via a resistor RID which is a current limiting resistor. A protective element 113 is disposed between the resistor RID and the light emitting thyristors L1 to L60. The light emitting thyristors L1 to L60 are made of AlGaAsP or GaAsP as an example and have a band gap of about 1.5V.

  A signal for driving the light emitting element array generated by the signal generating circuit 100 is sent to the bonding pad 82 provided on the light emitting chip C through the driving device 110. Then, it is further sent from the bonding pad 82 to the transfer thyristors S1 to S60, the light emitting thyristors L1 to L60, and the diodes CR0 to CR60. Therefore, the wirings connecting the transfer thyristors S1 to S60, the diodes CR0 to CR60, and the transfer thyristors S1 to S60, the light emitting thyristors L1 to L60, and the diodes CR0 to CR60 are connected to the light emitting thyristors L1 to L60 that are light emitting element arrays and the electrode portions. It can be understood as a wiring portion that connects a certain bonding pad 82. In the present embodiment, the protective element 113 is connected to the wiring portion and plays a role of protecting the wiring portion and the light emitting thyristors L1 to L60 from disturbances input to the wiring portion.

Next, the operation of the present embodiment will be described with reference to the timing chart shown in FIG.
(1) In the initial state, since no current flows through all the transfer thyristors S1, S2, S3, S4,..., S60, they are turned off (FIG. 7A).

  (2) When the transfer signal CK1R is set to a low level (“L”) from the initial state (FIG. 7B), in the level shift circuit 111, a current flows in the direction of the arrow as shown in FIG. Eventually, the potential of the transfer signal CK1 becomes GND. Since the potential of the transfer signal CK1C is 3.3V, the potential across the capacitor C1 is 3.3V (VDD). In this case, the transfer signal CKS may be set to a high level (“H”) as indicated by a dotted line portion in FIG.

  (3) At the same time, when the transfer signal CKS is set to “H” and the transfer signal CK1C is set to “L” (FIG. 7C), the charge of the transfer signal CK1 is accumulated in the capacitor C1. It becomes about -33V. The gate G1 potential is ΦS potential −Vf = about 1.8V. Here, ΦS potential = about 3.3V, and Vf means a diode forward voltage of AlGaAs, which is about 1.5V. Further, Φ1 potential = G1 potential−Vf = 0.3V. For this reason, a potential difference of about 3.7 V is generated between the signal line Φ1 and the transfer signal CK1.

In this state, as shown in FIG. 8B, the gate current of the transfer thyristor S1 starts to flow through the route of the gate G1 → the signal line Φ1 → the transfer signal CK1. At that time, the tri-state buffer B1R of the signal generation circuit 100 is set to high impedance (Hi-Z) to prevent current backflow.
Thereafter, Tr2 is turned on by the gate current of the transfer thyristor S1, whereby the Tr1 source current (collector current of Tr2) flows, and the transfer thyristor S1 starts to turn on in the order that the Tr1 is turned on. To rise. At the same time, when a current flows into the capacitor C1 of the level shift circuit 111, the potential of the transfer signal CK1 also gradually increases.

(4) After the elapse of a predetermined time (time when the potential of the transfer signal CK1 becomes near GND), the tristate buffer B1R of the signal generation circuit 100 is set to “L” (FIG. 7D). As a result, the potential of the signal line Φ1 and the potential of the transfer signal CK1 rise due to the rise of the gate G1 potential, and accordingly, a current starts to flow to the resistor R1B side of the level shift circuit 111. On the other hand, as the potential of the transfer signal CK1 increases, the current flowing into the capacitor C1 of the level shift circuit 111 gradually decreases.
When the transfer thyristor S1 is completely turned on and enters a steady state, the potential at each point is as shown in FIG. That is, a current for maintaining the on state of the transfer thyristor S1 flows through the resistor R1B of the level shift circuit 111, but does not flow through the capacitor C1. Note that the potential of the transfer signal CK1 is CK1 potential = 1.8−1.8 × R1B / (R1A + R1B).

  (5) The lighting signal ID is set to “L” in a state where the transfer thyristor S1 is completely turned on (FIG. 7E). At this time, since the gate G1 potential> the gate G2 potential (gate G1 potential−gate G2 potential = 1.8 V), the light-emitting thyristor L1 having the thyristor structure is turned on earlier and is lit. As the light emitting thyristor L1 is turned on, the potential of the signal line Φ1 rises, and the potential of the signal line Φ1 = the gate G2 potential = 1.8 V. Therefore, the light emitting thyristors after the light emitting thyristor L2 are not turned on. That is, in L1, L2, L3, L4,..., L60, only the light emitting thyristor having the highest gate voltage is turned on (lit).

  (6) Next, when the transfer signal CK2R is set to “L” (FIG. 7 (f)), a current flows as in FIG. 7 (b), and a voltage is generated across the capacitor C2 of the level shift circuit 112. To do. In the steady state immediately before the end of FIG. 7 (f), since the gate G2 potential is 1.8V, the voltage value at each point is slightly different from that in FIG. 7 (b), but there is no influence on the operation. This is because the signal line Φ2 potential = gate G2 potential−Vf = 1.8V−1.5V = 0.3V in the steady state just before the end of FIG. 7F, as shown in FIG. In addition, a gate current flows through the transfer thyristor S2 in the direction of the dotted line, but this is so small that the transfer thyristor S2 is not turned on. In this case, the potential of the transfer signal CK2 is about CK2 potential = 0.3−0.3 × R2B / (R2A + R2B) ≈0.15.

  (7) When the transfer signal CK2C is set to “L” in this state (FIG. 7 (g)), the transfer thyristor switch S2 is turned on.

  (8) When the transfer signals CK1C and CK1R are both set to “H” (FIG. 7 (h)), the transfer thyristor switch S1 is turned off and discharged through the resistor R1, whereby the gate G1 potential gradually decreases. . At that time, the gate G2 of the transfer thyristor switch S2 becomes 3.3V and is completely turned on. Accordingly, by turning the lighting signal ID terminal corresponding to the image data “L” / “H”, the light emitting thyristor L2 can be turned on / off. In this case, since the potential of the gate G1 is already lower than the potential of the gate G2, the light emitting thyristor L1 is not turned on.

  Thus, according to the present embodiment, by alternately driving the transfer signals CK1 and CK2, the ON state of the transfer thyristor switches of the transfer thyristors S1, S2, S3, S4. Therefore, lighting / non-lighting of the light emitting thyristors L1, L2, L3, L4,.

<Description of protection element>
Next, the protection element 113 will be described in more detail.
FIG. 9 is a diagram illustrating a first form of the protection element 113.
FIG. 9 is a cross-sectional view of the light-emitting chip C on which the protection element 113 is arranged, and shows a cross-section along the signal line 101 that transmits the lighting signal φI. As shown in FIG. 9, in the light emitting chip C, a bonding pad 82 for inputting a lighting signal φI, a protective element 113, and light emitting thyristors L1 to L60 are sequentially formed on a substrate 80. Further, the signal line 101 extends on the bonding pad 82, the protection element 113, and the light emitting thyristors L1 to L60 via the insulating layer 114. The signal line 101 is connected to the bonding pad 82, the protective element 113, and the light emitting thyristors L1 to L60 via the cathode terminal 115.

  In the present embodiment, the protection element 113 is formed in the light emitting chip C using the structure of the light emitting thyristors L1 to L60. That is, each of the light emitting thyristors L1 to L60 has either a pnpn-type four-layer structure or an npnp-type four-layer structure from the substrate 80 side. The protective element 113 can be formed using this four-layer structure as it is. Accordingly, since the protection element 113 can be manufactured together with the light emitting thyristors L1 to L60, the protection element 113 can be manufactured as a dummy of the light emitting thyristors L1 to L60, for example, without providing a separate process. In the present embodiment, the case where the light-emitting thyristors L1 to L60 and the protection element 113 have a pnpn type four-layer structure will be described.

  When a disturbance such as noise or surge is input through the bonding pad 82, the disturbance is transmitted through the signal line 101. However, since the protective element 113 is provided between the bonding pad 82 and the light emitting thyristor L1, this disturbance reaches the protective element 113 earlier than the light emitting thyristor L1. At this time, when the disturbance voltage is larger than a predetermined value (for example, 20 V to 30 V), the protection element 113 is turned on, and the disturbance can be released to the substrate 80 side. That is, since the reverse bias state region generated between the pn junctions of each layer of the thyristor exists in the protective element 113, the protective element 113 is not turned on by the voltage of the lighting signal φI flowing through the normal signal line 101. However, when a voltage larger than a predetermined value is applied to the protective element 113, the protective element 113 is turned on, and the current is released to the substrate 80 side. Therefore, the inside of the light emitting chip C can be protected. Even when the disturbance is equal to or lower than a predetermined voltage (for example, 2 V to 3 V), since the region of the reverse bias exists in the protection element 113, the disturbance is mitigated. That is, in this case, the protection element 113 exhibits a function as a capacitive protection element, and therefore, the inside of the light emitting chip C is hardly damaged.

  Even when the protective element 113 is actually turned on and a disturbance is released to the substrate 80 side, the protective function of the protective element 113 is rarely lost. That is, in this case, gold (Au) or the like that constitutes the cathode terminal 115 and aluminum (Al) or the like that constitutes the signal line 101 forms an alloy and causes deterioration, but the protection function of the protection element 113 is It can often be used again.

  In the above-described example, the protection element 113 uses the four-layer structure of the thyristor as it is, but is not limited to this, and it is sufficient that the protection element 113 is formed using at least three layers on the substrate 80 side.

FIG. 10 is a diagram illustrating a second form of the protection element 113.
FIG. 10 is a cross-sectional view of the light emitting chip C on which the protection element 113 is arranged. The light emitting chip C shown in FIG. 10 is different from the light emitting chip C shown in FIG. 9 in that the protective element 113 has a three-layer structure. That is, the protection element 113 is formed using three layers of the thyristor on the substrate 80 side.
Even in such a form of the protection element 113, a region in the reverse bias state exists between the pn junctions of each layer of the pnp, so that the function as the protection element can be provided. The protective element 113 shown in FIG. 10 has a three-layer structure, so that there are fewer steps with the substrate 80. Therefore, there are fewer steps when forming the signal line 101 than when the signal line 101 is formed as shown in FIG. Therefore, there is an advantage that disconnection of the signal line 101 is difficult to occur.

FIG. 11 is a diagram illustrating a third form of the protection element 113.
FIG. 11 is a cross-sectional view of the light-emitting chip C on which the protection element 113 is arranged. In the light emitting chip C illustrated in FIG. 11, a protection element 113 is provided in the middle of the signal line 101 with respect to the light emitting chip C illustrated in FIG. 9. Therefore, the signal line 101 is not continuously formed on the protection element 113 but connected to both ends of the protection element 113. By adopting such a form, the protection element 113 can be further provided with a function as a current limiting resistor. That is, the protective element 113 has a thyristor four-layer structure, but the cathode layer, which is the uppermost layer in FIG. 11, has a lower sheet resistance than other layers, and can be used as a resistance. When the protective element 113 is formed, the protective element 113 can have a predetermined resistance value by adjusting the area occupied on the substrate 80. Therefore, the protection element 113 also has a function of a resistor RID (see FIG. 6) that is a current limiting resistor. Note that when the protective element 113 is further provided with a function as a current limiting resistor as in the case of the present embodiment, the resistor RID may not be provided.

In the above-described example, the protection element 113 is connected to the signal line 101. However, the protection element 113 is not limited to this and may be connected to the signal lines 102, 103, and 104.
However, it is more preferable that the protection element 113 is connected to the signal line 101 that transmits the lighting signal φI and the signal line 104 that transmits the transfer signal CKS, and it is particularly preferable to connect the protection element 113 to the signal line 101 that transmits the lighting signal φI. preferable.

  That is, as shown in FIG. 6, the signal line 102 that transmits the transfer signal CK1 and the signal line 103 that transmits the transfer signal CK2 are provided with resistors R1A and R2A as current limiting resistors inside the light emitting chip C, respectively. In this case, the disturbance can be mitigated by the resistors R1A and R2A. Therefore, the possibility that the inside of the light emitting chip C is damaged is relatively low. On the other hand, the signal line 101 and the signal line 104 are provided with a resistor RS and a resistor RID that can function as a current limiting resistor outside the light emitting chip C, not inside the light emitting chip C. Therefore, when a disturbance is mixed in after the resistor RS and the resistor RID, there is no means for protecting the inside of the light-emitting chip C unless the protection element 113 is provided.

  Further, the signal line 101 is designed to have a relatively low impedance because it needs to pass a larger current than the other signal lines in order to transmit the lighting signal φI. Therefore, the light emitting thyristors L1, L2, L3,. Therefore, it is particularly effective to provide the protection element 113 of this embodiment in the signal line 101.

Note that the current limiting resistor also has a function of mitigating disturbance as described above, and performs a function similar to the function of the protection element 113 of the present embodiment. However, when the protection element is configured with a current limiting resistor, the light emitting chip may not function due to disconnection when subjected to a disturbance. On the other hand, in the protection element 113 of the present embodiment, even if the protection function against the disturbance is lost as a result of the disturbance, no disconnection occurs, and the light-emitting chip C functions as it is.
Further, when a current limiting resistor is manufactured at the subsequent stage of the bonding pad 82, that is, when a current limiting resistor is manufactured by connecting to the wiring portion, in order to give a predetermined resistance value (for example, 50Ω to 100Ω) The area occupied by the current limiting resistor in the light emitting chip tends to increase. For this reason, the overall size of the light emitting chip tends to be large. On the other hand, in the protective element 113 of the present embodiment, the area occupied by the protective element 113 in the light emitting chip C is generally sufficient to be the same size as the light emitting thyristors L1 and L2. Therefore, the size of the entire light emitting chip is not easily increased.

  In the present embodiment, the bonding pad 82 can be manufactured using a pnpn-type four-layer structure that constitutes the light-emitting thyristors L1 to L60. However, it may be difficult to use the bonding pad 82 as a protective element. That is, the bonding pad 82 needs to have a large area because it is necessary to connect wiring from the outside of the light emitting chip C. Therefore, depending on the area of the bonding pad 82, the capacitance value becomes too large, and even when disturbances such as noise and surge are mixed, it may be difficult to turn on. Further, when a plurality of bonding pads 82 are formed by using one pnpn type four-layer structure, there is a concern about a secondary failure such as a disturbance being transmitted between the bonding pads 82. In such a case, it is difficult to provide the bonding pad 82 with a function as a protective element.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 12 ... Photosensitive drum, 14 ... Light emitting element head, 23 ... Transfer roll, 24 ... Fixing device, 64 ... Rod lens array, 81 ... Light emitting element, 82 ... Bonding pad, 100 ... Signal generating circuit, 113 ... Protection element, φI1 to φI60 ... Lighting signal, C1 to C60 ... Light emitting chip, S1, S2, S3, ..., S60 ... Transfer thyristor, L1, L2, L3, ..., L60 ... Light emitting thyristor

Claims (4)

A light emitting element array having a plurality of light emitting elements arranged in a row in the main scanning direction;
An electrode part for inputting and outputting a signal for driving the light emitting element array;
A wiring portion connecting the light emitting element array and the electrode portion;
A protective element formed between the light emitting element array and the electrode part and connected to the wiring part to protect the wiring part and the light emitting element array from disturbances input to the wiring part;
Equipped with a,
The light emitting device is formed of four layers having a pnpn structure formed on a substrate,
The protection element is formed of three layers on the substrate side of the pnpn structure,
The light emitting element array chip , wherein the wiring portion is electrically connected to a third layer from the substrate side, which is the uppermost layer of the protection element, at one point . The light emitting element array chip according to claim 1 , wherein the protection element is connected to a wiring portion that transmits a lighting signal for lighting the light emitting element. A light emitting element array having a plurality of light emitting elements arranged in a row in the main scanning direction, an electrode part for inputting / outputting a signal for driving the light emitting element array, and the light emitting element array and the electrode part are connected to each other And a protection for protecting the wiring part and the light emitting element array from disturbances input to the wiring part and formed between the light emitting element array and the electrode part and connected to the wiring part. A light emitting element array chip comprising:
An optical element for imaging the light output of the light emitting element array to expose the photoconductor to form an electrostatic latent image;
Equipped with a,
The light emitting device is formed of four layers having a pnpn structure formed on a substrate,
The protection element is formed of three layers on the substrate side of the pnpn structure,
The light emitting element head , wherein the wiring portion is electrically connected to a third layer from the substrate side, which is the uppermost layer of the protection element, at one point . Toner image forming means for forming a toner image;
Transfer means for transferring the toner image to a recording medium;
Fixing means for fixing the toner image to a recording medium,
The toner image forming unit includes:
A light emitting element array having a plurality of light emitting elements arranged in a row in the main scanning direction, an electrode part for inputting / outputting a signal for driving the light emitting element array, and the light emitting element array and the electrode part are connected to each other And a protection for protecting the wiring part and the light emitting element array from disturbances input to the wiring part and formed between the light emitting element array and the electrode part and connected to the wiring part. An optical element for forming an electrostatic latent image by exposing a photosensitive member by imaging a light output of the light emitting element array;
A light-emitting element head having,
The light emitting device is formed of four layers having a pnpn structure formed on a substrate,
The protection element is formed of three layers on the substrate side of the pnpn structure,
The image forming apparatus , wherein the wiring portion is electrically connected to a third layer from the substrate side, which is the uppermost layer of the protection element, at one point .

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