JP2013042010A - Light-emitting component, print head, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light-emitting component and the like that include a light-emitting element array having a plurality of light-emitting elements arranged in rows, and efficiently extract light by providing lenses on light-emitting surfaces of the respective light-emitting elements.SOLUTION: A light-emitting thyristor L1 is provided on a first island 301. The light-emitting thyristor L1 includes on a light-emitting surface 311 thereof an opening 92a that opens in a direction intersecting with the light-emitting surface 311, and a lens 92 that is connected with an edge on the farther side from the light-emitting surface 311 of the opening 92a and includes a curved-surface part 92b having a surface (curved surface 92c) that has a convex shape in a direction getting away from the light-emitting surface 311 as getting away from the opening 92a in a direction along the light-emitting surface 311 and approaching to the light-emitting surface 311.

Description

  The present invention relates to a light emitting component, a print head, and an image forming apparatus.

  In the light emitting component, a lens (microlens or microbead) is provided so as to correspond to the light emitting surface in order to condense the light emitted from the light emitting surface of the light emitting element in a predetermined direction and efficiently extract the light. Things have been done.

Patent Document 1 discloses a light extraction lens having a circular bottom surface, side surface, and top surface, and a surface light source having a finite size at the center of the bottom surface, the center of the bottom surface being the origin. Assuming cylindrical coordinates (r, φ, z) with the normal passing through the center of the bottom surface as the z-axis, the top surface is the side surface and the top surface of the semi-solid solid angle radiation emitted from the surface light source. A light extraction lens composed of an aspherical surface that is rotationally symmetric with respect to the z-axis is described for totally reflecting a part of a radiation component having a polar angle smaller than the polar angle Θ _{0 at} the intersection of the two.

JP 2007-102139 A

  An object of the present invention is to provide a light-emitting component or the like that can efficiently extract light from each light-emitting element of a light-emitting element array in which a plurality of light-emitting elements are arranged in a row by using a lens effect.

The invention according to claim 1 is provided respectively facing a plurality of light emitting elements arranged in a row on a substrate and a light emitting surface that emits light of each light emitting element of the plurality of light emitting elements, An opening that opens in a cylindrical shape in a direction intersecting with the light emitting surface, and is disposed on the light emitting element around the opening, and approaches the light emitting surface as the distance from the opening in the direction along the light emitting surface increases. In addition, the light-emitting component includes a curved surface portion having a convex surface and a plurality of lenses that collect light emitted from the light-emitting element.
According to a second aspect of the present invention, the light emitting surface of each light emitting element of the plurality of light emitting elements has a convex surface without a lens corresponding to the light emitting element in the plurality of lenses. The light-emitting component according to claim 1, wherein the light-emitting component is provided on a principal point side of the lens with respect to a focus position when the shape extends to the opening.
According to a third aspect of the present invention, the opening of each lens of the plurality of lenses is opposed to a portion of the light emitting element corresponding to the lens where the emission intensity of the light emitting surface is high. The light-emitting component according to claim 1, wherein the light-emitting component is provided on the light-emitting component.
According to a fourth aspect of the present invention, a pedestal that transmits light emitted from the light emitting element is provided between each of the plurality of lenses and a light emitting element corresponding to the lens in the plurality of light emitting elements. It is provided, It is a light emitting component of any one of Claim 1 thru | or 3.
According to a fifth aspect of the present invention, in the light-emitting component according to any one of the first to fourth aspects, the plurality of light-emitting elements are a plurality of light-emitting thyristors provided in a self-scanning light-emitting element array. It is.
According to a sixth aspect of the present invention, a plurality of light emitting elements arranged in a row on a substrate and a light emitting surface that emits light of each light emitting element of the plurality of light emitting elements are provided to face each other, An opening that opens in a cylindrical shape in a direction intersecting with the light emitting surface, and is disposed on the light emitting element around the opening, and approaches the light emitting surface as the distance from the opening in the direction along the light emitting surface increases. And a curved surface portion having a convex surface, and a light emitting means comprising a plurality of lenses for condensing light emitted from the light emitting element, and images light emitted from the light emitting means A print head provided with optical means.
According to a seventh aspect of the present invention, there is provided an image holding member, a charging unit for charging the image holding member, a plurality of light emitting elements arranged in a row on a substrate, and each of the light emitting elements. An opening that is provided opposite to the light emitting surface that emits the light, and is opened in a cylindrical shape in a direction intersecting the light emitting surface, and is disposed on the light emitting element around the opening, and the opening And a curved surface portion having a convex surface as the distance from the light emitting surface increases in the direction along the light emitting surface, and a plurality of lenses that collect the light emitted from the light emitting element. An exposure unit that exposes the image carrier through an optical unit; a development unit that develops an electrostatic latent image that is exposed by the exposure unit and formed on the image carrier; and the image carrier that is developed. Transfer means for transferring an image to a transfer medium An image forming apparatus having a.

According to the first aspect of the present invention, light can be extracted more efficiently than when a lens having no opening is used.
According to invention of Claim 2, light can be condensed more compared with the case where a light emission surface is provided outside the position of a focus.
According to the invention of claim 3, it is possible to extract light more efficiently than in the case where this configuration is not provided.
According to the invention of claim 4, it is possible to form the lens more easily than in the case where the present configuration is not provided.
According to the fifth aspect of the present invention, the light emitting component can be further downsized as compared with the case where this configuration is not provided.
According to the sixth aspect of the present invention, the light utilization efficiency of the print head is further improved as compared with the case where this configuration is not provided.
According to the seventh aspect of the present invention, power consumption in image formation can be further reduced as compared with the case where this configuration is not provided.

1 is a diagram illustrating an example of an overall configuration of an image forming apparatus to which a first exemplary embodiment is applied. It is sectional drawing which showed the structure of the print head. It is a top view of a light-emitting device. It is the figure which showed the structure of the light emitting chip | tip, the structure of the signal generation circuit of a light-emitting device, and the structure of the wiring (line) on a circuit board. It is an equivalent circuit diagram for demonstrating the circuit structure of the light emitting chip in which the self-scanning light emitting element array (SLED) is mounted. It is the plane layout figure and sectional drawing of the light emitting chip to which 1st Embodiment is applied. It is sectional drawing explaining the method of manufacturing the light emitting chip of 1st Embodiment. 6 is a timing chart for explaining operations of the light emitting device and the light emitting chip. It is a schematic diagram which shows the relationship between the light emission surface of a light emission thyristor, and the lens which does not have an opening part in the cross section containing an optical axis. It is a schematic diagram which shows the relationship between the light emission surface of a light emission thyristor, and the lens which has an opening part in the cross section containing an optical axis. It is the figure which showed the shape of the lens used for simulation. It is an example of the plane layout figure and sectional drawing of the light emitting thyristor part in the light emitting chip when not making the center of the opening part of a lens and the center of a light emitting surface correspond. It is an example of the plane layout figure and sectional drawing of the light emitting thyristor part in the light emitting chip in case the opening part of a lens is not circular. It is an example of the planar layout figure and sectional drawing of the light emitting thyristor part in the light emitting chip in 2nd Embodiment. It is sectional drawing explaining the method to manufacture the light emitting chip of 2nd Embodiment.

In an image forming apparatus such as a printer, copier, or facsimile that employs an electrophotographic system, an electrostatic latent image is obtained by irradiating image information onto a charged photosensitive member by an optical recording means, and then the static image is obtained. An image is formed by adding toner to the electrostatic latent image to make it visible, and transferring and fixing it on a recording sheet. In addition to the optical scanning method in which a laser is used as the optical recording means and the exposure is performed by scanning the laser beam in the main scanning direction, in recent years, a light emitting diode (LED: Light) as a light emitting element in response to a request for downsizing of the apparatus. A recording apparatus using an LED print head (LPH: LED Print Head) in which a plurality of emitting diodes (LEDs) are arranged in the main scanning direction to form a light emitting element array is employed.
A light-emitting thyristor is used as a light-emitting element in a light-emitting chip on which a plurality of light-emitting elements are provided in a row on a substrate and a self-scanning light-emitting element array (SLED) that is sequentially controlled to be lit is mounted. A light-emitting thyristor has a pnpn four-layer structure unlike a light-emitting diode, and mainly emits light in two layers inside the four-layer structure. Therefore, the amount of light that can be extracted outside a simple two-layer general light-emitting diode (light amount) ) Is small. Therefore, in the light emitting thyristor, in order to increase the amount of light emitted from each light emitting element, it is more demanded to take a wide light emitting surface for emitting light from the light emitting element and to efficiently extract light from the light emitting element. .
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

[First Embodiment]
(Image forming apparatus 1)
FIG. 1 is a diagram illustrating an example of the overall configuration of an image forming apparatus 1 to which the first exemplary embodiment is applied. An image forming apparatus 1 shown in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process unit 10 that forms an image corresponding to image data of each color, an image output control unit 30 that controls the image forming process unit 10, such as a personal computer (PC) 2 or an image reading device. 3 and an image processing unit 40 that performs predetermined image processing on image data received from these.

The image forming process unit 10 includes an image forming unit 11 including a plurality of engines arranged in parallel at predetermined intervals. The image forming unit 11 includes four image forming units 11Y, 11M, 11C, and 11K. The image forming units 11Y, 11M, 11C, and 11K have predetermined surfaces of the photosensitive drum 12 and the photosensitive drum 12 as an example of an image holding body that forms an electrostatic latent image and holds a toner image, respectively. An example of a charging unit 13 as an example of a charging unit that charges at a potential, a print head 14 that exposes a photosensitive drum 12 charged by the charging unit 13, and an example of a developing unit that develops an electrostatic latent image obtained by the print head 14 The developing device 15 is provided. The image forming units 11Y, 11M, 11C, and 11K respectively form yellow (Y), magenta (M), cyan (C), and black (K) toner images.
Further, the image forming process unit 10 performs multiple transfer of the toner images of each color formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K onto a recording sheet 25 as an example of a transfer target. In addition, the sheet conveying belt 21 that conveys the recording sheet 25, the driving roll 22 that is a roll for driving the sheet conveying belt 21, and a transfer unit that transfers the toner image on the photosensitive drum 12 to the recording sheet 25 are exemplified. A transfer roll 23 and a fixing device 24 for fixing the toner image on the recording paper 25 are provided.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the image output control unit 30. The image data received from the personal computer (PC) 2 or the image reading device 3 under the control of the image output control unit 30 is subjected to image processing by the image processing unit 40 and supplied to the image forming unit 11. The For example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged in a predetermined potential by the charger 13 while rotating in the direction of arrow A, and the image supplied from the image processing unit 40 is supplied. Exposure is performed by the print head 14 that emits light based on the data. As a result, an electrostatic latent image related to a black (K) color image is formed on the photosensitive drum 12. The electrostatic latent image formed on the photosensitive drum 12 is developed by the developing device 15, and a black (K) toner image is formed on the photosensitive drum 12. In the image forming units 11Y, 11M, and 11C, yellow (Y), magenta (M), and cyan (C) color toner images are formed, respectively.

Each color toner image on the photosensitive drum 12 formed by each image forming unit 11 is applied to the transfer roll 23 on the recording paper 25 supplied with the movement of the paper conveying belt 21 moving in the direction of arrow B. Electrostatic transfer is sequentially performed by the transfer electric field, and a composite toner image in which toner of each color is superimposed on the recording paper 25 is formed.
Thereafter, the recording paper 25 on which the composite toner image has been electrostatically transferred is conveyed to the fixing device 24. The synthesized toner image on the recording paper 25 conveyed to the fixing device 24 is fixed on the recording paper 25 by the fixing processing by heat and pressure by the fixing device 24, and is discharged from the image forming apparatus 1.

(Print head 14)
FIG. 2 is a cross-sectional view showing the configuration of the print head 14. The print head 14 as an example of an exposure unit includes a light source unit 63 that includes a housing 61 and a plurality of light emitting elements that expose the photosensitive drum 12 (in this embodiment, a light emitting thyristor as an example of the light emitting element). A light emitting device 65 as an example of a means and a rod lens array 64 as an example of an optical means for imaging light emitted from the light source unit 63 on the surface of the photosensitive drum 12 are provided.
The light emitting device 65 includes a circuit board 62 on which the above-described light source unit 63, a signal generation circuit 110 (see FIG. 3 described later) for driving the light source unit 63, and the like are mounted.

  The housing 61 is made of, for example, metal, supports the circuit board 62 and the rod lens array 64, and is set so that the light emitting surface of the light emitting element of the light source unit 63 becomes the focal plane of the rod lens array 64. Further, the rod lens array 64 is arranged along the axial direction of the photosensitive drum 12 (the main scanning direction and the X direction in FIGS. 3 and 4B described later).

(Light emitting device 65)
FIG. 3 is a top view of the light emitting device 65.
In the light emitting device 65 shown as an example in FIG. 3, the light source unit 63 includes light emitting chips C <b> 1 to C <b> 40 as examples of 40 light emitting components on a circuit board 62 in a staggered manner in two rows in the X direction that is the main scanning direction. Arranged in a shape.
In the present specification, “to” indicates a plurality of constituent elements each distinguished by a number, and includes those described before and after “to” and those between them. For example, the light emitting chips C1 to C40 include the light emitting chip C1 to the light emitting chip C40 in numerical order.

The configurations of the light emitting chips C1 to C40 may be the same. Therefore, when the light emitting chips C1 to C40 are not distinguished from each other, they are referred to as light emitting chips C.
In the present embodiment, a total of 40 light emitting chips C are used, but the present invention is not limited to this.
The light emitting device 65 includes a signal generation circuit 110 that drives the light source unit 63. The signal generation circuit 110 is configured by, for example, an integrated circuit (IC). Note that the light emitting device 65 does not have to include the signal generation circuit 110. At this time, the signal generation circuit 110 is provided outside the light emitting device 65 and supplies a control signal for controlling the light emitting chips C1 to C40 through a cable or the like. Here, it is assumed that the light emitting device 65 includes the signal generation circuit 110.
Details of the arrangement of the light emitting chips C1 to C40 will be described later.

  FIG. 4 is a diagram showing the configuration of the light emitting chip C, the configuration of the signal generation circuit 110 of the light emitting device 65, and the configuration of wiring (lines) on the circuit board 62. 4A shows the configuration of the light-emitting chip C, and FIG. 4B shows the configuration of the signal generation circuit 110 of the light-emitting device 65 and the configuration of wiring (lines) on the circuit board 62.

First, the configuration of the light-emitting chip C shown in FIG.
The light-emitting chip C includes a plurality of light-emitting elements (in the present embodiment, light-emitting thyristors L1 and L2) arranged in a row along the long side on the side close to one side of the long side on the surface of the substrate 80 having a rectangular surface shape. L2 and L3,...)) Are provided. Further, the light emitting chip C has terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) which are a plurality of bonding pads for taking in various control signals and the like at both ends in the long side direction of the surface of the substrate 80. I have. These terminals are provided in the order of the φ1 terminal and the Vga terminal from one end of the substrate 80, and are provided in the order of the φI terminal and the φ2 terminal from the other end of the substrate 80. The light emitting unit 102 is provided between the Vga terminal and the φ2 terminal. Further, a back electrode 85 (see FIG. 6 described later) is provided on the back surface of the substrate 80 as a Vsub terminal.

  Note that the “column shape” is not limited to the case where a plurality of light emitting elements are arranged in a straight line as illustrated in FIG. 4A, and the light emitting elements of the plurality of light emitting elements are arranged in the column direction. It may be in a state where they are arranged with different amounts of displacement with respect to the orthogonal direction. For example, when the light emitting surface 311 (see FIG. 6 described later) of the light emitting element is a pixel, each light emitting element is arranged with a shift amount of several pixels or several tens of pixels in a direction orthogonal to the column direction. Also good. Moreover, you may arrange | position zigzag alternately between adjacent light emitting elements or for every several light emitting element.

Next, the configuration of the signal generation circuit 110 of the light emitting device 65 and the configuration of the wiring (line) on the circuit board 62 will be described with reference to FIG.
As described above, the signal generating circuit 110 and the light emitting chips C1 to C40 are mounted on the circuit board 62 of the light emitting device 65, and wirings (lines) for connecting the signal generating circuit 110 and the light emitting chips C1 to C40 are provided. ing.

First, the configuration of the signal generation circuit 110 will be described.
Image signal processed image data and various control signals are input to the signal generation circuit 110 from the image output control unit 30 and the image processing unit 40 (see FIG. 1). Based on these image data and various control signals, the signal generation circuit 110 rearranges the image data and corrects the amount of light.
The signal generation circuit 110 includes a transfer signal generation unit 120 that transmits the first transfer signal φ1 and the second transfer signal φ2 to the light emitting chips C1 to C40 based on various control signals.
In addition, the signal generation circuit 110 includes a lighting signal generation unit 140 that transmits the lighting signals φI1 to φI40 to the light emitting chips C1 to C40 based on various control signals. When the lighting signals φI1 to φI40 are not distinguished from each other, they are expressed as a lighting signal φI.
Furthermore, the signal generation circuit 110 supplies a reference potential supply unit 160 that supplies a reference potential Vsub that serves as a potential reference to the light emitting chips C1 to C40, and a power supply potential that supplies a power supply potential Vga for driving the light emitting chips C1 to C40. A supply unit 170 is provided.

Next, the arrangement of the light emitting chips C1 to C40 will be described.
The odd-numbered light emitting chips C1, C3, C5,... Are arranged in a line at intervals in the long side direction of each substrate 80. The even-numbered light emitting chips C2, C4, C6,... Are similarly arranged in a row at intervals in the direction of the long side of each substrate 80. The odd numbered light emitting chips C1, C3, C5,... And the even numbered light emitting chips C2, C4, C6,... Are arranged so that the long sides on the light emitting unit 102 side provided in the light emitting chip C face each other. They are arranged in a zigzag pattern in a state rotated by 180 °. The positions of the light emitting chips C are also set so that the light emitting elements are arranged at predetermined intervals in the main scanning direction (X direction). In FIG. 4B, the light emitting chips C1, C2, C3,... Are arranged with the light emitting elements of the light emitting unit 102 shown in FIG. 4A (in this embodiment, the light emitting thyristors L1, L2, L3,... (In order of numbers) are indicated by arrows.

A wiring (line) connecting the signal generation circuit 110 and the light emitting chips C1 to C40 will be described.
The circuit board 62 is connected to a Vsub terminal provided on a back electrode 85 (see FIG. 6 described later) which is a Vsub terminal provided on the back surface of the substrate 80 of the light emitting chip C, and supplies a reference potential Vsub. Is provided.
The circuit board 62 is provided with a power supply line 200b that is connected to a Vga terminal provided on the light emitting chip C and supplies a power supply potential Vga for driving.

  The circuit board 62 includes a first transfer signal line 201 for transmitting the first transfer signal φ1 from the transfer signal generator 120 of the signal generation circuit 110 to the φ1 terminals of the light emitting chips C1 to C40, and the light emitting chips C1 to C40. A second transfer signal line 202 for transmitting the second transfer signal φ2 to the φ2 terminal is provided. The first transfer signal φ1 and the second transfer signal φ2 are transmitted in common (in parallel) to the light emitting chips C1 to C40.

  Further, the lighting signals φI1 to φI40 are transmitted to the circuit board 62 from the lighting signal generation unit 140 of the signal generation circuit 110 to the respective φI terminals of the respective light emitting chips C1 to C40 via the current limiting resistors RI. Lighting signal lines 204-1 to 204-40 are provided.

As described above, the reference potential Vsub and the power supply potential Vga are commonly supplied to all the light emitting chips C1 to C40 on the circuit board 62. The first transfer signal φ1 and the second transfer signal φ2 are also transmitted in common (in parallel) to the light emitting chips C1 to C40. On the other hand, the lighting signals φI1 to φI40 are individually transmitted to the light emitting chips C1 to C40, respectively.
If the light emitting device 65 does not include the signal generation circuit 110, the light emitting device 65 includes power supply lines 200a and 200b, a first transfer signal line 201, a second transfer signal line 202, and a lighting signal line 204-1. ˜204-40 are connected to a connector or the like instead of the signal generation circuit 110. And it connects to the signal generation circuit 110 provided outside by the cable connected to a connector etc.

(Light emitting chip C)
FIG. 5 is an equivalent circuit diagram for explaining a circuit configuration of the light-emitting chip C on which the self-scanning light-emitting element array (SLED) is mounted. Each element described below is arranged based on a layout (see FIG. 6 described later) on the light emitting chip C except for terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal). Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for convenience of explanation. The Vsub terminal provided on the back surface of the substrate 80 is drawn out of the substrate 80.
Here, the light emitting chip C will be described taking the light emitting chip C1 as an example in relation to the signal generation circuit 110. Therefore, in FIG. 5, the light-emitting chip C is referred to as a light-emitting chip C <b> 1 (C). The configuration of the other light emitting chips C2 to C40 is the same as that of the light emitting chip C1.

The light-emitting chip C1 (C) is a light-emitting thyristor array (light-emitting portion 102 (see FIG. 4A)) composed of the light-emitting thyristors L1, L2, L3,. ).
The light emitting chip C1 (C) includes a transfer thyristor array composed of transfer thyristors T1, T2, T3,... Arranged in a row like the light emitting thyristor array.

Further, the light emitting chip C1 (C) includes two pairs of transfer thyristors T1, T2, T3,... In the order of numbers and coupling diodes Dx1, Dx2, Dx3,.
Further, the light emitting chip C1 (C) includes power line resistances Rgx1, Rgx2, Rgx3,.

  The light emitting chip C1 (C) includes one start diode Dx0. In order to prevent an excessive current from flowing through a first transfer signal line 72 to which a first transfer signal φ1 to be described later is transmitted and a second transfer signal line 73 to which a second transfer signal φ2 is transmitted. Current limiting resistors R1 and R2.

The light emitting thyristors L1, L2, L3,... Of the light emitting thyristor array and the transfer thyristors T1, T2, T3,. Further, the coupling diodes Dx1, Dx2, Dx3,..., The power line resistances Rgx1, Rgx2, Rgx3,.
The light emitting thyristor array and the transfer thyristor array are arranged in the order of the transfer thyristor array and the light emitting thyristor array from the top in FIG.

  Here, the light emitting thyristors L1, L2, L3,..., The transfer thyristors T1, T2, T3,..., The coupling diodes Dx1, Dx2, Dx3,..., The power line resistances Rgx1, Rgx2, Rgx3,. The light-emitting thyristor L, the transfer thyristor T, the coupling diode Dx, and the power supply line resistance Rgx are represented.

The number of light emitting thyristors L in the light emitting thyristor array may be a predetermined number. In this embodiment, if the number of light emitting thyristors L is, for example, 128, the number of transfer thyristors T is also 128. Similarly, the number of power line resistances Rgx is 128. However, the number of coupling diodes Dx is 127, which is one less than the number of transfer thyristors T.
The number of transfer thyristors T may be larger than the number of light emitting thyristors L.

  The thyristor (light-emitting thyristor L, transfer thyristor T) is a semiconductor element having three terminals: a gate terminal, an anode terminal, and a cathode terminal.

Next, electrical connection of each element in the light emitting chip C1 (C) will be described.
The anode terminals of the transfer thyristor T and the light emitting thyristor L are connected to the substrate 80 of the light emitting chip C1 (C) (anode common).
These anode terminals are connected to a power supply line 200a (see FIG. 4B) via a back electrode 85 (see FIG. 6 described later) which is a Vsub terminal provided on the back surface of the substrate 80. The power supply line 200a is supplied with the reference potential Vsub from the reference potential supply unit 160.

Along with the arrangement of the transfer thyristors T, the cathode terminals of the odd-numbered (odd-numbered) transfer thyristors T1, T3,... Are connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via the current limiting resistor R1. The first transfer signal line 201 (see FIG. 4B) is connected to the φ1 terminal, and the first transfer signal φ1 is transmitted from the lighting signal generator 140.
On the other hand, the cathode terminals of the even-numbered (even-numbered) transfer thyristors T 2, T 4,... The second transfer signal line 73 is connected to the φ2 terminal via the current limiting resistor R2. The second transfer signal line 202 (see FIG. 4B) is connected to the φ2 terminal, and the second transfer signal φ2 is transmitted from the lighting signal generator 140.

  The cathode terminals of the light emitting thyristors L 1, L 2, L 3,... Are connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal. In the light emitting chip C1, the φI terminal is connected to the lighting signal line 204-1 via the current limiting resistor RI, and the lighting signal φI1 is transmitted from the lighting signal generator 140. The lighting signal φI1 supplies a current for lighting to the light emitting thyristors L1, L2, L3,. The lighting signal lines 204-2 to 204-40 are connected to the φI terminals of the other light emitting chips C2 to C40 via current limiting resistors RI, respectively, and the lighting signals φI2 to φI40 are transmitted from the lighting signal generator 140. Is done.

  The gate terminals Gt1, Gt2, Gt3,... Of the transfer thyristors T1, T2, T3,... Have a one-to-one correspondence with the gate terminals Gl1, Gl2, Gl3,. Connected with. Therefore, the gate terminals Gt1, Gt2, Gt3,... And the gate terminals Gl1, Gl2, Gl3,. Therefore, for example, the gate terminal Gt1 (gate terminal Gl1) is expressed and indicates that the potentials are the same.

  Here, the gate terminals Gt1, Gt2, Gt3,..., And the gate terminals Gl1, Gl2, Gl3,. It is expressed as a gate terminal Gt (gate terminal Gl) and indicates that the potential is the same.

  Coupling diodes Dx1, Dx2, Dx3,... Are connected between the gate terminals Gt, each of which is a pair of gate terminals Gt1, Gt2, Gt3,... Of transfer thyristors T1, T2, T3,. Yes. That is, the coupling diodes Dx1, Dx2, Dx3,... Are connected in series so as to be sandwiched between the gate terminals Gt1, Gt2, Gt3,. The direction of the coupling diode Dx1 is connected in a direction in which a current flows from the gate terminal Gt1 toward the gate terminal Gt2. The same applies to the other coupling diodes Dx2, Dx3, Dx4,.

  The gate terminal Gt (gate terminal Gl) of the transfer thyristor T is connected to the power supply line 71 via the power supply line resistance Rgx provided corresponding to each of the transfer thyristors T. The power supply line 71 is connected to the Vga terminal. A power supply line 200b (see FIG. 4B) is connected to the Vga terminal, and the power supply potential Vga is supplied from the power supply potential supply unit 170.

  The gate terminal Gt1 of the transfer thyristor T1 on one end side of the transfer thyristor array is connected to the cathode terminal of the start diode Dx0. On the other hand, the anode terminal of the start diode Dx 0 is connected to the second transfer signal line 73.

  In FIG. 5, a portion including the transfer thyristor T, the coupling diode Dx, the power supply line resistance Rgx, the start diode Dx0, and the current limiting resistors R1 and R2 of the light emitting chip C1 (C) is referred to as a transfer unit 101. A portion including the light emitting thyristor L corresponds to the light emitting unit 102.

FIG. 6 is an example of a plan layout view and a cross-sectional view of the light emitting chip C to which the first embodiment is applied. Here, since the connection relationship between the light-emitting chip C and the signal generation circuit 110 is not shown, it is not necessary to use the light-emitting chip C1 as an example. Therefore, it is expressed as a light emitting chip C.
FIG. 6A is a plan layout diagram of the light emitting chip C, and shows a portion centering on the light emitting thyristors L1 to L4 and the transfer thyristors T1 to T4. Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for convenience of explanation. The Vsub terminal provided on the back surface of the substrate 80 is drawn out of the substrate 80. If terminals are provided corresponding to FIG. 4A, the φ2 terminal, the φI terminal, and the current limiting resistor R2 are provided at the right end portion of the substrate 80 in FIG. 6A. The start diode Dx0 may be provided at the right end portion of the substrate 80.
FIG. 6B is a cross-sectional view taken along line VIB-VIB shown in FIG. Therefore, in the cross-sectional view of FIG. 6B, a cross section of the light emitting thyristor L1, the transfer thyristor T1, the coupling diode Dx1, and the power supply line resistance Rgx1 is shown from the bottom in the figure. In addition, in FIG. 6A and FIG. 6B, main elements and terminals are indicated by names.

As shown in FIG. 6B, the light-emitting chip C includes a p-type first semiconductor layer 81, an n-type second semiconductor layer 82, a p-type third semiconductor layer 83, and a p-type substrate 80. The n-type fourth semiconductor layer 84 is composed of a plurality of islands (islands) (a first island 301, a second island 302, a third island 303, etc., which will be described later) stacked in order. That is, as shown in FIG. 6B, at least the n-type second semiconductor layer 82, the p-type third semiconductor layer 83, and the n-type fourth semiconductor layer 84 are separated from each other in the plurality of islands. Has been. Note that the p-type first semiconductor layer 81 may or may not be separated. In FIG. 6B, the p-type first semiconductor layer 81 is partially separated in the thickness direction. The p-type first semiconductor layer 81 may also serve as the substrate 80.
Further, as will be described below, each of the plurality of islands partially includes an n-type fourth semiconductor layer 84 (for example, a first island 301 described later) or the n-type fourth semiconductor layer 84. (For example, a third island 303 described later).
As shown in FIG. 6B, the light emitting chip C is provided with an insulating layer 86 provided so as to cover the surface and side surfaces of these islands. These islands and wiring such as the power supply line 71, the first transfer signal line 72, the second transfer signal line 73, and the lighting signal line 75 are formed through holes (in FIG. 6A). It is connected via). In the following description, description of the insulating layer 86 and the opening is omitted.

As shown in FIG. 6A, the first island 301 is provided with a light emitting thyristor L1. 6B, a lens 92 is provided so as to face the light emitting surface 311 which is the surface of the n-type fourth semiconductor layer 84 of the light-emitting thyristor L1 (opposite side of the p-type substrate 80). It has been.
In the light emitting thyristor L, light is emitted mainly by the n-type second semiconductor layer 82 and the p-type third semiconductor layer 83. Here, in order to extract light from the n-type fourth semiconductor layer 84 serving as a cathode, the surface of the n-type fourth semiconductor layer 84 of the light-emitting thyristor L is referred to as a light-emitting surface 311.
Here, it is assumed that the planar shape of the light emitting surface 311 is a square, and the n-type ohmic electrode 321 is provided at the center of the light emitting surface 311.

The lens 92 includes a light emitting surface 311 of the light emitting thyristor L1, an insulating layer 86 that covers the n-type ohmic electrode 321, and a lighting signal line 75 (branch) connected to the n-type ohmic electrode 321 through a through hole provided in the insulating layer 86. Part 75b).
Then, as shown in FIG. 6B, the lens 92 is disposed on the light emitting thyristor L1 around the opening 92a and the opening 92a that is cylindrically opened in the direction intersecting the light emitting surface 311. A curved surface portion 92b having a convex surface (curved surface 92c) is provided while approaching the light emitting surface 311 as the distance from the portion 92a in the direction along the light emitting surface 311 is increased.
The curved surface portion 92b is continuous with the end of the opening 92a on the side far from the light emitting surface 311.
The lens 92 can also be considered as a configuration in which an opening 92a is provided in a cylindrical shape along the optical axis in a lens having an optical axis perpendicular to the light emitting surface 311 and a convex surface. That is, a portion obtained by removing the opening 92a from a lens having an optical axis perpendicular to the light emitting surface 311 and having a convex surface is the curved surface portion 92b.
In the following description, it is assumed that the curved surface portion 92b surrounds the opening 92a. However, the curved surface portion 92b does not need to completely surround the opening portion 92a, and may be opened at a part or a plurality of portions.

  The inner surface 92d of the opening 92a rises from the light emitting surface 311 and the end far from the light emitting surface 311 is connected to the curved surface 92c of the curved surface portion 92b. Note that the inner side surface 92d of the opening 92a is illustrated as being perpendicular to the light emitting surface 311 in FIG. 6B, but is not necessarily perpendicular and may be inclined with respect to the light emitting surface 311. Good. Furthermore, the opening 92a may not have the same cross-sectional shape on the side closer to the light emitting surface 311 and on the side farther from the light emitting surface 311, and either one may be larger than the other. Further, the shape of the cross section of the opening 92a may change between the side closer to the light emitting surface 311 and the side farther from the light emitting surface 311.

  As described above, the lens 92 includes the opening 92a and the curved surface 92b. The curved surface portion 92b is provided in contact with the light emitting thyristor L, and is surrounded by the curved surface 92c and the inner side surface 92d of the opening 92a.

The center of the opening 92 a is made to coincide with the center of the light emitting surface 311. Here, the center of the opening 92a means the center of gravity when it is assumed that the surface formed when the end of the opening 92a on the light emitting surface 311 side is projected onto the light emitting surface 311 is a plate having the same density. Similarly, the center of the light emitting surface 311 refers to the center of gravity when the light emitting surface 311 is assumed to be a plate having the same density.
A portion of the light emitting surface 311 facing the opening 92a is a central portion of the light emitting surface 311 and a portion of the light emitting surface 311 corresponding to the curved surface portion 92b is a peripheral portion of the light emitting surface 311.

The second island 302 is provided with a transfer thyristor T1 and a coupling diode Dx1. The third island 303 is provided with a power supply line resistance Rgx1. The fourth island 304 is provided with a start diode Dx0. The fifth island 305 is provided with a current limiting resistor R1, and the sixth island 306 is provided with a current limiting resistor R2.
In the light emitting chip C, a plurality of islands similar to the first island 301, the second island 302, and the third island 303 are formed in parallel. These islands include light emitting thyristors L2, L3, L4,..., Transfer thyristors T2, T3, T4,..., Coupling diodes Dx2, Dx3, Dx4,. It is provided in the same manner as the island 303. Further, a lens 92 is provided on each of the light emitting thyristors L2, L3,.
Further, as shown in FIG. 6B, a back surface electrode 85 serving as a Vsub terminal is provided on the back surface of the substrate 80.

  The plurality of lenses 92 provided in each of the light emitting thyristors L1, L2, L3,... Constitutes a lens row provided along the row direction of the light emitting thyristor row. That is, in the row direction of the lens row, the curved surface portions 92b of the lenses 92 of the plurality of lenses 92 are in contact with each other and integrated (see FIG. 7D described later). In other words, the curved surface 92c of the lens 92 can extend beyond the area of the light emitting surface 311, but the overlapping portion between the adjacent light emitting thyristors L is cut out, and the curved surface portions 92b are in contact with each other and integrated.

On the other hand, in the curved surface portion 92b of the lens 92, the curved surface 92c is cut off by an outer surface 92e perpendicular to the substrate 80 on both ends in the row direction of the lens row and on the side orthogonal to the row direction of the lens row. In other words, the curved surface 92c of the lens 92 can extend beyond the area of the light emitting surface 311. However, a portion protruding from the light emitting surface 311 is cut off on the side orthogonal to the column direction of the lens array. In addition, what is necessary is just to set the part to cut off by the improvement effect of the extraction efficiency of the light radiate | emitted from the light emitting thyristor L.
Here, it is assumed that a lens 92 is provided for each light-emitting thyristor L even if the lenses 92 are in contact with each other at the curved surface portion 92b between the adjacent light-emitting thyristors L.
The shape of the lens 92 will be described in detail later.

Here, with reference to FIGS. 6A and 6B, the first island 301 to the sixth island 306 will be described in detail.
The light-emitting thyristor L1 provided on the first island 301 includes the p-type first semiconductor layer 81 provided on the p-type substrate 80 as an anode terminal and the n-type provided on the n-type fourth semiconductor layer 84. The ohmic electrode 321 is a cathode terminal, and the p-type ohmic electrode 331 provided on the p-type third semiconductor layer 83 exposed by removing the n-type fourth semiconductor layer 84 is a gate terminal Gl1. The light is transmitted by the branch portion 75 b for connecting the n-type ohmic electrode 321 and the lighting signal line 75 to the n-type ohmic electrode 321 on the surface of the n-type fourth semiconductor layer 84 that is the light emitting surface 311. The light is transmitted through the insulating layer 86 from the portion excluding the portion where the emission is blocked (shielded). The emitted light is condensed by the lens 92 and extracted.
The portion of the light emitting surface 311 that emits light is a portion that surrounds the branch portion 75b of the lighting signal line 75 and the n-type ohmic electrode 321, and has a horseshoe shape.
The term of the light emitting surface 311 is used not only for the light emitting thyristor L1, but also for other light emitting thyristors L.

The transfer thyristor T1 provided on the second island 302 is provided on the region 313 of the n-type fourth semiconductor layer 84 with the p-type first semiconductor layer 81 provided on the p-type substrate 80 as an anode terminal. The n-type ohmic electrode 323 is a cathode terminal, and the p-type ohmic electrode 332 provided on the p-type third semiconductor layer 83 exposed by removing the n-type fourth semiconductor layer 84 is a gate terminal Gt1.
Similarly, the coupling diode Dx1 provided on the second island 302 has the n-type ohmic electrode 324 provided on the region 314 of the n-type fourth semiconductor layer 84 as the cathode terminal and the p-type third semiconductor layer 83. The provided p-type ohmic electrode 332 is used as an anode terminal. The anode terminal of the coupling diode Dx1 and the gate terminal Gt1 of the transfer thyristor T1 are common to the p-type ohmic electrode 332.

The power supply line resistance Rgx1 provided on the third island 303 includes the p-type ohmic electrode 333 provided on the p-type third semiconductor layer 83 exposed by removing the n-type fourth semiconductor layer 84 and the p-type. A p-type third semiconductor layer 83 between the ohmic electrodes 334 is provided as a resistor.
The start diode Dx0 provided on the fourth island 304 removes the n-type fourth semiconductor layer 84 from the n-type ohmic electrode 325 provided on the region 315 of the n-type fourth semiconductor layer 84 as a cathode terminal. A p-type ohmic electrode 335 provided on the exposed p-type third semiconductor layer 83 is used as an anode terminal.
The current limiting resistor R1 provided on the fifth island 305 and the current limiting resistor R2 provided on the sixth island 306 are each two p-types like the power supply line resistor Rgx1 provided on the third island 303. A p-type third semiconductor layer 83 between ohmic electrodes (not shown) is used as a resistor.

In FIG. 6A, the connection relationship between each element will be described.
The lighting signal line 75 includes a trunk portion 75a and a plurality of branch portions 75b, and the trunk portion 75a is provided so as to extend in the column direction of the light emitting thyristor row. The branch portion 75 b branches off from the trunk portion 75 a and is connected to an n-type ohmic electrode 321 that is a cathode terminal of the light emitting thyristor L 1 provided on the first island 301. Similarly, the cathode terminals of the other light emitting thyristors L are connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal.

The first transfer signal line 72 is connected to an n-type ohmic electrode 323 which is a cathode terminal of the transfer thyristor T1 provided on the second island 302. The cathode terminals of other odd-numbered transfer thyristors T provided on an island similar to the second island 302 are also connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via a current limiting resistor R1 provided on the fifth island 305.
On the other hand, the second transfer signal line 73 is connected to an n-type ohmic electrode (unsigned) that is a cathode terminal of an even-numbered transfer thyristor T provided on an island without a symbol. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2 provided on the sixth island 306.

  The power supply line 71 is connected to the p-type ohmic electrode 334 that is one terminal of the power supply line resistance Rgx1 provided on the third island 303. One terminal of the other power line resistor Rgx is also connected to the power line 71. The power supply line 71 is connected to the Vga terminal.

  The p-type ohmic electrode 331 (gate terminal Gl1) of the light-emitting thyristor L1 provided on the first island 301 is connected to the p-type ohmic electrode 332 (gate terminal Gt1) of the second island 302 by a connection wiring 76. .

The p-type ohmic electrode 332 (gate terminal Gt1) is connected to the p-type ohmic electrode 333 (the other terminal of the power supply line resistance Rgx1) provided on the third island 303 by a connection wiring 77.
The n-type ohmic electrode 324 (the cathode terminal of the coupling diode Dx1) provided on the second island 302 is connected to the p-type ohmic electrode (not indicated) that is the gate terminal Gt2 of the adjacent transfer thyristor T2. 79 is connected.
Although not described here, the same applies to other light-emitting thyristors L, transfer thyristors T, coupling diodes Dx, and the like.

The p-type ohmic electrode 332 (gate terminal Gt1) of the second island 302 is connected to the n-type ohmic electrode 325 (cathode terminal of the start diode Dx0) provided on the fourth island 304 by a connection wiring 78. The p-type ohmic electrode 335 (the anode terminal of the start diode Dx0) is connected to the second transfer signal line 73.
In this way, the light emitting chip C1 (C) shown in FIG. 5 is configured.

(Method for manufacturing light-emitting chip C)
A method for manufacturing the light-emitting chip C will be described.
First, a method for manufacturing the light-emitting chip C before the lens 92 is installed will be described.
The light-emitting chip C uses a compound semiconductor such as GaAs or GaAlAs, for example, on a p-type substrate 80, a p-type first semiconductor layer 81, an n-type second semiconductor layer 82, and a p-type third semiconductor layer 83. And the n-type fourth semiconductor layer 84 are sequentially stacked, and then the n-type fourth semiconductor layer 84, the p-type third semiconductor layer 83, the n-type second semiconductor layer 82, and the n-type second semiconductor layer 84. A plurality of islands (first island 301 to sixth island 306 and reference numerals) separated from each other by removing the p-type first semiconductor layer 81 having a predetermined depth from the interface with the semiconductor layer 82 by etching. An island not attached) is formed. Such an island is called mesa, and the etching for forming the island is called mesa etching.

In some islands, a part of the n-type fourth semiconductor layer 84 is removed in some islands, and in the other islands, the whole of the n-type fourth semiconductor layer 84 is removed. The third semiconductor layer 83 is exposed.
Then, n-type ohmic electrodes such as n-type ohmic electrodes 321, 323, 324, and 325 are formed on the surface of the n-type fourth semiconductor layer 84, and p is formed on the exposed surface of the p-type third semiconductor layer 83. P-type ohmic electrodes such as type ohmic electrodes 331, 332, 333, 334, and 335 are formed.
Then, an insulating layer 86 such as silicon dioxide (SiO ₂ ) is formed so as to cover the surface and side surfaces of the island. Next, after providing an opening in the insulating layer 86 on the n-type ohmic electrode and the p-type ohmic electrode, a metal film such as aluminum (Al) is deposited, and the power line 71 and the first transfer are performed by photolithography. The signal lines 72, the second transfer signal lines 73, the lighting signal lines 75 and the like are processed.
Thereby, the light emitting chip C before installing the lens 92 is manufactured.

Next, a method for forming the lens 92 of the light emitting chip C will be described.
The lens 92 can be formed by using, for example, a gray scale lithography method or an imprint method.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing the light-emitting chip C of the first embodiment. The cross section taken along line VII-VII in FIG. Here, the lens 92 is formed by a gray scale lithography method.
The gray scale lithography method is a lithography method performed using a photomask 95 having a transmitted light amount (exposure amount) distribution. The photomask 95 may have a fine dot pattern 96 that is not resolved at the exposure wavelength, for example, and may control the amount of transmitted light by the density distribution (density distribution) of the dot pattern 96. A portion with a low density of the dot pattern 96 has a large amount of transmitted light, and a portion with a high density of the dot pattern 96 has a small amount of transmitted light. Therefore, the distribution of the dot pattern 96 in the photomask 95 is set so that the photosensitive material 94 has the shape of the curved surface 92c of the curved surface portion 92b of the lens 92 depending on the difference in the amount of transmitted light.
The photosensitive material 94 includes a positive type in which a portion irradiated with light (exposure light) is decomposed and easily dissolved in a developer, and a portion irradiated with light (exposure light) is polymerized to be insoluble in the developer. There is a negative type.
Examples of such photosensitive material 94 include polyimide resin, phenol epoxy resin, acrylic resin, and cycloolefin resin.

Here, a case where a positive polyimide resin is used as the photosensitive material 94 will be described.
FIG. 7A shows the light emitting chip C before the lens 92 is formed.
As shown in FIG. 7B, a photosensitive material 94, which is a positive polyimide resin, is applied to the surface of the light emitting chip C before the lens 92 is formed.

Then, as shown in FIG. 7C, exposure light 97 that is sensitized by the photosensitive material 94 is irradiated through a photomask 95.
Here, the photomask 95 is provided on a substrate of synthetic quartz or the like having a high transmittance with respect to the exposure light 97, and a dot pattern 96 made of Cr or the like that blocks the exposure light 97 is provided so that the transmitted light amount is distributed. Yes. That is, at the portion corresponding to the curved surface portion 92b of the lens 92, the density of the dot pattern 96 decreases as the distance from the opening 92a corresponds to the curved surface 92c. In the portion corresponding to the opening 92a, the dot pattern 96 is not provided, and the exposure material 97 is irradiated with the photosensitive material 94. Further, the photosensitive material 94 is irradiated with the exposure light 97 without providing the dot pattern 96 even in a portion where the lens 92 other than the light emitting surface 311 is not provided.
The light amount (exposure amount) of the exposure light 97 is set so that the portions of the photosensitive material 94 where the opening 92a and the lens 92 are not provided are removed by development.

Thereafter, when immersed in a developing solution, as shown in FIG. 7D, the photosensitive material 94, which is a positive polyimide resin that has become soluble by irradiation with the exposure light 97, is dissolved and removed. At this time, the portion of the curved surface portion 92b corresponding to the curved surface 92c is far from the opening 92a and the exposure light 97 has a large amount of irradiation (exposure amount). Become more. On the other hand, the photosensitive material 94 is removed at the portion of the opening 92a and the portion where the lens 92 is not provided.
Then, by heating at a predetermined temperature, the solvent contained in the photosensitive material 94 is evaporated, and the polyimide precursor of the photosensitive material 94 is imidized to form a lens 92 made of polyimide resin. .
In this manner, the light emitting chip C including the lens 92 is manufactured.

  Although the transmitted light amount is controlled by the density distribution of the dot pattern 96 that blocks the exposure light 97 as the photomask 95, the transmitted light amount may be controlled by arranging dot patterns 96 having different sizes. Alternatively, the amount of transmitted light may be controlled by changing the film thickness using films having different light transmittances depending on the thickness.

Further, the lens 92 may be formed by using an imprint method instead of the gray scale lithography method.
The imprint method is a method of forming a lens 92 by producing a mold that is a female mold of the shape of the lens 92 and pressing the mold against a material that becomes the lens 92.
When a thermoplastic resin is used as the material for the lens 92, the thermoplastic resin is applied onto the light emitting chip C before the lens 92 is applied, and the mold is pressed while heating, so that the thermoplastic resin corresponds to the mold. The shape is deformed. Thereafter, the mold is removed after cooling to suppress the deformation of the thermoplastic resin. By doing in this way, the light emitting chip C provided with the lens 92 by a thermoplastic resin is manufactured (thermal imprint method).
In the case where a photocurable resin is used as the material for the lens 92, a mold is made of fused quartz or the like that transmits ultraviolet light or the like that cures the photocurable resin. Then, a light curable resin is applied on the light emitting chip C not provided with the lens 92, and light for curing the photo curable resin is irradiated through the mold in a state where the mold is pressed. After the photocurable resin is cured, the mold is removed. By doing in this way, the light emitting chip C provided with the lens 92 by a photocurable resin is manufactured (optical imprint method).

(Operation of the light emitting device 65)
Next, the operation of the light emitting device 65 will be described.
As described above, the light emitting device 65 includes the light emitting chips C1 to C40 (see FIGS. 3 and 4).
As shown in FIG. 4, the reference potential Vsub and the power supply potential Vga are commonly supplied to all the light emitting chips C <b> 1 to C <b> 40 on the circuit board 62. Similarly, the first transfer signal φ1 and the second transfer signal φ2 are transmitted in common (in parallel) to the light emitting chips C1 to C40.
On the other hand, the lighting signals φI1 to φI40 are individually transmitted to the light emitting chips C1 to C40. The lighting signals φI1 to φI40 are signals for setting the light emitting thyristors L of the respective light emitting chips C1 to C40 to be lit or not lit based on the image data. Therefore, the waveforms of the lighting signals φI1 to φI40 are different depending on the image data. However, the lighting signals φI1 to φI40 are transmitted in parallel at the same timing.
Since the light emitting chips C1 to C40 are driven in parallel, it is sufficient to describe the operation of the light emitting chip C1.

<Thyristor>
Before describing the operation of the light emitting chip C1, the basic operation of the thyristor (transfer thyristor T, light emitting thyristor L) will be described. As described above, the thyristor is a semiconductor element having three terminals: an anode terminal, a cathode terminal, and a gate terminal.
Hereinafter, as an example, the reference potential Vsub supplied to the back electrode 85 (see FIGS. 5 and 6), which is the Vsub terminal, is set to a high level potential (hereinafter referred to as “H”) at 0 V and the Vga terminal. The power supply potential Vga supplied will be described as −3.3 V as a low level potential (hereinafter referred to as “L”).
In the present embodiment, the light emitting device 65 is driven with a negative potential.

Since the p-type first semiconductor layer 81 that is the anode terminal of the thyristor has the same potential as the p-type substrate 80, the anode terminal of the thyristor has the reference potential Vsub (“H” (0 V)) supplied to the back electrode 85. It has become.
As shown in FIG. 6, for example, the thyristor includes a p-type semiconductor layer (p-type first semiconductor layer 81, p-type third semiconductor layer 83), an n-type semiconductor layer (n-type semiconductor layer) made of GaAs, GaAlAs, or the like. The second semiconductor layer 82 and the n-type fourth semiconductor layer 84) are stacked on the p-type substrate 80. Here, a forward potential (diffusion potential) Vd of a pn junction composed of a p-type semiconductor layer and an n-type semiconductor layer is described as 1.5 V as an example.

A thyristor in an off state in which no current flows between the anode terminal and the cathode terminal transitions to an on state (turn on) when a potential lower than the threshold voltage (a negative potential having a large absolute value) is applied to the cathode terminal. To do. Here, the threshold voltage of the thyristor is a value obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the gate terminal. Therefore, when the potential of the gate terminal is 0V, the threshold voltage of the thyristor is −1.5V. That is, when a potential lower than −1.5 V (a negative potential having a large absolute value) is applied to the cathode terminal, the thyristor is turned on. When the thyristor is turned on, a current flows between the anode terminal and the cathode terminal (ON state).
The potential of the gate terminal of the thyristor in the on state is close to the potential of the anode terminal. Here, since the anode terminal is set to the reference potential Vsub (0 V (“H”)), the potential of the gate terminal is assumed to be 0 V (“H”). Further, the cathode terminal of the thyristor in the on state has a potential close to the potential obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the anode terminal. Here, since the anode terminal is set to the reference potential Vsub (0 V (“H”)), the potential of the cathode terminal of the on-state thyristor is close to −1.5 V (the absolute value is larger than 1.5 V). Negative potential). Note that the potential of the cathode terminal is set in relation to a power source that supplies current to the thyristor in the on state.

Once the thyristor is turned on, the potential of the cathode terminal is higher than the potential necessary to maintain the on state (potential close to −1.5 V described above) (a negative potential having a small absolute value, 0 V or a positive potential). When (potential) is applied, it is turned off (turned off). For example, when the cathode terminal becomes “H” (0 V), the potential is higher than the potential necessary for maintaining the ON state, and the potential of the cathode terminal and the potential of the anode terminal are the same, so that the thyristor is turned off. To do.
On the other hand, a potential lower than the potential necessary to maintain the on state (a negative potential having a large absolute value) is continuously applied to the cathode terminal of the on state thyristor, and the current that can maintain the on state (sustain current) ) Is supplied, the thyristor remains on.
The light-emitting thyristor L is turned on (emits light) when turned on, and turned off (not lit) when turned off. The light emission amount of the light emitting thyristor L in the on state is determined by the area of the light emitting surface 311 and the current flowing between the cathode terminal and the anode terminal.

<Timing chart>
FIG. 8 is a timing chart for explaining operations of the light emitting device 65 and the light emitting chip C.
FIG. 8 shows a timing chart of a part that controls lighting (noted as lighting control) of the five light emitting thyristors L1 to L5 of the light emitting chip C1. As described above, since the other light emitting chips C2 to C40 operate in parallel with the light emitting chip C1, it is sufficient to describe the operation of the light emitting chip C1.
In FIG. 8, the light emitting thyristors L1, L2, L3, and L5 of the light emitting chip C1 are turned on, and the light emitting thyristor L4 is turned off (not lit).

In FIG. 8, it is assumed that time elapses in alphabetical order from time a to time k. The light emitting thyristor L1 is in the period T (1) from time b to time e, the light emitting thyristor L2 is in the period T (2) from time e to time i, and the light emitting thyristor L3 is in the period T (from time i to time j). In 3), the light-emitting thyristor L4 is controlled to be turned on or off (lighting control) in a period T (4) from time j to time k. Thereafter, the light-emitting thyristor L having a number of 5 or more is similarly controlled to be turned on.
Here, the periods T (1), T (2), T (3),... Have the same length, and are referred to as the period T when they are not distinguished from each other.
Note that the lengths of the periods T (1), T (2), T (3),... May be variable as long as the mutual relationship of signals described below is maintained.

  The waveforms of the first transfer signal φ1, the second transfer signal φ2, and the lighting signal φI1 will be described. Note that the period from time a to time b is a period during which the light emitting chip C1 (the same applies to the light emitting chips C2 to C40) is started. The signal in this period will be described in the description of the operation.

  The first transfer signal φ1 transmitted to the φ1 terminal (see FIGS. 5 and 6) and the second transfer signal φ2 transmitted to the φ2 terminal (see FIGS. 5 and 6) are “H” and “L”. A signal having two potentials. The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated in units of two consecutive periods T (for example, the period T (1) and the period T (2)).

The first transfer signal φ1 shifts from “H” to “L” at the start time b of the period T (1), and shifts from “L” to “H” at the time f. Then, at the end time i of the period T (2), the state shifts from “H” to “L”.
The second transfer signal φ2 is “H” at the start time b of the period T (1), and shifts from “H” to “L” at the time e. Then, “L” is maintained at the end time i of the period T (2).
Comparing the first transfer signal φ1 and the second transfer signal φ2, the second transfer signal φ2 corresponds to the first transfer signal φ1 shifted after the period T on the time axis. In the first transfer signal φ1, the waveforms in the period T (1) and the period T (2) are repeated after the period T (3). On the other hand, in the second transfer signal φ2, in the period T (1), the waveform indicated by the broken line and the waveform in the period T (2) are repeated after the period T (3). The waveform of the period T (1) of the second transfer signal φ2 is different from that after the period T (3) because the period T (1) is a period during which the light emitting device 65 starts operating.

  As will be described later, a set of transfer signals of the first transfer signal φ1 and the second transfer signal φ2 is transmitted in the ON state by causing the transfer thyristors T shown in FIGS. The light-emitting thyristor L having the same number as the transfer thyristor T is designated as a target for lighting or non-lighting control (lighting control).

  Next, the lighting signal φI1 transmitted to the φI terminal of the light emitting chip C1 will be described. Note that lighting signals φI2 to φI40 are transmitted to the other light emitting chips C2 to C40, respectively. The lighting signal φI1 is a signal having two potentials of “H” and “L”.

Here, the lighting signal φI1 will be described in the lighting control period T (1) for the light emitting thyristor L1 of the light emitting chip C1. Note that the light-emitting thyristor L1 is turned on.
The lighting signal φI1 is “H” at the start time b of the period T (1), and shifts from “H” to “L” at the time c. Then, it shifts from “L” to “H” at time d and maintains “H” at the end time e of the period T (1).

Now, the operations of the light emitting device 65 and the light emitting chip C1 will be described according to the timing chart shown in FIG. 8 with reference to FIGS. Hereinafter, the periods T (1) and T (2) in which the lighting thyristors L1 and L2 are controlled to be lighted will be described.
(1) Time a
<Light emitting device 65>
At time a, the reference potential supply unit 160 of the signal generation circuit 110 of the light emitting device 65 sets the reference potential Vsub to “H” (0 V). The power supply potential supply unit 170 sets the power supply potential Vga to “L” (−3.3 V). Then, the power supply line 200a on the circuit board 62 of the light emitting device 65 becomes “H” (0 V) of the reference potential Vsub, and the Vsub terminals of the light emitting chips C1 to C40 become “H”. Similarly, the power supply line 200b becomes “L” (−3.3 V) of the power supply potential Vga, and the Vga terminals of the light emitting chips C1 to C40 become “L” (see FIG. 4). Thereby, each power supply line 71 of the light emitting chips C1 to C40 becomes “L” (see FIG. 5).

  Then, the transfer signal generator 120 of the signal generation circuit 110 sets the first transfer signal φ1 and the second transfer signal φ2 to “H”, respectively. Then, the first transfer signal line 201 and the second transfer signal line 202 become “H” (see FIG. 4). As a result, the φ1 terminal and φ2 terminal of each of the light emitting chips C1 to C40 become “H”. The potential of the first transfer signal line 72 connected to the φ1 terminal via the current limiting resistor R1 also becomes “H”, and the second transfer signal line 73 connected to the φ1 terminal via the current limiting resistor R2 is also set. It becomes “H” (see FIG. 5).

  Further, the lighting signal generator 140 of the signal generation circuit 110 sets the lighting signals φI1 to φI40 to “H”, respectively. Then, the lighting signal lines 204-1 to 204-40 become “H” (see FIG. 4). Thereby, each φI terminal of the light emitting chips C1 to C40 becomes “H” via the current limiting resistor RI, and the lighting signal line 75 connected to the φI terminal also becomes “H” (see FIG. 5).

Next, the operation of the light emitting chip C1 will be described.
8 and the following description, it is assumed that the potential of each terminal changes in a step shape, but the potential of each terminal changes gradually. Therefore, even if the potential is changing, the thyristor may be turned on or turned off to change the state if the following conditions are satisfied.

<Light emitting chip C1>
Since the anode terminals of the transfer thyristor T and the light emitting thyristor L are connected to the Vsub terminal, they are set to “H” (0 V).

  The cathode terminals of the odd-numbered transfer thyristors T1, T3, T5,... Are connected to the first transfer signal line 72 and set to “H”. The cathode terminals of the even-numbered transfer thyristors T2, T4, T6,... Are connected to the second transfer signal line 73 and set to “H”. Therefore, the transfer thyristor T is in the OFF state because both the anode terminal and the cathode terminal are “H”.

  The cathode terminal of the light emitting thyristor L is connected to the “H” lighting signal line 75. Therefore, the light-emitting thyristor L is also in the off state because both the anode terminal and the cathode terminal are “H”.

As described above, the gate terminal Gt1 at one end of the transfer thyristor array in FIG. 5 is connected to the cathode terminal of the start diode Dx0. The gate terminal Gt1 is connected to the power supply line 71 of the power supply potential Vga (“L” (−3.3 V)) via the power supply line resistance Rgx1. The anode terminal of the start diode Dx0 is connected to the second transfer signal line 73, and is connected to the φ2 terminal of “H” (0 V) via the current limiting resistor R2. Therefore, the start diode Dx0 is forward-biased, and the cathode terminal (gate terminal Gt1) of the start diode Dx0 has a forward potential Vd (1) of the pn junction from the potential (“H” (0V)) of the anode terminal of the start diode Dx0. .5V) minus (-1.5V). When the gate terminal Gt1 becomes −1.5V, the coupling diode Dx1 has an anode terminal (gate terminal Gt1) of −1.5V and a cathode terminal connected to the power supply line 71 (“L” (“L”) via the power supply resistance Rgx2. -3.3V)), it is forward biased. Therefore, the potential of the gate terminal Gt2 becomes −3 V obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential (−1.5 V) of the gate terminal Gt1. However, the gate terminal Gt having a number of 3 or more is not affected by the fact that the anode terminal of the start diode Dx0 is “H” (0 V), and the potential of these gate terminals Gt is the potential of the power supply line 71. It is a certain “L” (−3.3 V).
Since the gate terminal Gt is connected to the gate terminal Gl, the potential of the gate terminal Gl is the same as the potential of the gate terminal Gt. Accordingly, the threshold voltages of the transfer thyristor T and the light emitting thyristor L are values obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potentials of the gate terminals Gt and Gl. That is, the threshold voltage of the transfer thyristor T1 and the light-emitting thyristor L1 is −3 V, the threshold voltage of the transfer thyristor T2 and the light-emitting thyristor L2 is −4.5 V, the threshold voltage of the transfer thyristor T and the light-emitting thyristor L having a number of 3 or more. Is -4.8V.

(2) Time b
At time b shown in FIG. 8, the first transfer signal φ1 shifts from “H” (0V) to “L” (−3.3V). Thereby, the light emitting device 65 starts operation.
When the first transfer signal φ1 shifts from “H” to “L”, the potential of the first transfer signal line 72 shifts from “H” to “L” via the φ1 terminal and the current limiting resistor R1. Then, the transfer thyristor T1 having a threshold voltage of −3V is turned on. However, an odd-numbered transfer thyristor T having a cathode terminal connected to the first transfer signal line 72 and having an odd number of 3 or more cannot be turned on because the threshold voltage is −4.8V. On the other hand, the even-numbered transfer thyristor T cannot be turned on because the second transfer signal φ2 is “H” (0 V) and the second transfer signal line 73 is “H”.
When the transfer thyristor T1 is turned on, the potential of the first transfer signal line 72 is obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential (“H” (0 V)) of the anode terminal. 5V.

When the transfer thyristor T1 is turned on, the potential of the gate terminal Gt1 (gate terminal Gl1) becomes “H” (0 V) which is the potential of the anode terminal of the transfer thyristor T1. The potential of the gate terminal Gt2 (gate terminal Gl2) is −1.5V, the potential of the gate terminal Gt3 (gate terminal Gl3) is −3V, and the potential of the gate terminal Gt (gate terminal Gl) having a number of 4 or more is “L”. (-3.3V).
Thus, the threshold voltage of the light emitting thyristor L1 is −1.5V, the threshold voltage of the transfer thyristor T2, the light emitting thyristor L2 is −3V, the threshold voltage of the transfer thyristor T3 and the light emitting thyristor L3 is −4.5V, and the number is The threshold voltage of four or more transfer thyristors T and light-emitting thyristors L becomes −4.8V.
However, since the first transfer signal line 72 is at −1.5 V by the transfer thyristor T1 in the on state, the odd-numbered transfer thyristor T in the off state is not turned on. Since the second transfer signal line 73 is “H”, the even-numbered transfer thyristor T is not turned on. Since the lighting signal line 75 is “H”, none of the light emitting thyristors L is turned on.

  Immediately after time b (in this case, when the thyristor or the like is changed due to a change in the signal potential at time b and then enters a steady state), the transfer thyristor T1 is in the on state, The transfer thyristor T and the light emitting thyristor L are in the off state.

(3) Time c
At time c, the lighting signal φI1 shifts from “H” to “L”.
When the lighting signal φI1 shifts from “H” to “L”, the lighting signal line 75 shifts from “H” to “L” via the current limiting resistor RI and the φI terminal. Then, the light emitting thyristor L1 having a threshold voltage of −1.5 V is turned on and lit (emits light). As a result, the potential of the lighting signal line 75 becomes a potential close to −1.5V (a negative potential having an absolute value greater than 1.5V). Note that the threshold voltage of the light emitting thyristor L2 is −3V, but the threshold voltage is as high as −1.5V (a negative potential having a small absolute value), the light emitting thyristor L1 is turned on, and the lighting signal line 75 is Since the potential is close to −1.5 V, the light emitting thyristor L2 is not turned on.
Immediately after time c, the transfer thyristor T1 is in the on state, and the light emitting thyristor L1 is lit (emitted) in the on state.

(4) Time d
At time d, the lighting signal φI1 shifts from “L” to “H”.
When the lighting signal φI1 shifts from “L” to “H”, the potential of the lighting signal line 75 shifts from “L” to “H” via the current limiting resistor RI and the φI terminal. Then, since the anode terminal and the cathode terminal both become “H”, the light emitting thyristor L1 is turned off and turned off (not lit). During the lighting period of the light emitting thyristor L1, the lighting signal φI1 from the time c when the lighting signal φI1 shifts from “H” to “L” to the time d when the lighting signal φI1 shifts from “L” to “H” is “ L ".
Immediately after time d, the transfer thyristor T1 is in the ON state.

(5) Time e
At time e, the second transfer signal φ2 shifts from “H” to “L”. Here, the period T (1) for controlling the lighting of the light emitting thyristor L1 ends, and the period T (2) for controlling the lighting of the light emitting thyristor L2 starts.
When the second transfer signal φ2 shifts from “H” to “L”, the potential of the second transfer signal line 73 shifts from “H” to “L” via the φ2 terminal. As described above, the transfer thyristor T2 is turned on because the threshold voltage is -3V. Thereby, the potential of the gate terminal Gt2 (gate terminal Gl2) is “H” (0 V), the potential of the gate terminal Gt3 (gate terminal Gl3) is −1.5 V “H” (0 V), and the gate terminal Gt4 (gate terminal Gl4). ) Becomes -3V. The potential of the gate terminal Gt (gate terminal Gl) having a number of 5 or more becomes −3.3V.
Immediately after time e, the transfer thyristors T1 and T2 are in the ON state.

(6) Time f
At time f, the first transfer signal φ1 shifts from “L” to “H”.
When the first transfer signal φ1 shifts from “L” to “H”, the potential of the first transfer signal line 72 shifts from “L” to “H” via the φ1 terminal. Then, the transfer thyristor T1 in the on state is turned off when both the anode terminal and the cathode terminal are set to “H”. Then, the potential of the gate terminal Gt1 (gate terminal Gl1) changes toward the power supply potential Vga (“L” (−3.3 V)) of the power supply line 71 via the power supply line resistance Rgx1. As a result, the coupling diode Dx1 is in a state in which a potential is applied in a direction in which no current flows (reverse bias). Therefore, the influence that the gate terminal Gt2 (gate terminal Gl2) is “H” (0 V) does not reach the gate terminal Gt1 (gate terminal Gl1). That is, in the transfer thyristor T having the gate terminal Gt connected by the reverse-biased coupling diode Dx, the threshold voltage becomes −4.8V, and the first transfer signal φ1 of “L” (−3.3V) or The second transfer signal φ2 does not turn on.
Immediately after time f, the transfer thyristor T2 is in the ON state.

(7) Others When the lighting signal φI1 shifts from “H” to “L” at time g, the light-emitting thyristor L2 is turned on and lit (emits light) in the same manner as the light-emitting thyristor L1 at time c.
At time h, when the lighting signal φI1 shifts from “L” to “H”, the light emitting thyristor L2 is turned off and turned off, similarly to the light emitting thyristor L1 at time d.
Further, when the first transfer signal φ1 shifts from “H” to “L” at time i, a transfer with a threshold voltage of −3 V is performed as in the transfer thyristor T1 at time b or the transfer thyristor T2 at time e. Thyristor T3 is turned on. At time i, the period T (2) for controlling the lighting of the light emitting thyristor L2 ends, and the period T (3) for controlling the lighting of the light emitting thyristor L3 starts.
Thereafter, the above description is repeated.

  When the light-emitting thyristor L is not turned on (emitted) but remains turned off (non-lighted), the lighting signal from time j to time k in the period T (4) during which the light-emitting thyristor L4 in FIG. As with φI1, the lighting signal φI may remain “H” (0 V). By doing in this way, even if the threshold voltage of the light emitting thyristor L4 is −1.5 V, the light emitting thyristor L4 remains off (not lit).

As described above, the gate terminals Gt of the transfer thyristors T are connected to each other by the coupling diode Dx. Therefore, when the potential of the gate terminal Gt changes, the potential of the gate terminal Gt connected to the gate terminal Gt whose potential has changed via the forward-biased coupling diode Dx changes. Then, the threshold voltage of the transfer thyristor T having the gate terminal whose potential has changed changes. When the threshold voltage of the transfer thyristor T is higher than “L” (−3.3 V) (a negative potential having a small absolute value), the first transfer signal φ1 or the second transfer signal φ2 is changed from “H” (0 V). Turns on at the timing of shifting to “L” (−3.3 V).
Since the threshold voltage of the light emitting thyristor L in which the gate terminal Gl is connected to the gate terminal Gt of the transfer thyristor T in the on state is −1.5 V, the lighting signal φI shifts from “H” to “L”. Then, it turns on and lights up (emits light).
That is, when the transfer thyristor T is turned on, the light emitting thyristor L that is the object of lighting control is designated, and the lighting signal φI sets the light emitting thyristor L that is the object of lighting control to be lit or not lit.
As described above, the waveform of the lighting signal φI is set according to the image data, and the lighting or non-lighting of each light-emitting thyristor L is controlled.

(Lens 92)
The lens 92 in the first embodiment will be described.
In the first embodiment, as shown in FIG. 6, the lens 92 has a cylindrical opening 92a at the center and a curved surface 92b having a convex outer surface. The reason for this will be described.

The light emitting surface 311 of the light emitting thyristor L is a flat surface. Therefore, the light-emitting thyristor L works not as a point light source but as a surface light source having a finite area. And it is thought that it is light-emitted so that (radiation) brightness | luminance may become equal in all directions from the fine area | region (surface element) which comprises the light emission surface 311 similarly to a perfect diffuse surface light source. Therefore, the (radiation) intensity in the direction perpendicular to the light emitting surface 311 is the strongest, and the (radiation) intensity decreases as the direction becomes oblique. Note that the light emission distribution having the same (radiant) luminance in all directions is called a Lambertian distribution.
For this reason, it is desirable that more light emitted from the light emitting surface 311 in the vertical direction can be extracted.

First, the lens 93 that does not have the opening 92a in the lens 92 will be described.
FIG. 9 is a schematic diagram showing the relationship between the light emitting surface 311 of the light emitting thyristor L and the lens 93 having no opening 92a in a cross section including an optical axis (a line passing through a principal point O and focal points F and F ′ described later). It is. Here, the insulating layer 86, the n-type ohmic electrode 321, and the branch portion 75b of the lighting signal line 75 are omitted.
The surface of the lens 93 is a curved surface 93b obtained by extending a curved surface 92c (see FIG. 6) of the curved surface portion 92b of the lens 92 to the opening 92a side. The lens 93 functions as a convex lens.
Here, the front principal point and the rear principal point of the lens 93 coincide with each other and are designated as a principal point O. Further, it is assumed that the focal points F and F ′ are at an equal distance from the principal point O, respectively.
The light emitting surface 311 is assumed to be between the principal point O and the focal point F of the lens 93. That is, the lens 93 functions as a magnifying glass (magnifying glass).

Further, the light emitted from the light emitting thyristor L is taken in by the rod lens array 64 having an opening angle θ through the lens 93 and the photosensitive drum 12 is exposed. That is, light having an angle exceeding the opening angle θ does not enter the rod lens array 64. Therefore, the amount of light incident within the opening angle θ is the amount of light (radiant energy) for exposing the photosensitive drum 12.
Here, description will be given focusing on one lens 93 corresponding to one light-emitting thyristor L. Even if the light emitted from the light emitting thyristor L is incident on the lens 93 provided in the adjacent light emitting thyristor L, the emitted light is emitted at an angle larger than the opening angle θ, and therefore does not enter the rod lens array 64. . Therefore, attention should be paid to one lens 93 corresponding to one light-emitting thyristor L.

FIG. 9A is a diagram showing an optical path from the light emitting point P1 at the central portion of the light emitting surface 311 (the portion facing the opening 92a in the case of the lens 92), and FIG. 9B is the periphery of the light emitting surface 311. The figure which shows the optical path from the light emission point P2 of the part (part facing the curved surface part 92b in the case of the lens 92), and FIG.9 (c) are from the light emission point P3 of the center part near the peripheral part of the light emission surface 311. It is a figure which shows these optical paths.
In these drawings, it is assumed that the optical path changes on a principal plane (indicated by a broken line in the figure) perpendicular to the optical axis (line passing through the principal point O and the focal points F and F ′) through the principal point O.

  As shown in FIG. 9A, light emitted from the light emitting point P1 at the center of the light emitting surface 311 through the lens 93 behaves like light emitted from the image point P1 ′ on the image surface. That is, the light emitted from the light emitting point P1 at the center of the light emitting surface 311 is emitted from the lens 93 in the range of the angle α. As can be seen from FIG. 9A, the light from the light emitting point P1 is focused in the optical axis direction. For this reason, the light quantity within the opening angle θ increases.

  On the other hand, as shown in FIG. 9B, the light emitted from the light emitting point P2 around the light emitting surface 311 through the lens 93 behaves like the light emitted from the image point P2 ′ on the image surface. That is, the light emitted from the light emitting point P2 around the light emitting surface 311 is emitted from the lens 93 in the range of the angle β. As can be seen from FIG. 9B, the light from the light emitting point P2 does not enter the opening angle θ. This indicates that light cannot be extracted from the periphery of the light emitting surface 311 because the lens 93 serves as a magnifying glass.

Now, as shown in FIG. 9C, the light emitted from the light emitting point P3 in the central part near the peripheral part of the light emitting surface 311 through the lens 93 is the light emitted from the image point P3 ′ on the image surface. Behave like this. That is, the light emitted from the light emitting point P3 is emitted from the lens 93 within the range of the angle δ. As can be seen from FIG. 9C, a part of the light from the light emitting point P3 is within the opening angle θ, but the other does not enter. Further, the light emitted perpendicularly to the light emitting surface 311 from the light emitting point P3 (light passing through the focal point F ′ in FIG. 9C) does not enter the opening angle θ.
This is because the lens 93 functions as a magnifying glass, so that light is extracted only from a portion near the optical axis at the center of the light emitting surface 311 and from a portion far from the optical axis at the center of the light emitting surface 311 or from the peripheral portion. By not taking in the light.

  Even if the lens 93 is used, as shown in FIG. 9A, there is an effect of condensing light emitted from the central portion of the light emitting surface 311. Therefore, compared to the case where the lens 93 is not used, the rod lens is used. The amount of light captured by the array 64 (see FIG. 2) increases. As a result, the amount of light irradiated onto the photosensitive drum 12 (see FIG. 2) increases. That is, the extraction efficiency of the light emitted from the light emitting thyristor L is improved.

As described above, the (radiant) intensity of light emitted from the light emitting surface 311 of the light emitting thyristor L (hereinafter referred to as light emission intensity) is greatest in the direction perpendicular to the light emitting surface 311 and the light emitting surface 311 The closer to the center, the bigger. From this, it is considered that the central portion of the light emitting surface 311 does not need to be condensed by the lens. That is, it is considered that it is not necessary to provide a lens for the central portion of the light emitting surface 311.
Therefore, in the first embodiment, as shown in FIG. 6B, an opening 92a is provided in a portion facing the central portion of the light emitting surface 311 of the lens 92.

Next, the lens 92 provided with the opening 92a will be described.
FIG. 10 is a schematic diagram showing the relationship between the light emitting surface 311 of the light emitting thyristor L and the lens 92 having the opening 92a in a cross section including the optical axis (line passing through the principal point O and the focal points F and F ′). Also here, the insulating layer 86, the n-type ohmic electrode 321, and the branch portion 75b of the lighting signal line 75 are omitted.
In the lens 92, the curved surface 92c of the curved surface portion 92b has the same shape as the corresponding portion of the curved surface 93b (shown by a dotted line in FIG. 10) of the lens 93 shown in FIG. The curved surface portion 92b of the lens 92 functions as a convex lens. The lens 92 has an opening 92 a facing the central portion of the light emitting surface 311.
It is assumed that the principal point O and the focal points F and F ′ of the curved surface portion 92 b in the lens 92 are at the same position as the lens 93. The light emitting surface 311 is assumed to be between the principal point O and the focal point F of the lens 92. Therefore, the curved surface portion 92 b of the lens 92 functions as a magnifying glass (magnifying glass) like the lens 93.
Furthermore, it is assumed that light within the opening angle θ is taken into the rod lens array 64.
Here, the description will be given focusing on one lens 93 corresponding to one light-emitting thyristor L.

FIG. 10A is a diagram showing an optical path from the light emitting point P1 at the center of the light emitting surface 311. FIG. 10B is a diagram showing an optical path from the light emitting point P2 at the peripheral portion of the light emitting surface 311. FIG. 10C is a diagram illustrating an optical path from the light emitting point P <b> 3 in the central portion near the peripheral portion of the light emitting surface 311.
Hereinafter, in the curved surface portion 92b, it is assumed that the optical path changes on a main surface (indicated by a broken line in the drawing) perpendicular to the optical axis through the main point O. Further, it is assumed that the lens 92 has no thickness.

As shown in FIG. 10A, the light emitted from the light emitting point P1 at the center of the light emitting surface 311 through the lens 92 passes through the opening 92a and is emitted in the range of the angle α0. The light is output in the range of the angle α1 through the left curved surface portion 92b of (a) and the light output at the angle α2 through the right curved surface portion 92b of FIG. 10A. The light emitted in the range of the angle α1 and the light emitted at the angle α2 are part of the light emitted at the angle α shown in FIG.
In addition, since the light radiate | emitted in the range of angle (alpha) 0 through the opening part 92a is not condensed, the light which does not enter in the opening angle (theta) arises. On the other hand, the light emitted in the range of the angle α1 and the range of the angle α2 through the curved surface portion 92b is condensed in the same manner as in the case of the lens 93 that does not have the opening 92a (see FIG. 9A). Falls within the opening angle θ.
Here, it is assumed that the lens 92 has no thickness. However, when the lens 92 has a thickness, light that is emitted obliquely with respect to the light-emitting surface 311 from the light-emitting surface 311 facing the opening 92a and cannot pass through the opening 92a is the opening 92a. This corresponds to the inner surface 92d (see FIG. 6). The light then enters the curved surface portion 92 b of the lens 92 and exits from the curved surface 92 c of the lens 92.
Further, light spreads by diffraction at the upper end of the opening 92 a of the lens 92.
Here, the influence of these lights is omitted.

On the other hand, as shown in FIG. 10B, the light emitted from the light emitting point P2 around the light emitting surface 311 through the lens 92 passes through the opening 92a and is emitted in the range of an angle β0. The light is emitted in the range of the angle β1 through the left curved surface 92c in FIG. 10B and the light emitted at the angle β2 through the right curved surface 92c in FIG. 10B.
As shown in FIG. 10B, the light emitted in each of these angles β0, β1, and β2 does not enter the opening angle θ. This is similar to the case of the lens 93 that does not have the opening 92a (see FIG. 9B).

Now, as shown in FIG. 10 (c), the light emitted from the central light emitting point P3 near the peripheral portion of the light emitting surface 311 through the lens 92 passes through the opening 92a and is emitted in the range of the angle δ0. And the light emitted at the angle δ1 through the left curved surface 92c of FIG. 10C and the light emitted at the angle δ2 through the right curved surface 92c of FIG. 10C are added. It becomes light.
And as shown in FIG.10 (c), the light emission point P3 is provided in the position facing the opening part 92a. Therefore, the light emitted perpendicularly with respect to the light emitting surface 311 from the light emitting point P3 enters the opening angle θ.
That is, light having the highest light emission intensity that travels in the vertical direction from the light emission point P3 between the central portion and the peripheral portion of the light emitting surface 311 enters the aperture angle θ.

As described above, by using the lens 92 having the opening 92a, as shown in FIG. 10C, light emission from the central portion (from position P4 to position P5) of the light emitting surface 311 facing the opening 92a. From this point, light having a high emission intensity emitted in a direction perpendicular to the light emitting surface 311 is emitted as it is in a direction perpendicular to the light emitting surface 311 and enters the opening angle θ.
That is, when the light emitting surface 311 is viewed from the outside of the lens 92 from the vertical direction, the lens effect does not work in the opening 92a, so that the light emitting surface 311 is compared to the case of the lens 93 without the opening 92a shown in FIG. You can see the whole of the center. For this reason, in the first embodiment, the emission intensity emitted from the central portion of the light emitting surface 311 in the direction perpendicular to the light emitting surface 311 is larger than when the lens 93 without the opening 92a is used. The light can be taken into the rod lens array 64. As a result, the amount of light applied to the photosensitive drum 12 increases. That is, the light emitted from the light emitting thyristor L can be extracted more efficiently.

As described above, the opening 92a may pass the light emitted from the central portion of the light emitting surface 311 as it is. Therefore, the opening 92 a is not necessarily perpendicular to the light emitting surface 311 and may be inclined with respect to the light emitting surface 311.
Furthermore, the opening 92a may not have the same cross-sectional shape on the side closer to the light emitting surface 311 and on the side farther from the light emitting surface 311, and either one may be larger than the other. Further, the shape of the cross section of the opening 92a may change between the side closer to the light emitting surface 311 and the side farther from the light emitting surface 311.

  The shape of the lens 92 shown in FIG. 10 is an example. Therefore, the positions of the focal points F and F ′, the size of the opening 92a, the size of the opening angle θ, and the like are set so that the amount of light taken into the rod lens array 64 is maximized (in this embodiment, The shape may be set in consideration of the shape of the light emitting surface of the light emitting thyristor L) and the distribution of light emission intensity.

Next, the amount of light emitted from the light emitting surface 311 of the light emitting thyristor L to the photosensitive drum 12 via the rod lens array 64 was obtained by simulation.
FIG. 11 is a diagram showing the shape of the lens used in the simulation. FIG. 11A shows a lens 93 having no opening 92a, and FIG. 11B shows a lens 92 having an opening 92a in the present embodiment.

First, the lens 93 will be described with reference to FIG. As described with reference to FIG. 9, the lens 93 does not have the opening 92a. Here, the insulating layer 86, the n-type ohmic electrode 321, and the branch portion 75 b of the lighting signal line 75 are omitted, and the lens 93 is provided on the light emitting surface 311. The light emitting surface 311 is a square having a side length w of 30 μm, and the distance s between the apex of the lens 93 farthest from the light emitting surface 311 and the light emitting surface 311 is 20 μm. Further, the radius of curvature r of the curved surface 93b of the lens 93 was set to 16.3 μm. When the lens 93 has a refractive index of 1.63, the focal length between the focal point F and the principal point O is 21.22 μm. Thereby, the light emitting surface 311 is located between the focal point F and the principal point O (see FIG. 9).
Further, the opening angle θ of the rod lens array 64 was set to 34 °.

Next, the lens 92 shown in FIG. 11B will be described. The lens 92 has the opening 92a as described with reference to FIG. The light emitting surface 311 is a square having a side length w of 30 μm, the opening 92 a is a cylindrical shape provided corresponding to the central portion of the light emitting surface 311, and its radius u is 5 μm. The radius of curvature r of the curved surface 92c of the curved surface portion 92b was set to 16.3 μm similarly to the lens 93 of the comparative example.
Other values are the same as those of the lens 93.

According to the simulation, the amount of light applied to the photosensitive drum 12 was 2.18 times when the lens 93 was used (FIG. 11A) compared to when the lens 93 was not used. Further, in the case where the lens 92 was used (FIG. 11B), it was 2.38 times that in the case where the lens 92 was not used. Therefore, when the lens 92 having the opening 92a in the first embodiment is used, the amount of light irradiated on the photosensitive drum 12 is increased by about 10% compared to the case where the lens 93 having no opening 92a is used. .
As described above, by using the lens 92 having the opening 92a in the first embodiment, the extraction efficiency of the light emitted from the light emitting thyristor L is improved.

So far, the case where the center of the opening 92a of the lens 92 and the center of the light emitting surface 311 are matched has been described.
Next, a case where the center of the opening 92a of the lens 92 and the center of the light emitting surface 311 are not matched will be described.
FIG. 12 is an example of a plan layout view and a cross-sectional view of the light emitting thyristor L portion in the light emitting chip C when the center of the opening 92a of the lens 92 and the center of the light emitting surface 311 are not aligned.
12A is a plan layout view of the light-emitting chip C, FIG. 12B is a cross-sectional view taken along line XIIB-XIIB shown in FIG. 12A, and FIG. 12C is shown in FIG. It is sectional drawing in the XIIC-XIIC line.

As shown in FIG. 12A, an n-type ohmic electrode 321 is provided at the center of the light emitting surface 311 of the light emitting thyristor L. A branch portion 75 b that connects the trunk portion 75 a of the lighting signal line 75 and the n-type ohmic electrode 321 is provided across the light emitting surface 311. Therefore, no light is emitted from the portion of the light emitting surface 311 covered with the n-type ohmic electrode 321 and the branch portion 75b.
For this reason, the portion with the highest emission intensity of the emitted light is a portion (horse-shoe region 90) surrounding the n-type ohmic electrode 321 and the branch portion 75b in a horseshoe shape. For this reason, as shown in FIGS. 12A and 12B, the center of the light emitting surface 311 is removed so that the center of the opening 92a of the lens 92 is removed from the portion where the n-type ohmic electrode 321 and the branch portion 75b are provided. To the horseshoe-shaped region 90 where the emission intensity is high (y-direction shift amount−Sy).
In addition, when the portion with high emission intensity is shifted in the x direction from the center of the light emitting surface 311, the center of the opening 92 a of the lens 92 may be shifted in the x direction.

So far, the case where the planar shape of the opening 92a of the lens 92 is circular has been described. However, the planar shape of the opening 92a of the lens 92 is not necessarily circular.
FIG. 13 is an example of a planar layout diagram and a cross-sectional view of the light emitting thyristor L portion in the light emitting chip C when the planar shape of the opening 92a of the lens 92 is not circular.
13A is a plan layout view of the light-emitting chip C, FIG. 13B is a cross-sectional view taken along line XIIIB-XIIIB shown in FIG. 13A, and FIG. 13C is shown in FIG. It is sectional drawing in the XIIIC-XIIIC line.
As shown in FIG. 13A, the light emitting surface 311 of the light emitting thyristor L is a rectangle having a longer y direction than the x direction. As described above, when the light emitting surface 311 of the light emitting thyristor L is enlarged in the direction orthogonal to the light emitting thyristor array, the light amount is increased without changing the pitch of the light emitting thyristors L.
In this case, as shown in FIGS. 13A and 13B, the planar shape of the opening 92a of the lens 92 is a rectangle with rounded corners so as to correspond to the shape of the light emitting surface 311 of the light emitting thyristor L. May be. Further, it may be oval or rectangular. That is, the cross-sectional shape of the opening 92a may be a rectangle with rounded corners, an ellipse, a rectangle, or the like.
The center of the planar shape of the opening 92a such as a rectangle with rounded corners, an ellipse, or a rectangle may be shifted from the center of the light emitting surface 311 as described with reference to FIG.

  Further, the curved surface 92c of the curved surface portion 92b of the lens 92 does not necessarily have to be a spherical surface having a constant curvature, and may be any shape as long as the light emitted from the light emitting surface 311 can be condensed in a predetermined direction. What is necessary is just to set by the shape of the light emission surface 311, the distribution of the emitted light intensity which the light emission surface 311 radiate | emits.

[Second Embodiment]
In the first embodiment, the lens 92 is provided on the light emitting thyristor L. In the second embodiment, a pedestal 91 is provided between the light emitting thyristor L and the lens 92.
FIG. 14 is an example of a plan layout view and a cross-sectional view of the light-emitting thyristor L portion in the light-emitting chip C in the second embodiment. 14A is a plan layout view of the light-emitting chip C, FIG. 14B is a cross-sectional view taken along line XIVB-XIVB in FIG. 14A, and FIG. 14C is XIVC-XIVC in FIG. It is sectional drawing in a line.
The pedestal 91 is a member having a flat surface provided to face the light emitting surface 311 of the light emitting thyristor L. The lens 92 is the same as the lens 92 of the first embodiment, and has an opening 92a. The opening 92 a of the lens 92 reaches the surface of the pedestal 91.
In FIG. 14, the pedestal 91 is provided on the light emitting surface 311 so as to face the light emitting surface 311, but includes the entire surface of the light emitting chip C excluding the terminal portion or the portion facing the light emitting surface 311. May be provided so as to cover a part of the light emitting chip C.

FIG. 15 is a cross-sectional view illustrating a method for manufacturing the light-emitting chip C of the second embodiment. The cross section shown in FIG. 15 is a cross section taken along the line XIVC-XIVC in FIG.
Here, it is assumed that the pedestal 91 is formed of a photosensitive material 94a made of negative polyimide resin, and the lens 92 is made of a photosensitive material 94b made of positive polyimide resin.
FIG. 15A shows the light emitting chip C before the lens 92 is formed.
As shown in FIG. 15B, a photosensitive material 94a, which is a negative polyimide resin, is applied to the surface of the light emitting chip C before the base 91 is formed, and the photosensitive material 94a is exposed via a photomask (not shown). The exposure light (not shown) which the photosensitive material 94a exposes is irradiated. Then, the part irradiated with the exposure light of the photosensitive material 94a is polymerized. When immersed in the developer, the portion of the photosensitive material 94a that has not been irradiated with the exposure light is dissolved and removed, and the polymerized portion remains insoluble, thereby forming the base 91. The photosensitive material 94a remaining after development is heat-treated (baked) at a predetermined temperature in order to evaporate the contained solvent and imidize the polyimide precursor of the photosensitive material 94a.
In FIG. 15B, the pedestals 91 are connected along the light emitting thyristor rows, but the pedestals 91 may be separated for each light emitting thyristor L.
Here, it is assumed that the pedestal 91 is provided for each lens 92 regardless of whether the pedestals 91 are connected along the light emitting thyristor row or separated for each light emitting thyristor L.

  And as shown in FIG.15 (c), the photosensitive material 94b which is a positive polyimide resin is apply | coated to the surface of the light emitting chip C in which the base 91 was formed, and the photosensitive material is passed through the photomask 95. The exposure light 97 which 94b exposes is irradiated. Here, in the same way as described in the first embodiment, the photomask 95 has the density of the dot pattern 96 in order to form the curved surface 92c (see FIG. 15D) of the lens 92 by the gray scale lithography method. A transmittance distribution is provided by the distribution.

Thereafter, as shown in FIG. 15D, the portion of the photosensitive material 94 that has become soluble by irradiation with the exposure light 97 is dissolved and removed by immersing in a developing solution (not shown). Then, by heating at a predetermined temperature, the solvent contained in the photosensitive material 94b is evaporated, and the polyimide precursor of the photosensitive material 94b is imidized, whereby the curved surface of the lens 92 made of polyimide resin. A portion 92b is formed.
Similar to the pedestal 91, the lenses 92 may be connected to each other along the light emitting thyristor row, or may be separated for each light emitting thyristor L.
Here, it is assumed that the lens 92 is provided for each light emitting thyristor L, whether the lenses 92 are connected along the light emitting thyristor row or separated for each light emitting thyristor L.
In this way, the light emitting chip C including the lens 92 including the base 91 and the lens 92 is manufactured.

  The amount of light transmitted through the photomask 95 is controlled by the density distribution of the dot pattern 96 that blocks the exposure light 97, but may be controlled by arranging dot patterns 96 having different sizes. Further, it may be controlled by changing the film thickness using a film having a different light transmittance depending on the thickness.

  Furthermore, as described in the first embodiment, the lens 92 may be formed by an imprint method.

  Also in the second embodiment, as described in the first embodiment, the center of the planar shape of the opening 92a of the lens 92 is opposed to the portion where the emission intensity of the light emitting surface 311 is high. The center of the light emitting surface 311 may be shifted from the center, and the planar shape of the opening 92a of the lens 92 may be a rectangle with a rounded corner, an ellipse, a rectangle, or the like corresponding to the planar shape of the light emitting surface 311. .

In the second embodiment, since the pedestal 91 is provided between the lens 92 and the light emitting thyristor L, restrictions on the formation of the lens 92 are reduced, and the formation of the lens 92 is facilitated.
In the second embodiment, when the lens 92 and the pedestal 91 are made of materials having different refractive indexes, light is refracted at the boundary between the pedestal 91 and the lens 92, and the light emitted from the light emitting surface 311 is more light. Concentrate in the axial direction.
Further, if the stress generated by the photosensitive material 94a of the pedestal 91 is smaller than the stress generated by the photosensitive material 94b of the lens 92, the warp of the light emitting chip C caused by the stress is reduced as compared with the case where the pedestal 91 is not provided. To do.

  As shown in FIG. 15, the pedestal 91 and the lens 92 may not be formed separately. In FIG. 7C, the dot pattern 96 is not provided in the portion of the photomask 95 corresponding to the opening 92a. However, by providing the dot pattern 96 so that a predetermined amount of transmitted light can be obtained, the development can be performed after development. A photosensitive material 94 having a predetermined thickness may remain in the opening 92a. Here, the portion remaining in the opening 92 a may be considered as the pedestal 91. At this time, the base 91 and the lens 92 are made of the same material.

  As described above, by providing the light emitting thyristor L with the lens 92 having the opening 92a, the amount of light irradiated on the photosensitive drum 12 is increased as compared with the case where the opening 92a is not provided. That is, the extraction efficiency of light emitted from the light emitting surface 311 of the light emitting thyristor L is improved.

In the first and second embodiments, the thyristor (transfer thyristor T, light-emitting thyristor L) has been described as an anode common in which the anode terminal is connected to the substrate 80. The thyristor (transfer thyristor T, light-emitting thyristor L) may be a cathode common whose cathode terminal is connected to the substrate 80 by changing the polarity of the circuit.
Further, although the n-type ohmic electrode 321 is provided at the center of the light emitting surface 311 of the light emitting thyristor L, the n-type ohmic electrode 321 may be provided at a position shifted from the center of the light emitting surface 311. .
Further, the n-type ohmic electrode 321 may not be provided.

Further, in the first embodiment and the second embodiment, the self-scanning light-emitting element array (SLED) including the light-emitting thyristor L and the transfer thyristor T has been described, but the self-scanning light-emitting element array ( SLED) may include other members such as a control thyristor, a diode, and a resistor in addition to the light emitting thyristor L and the transfer thyristor T.
In the first embodiment and the second embodiment, the transfer thyristor T is connected by the coupling diode Dx. However, a member that can transmit a change in potential such as a resistance may be used.

  In the first embodiment and the second embodiment, the light emitting element is the light emitting thyristor L. The light emitting element is a light emitting diode (LED) in which a p-type semiconductor layer and an n-type semiconductor layer are stacked. ).

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 10 ... Image forming process part, 11 ... Image forming unit, 12 ... Photosensitive drum, 14 ... Print head, 30 ... Image output control part, 40 ... Image processing part, 62 ... Circuit board, 63 ... Light source unit, 64 ... rod lens array, 65 ... light emitting device, 71 ... power supply line, 72 ... first transfer signal line, 73 ... second transfer signal line, 75 ... lighting signal line, 75a ... trunk, 75b ... branch, 91: pedestal, 92, 93 ... lens, 92a ... opening, 92b ... curved surface, 92c, 93b ... curved surface, 92d ... inner surface, 92e ... outer surface, 94, 94a, 94b ... photosensitive material, 110 ... signal generation Circuit 120, transfer signal generator 140, lighting signal generator 160, reference potential supply unit 170, power supply potential supply unit, φ 1, first transfer signal, φ 2, second transfer signal, φI (φI 1 to φI 40) ... Lighting signal , C (C1 to C40): light emitting chip, L: light emitting thyristor, T: transfer thyristor, Dx: coupling diode, Vga: power supply potential, Vsub: reference potential

Claims (7)

A plurality of light emitting elements arranged in a row on a substrate;
Each of the plurality of light emitting elements is provided to face a light emitting surface that emits light of each light emitting element, and is opened in a cylindrical shape in a direction intersecting with the light emitting surface, and around the opening Light that is disposed on the light emitting element and has a curved surface portion that has a convex surface and approaches the light emitting surface as the distance from the opening in the direction along the light emitting surface increases. And a plurality of lenses that collect light.   The light emitting surface of each light emitting element of the plurality of light emitting elements has a shape in which a lens corresponding to the light emitting element in the plurality of lenses does not have the opening but extends a convex surface to the opening. The light-emitting component according to claim 1, wherein the light-emitting component is provided closer to the principal point side of the lens than the position of the focal point.   The opening of each lens of the plurality of lenses is provided to face a portion of the light emitting element corresponding to the lens in the plurality of light emitting elements where the light emission intensity of the light emitting surface is high. The light emitting component according to claim 1 or 2.   2. A pedestal that transmits light emitted from the light emitting element is provided between each of the plurality of lenses and a light emitting element corresponding to the lens in the plurality of light emitting elements. 4. The light-emitting component according to any one of items 3 to 3.   5. The light-emitting component according to claim 1, wherein the plurality of light-emitting elements are a plurality of light-emitting thyristors included in a self-scanning light-emitting element array. A plurality of light emitting elements arranged in a row on the substrate and a light emitting surface that emits light of each light emitting element of the plurality of light emitting elements, respectively, are provided in a cylindrical shape in a direction intersecting the light emitting surface A surface that is disposed on the light-emitting element around the opening, and approaches the light-emitting surface as it moves away from the opening in a direction along the light-emitting surface, and has a convex surface A light emitting means comprising a plurality of lenses for condensing the light emitted from the light emitting element,
And a print head including an optical unit that forms an image of light emitted from the light emitting unit. An image carrier,
Charging means for charging the image carrier;
A plurality of light emitting elements arranged in a row on the substrate and a light emitting surface that emits light of each light emitting element of the plurality of light emitting elements, respectively, are provided in a cylindrical shape in a direction intersecting the light emitting surface A surface that is disposed on the light-emitting element around the opening, and approaches the light-emitting surface as it moves away from the opening in a direction along the light-emitting surface, and has a convex surface An exposure unit that exposes the image carrier through an optical unit, and a plurality of lenses that collect light emitted from the light emitting element.
Developing means for developing the electrostatic latent image exposed by the exposure means and formed on the image carrier;
An image forming apparatus comprising transfer means for transferring an image developed on the image holding member to a transfer target.

Images