JP6011296B2 - Light emitting component, print head, and image forming apparatus - Google Patents

Description

  The present invention relates to a light emitting component, a print head, an image forming apparatus, and a method for manufacturing the light emitting component.

  As a prior art described in the publication, an edge-emitting light-emitting diode having a laminated structure including at least a light-emitting layer of a light-emitting diode and an electrode for causing the light-emitting layer to emit light and providing light output from a laminated end face is provided at an interval. In the semiconductor light emitting device constituted by the edge emitting light emitting diode array formed by separating each layer electrically and spatially by a plurality of separation grooves, the wiring of each edge emitting light emitting diode constituting the edge emitting light emitting diode array There is a semiconductor light emitting device having a shape in which at least one surface having an angle of more than 90 degrees with the substrate surface exists on the end surface in the drawing direction (see Patent Document 1).

  As a prior art described in another publication, a first compound semiconductor layer of a first conductivity type that emits light from a surface, and a first compound semiconductor layer formed on the first compound semiconductor layer and the first compound semiconductor layer A second compound semiconductor layer of a second conductivity type having an end portion that generates a stepped portion therebetween, and at least one protruding portion protruding from the end portion is formed at the end portion, The projecting portion includes a first side portion having a surface that is connected to the end portion and inclined in the forward direction, a second side portion that is connected to the end portion and has a surface inclined in the forward direction, There is a surface light emitting device having a first side portion and a third side portion connected to the second side portion and having a surface inclined in a direction opposite to the forward direction (see Patent Document 2).

JP-A-7-193277 JP 2011-204771 A

  An object of this invention is to provide the light emitting component etc. which arrange | positioned the light emitting element at high density, suppressing the disconnection of wiring.

According to the first aspect of the present invention, a substrate and a plurality of semiconductor layers having different conductivity types are stacked on the substrate, and a light emitting element and a driving element provided corresponding to the light emitting element and driving the light emitting element, respectively. preparative a plurality of islands provided is provided on the substrate, wherein a plurality of connected with each of the light emitting element of the island lighting signal line for supplying a current for lighting each of the plurality of islands A driving signal line for driving the driving element, and each of the plurality of islands includes a first side surface and a second side surface having a smaller inclination angle than the first side surface, and the lighting signal line The drive signal line is a light emitting component provided so as to intersect with the second side surface.
According to a second aspect of the present invention, in the island provided with the light emitting element, a side surface adjacent to a light emitting surface that emits light is configured by the first side surface. It is a light emitting component as described in above.
According to a third aspect of the present invention, a substrate and a plurality of semiconductor layers having different conductivity types are stacked on the substrate, and a light emitting element and a drive element that drives the light emitting element are provided corresponding to the light emitting element respectively. preparative a plurality of islands provided is provided on the substrate, and the lighting signal line for supplying a current for lighting each of the light-emitting element of the plurality of islands, each of the driving of the plurality of islands and a drive signal line for driving the element, each of the plurality of islands, and a smaller second side inclination angle than the first side surface and the first side surface, the light-up signal line and the drive The signal line is a print head including light emitting means provided so as to intersect with the second side surface and optical means for imaging light emitted from the light emitting means.
According to a fourth aspect of the present invention, an image carrier, a charging unit for charging the image carrier, a substrate, and a plurality of semiconductor layers having different conductivity types are stacked on the substrate, and a light emitting element and A plurality of islands provided corresponding to the light-emitting elements and driving elements for driving the light-emitting elements, and a current for lighting on the light-emitting elements of the plurality of islands provided on the substrate. A lighting signal line to be supplied and a drive signal line for driving the drive element of each of the plurality of islands, each of the plurality of islands having an inclination angle from the first side surface and the first side surface. The lighting signal line and the drive signal line are provided with light-emitting means provided so as to intersect the second side face, and are charged by the charging means via optical means. Exposure means for exposing the image carrier; and An image forming apparatus comprising: a developing unit that develops an electrostatic latent image that is exposed by a light unit and formed on the image carrier; and a transfer unit that transfers an image developed on the image carrier to a transfer target. is there.

According to invention of Claim 1, compared with the case where the 2nd side is not provided, a light emitting element can be arrange | positioned with high density, suppressing the disconnection of wiring.
According to the second aspect of the present invention, the area of the light emitting surface of the light emitting element can be increased as compared with the case where this configuration is not provided.
According to the third aspect of the present invention, the print head can be made with higher definition than when the present configuration is not provided.
According to the fourth aspect of the present invention, a higher definition image can be formed in image formation than in the case where this configuration is not provided.

1 is a diagram illustrating an example of an overall configuration of an image forming apparatus to which a first exemplary embodiment is applied. It is sectional drawing which showed the structure of the print head. It is a top view of a light-emitting device. It is the figure which showed the structure of the light emitting chip, the structure of the signal generation circuit of a light-emitting device, and the wiring structure on a circuit board. It is an equivalent circuit diagram explaining the circuit configuration of a light emitting chip on which a self-scanning light emitting element array (SLED) is mounted. It is an example of the planar layout figure and sectional drawing of the light emitting chip in 1st Embodiment. 6 is a timing chart for explaining operations of the light emitting device and the light emitting chip. FIG. 7 is a diagram showing an example of a mask pattern for forming the first island and the second island of FIG. 6 in the photomask for forming islands in the first embodiment. It is a figure explaining the manufacturing method of a light emitting chip. It is an example of the planar layout figure and sectional drawing of the light emitting chip in 2nd Embodiment.

In an image forming apparatus such as a printer, copier, or facsimile that employs an electrophotographic system, an electrostatic latent image is obtained by irradiating image information onto a charged photosensitive member by an optical recording means, and then the static image is obtained. An image is formed by adding toner to the electrostatic latent image to make it visible, and transferring and fixing it on a recording sheet. In addition to the optical scanning method in which a laser is used as the optical recording means and the exposure is performed by scanning the laser beam in the main scanning direction, in recent years, a light emitting diode (LED: Light) as a light emitting element in response to a request for downsizing of the apparatus. 2. Description of the Related Art A recording apparatus using an LED print head (LPH: LED Print Head) in which a plurality of light emitting elements such as Emitting Diodes are arranged in the main scanning direction to form a light emitting element array is employed.
In such a light-emitting element array, it is required to arrange the light-emitting elements at high density as the image to be formed becomes higher in definition.
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

[First Embodiment]
(Image forming apparatus 1)
FIG. 1 is a diagram illustrating an example of an overall configuration of an image forming apparatus 1 to which the first exemplary embodiment is applied. An image forming apparatus 1 shown in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process unit 10 that forms an image corresponding to image data of each color, an image output control unit 30 that controls the image forming process unit 10, such as a personal computer (PC) 2 or an image reading device. 3 and an image processing unit 40 that performs predetermined image processing on image data received from these.

The image forming process unit 10 includes four image forming units 11Y, 11M, 11C, and 11K that are arranged in parallel at predetermined intervals. The image forming units 11Y, 11M, 11C, and 11K have predetermined surfaces of the photosensitive drum 12 and the photosensitive drum 12 as an example of an image holding body that forms an electrostatic latent image and holds a toner image, respectively. An example of a charging unit 13 as an example of a charging unit that charges at a potential, a print head 14 that exposes a photosensitive drum 12 charged by the charging unit 13, and an example of a developing unit that develops an electrostatic latent image obtained by the print head 14 The developing device 15 is provided. The image forming units 11Y, 11M, 11C, and 11K respectively form yellow (Y), magenta (M), cyan (C), and black (K) toner images. Note that when the image forming units 11Y, 11M, 11C, and 11K are not distinguished from each other, they are referred to as image forming units 11.
Further, the image forming process unit 10 performs multiple transfer of the toner images of each color formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K onto a recording sheet 25 as an example of a transfer target. In addition, a sheet conveying belt 21 that conveys the recording sheet 25, a drive roll 22 that drives the sheet conveying belt 21, and a transfer roll 23 as an example of a transfer unit that transfers the toner image on the photosensitive drum 12 to the recording sheet 25. And a fixing device 24 for fixing the toner image on the recording paper 25.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the image output control unit 30. The image data received from the personal computer (PC) 2 or the image reading device 3 under the control of the image output control unit 30 is subjected to image processing by the image processing unit 40 and supplied to the image forming unit 11. The For example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged in a predetermined potential by the charger 13 while rotating in the direction of arrow A, and the image supplied from the image processing unit 40 is supplied. Exposure is performed by a print head 14 as an example of an exposure unit that emits light based on data. As a result, an electrostatic latent image related to a black (K) color image is formed on the photosensitive drum 12. The electrostatic latent image formed on the photosensitive drum 12 is developed by the developing device 15, and a black (K) toner image is formed on the photosensitive drum 12. In the image forming units 11Y, 11M, and 11C, yellow (Y), magenta (M), and cyan (C) color toner images are formed, respectively.

Each color toner image on the photosensitive drum 12 formed by each image forming unit 11 is applied to the transfer roll 23 on the recording paper 25 supplied with the movement of the paper conveying belt 21 moving in the direction of arrow B. The toner images are sequentially electrostatically transferred by the transfer electric field, and a composite toner image is formed on the recording paper 25 in which the toners of the respective colors are superimposed.
Thereafter, the recording paper 25 on which the composite toner image has been electrostatically transferred is conveyed to the fixing device 24. The synthesized toner image on the recording paper 25 conveyed to the fixing device 24 is fixed on the recording paper 25 by the fixing processing by heat and pressure by the fixing device 24, and is discharged from the image forming apparatus 1.

(Print head 14)
FIG. 2 is a cross-sectional view showing an example of the configuration of the print head 14. The print head 14 is an example of a light emitting unit including a light source unit 63 including a housing 61 and a plurality of light emitting elements that expose the photosensitive drum 12 (light emitting thyristors as examples of the light emitting elements in the first embodiment). The light emitting device 65 and the rod lens array 64 as an example of optical means for imaging the light emitted from the light source unit 63 on the surface of the photosensitive drum 12 are provided.
In addition to the light source unit 63 described above, the light emitting device 65 includes a circuit board 62 on which a signal generation circuit 110 (see FIG. 3 described later) that drives the light source unit 63 is mounted.

  The housing 61 is made of, for example, metal, supports the circuit board 62 and the rod lens array 64, and is set so that the light emitting surface of the light emitting element in the light source unit 63 becomes the focal plane of the rod lens array 64. Further, the rod lens array 64 is arranged along the axial direction of the photosensitive drum 12 (the main scanning direction and the X direction in FIGS. 3 and 4B described later).

(Light emitting device 65)
FIG. 3 is a top view of the light emitting device 65.
In the light emitting device 65 shown as an example in FIG. 3, the light source unit 63 staggers light emitting chips C <b> 1 to C <b> 40 as examples of 40 light emitting components on the circuit board 62 in two rows in the X direction that is the main scanning direction. It is arranged and arranged. Details of the arrangement of the light emitting chips C1 to C40 will be described later.
In the present specification, “to” indicates a plurality of constituent elements each distinguished by a number, and includes those described before and after “to” and those between them. For example, the light emitting chips C1 to C40 include the light emitting chip C1 to the light emitting chip C40 in numerical order.

Each structure of the light emitting chips C1 to C40 may be the same. Therefore, when the light emitting chips C1 to C40 are not distinguished from each other, they are referred to as light emitting chips C.
In the first embodiment, a total of 40 light emitting chips C are used, but the present invention is not limited to this.

  The light emitting device 65 includes a signal generation circuit 110 that drives the light source unit 63. The signal generation circuit 110 is configured by, for example, an integrated circuit (IC). Note that the light emitting device 65 may not include the signal generation circuit 110. At this time, the signal generation circuit 110 is provided outside the light emitting device 65 and supplies a control signal or the like for controlling the light emitting chips C1 to C40 to the light emitting device 65 via a cable or the like. Here, it is assumed that the light emitting device 65 includes the signal generation circuit 110.

  FIG. 4 is a diagram showing the configuration of the light emitting chip C, the configuration of the signal generation circuit 110 of the light emitting device 65, and the configuration of wiring (lines) on the circuit board 62. 4A shows the configuration of the light-emitting chip C, and FIG. 4B shows the configuration of the signal generation circuit 110 of the light-emitting device 65 and the configuration of wiring (lines) on the circuit board 62.

First, the configuration of the light-emitting chip C shown in FIG.
The light-emitting chip C has a plurality of light-emitting elements arranged in a row along the long side (in the x direction of FIG. 4A) on the substrate 80 having a rectangular surface shape on the side close to one long side of the rectangle. (In the first embodiment, a light emitting unit 102 including light emitting thyristors L1, L2, L3,...) Is provided. Further, the light-emitting chip C includes a plurality of terminals (φ1 terminal, φ2 terminal, φI terminal, Vga terminal) for capturing various control signals and the like at both ends in the long side direction.
These terminals are provided in order of the φ1 terminal and the Vga terminal from one end of the substrate 80, and are provided in the order of the φI terminal and the φ2 terminal from the other end of the substrate 80. The light emitting unit 102 is provided between the Vga terminal and the φ2 terminal. Further, a back electrode 85 (see FIG. 6 described later) is provided on the back surface of the substrate 80 as a Vsub terminal.
Terminals (φ1 terminal, φ2 terminal, φI terminal, Vga terminal) are bonding pads, and are connected to wirings (lines) on the circuit board 62 via bonding wires.
Note that the terminals (φ1 terminal, φ2 terminal, φI terminal, Vga terminal) do not have to be arranged as shown in FIG. 4A, and the order may be different.

  Here, the “row” is not limited to the case where a plurality of light emitting elements are arranged in a straight line in the x direction as shown in FIG. In this case, they may be arranged with different amounts of displacement with respect to the y direction orthogonal to the column direction. For example, when a light emitting surface 311 (see FIG. 6 described later) of the light emitting element is used as a pixel, each light emitting element is displaced by several pixels or several tens of pixels in the y direction orthogonal to the column direction x direction. May be arranged. Moreover, you may arrange | position zigzag alternately between adjacent light emitting elements or for every several light emitting element.

Next, the configuration of the signal generation circuit 110 of the light emitting device 65 and the configuration of the wiring (line) on the circuit board 62 will be described with reference to FIG.
As described above, the signal generating circuit 110 and the light emitting chips C1 to C40 are mounted on the circuit board 62 of the light emitting device 65, and wirings (lines) for connecting the signal generating circuit 110 and the light emitting chips C1 to C40 are provided. ing.

First, the configuration of the signal generation circuit 110 will be described.
Image signal processed image data and various control signals are input to the signal generation circuit 110 from the image output control unit 30 and the image processing unit 40 shown in FIG. Based on these image data and various control signals, the signal generation circuit 110 rearranges the image data and corrects the light amount.
The signal generation circuit 110 includes a transfer signal generation unit 120 that transmits the first transfer signal φ1 and the second transfer signal φ2 to the light emitting chips C1 to C40 based on various control signals.
In addition, the signal generation circuit 110 includes a lighting signal generation unit 140 that transmits the lighting signals φI1 to φI40 to the light emitting chips C1 to C40 based on various control signals. When the lighting signals φI1 to φI40 are not distinguished from each other, they are expressed as a lighting signal φI.
Furthermore, the signal generation circuit 110 supplies a reference potential supply unit 160 that supplies a reference potential Vsub that serves as a potential reference to the light emitting chips C1 to C40, and a power supply potential that supplies a power supply potential Vga for driving the light emitting chips C1 to C40. A supply unit 170 is provided.

Next, the arrangement of the light emitting chips C1 to C40 will be described.
The odd-numbered light emitting chips C1, C3, C5,... Are arranged in a line at intervals in the long side direction of each substrate 80. The even-numbered light emitting chips C2, C4, C6,... Are similarly arranged. The odd-numbered light emitting chips C1, C3, C5,... And the even-numbered light emitting chips C2, C4, C6,... Rotate 180 ° so that the long sides of the light emitting chip C on the light emitting unit 102 side face each other. It is arranged in a staggered state. The positions of the light emitting chips C are set so that the light emitting elements are also arranged between the light emitting chips C at intervals of the light emitting elements in the light emitting chip C in the main scanning direction (X direction).
In addition, in FIG.4 (b), the light emitting chips C1-C9 are shown. Then, the direction of the arrangement of the light emitting elements of the light emitting unit 102 shown by arrows in the light emitting chips C1 to C9 (in the first embodiment, in the order of the numbers of the light emitting thyristors L1, L2, L3,...). Is shown.

A wiring (line) connecting the signal generation circuit 110 and the light emitting chips C1 to C40 will be described.
The circuit board 62 is provided with a power supply line 200a for supplying a reference potential Vsub. The power supply line 200a is connected to a Vsub terminal provided on a back electrode 85 (see FIG. 6 described later) which is a Vsub terminal provided on the back surface of the substrate 80 of the light emitting chip C.
The circuit board 62 is provided with a power supply line 200b for supplying a power supply potential Vga for driving the light emitting chip C. The power supply line 200b is connected to a Vga terminal provided on the light emitting chip C.

  On the circuit board 62, the first transfer signal line 201 for transmitting the first transfer signal φ1 to the light emitting chip C and the second transfer signal for transmitting the second transfer signal φ2 from the transfer signal generator 120 of the signal generation circuit 110. A signal line 202 is provided. The first transfer signal line 201 is connected to the φ1 terminal of the light emitting chip C, and the second transfer signal line 202 is connected to the φ2 terminal of the light emitting chip C. The first transfer signal φ1 and the second transfer signal φ2 are transmitted in common (in parallel) to the light emitting chips C1 to C40.

  The circuit board 62 is also provided with lighting signal lines 204-1 to 204-40 for transmitting the lighting signals φI1 to φI40 from the lighting signal generator 140 of the signal generation circuit 110 to the light emitting chips C1 to C40, respectively. It has been. The lighting signal lines 204-1 to 204-40 are connected to the respective φI terminals of the light emitting chips C1 to C40 through current limiting resistors RI.

As described above, the reference potential Vsub and the power supply potential Vga are commonly supplied to the light emitting chips C1 to C40 on the circuit board 62. The first transfer signal φ1 and the second transfer signal φ2 are also transmitted in common (in parallel) to the light emitting chips C1 to C40. On the other hand, the lighting signals φI1 to φI40 are individually transmitted to the light emitting chips C1 to C40, respectively.
When the light emitting device 65 does not include the signal generation circuit 110, the power supply lines 200a and 200b, the first transfer signal line 201, the second transfer signal line 202, and the lighting signal lines 204-1 to 204-40 are Instead of the signal generation circuit 110, it is connected to a connector or the like provided on the light emitting device 65. And it connects to the signal generation circuit 110 provided outside via the cable connected to this connector etc.

(Configuration of Light-Emitting Chip C)
FIG. 5 is an equivalent circuit diagram illustrating a circuit configuration of the light-emitting chip C on which the self-scanning light-emitting element array (SLED) is mounted. Each element described below is arranged based on a layout (see FIG. 6 described later) on the light emitting chip C except for terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal). Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for convenience of explanation. The Vsub terminal provided on the back surface of the substrate 80 is drawn out of the substrate 80.
Here, in order to describe the connection relationship with the signal generation circuit 110, the light-emitting chip C will be described by taking the light-emitting chip C1 as an example. Therefore, in FIG. 5, the light-emitting chip C is expressed as a light-emitting chip C <b> 1 (C). The configuration of the other light emitting chips C2 to C40 is the same as that of the light emitting chip C1.

The light emitting chip C1 (C) includes the light emitting unit 102 (see FIG. 4A) configured by the light emitting thyristors L1, L2, L3,... Arranged in a row on the substrate 80 as described above. .
The light emitting chip C1 (C) includes transfer thyristors T1, T2, T3,... Arranged in a row like the light emitting unit 102.
In FIG. 5, in the light-emitting chip C1 (C), the portions centering on the light-emitting thyristors L1 to L4 and the transfer thyristors T1 to T4 are shown.

Further, the light emitting chip C1 (C) includes two pairs of transfer thyristors T1, T2, T3,... In the order of numbers and coupling diodes Dx1, Dx2, Dx3,.
Further, the light emitting chip C1 (C) includes power line resistances Rgx1, Rgx2, Rgx3,.

  The light emitting chip C1 (C) includes one start diode Dx0. In order to prevent an excessive current from flowing in a first transfer signal line 72 to which a first transfer signal φ1 to be described later is transmitted and a second transfer signal line 73 to which a second transfer signal φ2 is transmitted, Limiting resistors R1 and R2 are provided.

The light-emitting thyristors L1, L2, L3,..., The transfer thyristors T1, T2, T3,. Further, the coupling diodes Dx1, Dx2, Dx3,..., The power line resistances Rgx1, Rgx2, Rgx3,.
The light emitting thyristors L1, L2, L3,..., The transfer thyristors T1, T2, T3,... Are in order of the transfer thyristors T1, T2, T3,. Are lined up.

  Here, the light emitting thyristors L1, L2, L3,..., The transfer thyristors T1, T2, T3,..., The coupling diodes Dx1, Dx2, Dx3,..., The power line resistances Rgx1, Rgx2, Rgx3,. The light-emitting thyristor L, the transfer thyristor T, the coupling diode Dx, and the power supply line resistance Rgx are represented.

The number of light-emitting thyristors L may be a predetermined number. In the first embodiment, the number of light emitting thyristors L is, for example, 128. Then, the number of transfer thyristors T is also 128. Similarly, the number of power line resistances Rgx is 128. However, the number of coupling diodes Dx is 127, which is one less than the number of transfer thyristors T.
The number of transfer thyristors T may be larger than the number of light emitting thyristors L.

  The thyristor (light-emitting thyristor L, transfer thyristor T) is a semiconductor element having three terminals: a gate terminal, an anode terminal, and a cathode terminal.

The anode terminals of the transfer thyristor T and the light emitting thyristor L are connected to the substrate 80 of the light emitting chip C1 (C) (anode common).
These anode terminals are connected to a power supply line 200a (see FIG. 4B) via a back electrode 85 (see FIG. 6 described later) which is a Vsub terminal provided on the back surface of the substrate 80. The power supply line 200a is supplied with the reference potential Vsub from the reference potential supply unit 160.

Along with the arrangement of the transfer thyristors T, the cathode terminals of the odd-numbered (odd-numbered) transfer thyristors T1, T3,... Are connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via the current limiting resistor R1. The φ1 terminal receives the first transfer signal φ1.
On the other hand, the cathode terminals of the even-numbered (even-numbered) transfer thyristors T2, T4,... Are connected to the second transfer signal line 73 along the arrangement of the transfer thyristors T. The second transfer signal line 73 is connected to the φ2 terminal via the current limiting resistor R2. The φ2 terminal receives the second transfer signal φ2.

  The cathode terminals of the light emitting thyristors L 1, L 2, L 3,... Are connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal. The φI terminal of the light emitting chip C1 is connected to the lighting signal line 204-1 via the current limiting resistor RI and receives the lighting signal φI1 from the lighting signal generator 140. Note that the lighting signal lines 204-2 to 204-40 are connected to the φI terminals of the other light emitting chips C2 to C40 via current limiting resistors RI, respectively, and receive the lighting signals φI2 to φI40 from the lighting signal generator 140. .

  The gate terminals Gt1, Gt2, Gt3,... Of the transfer thyristors T1, T2, T3,... Have a one-to-one correspondence with the gate terminals Gl1, Gl2, Gl3,... Of the light emitting thyristors L1, L2, L3,. Connected with. Therefore, the gate terminals Gt1, Gt2, Gt3,... And the gate terminals Gl1, Gl2, Gl3,. Thus, for example, the gate terminal Gt1 (Gl1) may be described.

  Here, the gate terminals Gt1, Gt2, Gt3,..., And the gate terminals Gl1, Gl2, Gl3,. And, it may be expressed as a gate terminal Gt (Gl).

  Coupling diodes Dx1, Dx2, Dx3,... Are connected between the gate terminals Gt, each of which is a pair of gate terminals Gt1, Gt2, Gt3,... Of transfer thyristors T1, T2, T3,. Yes. That is, the coupling diodes Dx1, Dx2, Dx3,... Are connected in series so as to be sandwiched between the gate terminals Gt1, Gt2, Gt3,. The direction of the coupling diode Dx1 is connected in a direction in which a current flows from the gate terminal Gt1 toward the gate terminal Gt2. The same applies to the other coupling diodes Dx2, Dx3, Dx4,.

  The gate terminal Gt (Gl) of the transfer thyristor T is connected to the power supply line 71 via the power supply line resistance Rgx provided corresponding to each of the transfer thyristors T. The power supply line 71 is connected to the Vga terminal.

  The gate terminal Gt1 of the transfer thyristor T1 on one end side of the transfer thyristor array is connected to the cathode terminal of the start diode Dx0. On the other hand, the anode terminal of the start diode Dx 0 is connected to the second transfer signal line 73.

  In FIG. 5, a portion including the transfer thyristor T, the coupling diode Dx, the power supply line resistance Rgx, the start diode Dx0, and the current limiting resistors R1 and R2 of the light emitting chip C1 (C) is referred to as a transfer unit 101. As described above, the portion including the light emitting thyristor L corresponds to the light emitting unit 102.

FIG. 6 is an example of a plan layout view and a cross-sectional view of the light-emitting chip C in the first embodiment. Here, since the connection relationship between the light-emitting chip C and the signal generation circuit 110 is not shown, it is not necessary to use the light-emitting chip C1 as an example. Therefore, it is expressed as a light emitting chip C.
FIG. 6A is a plan layout diagram of the light emitting chip C, and shows a portion centering on the light emitting thyristors L1 to L4 and the transfer thyristors T1 to T4. Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for convenience of explanation. The Vsub terminal provided on the back surface of the substrate 80 is drawn out of the substrate 80. If terminals are provided corresponding to FIG. 4A, the φ2 terminal, the φI terminal, and the current limiting resistor R2 are provided at the right end portion of the substrate 80 in FIG. 6A. The start diode Dx0 may be provided at the right end portion of the substrate 80.
FIG. 6B is a cross-sectional view taken along line VIB-VIB shown in FIG. Therefore, in the cross-sectional view of FIG. 6B, a cross section of the light emitting thyristor L1, the transfer thyristor T1, the coupling diode Dx1, and the power supply line resistance Rgx1 is shown from the bottom in the figure. In addition, in FIG. 6A and FIG. 6B, main elements and terminals are indicated by names.

As shown in FIG. 6B, the light-emitting chip C includes a p-type first semiconductor layer 81, a n-type second semiconductor layer 82, and a p-type on a p-type substrate 80. The third semiconductor layer 83 and the n-type fourth semiconductor layer 84 are sequentially stacked, and at least the n-type second semiconductor layer 82, the p-type third semiconductor layer 83, and the n-type fourth semiconductor layer 84 are separated from each other. It is composed of a plurality of islands (islands) (first island 301 to fifth island 305, which will be described later) separated by grooves.
The p-type first semiconductor layer 81 may or may not be separated. In FIG. 6B, a part of the p-type first semiconductor layer 81 is removed in the thickness direction. The p-type first semiconductor layer 81 may also serve as the substrate 80.

  Note that, in some islands of the plurality of islands, the n-type fourth semiconductor layer 84 is partially removed (for example, a first island 301 described later). In other islands of the plurality of islands, the n-type fourth semiconductor layer 84 is removed (for example, a second island 302 described later).

  Further, the light-emitting chip C includes a p-type ohmic electrode (such as a p-type ohmic electrode 331 described later) that is ohmically connected to the p-type third semiconductor layer 83 and a pn-type ohmic electrode that is ohmically connected to the n-type fourth semiconductor layer 84. (Such as an n-type ohmic electrode 321 described later). Note that an example of a material that is ohmic-connected to the p-type third semiconductor layer 83 is gold (Au) containing zinc (Zn) (hereinafter referred to as AuZn), and the n-type fourth semiconductor layer 84 is ohmic-contacted. An example of the material to be connected is gold (Au) containing germanium (Ge) (hereinafter referred to as AuGe).

  Then, as shown in FIG. 6B, the light emitting chip C is provided with an insulating layer 86 so as to cover the surface and side surfaces of these islands. These islands and wiring such as the power supply line 71, the first transfer signal line 72, the second transfer signal line 73, and the lighting signal line 75 are formed through holes (in FIG. 6A). It is connected via). In the following description, descriptions of the insulating layer 86 and the through hole are omitted.

First, the configuration of the first island 301 to the fifth island 305 will be described with reference to FIGS.
The first island 301 has a rectangular surface shape, and is provided with a light emitting thyristor L1, a transfer thyristor T1, and a coupling diode Dx1.
The light emitting thyristor L1 includes a p-type first semiconductor layer 81 provided on a p-type substrate 80 as an anode terminal, an n-type ohmic electrode 321 provided on an n-type fourth semiconductor layer 84 as a cathode terminal, n The p-type ohmic electrode 331 provided on the p-type third semiconductor layer 83 exposed by removing the fourth type semiconductor layer 84 is defined as a gate terminal Gl1 (Gt1 (Gl1) in FIG. 6A). .

The light emitting thyristor L emits light mainly at the interface between the n-type second semiconductor layer 82 and the p-type third semiconductor layer 83. Here, in order to extract light from the n-type fourth semiconductor layer 84 serving as a cathode, the surface of the n-type fourth semiconductor layer 84 of the light-emitting thyristor L is referred to as a light emitting surface 311.
The planar shape of the light emitting surface 311 is assumed to be a square, and the n-type ohmic electrode 321 is provided at the center of the light emitting surface 311.

The transfer thyristor T1 has a p-type first semiconductor layer 81 provided on a p-type substrate 80 as an anode terminal and a n-type ohmic electrode 322 provided on a region 312 of the n-type fourth semiconductor layer 84 as a cathode. The p-type ohmic electrode 331 provided on the p-type third semiconductor layer 83 exposed by removing the terminal and the n-type fourth semiconductor layer 84 is connected to the gate terminal Gt1 (Gt1 (Gl1) in FIG. 6A). ).
Similarly, the coupling diode Dx1 includes an n-type ohmic electrode 323 provided on the region 313 of the n-type fourth semiconductor layer 84 as a cathode terminal and a p-type ohmic electrode provided on the p-type third semiconductor layer 83. 331 is an anode terminal. The p-type ohmic electrode 331 is the anode terminal of the coupling diode Dx1, the gate terminal Gt1 of the transfer thyristor T1, and the gate terminal Gl1 of the light emitting thyristor L1.

  The second island 302 has a rectangular surface shape and is provided with a power supply line resistance Rgx1. The power supply line resistance Rgx1 is formed between the p-type ohmic electrode 332 and the p-type ohmic electrode 333 provided on the p-type third semiconductor layer 83 exposed by removing the n-type fourth semiconductor layer 84. The third semiconductor layer 83 of the type is used as a resistor.

  The third island 303 has a rectangular surface shape and is provided with a start diode Dx0. The start diode Dx0 is a p-type third electrode in which the n-type ohmic electrode 324 provided on the region 314 of the n-type fourth semiconductor layer 84 is exposed as a cathode terminal and the n-type fourth semiconductor layer 84 is removed. The p-type ohmic electrode 334 provided on the semiconductor layer 83 is used as an anode terminal.

  The fourth island 304 and the fifth island 305 are rectangular in shape like the second island 302. The fourth island 304 is provided with a current limiting resistor R1, and the fifth island 305 is provided with a current limiting resistor R2. It has been. Similarly to the power supply line resistance Rgx1 provided on the second island 302, each of the current limiting resistance R1 and the current limiting resistance R2 is a p-type third semiconductor layer 83 between two p-type ohmic electrodes (not shown). Is the resistance.

As shown in FIG. 6B, a back surface electrode 85 serving as a Vsub terminal is provided on the back surface of the substrate 80.
In the light emitting chip C, a plurality of islands similar to the first island 301 and the second island 302 are formed in parallel. These islands include light emitting thyristors L2, L3, L4,..., Transfer thyristors T2, T3, T4,..., Coupling diodes Dx2, Dx3, Dx4,..., Power line resistances Rgx2, Rgx3, Rgx4,. It is provided in the same manner as the first island 301 and the second island 302.

Next, with reference to FIG. 6A, the connection relationship between the elements provided on the first island 301 to the fifth island 305 will be described.
The lighting signal line 75 includes a trunk portion 75a and a plurality of branch portions 75b, and the trunk portion 75a is provided so as to extend in the x direction that is the column direction of the light emitting thyristors L. The branch portion 75 b branches from the trunk portion 75 a in the −y direction, and is connected to the n-type ohmic electrode 321 that is the cathode terminal of the light emitting thyristor L <b> 1 provided on the first island 301. The same applies to the cathode terminals of the other light-emitting thyristors L. The lighting signal line 75 is connected to the φI terminal.

The first transfer signal line 72 is connected to an n-type ohmic electrode 322 that is a cathode terminal of the transfer thyristor T1 provided on the first island 301. The cathode terminals of other odd-numbered transfer thyristors T provided on the same island as the first island 301 are also connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via a current limiting resistor R 1 provided on the fourth island 304.
On the other hand, the second transfer signal line 73 is connected to an n-type ohmic electrode (unsigned) that is a cathode terminal of an even-numbered transfer thyristor T provided on an island without a symbol. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2 provided on the fifth island 305.

  The power supply line 71 is connected to the p-type ohmic electrode 333 that is one terminal of the power supply line resistance Rgx1 provided on the second island 302. One terminal of the other power line resistor Rgx is also connected to the power line 71. The power supply line 71 is connected to the Vga terminal.

The p-type ohmic electrode 331 (gate terminal Gt1 (Gl1)) is connected to the p-type ohmic electrode 332 (the other terminal of the power supply line resistance Rgx1) provided on the second island 302 by a connection wiring 76.
The n-type ohmic electrode 323 (the cathode terminal of the coupling diode Dx1) provided on the first island 301 is connected to the p-type ohmic electrode (not indicated) which is the gate terminal Gt2 (Gl2) of the transfer thyristor T2 provided adjacently. They are connected by connection wiring 77.
Although not described here, the same applies to other light-emitting thyristors L, transfer thyristors T, coupling diodes Dx, and the like.

The p-type ohmic electrode 331 (gate terminal Gt1 (Gl1)) of the first island 301 is connected to the n-type ohmic electrode 324 (cathode terminal of the start diode Dx0) provided on the third island 303 by the connection wiring 78. . The p-type ohmic electrode 334 (the anode terminal of the start diode Dx0) is connected to the second transfer signal line 73.
In this way, the light emitting chip C is configured.

As described above, the power supply line 71, the first transfer signal line 72, the second transfer signal line 73, the lighting signal line 75, the connection wirings 76, 77, 78, and the like are provided so as to connect the islands. ing. In particular, the power supply line 71, the first transfer signal line 72, the second transfer signal line 73, the lighting signal line 75, and the like are light emitting chips along the longitudinal direction of the light emitting chip C (the x direction shown in FIG. 6A). It is connected from one end of C to the other end.
Note that the transfer thyristor T, the coupling diode Dx, the power supply line resistance Rgx, the start diode Dx0, and the current limiting resistances R1 and R2 are examples of driving elements, and include a power supply line 71, a first transfer signal line 72, and a second transfer signal line. 73, connection wirings 76, 77, and 78 are examples of drive signal lines.

Here, the cross-sectional structure of the island and the wiring will be described.
As described above, the island is formed on the p-type substrate 80 by the p-type first semiconductor layer 81, the n-type second semiconductor layer 82, the p-type third semiconductor layer 83, and the n-type fourth semiconductor layer. 84 is sequentially stacked, and at least the n-type second semiconductor layer 82, the p-type third semiconductor layer 83, and the n-type fourth semiconductor layer 84 are separated from each other. That is, a separation groove (trench) having a depth corresponding to the thickness of at least the n-type second semiconductor layer 82, the p-type third semiconductor layer 83, and the n-type fourth semiconductor layer 84 exists between the islands. To do. The depth of the separation groove is 2 μm, for example.
Therefore, the above wiring is provided from one island to the adjacent island via the bottom of the separation groove.

The wiring is formed by depositing a metal film such as aluminum or gold on the insulating layer 86 provided with a through hole by a technique such as vacuum vapor deposition or sputtering, and then processing by a technique such as photolithography and etching.
In techniques such as vacuum evaporation and sputtering, molten metal or metal particles that have jumped out of the target fly and deposit on the insulating layer 86. Here, the molten metal or the metal particles jumping out of the target do not fly from one direction but fly with an angular distribution set by an apparatus such as vacuum deposition or sputtering.

  Photolithography refers to a photoresist pattern (resist) by exposing a photoresist, which is a photosensitive organic material, applied to the surface of a material (substrate, film, etc.) to be processed with light having a short wavelength such as ultraviolet light. Pattern). Etching is a technique for removing a material not covered with a resist pattern with a liquid or a gas for removing the material. As a result, the material (substrate, film, etc.) is processed into a predetermined shape.

  By the way, in order to form a higher-definition image (higher definition), it is required to arrange the light emitting thyristors L more finely (smaller) and to arrange them at high density. The light quantity of the light emitting thyristor L is determined by the area of the light emitting surface 311. Therefore, in order not to reduce the amount of light, it is preferable to make the width of the separation groove between islands narrower (smaller) and increase the area of the light emitting surface 311.

However, when the width of the separation groove between the islands is reduced, the ratio of the depth to the width of the separation groove (aspect ratio) is increased. In particular, since the depth of the separation groove is as large as 2 μm, for example, the aspect ratio increases when the width of the separation groove is reduced.
When the aspect ratio of the separation groove is increased, metal particles are less likely to fly into the separation groove, particularly the side surface and bottom of the separation groove, and the thickness of the metal film is reduced or formed as a continuous film in the separation groove. Or not. As a result, the resistance of the wiring increases or the wire breaks, and the yield decreases. This is because metal particles flying from an oblique direction with respect to the separation groove are blocked by the side surface (side wall) of the island surrounding the separation groove in a technique such as vacuum deposition or sputtering, and it becomes difficult to reach the inside of the separation groove. (Shadow effect).

Therefore, the width of the wiring is widened to suppress an increase in wiring resistance by increasing the width, or to reduce the probability of disconnection.
However, when the width of the wiring is increased, the length of the light emitting chip C in the width direction of the wiring, that is, the width of the light emitting chip C (the length in the y direction shown in FIG. 6) increases. For this reason, the number of light emitting chips C per wafer decreases, and the cost of the light emitting chips C increases.

On the other hand, the side surface of the separation groove is tapered (inclined), that is, the cross section of the island is trapezoidal. When the side surface of the separation groove is tapered, metal particles flying from an oblique direction with respect to the separation groove are likely to reach the separation groove in a technique such as vacuum deposition or sputtering. As a result, an increase in wiring resistance is suppressed, and the probability of occurrence of disconnection is lowered and yield is improved.
However, if the side surface of the separation groove is tapered, the tapered portion cannot be used as an element. Therefore, the distance between the light emitting surface 311 and the end of the island (first island 301) is set in consideration of the tapered portion.
For this reason, if it is going to make the pitch which arrange | positions the light emitting thyristor L small for high definition, the area of the light emission surface 311 must be made small. Then, the light quantity of the light emitting thyristor L is reduced. On the other hand, if the area of the light emitting surface 311 is to be maintained, the pitch for arranging the light emitting thyristors L cannot be reduced, and high definition cannot be achieved.

  Therefore, in the first embodiment, the side surface is tapered (inclined) for the portion where the island wiring intersects, and the side surface is not tapered for the portion where the wiring does not intersect. The side surface that is not tapered is an example of the first side surface, and the tapered side surface is an example of the second side surface having a smaller inclination angle than the first side surface. Note that the tilt angle is the tilt of the side surface with respect to the surface of the substrate.

  For example, as shown in FIGS. 6A and 6B, the portion of the first island 301 where the transfer thyristor T1 and the coupling diode Dx1 are provided is tapered on the side surface 301b (FIG. 6B). As shown, the first transfer signal line 72, the second transfer signal line 73, and the connection wirings 76, 77, 78 intersect the inclination angle β). On the other hand, as for the portion where the light emitting thyristor L1 is provided (the portion adjacent to the light emitting surface 311), the wiring does not intersect, so the side surface 301a (inclination angle α as shown in FIG. 6B) is not tapered. Yes. The inclination angle β is smaller than the inclination angle α.

  The same applies to other islands (second island 302, third island 303, fourth island 304, fifth island 305, and islands without reference numerals). That is, the island portion where the wiring intersects has a tapered side surface, and the portion where the wiring does not intersect has a non-tapered side surface.

  In the light-emitting thyristor L, the light emission amount increases as the area of the light-emitting surface 311 increases. On the other hand, as will be described later, the transfer thyristor T and the coupling diode Dx need only be able to set the potential of the gate terminal Gl of the light-emitting thyristor L, and can have a smaller area than the light-emitting thyristor L (see FIG. 6A). Therefore, the area where the transfer thyristor T and the coupling diode Dx are formed in the first island 301 may be small.

By doing so, the distance between the light emitting surface 311 of the light emitting thyristor L and the end portion of the island (first island 301) can be reduced as compared with the case where the side surface of the island is tapered (inclined). It is possible to suppress the area of the light emitting surface 311 from being reduced.
Therefore, even if the pitch in which the light emitting thyristors L are arranged is reduced for high definition, the area of the light emitting surface 311 of the light emitting thyristor L is suppressed from being reduced, and the wiring resistance is reduced. An increase in the probability of increase and disconnection is suppressed.

Here, the taper shape is a straight line in which the side on the substrate side is longer than the side on the opposite side of the substrate and connects one end of the side on the substrate and the opposite end on the opposite side in the island cross section. Is inclined with respect to the substrate. At this time, the side surfaces may coincide with the straight line, and may be convex on either the inner side or the outer side. There may also be unevenness. The relationship between the other end of the side on the substrate side and the opposite end of the opposite side may be the same. In other words, any shape that prevents the metal particles forming the wiring from being deposited in the separation groove by the side surfaces of the islands is suppressed.
And not being tapered means that the inclination angle of the side surface is steeper (for example, α in FIG. 6B) than the tapered side surface (for example, β in FIG. 6B).
For example, when the depth of the separation groove is 2 μm and the width of the separation groove is 2 μm, the inclination angle β may be 70 ° or less.

(Operation of the light emitting device 65)
Next, the operation of the light emitting device 65 will be described.
As described above, the light emitting device 65 includes the light emitting chips C1 to C40 (see FIGS. 3 and 4).
As shown in FIG. 4, the reference potential Vsub and the power supply potential Vga are commonly supplied to all the light emitting chips C <b> 1 to C <b> 40 on the circuit board 62. Similarly, the first transfer signal φ1 and the second transfer signal φ2 are transmitted in common (in parallel) to the light emitting chips C1 to C40.
On the other hand, the lighting signals φI1 to φI40 are individually transmitted to the light emitting chips C1 to C40. The lighting signals φI1 to φI40 are signals for setting the light emitting thyristors L of the respective light emitting chips C1 to C40 to be lit or not lit based on the image data. Therefore, the waveforms of the lighting signals φI1 to φI40 are different depending on the image data. However, the lighting signals φI1 to φI40 are transmitted in parallel at the same timing.
Since the light emitting chips C1 to C40 are driven in parallel, it is sufficient to describe the operation of the light emitting chip C1.

<Thyristor>
Before describing the operation of the light emitting chip C1, the basic operation of the thyristor (transfer thyristor T, light emitting thyristor L) will be described. As described above, the thyristor is a semiconductor element having three terminals: an anode terminal, a cathode terminal, and a gate terminal.
Hereinafter, as an example, the reference potential Vsub supplied to the back electrode 85 (see FIGS. 5 and 6), which is the Vsub terminal, is set to a high level potential (hereinafter referred to as “H”) at 0 V and the Vga terminal. The power supply potential Vga supplied will be described as −3.3 V as a low level potential (hereinafter referred to as “L”).
In the first embodiment, the light emitting device 65 is driven with a negative potential.

Since the p-type first semiconductor layer 81 that is the anode terminal of the thyristor has the same potential as the p-type substrate 80, the anode terminal of the thyristor has the reference potential Vsub (“H” (0 V)) supplied to the back electrode 85. It has become.
As shown in FIG. 6, the thyristor includes a p-type semiconductor layer (p-type first semiconductor layer 81, p-type third semiconductor layer 83), n-type semiconductor layer (n-type second layer) made of GaAs, GaAlAs, or the like. A semiconductor layer 82 and an n-type fourth semiconductor layer 84) are stacked on a p-type substrate 80. Here, a forward potential (diffusion potential) Vd of a pn junction composed of a p-type semiconductor layer and an n-type semiconductor layer is described as 1.5 V as an example.

  A thyristor in an off state in which no current flows between the anode terminal and the cathode terminal transitions to an on state (turn on) when a potential lower than the threshold voltage (a negative potential having a large absolute value) is applied to the cathode terminal. To do. Here, the threshold voltage of the thyristor is a value obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the gate terminal. Therefore, when the potential of the gate terminal is 0V, the threshold voltage of the thyristor is −1.5V. That is, when a potential lower than −1.5 V (a negative potential having a large absolute value) is applied to the cathode terminal, the thyristor is turned on. When the thyristor is turned on, a current flows between the anode terminal and the cathode terminal (ON state).

  The potential of the gate terminal of the thyristor in the on state is close to the potential of the anode terminal. Here, since the anode terminal is set to the reference potential Vsub (0 V (“H”)), the potential of the gate terminal is assumed to be 0 V (“H”). Further, the cathode terminal of the thyristor in the on state has a potential close to the potential obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the anode terminal. Here, since the anode terminal is set to the reference potential Vsub (0 V (“H”)), the potential of the cathode terminal of the on-state thyristor is close to −1.5 V (the absolute value is larger than 1.5 V). Negative potential). Note that the potential of the cathode terminal is set in relation to a power source that supplies current to the thyristor in the on state.

Once the thyristor is turned on, the potential of the cathode terminal is higher than the potential necessary to maintain the on state (potential close to −1.5 V described above) (a negative potential having a small absolute value, 0 V or a positive potential). When (potential) is applied, it is turned off (turned off). For example, when the cathode terminal becomes “H” (0 V), the potential is higher than the potential necessary for maintaining the ON state, and the potential of the cathode terminal and the potential of the anode terminal are the same, so that the thyristor is turned off. To do.
On the other hand, a potential lower than the potential necessary to maintain the on state (a negative potential having a large absolute value) is continuously applied to the cathode terminal of the on state thyristor, and the current that can maintain the on state (sustain current) ) Is supplied, the thyristor remains on.
The light-emitting thyristor L is turned on (emits light) when turned on, and turned off (not lit) when turned off. The light emission amount of the light emitting thyristor L in the on state is determined by the area of the light emitting surface 311 and the current flowing between the cathode terminal and the anode terminal.

<Timing chart>
FIG. 7 is a timing chart for explaining operations of the light emitting device 65 and the light emitting chip C.
FIG. 7 shows a timing chart of a part that controls lighting (noted as lighting control) of the five light emitting thyristors L1 to L5 of the light emitting chip C1. As described above, since the other light emitting chips C2 to C40 operate in parallel with the light emitting chip C1, it is sufficient to describe the operation of the light emitting chip C1.
In FIG. 7, the light emitting thyristors L1, L2, L3, and L5 of the light emitting chip C1 are turned on, and the light emitting thyristor L4 is turned off (not lighted).

  In FIG. 7, it is assumed that time elapses from time a to time k in alphabetical order. The light emitting thyristor L1 is in the period T (1) from time b to time e, the light emitting thyristor L2 is in the period T (2) from time e to time i, and the light emitting thyristor L3 is in the period T (from time i to time j). In 3), the light-emitting thyristor L4 is controlled to be turned on or off (lighting control) in a period T (4) from time j to time k. Thereafter, the light-emitting thyristor L having a number of 5 or more is similarly controlled to be turned on.

  The waveforms of the first transfer signal φ1, the second transfer signal φ2, and the lighting signal φI1 will be described. Note that the period from time a to time b is a period during which the light emitting chip C1 (the same applies to the light emitting chips C2 to C40) is started. The signal in this period will be described in the description of the operation.

  The first transfer signal φ1 transmitted to the φ1 terminal (see FIGS. 5 and 6) and the second transfer signal φ2 transmitted to the φ2 terminal (see FIGS. 5 and 6) are “H” and “L”. A signal having two potentials. The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated in units of two consecutive periods T (for example, the period T (1) and the period T (2)).

The first transfer signal φ1 shifts from “H” to “L” at the start time b of the period T (1), and shifts from “L” to “H” at the time f. Then, at the end time i of the period T (2), the state shifts from “H” to “L”.
The second transfer signal φ2 is “H” at the start time b of the period T (1), and shifts from “H” to “L” at the time e. Then, “L” is maintained at the end time i of the period T (2).
Comparing the first transfer signal φ1 and the second transfer signal φ2, the second transfer signal φ2 corresponds to the first transfer signal φ1 shifted after the period T on the time axis. In the first transfer signal φ1, the waveforms in the period T (1) and the period T (2) are repeated after the period T (3). On the other hand, in the second transfer signal φ2, in the period T (1), the waveform indicated by the broken line and the waveform in the period T (2) are repeated after the period T (3). The waveform of the period T (1) of the second transfer signal φ2 is different from that after the period T (3) because the period T (1) is a period during which the light emitting device 65 starts operating.

  As will be described later, a set of transfer signals of the first transfer signal φ1 and the second transfer signal φ2 is transmitted in the ON state by causing the transfer thyristors T shown in FIGS. The light-emitting thyristor L having the same number as the transfer thyristor T is designated as a target for lighting or non-lighting control (lighting control).

  Next, the lighting signal φI1 transmitted to the φI terminal of the light emitting chip C1 will be described. Note that lighting signals φI2 to φI40 are transmitted to the other light emitting chips C2 to C40, respectively. The lighting signal φI1 is a signal having two potentials of “H” and “L”.

Here, the lighting signal φI1 will be described in the lighting control period T (1) for the light emitting thyristor L1 of the light emitting chip C1. Note that the light-emitting thyristor L1 is turned on.
The lighting signal φI1 is “H” at the start time b of the period T (1), and shifts from “H” to “L” at the time c. Then, it shifts from “L” to “H” at time d and maintains “H” at the end time e of the period T (1).

Now, the operations of the light emitting device 65 and the light emitting chip C1 will be described according to the timing chart shown in FIG. 7 with reference to FIGS. Hereinafter, the periods T (1) and T (2) in which the lighting thyristors L1 and L2 are controlled to be lighted will be described.
(1) Time a
<Light emitting device 65>
At time a, the reference potential supply unit 160 of the signal generation circuit 110 of the light emitting device 65 sets the reference potential Vsub to “H” (0 V). The power supply potential supply unit 170 sets the power supply potential Vga to “L” (−3.3 V). Then, the power supply line 200a on the circuit board 62 of the light emitting device 65 becomes “H” (0 V) of the reference potential Vsub, and the Vsub terminals of the light emitting chips C1 to C40 become “H”. Similarly, the power supply line 200b becomes “L” (−3.3 V) of the power supply potential Vga, and the Vga terminals of the light emitting chips C1 to C40 become “L” (see FIG. 4). Thereby, each power supply line 71 of the light emitting chips C1 to C40 becomes “L” (see FIG. 5).

  Then, the transfer signal generator 120 of the signal generation circuit 110 sets the first transfer signal φ1 and the second transfer signal φ2 to “H”, respectively. Then, the first transfer signal line 201 and the second transfer signal line 202 become “H” (see FIG. 4). As a result, the φ1 terminal and φ2 terminal of each of the light emitting chips C1 to C40 become “H”. The potential of the first transfer signal line 72 connected to the φ1 terminal via the current limiting resistor R1 also becomes “H”, and the second transfer signal line 73 connected to the φ1 terminal via the current limiting resistor R2 is also set. It becomes “H” (see FIG. 5).

  Further, the lighting signal generator 140 of the signal generation circuit 110 sets the lighting signals φI1 to φI40 to “H”, respectively. Then, the lighting signal lines 204-1 to 204-40 become “H” (see FIG. 4). Thereby, each φI terminal of the light emitting chips C1 to C40 becomes “H” via the current limiting resistor RI, and the lighting signal line 75 connected to the φI terminal also becomes “H” (see FIG. 5).

<Light emitting chip C1>
Since the anode terminals of the transfer thyristor T and the light emitting thyristor L are connected to the Vsub terminal, they are set to “H” (0 V).

  The cathode terminals of the odd-numbered transfer thyristors T1, T3, T5,... Are connected to the first transfer signal line 72 and set to “H”. The cathode terminals of the even-numbered transfer thyristors T2, T4, T6,... Are connected to the second transfer signal line 73 and set to “H”. Therefore, the transfer thyristor T is in the OFF state because both the anode terminal and the cathode terminal are “H”.

  The cathode terminal of the light emitting thyristor L is connected to the “H” lighting signal line 75. Therefore, the light-emitting thyristor L is also in the off state because both the anode terminal and the cathode terminal are “H”.

As described above, the gate terminal Gt1 at one end of the transfer thyristor array in FIG. 5 is connected to the cathode terminal of the start diode Dx0. The gate terminal Gt1 is connected to the power supply line 71 of the power supply potential Vga (“L” (−3.3 V)) via the power supply line resistance Rgx1. The anode terminal of the start diode Dx0 is connected to the second transfer signal line 73, and is connected to the φ2 terminal of “H” (0 V) via the current limiting resistor R2. Therefore, the start diode Dx0 is forward biased, and the cathode terminal (gate terminal Gt1 (Gl1)) of the start diode Dx0 is forward potential of the pn junction from the potential (“H” (0 V)) of the anode terminal of the start diode Dx0. A value obtained by subtracting Vd (1.5 V) (−1.5 V). When the gate terminal Gt1 becomes −1.5V, the coupling diode Dx1 has an anode terminal (gate terminal Gt1) of −1.5V and a cathode terminal connected to the power supply line 71 (“L” (“L”) via the power supply resistance Rgx2. -3.3V)), it is forward biased. Therefore, the potential of the gate terminal Gt2 becomes −3 V obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential (−1.5 V) of the gate terminal Gt1. However, the gate terminal Gt having a number of 3 or more is not affected by the fact that the anode terminal of the start diode Dx0 is “H” (0 V), and the potential of these gate terminals Gt is the potential of the power supply line 71. It is a certain “L” (−3.3 V).
As described above, since the gate terminal Gt is connected to the gate terminal Gl, the potential of the gate terminal Gl is the same as the potential of the gate terminal Gt. Therefore, the threshold voltage of the transfer thyristor T and the light emitting thyristor L is a value obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the gate terminal Gt (Gl). That is, the threshold voltage of the transfer thyristor T1 and the light-emitting thyristor L1 is −3 V, the threshold voltage of the transfer thyristor T2 and the light-emitting thyristor L2 is −4.5 V, the threshold voltage of the transfer thyristor T and the light-emitting thyristor L having a number of 3 or more. Is -4.8V.

(2) Time b
At time b shown in FIG. 7, the first transfer signal φ1 shifts from “H” (0V) to “L” (−3.3V). As a result, the light emitting device 65 and the light emitting chip C1 start operating. Hereinafter, the operation of the light emitting chip C1 will be described.
When the first transfer signal φ1 shifts from “H” to “L”, the potential of the first transfer signal line 72 shifts from “H” to “L” via the φ1 terminal and the current limiting resistor R1. Then, the transfer thyristor T1 having a threshold voltage of −3V is turned on.
When the transfer thyristor T1 is turned on, the potential of the first transfer signal line 72 is obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential (“H” (0 V)) of the anode terminal. 5V.

When the transfer thyristor T1 is turned on, the potential of the gate terminal Gt1 (Gl1) becomes “H” (0 V) which is the potential of the anode terminal of the transfer thyristor T1. The potential of the gate terminal Gt2 (Gl2) is −1.5 V, the potential of the gate terminal Gt3 (Gl3) is −3 V, and the potential of the gate terminal Gt (Gl) having a number of 4 or more is “L” (−3.3 V). )become.
Thus, the threshold voltage of the light emitting thyristor L1 is −1.5V, the threshold voltage of the transfer thyristor T2, the light emitting thyristor L2 is −3V, the threshold voltage of the transfer thyristor T3 and the light emitting thyristor L3 is −4.5V, and the number is The threshold voltage of four or more transfer thyristors T and light-emitting thyristors L becomes −4.8V.

(3) Time c
At time c, the lighting signal φI1 shifts from “H” to “L”.
Then, the lighting signal line 75 shifts from “H” to “L” via the current limiting resistor RI and the φI terminal. Then, the light emitting thyristor L1 having a threshold voltage of −1.5 V is turned on and lit (emits light). As a result, the potential of the lighting signal line 75 becomes a potential close to −1.5V (a negative potential having an absolute value greater than 1.5V).

(4) Time d
At time d, the lighting signal φI1 shifts from “L” to “H”.
Then, the potential of the lighting signal line 75 shifts from “L” to “H” via the current limiting resistor RI and the φI terminal. Then, since the anode terminal and the cathode terminal both become “H”, the light emitting thyristor L1 is turned off and turned off (not lit). During the lighting period of the light emitting thyristor L1, the lighting signal φI1 from the time c when the lighting signal φI1 shifts from “H” to “L” to the time d when the lighting signal φI1 shifts from “L” to “H” is “ L ".

(5) Time e
At time e, the second transfer signal φ2 shifts from “H” to “L”. Here, the period T (1) for controlling the lighting of the light emitting thyristor L1 ends, and the period T (2) for controlling the lighting of the light emitting thyristor L2 starts.
When the second transfer signal φ2 shifts from “H” to “L”, the potential of the second transfer signal line 73 shifts from “H” to “L” via the φ2 terminal. As described above, the transfer thyristor T2 is turned on because the threshold voltage is -3V. Accordingly, the potential of the gate terminal Gt2 (Gl2) is “H” (0 V), the potential of the gate terminal Gt3 (Gl3) is −1.5 V “H” (0 V), and the potential of the gate terminal Gt4 (Gl4) is −3 V. become. Then, the potential of the gate terminal Gt (Gl) having a number of 5 or more becomes −3.3V.

(6) Time f
At time f, the first transfer signal φ1 shifts from “L” to “H”.
Then, the potential of the first transfer signal line 72 shifts from “L” to “H” via the φ1 terminal. Then, the transfer thyristor T1 in the on state is turned off when both the anode terminal and the cathode terminal are set to “H”. Then, the potential of the gate terminal Gt1 (Gl1) changes toward the power supply potential Vga (“L” (−3.3 V)) of the power supply line 71 via the power supply line resistance Rgx1. As a result, the coupling diode Dx1 is in a state in which a potential is applied in a direction in which no current flows (reverse bias). Therefore, the influence that the gate terminal Gt2 (Gl2) is “H” (0 V) does not reach the gate terminal Gt1 (Gl1). That is, in the transfer thyristor T having the gate terminal Gt connected by the reverse-biased coupling diode Dx, the threshold voltage becomes −4.8V, and the first transfer signal φ1 of “L” (−3.3V) or The second transfer signal φ2 does not turn on.

(7) Others When the lighting signal φI1 shifts from “H” to “L” at time g, the light-emitting thyristor L2 is turned on and lit (emits light) in the same manner as the light-emitting thyristor L1 at time c.
At time h, when the lighting signal φI1 shifts from “L” to “H”, the light emitting thyristor L2 is turned off and turned off, similarly to the light emitting thyristor L1 at time d.
Further, when the first transfer signal φ1 shifts from “H” to “L” at time i, a transfer with a threshold voltage of −3 V is performed as in the transfer thyristor T1 at time b or the transfer thyristor T2 at time e. Thyristor T3 is turned on. At time i, the period T (2) for controlling the lighting of the light emitting thyristor L2 ends, and the period T (3) for controlling the lighting of the light emitting thyristor L3 starts.
Thereafter, the above description is repeated.

  When the light-emitting thyristor L is not turned on (emitted) but remains turned off (non-lighted), the lighting signal shown from the time j to the time k in the period T (4) during which the light-emitting thyristor L4 in FIG. As with φI1, the lighting signal φI may remain “H” (0 V). By doing in this way, even if the threshold voltage of the light emitting thyristor L4 is −1.5 V, the light emitting thyristor L4 remains off (not lit).

As described above, the gate terminals Gt of the transfer thyristors T are connected to each other by the coupling diode Dx. Therefore, when the potential of the gate terminal Gt changes, the potential of the gate terminal Gt connected to the gate terminal Gt whose potential has changed via the forward-biased coupling diode Dx changes. Then, the threshold voltage of the transfer thyristor T having the gate terminal whose potential has changed changes. When the threshold voltage of the transfer thyristor T is higher than “L” (−3.3 V) (a negative potential having a small absolute value), the first transfer signal φ1 or the second transfer signal φ2 is changed from “H” (0 V). Turns on at the timing of shifting to “L” (−3.3 V).
Since the threshold voltage of the light emitting thyristor L in which the gate terminal Gl is connected to the gate terminal Gt of the transfer thyristor T in the on state is −1.5 V, the lighting signal φI shifts from “H” to “L”. Then, it turns on and lights up (emits light).
That is, when the transfer thyristor T is turned on, the light emitting thyristor L that is the object of lighting control is designated, and the lighting signal φI sets the light emitting thyristor L that is the object of lighting control to be lit or not lit.
As described above, the waveform of the lighting signal φI is set according to the image data, and the lighting or non-lighting of each light-emitting thyristor L is controlled.

In the first embodiment, as shown in FIG. 6, the side surface of the portion where the wiring intersects in the island is tapered. The side surface of the island where the wiring does not intersect is not tapered.
Next, a description will be given of a method in which a part of the side surface of the island is tapered and the other side surface is not tapered.

In the first embodiment, a photoresist pattern (resist pattern) having a tapered side surface (for example, a trapezoidal cross section) is formed on a portion of the island having a tapered side surface, and dry etching is performed. The cross-sectional shape of the resist pattern is transferred to the island. On the other hand, a resist pattern having a non-tapered side surface is formed on a portion of the island where the side surface is not tapered, and dry etching is performed.
Here, gray scale lithography is used to taper the side surface of the island.

Next, gray scale lithography will be described.
Grayscale lithography is lithography performed using a photomask in which the light transmission amount (exposure amount) of exposure light has a distribution (gradation) in photolithography.

  A photomask used for photolithography that is not grayscale lithography includes a transmission region through which exposure light is transmitted and a light-shielding region through which exposure light is blocked. The photomask is obtained by forming a light-shielding region with a highly light-shielding film such as chromium on a glass substrate such as fused silica. The transmissive region is formed by removing a film with high light shielding properties by etching or the like, and the light shielding region is left without removing the film with high light shielding properties. Here, the light transmission amount of the transmission region is 100%, and the light transmission amount of the light shielding region is 0%.

  There are positive and negative photoresists. A positive photoresist is dissolved in a developing solution by being decomposed and reduced in molecular weight by irradiation with exposure light, and a portion where the exposure light is shielded becomes insoluble in the developing solution. On the other hand, a negative photoresist is polymerized by exposure to exposure light and becomes insoluble in the developer, and a portion where the exposure light is shielded is dissolved in the developer.

  Therefore, in the case of a positive type photoresist, a portion facing the transmission region of the photomask is dissolved in the developer, and a portion facing the light shielding region remains.

On the other hand, in a photomask used for gray scale lithography, in addition to a transmission region and a light shielding region, a region where the light transmission amount of exposure light is between 0% and 100% (hereinafter referred to as a gray scale (semi-transmission) region) ).
The gray scale region is obtained by, for example, processing a light-shielding film into fine dots that are not resolved by the photoresist, and setting the equivalent light transmission amount of exposure light according to the dot distribution (dot density). It is done. That is, the light transmission amount between 0% and 100% can be set depending on the dot density. As the dots on the photomask, for example, sub-μm size dots formed by an electron beam exposure apparatus or the like can be used. Then, the photoresist may be exposed by an exposure apparatus using i-line or the like.

For example, in a positive type photoresist, an exposure time (exposure amount) is set so that the entire film thickness of the photoresist is just decomposed and removed by development in a portion corresponding to the transmission region of the photomask. At this time, in the gray scale region, the surface (surface far from the light emitting chip C of the photoresist) irradiated with the exposure light of the photoresist is decomposed and removed by development, but the back surface (light emission of the photoresist). The surface near the chip C) remains. In the light shielding region, the photoresist remains without being removed by development.
Therefore, the photoresist is formed so that the thickness of the developed photoresist differs at the surface location of the material to be processed (substrate, film, etc.) corresponding to the light transmission amount of the exposure light of the photomask.

  Then, when the material to be processed is etched by an etching method in which the difference in etching speed between the material to be processed and the photoresist is small, the photoresist is also etched (removed) together with the material to be processed. Is transferred as a cross-sectional shape (profile) in the depth direction of the work material.

  FIG. 8 shows a mask pattern for forming the first island 301 and the second island 302 in FIG. 6 in the photomask for forming islands in the first embodiment (a photomask 95 in FIG. 9 to be described later). It is a figure which shows an example of 401,402. Here, it is assumed that the photoresist (the photoresist 90 in FIG. 9 described later) is a positive type. Therefore, the portions other than the mask patterns 401 and 402 painted black in FIG. 8 are transmission regions through which the exposure light (exposure light 97 in FIG. 9 described later) is transmitted. The mask pattern 401 corresponds to the first island 301, and the mask pattern 402 corresponds to the second island 302.

The mask pattern 401 includes a light shielding area 401a and a gray scale area 401b. The gray scale region 401b corresponds to the tapered side surface 301b shown in FIG. Similarly, the mask pattern 402 also includes a light shielding area 402a and a gray scale area 402b. The gray scale region 402b corresponds to the tapered side surface (not shown) shown in FIG.
Here, the gray scale regions 401b and 402b are both composed of fine dots. The dot density is higher as it is closer to the respective light shielding regions 401a and 402a, and lower as it is farther away.
Each dot sets the amount of light transmission equivalently depending on the density. Therefore, in the gray scale regions 401b and 402b, the closer to the light shielding regions 401a and 402a, the lower the light transmission amount, and the farther away, the higher the light transmission amount.

In the case of using a positive type photoresist, the photoresist remains in the portions corresponding to the light shielding regions 401a and 402a without being removed by development. On the other hand, the photoresist is removed by development at a portion corresponding to the transmission region. In the portions corresponding to the intermediate gray scale regions 401b and 402b, the amount of the photoresist removed by development is small in the portion where the light transmission amount is high, and the amount of the photoresist removed by development in the portion where the light transmission amount is low. There are many. Therefore, in the resist pattern formed by the mask patterns 401 and 402, portions corresponding to the gray scale regions 401b and 402b are tapered side surfaces.
Note that if the light shielding regions 401a and 402a are changed from the light shielding regions 401a and 402a to the transmission region without the gray scale regions 401b and 402b, the inclination of the side surface of the resist pattern becomes steeper than that of the tapered side surface.

  The photoresist may be of a negative type as long as the positive / negative relationship of the photomask is reversed.

  As a method for making the side surface of the resist pattern tapered or gentle, the resist pattern is viscously flowed by heat treatment (post-bake), and the edge of the resist pattern is gently (rounded) by surface tension. Done. In this case, the end portions of all resist patterns become gentle. For this reason, as described above, all the side surfaces of the island have a tapered shape or a gentle shape, which is not preferable for arranging the light emitting thyristors at a high density.

  In the first embodiment, the side surface of the island corresponding to the transfer unit 101 is tapered by applying the gray scale lithography described above, and the side surface of the island corresponding to the light emitting unit 102 is gray. The scale lithography is not applied and the taper is not used.

Next, a method for manufacturing the light emitting chip C will be described.
(Method for manufacturing light-emitting chip C)
FIG. 9 is a diagram illustrating a method for manufacturing the light-emitting chip C. FIGS. 9A1 to 9F1 are views for explaining a manufacturing method in the section taken along line IXA-IXA in FIG. That is, it is a cross section at a portion of the light emitting thyristors L1 to L4 (hereinafter referred to as the light emitting portion 102). On the other hand, FIGS. 9A2 to 9F2 are views for explaining the manufacturing method in the section taken along line IXB-IXB in FIG. That is, it is a cross section at the portions of the transfer thyristors T1 and T3 and the first transfer signal line 72 (hereinafter referred to as the transfer unit 101). Also in FIG. 8, in the mask pattern 401 of the photomask 95, the IXA′-IXA ′ line is shown in the corresponding part of the light emitting unit 102, and the IXB′-IXB ′ line is shown in the corresponding part of the transfer unit 101.
In manufacturing the light emitting chip C, for example, a plurality of light emitting chips C are formed on a circular wafer (substrate 80), and the wafer is divided for each light emitting chip C. Here, the manufacturing method will be described using the internal structure of the light-emitting chip C, so that it will be referred to as the light-emitting chip C instead of the wafer. And even if it is in the middle of manufacture, it describes with the light emitting chip C.

  In the cross section of the light emitting unit 102 in FIGS. 9A1 to 9F1, the side surfaces of the islands (the first island 301 and the islands that are not numbered in parallel with the first island 301) are not tapered. . On the other hand, in the cross section of the transfer unit 101 in FIGS. 9A2 to 9F2, the side surface of the island is tapered.

9A1 and 9A2 illustrate a process of applying a photoresist 90 to the light-emitting chip C before forming an island and irradiating the exposure light 97 through the photomask 95. FIG.
The light emitting chip C before forming the island is formed on a p-type substrate 80 of a compound semiconductor such as GaAs or GaAlAs, for example, on a p-type first semiconductor layer 81, an n-type second semiconductor layer 82, and a p-type first semiconductor layer 82. The third semiconductor layer 83 and the n-type fourth semiconductor layer 84 are sequentially stacked (step of forming a stacked semiconductor). Note that the stacked p-type first semiconductor layer 81, n-type second semiconductor layer 82, p-type third semiconductor layer 83, and n-type fourth semiconductor layer 84 are referred to as a stacked semiconductor, and a stacking process is performed. This is called a step of forming a laminated semiconductor.
Then, as shown in FIG. 6, in the first island 301 to the fifth island 305, etc., etching for removing the n-type fourth semiconductor layer 84 and exposing the surface of the p-type third semiconductor layer 83 ( Gate out etching) is performed. For example, in the first island 301, the n-type fourth semiconductor layer 84 is removed leaving the light emitting surface 311 of the light emitting thyristor L1, the region 312 of the coupling diode Dx1, and the region 313 of the transfer thyristor T1.
The thickness of the n-type fourth semiconductor layer 84 is, for example, 0.5 μm. The thickness of the n-type fourth semiconductor layer 84 is smaller than the depth of the separation groove, for example, 2 μm. Therefore, the influence on the formation of the wiring is smaller than that of the separation groove.

  A photoresist 90 is applied on the light emitting chip C. Here, the photoresist 90 is a positive type.

As shown in FIG. 9A1, the side surface of the island is not tapered in the light emitting portion 102. Therefore, the photomask 95 is formed with a light shielding region 401a that shields the exposure light 97 (see the line IXA′-IXA ′ in FIG. 8).
On the other hand, as shown in FIG. 9 (a2), the side surface of the island is tapered in the transfer portion 101 portion. Therefore, the photomask 95 is provided with a light shielding region 401a and a gray scale region 401b in which the amount of transmitted light gradually increases as it goes outward with the light shielding region 401a interposed therebetween (see the line IXB′-IXB ′ in FIG. 8). ).

  Through this photomask 95, the photoresist 90 formed on the light emitting chip C is exposed with exposure light 97 (step of exposing the photoresist). Then, development is performed with a predetermined developer to form resist patterns 91 and 92 (step of forming a resist pattern).

FIGS. 9B1 and 9B2 are views showing a cross section of the light-emitting chip C after the development process of the photoresist 90. FIG.
As shown in FIG. 9 (b1), the resist pattern 91 of the light emitting portion 102 is not tapered on the side surface (in FIG. 9 (b1), it is shown perpendicular to the surface of the light emitting chip C). On the other hand, as shown in FIG. 9 (b2), the resist pattern 92 of the transfer unit 101 reflects the gray scale region 401b, and the side surface is tapered (in FIG. 9 (b2), the cross section is represented by a trapezoid. ).
Note that the side surface of the resist pattern 91 may not be perpendicular to the surface of the light emitting chip C, may have a taper shape steeper than the side surface of the resist pattern 92 (the cross section is trapezoidal), and the reverse taper is narrower at the lower part than at the upper part. (The cross section is an inverted trapezoid).

FIGS. 9C1 and 9C2 are views showing a cross section of the light-emitting chip C after an island processing step by dry etching such as reactive ion etching.
Here, it is assumed that an island is formed by reactive ion etching (RIE). In RIE, a gas that reacts with a compound semiconductor such as GaAs or GaAlAs is ionized and irradiated to the compound semiconductor, whereby a third semiconductor layer 83, a second semiconductor layer 82, a first semiconductor layer made of a compound semiconductor such as GaAs or GaAlAs are irradiated. The semiconductor layer 81 is etched together with the resist patterns 91 and 92 (etching step). Etching in RIE proceeds in a direction perpendicular to the substrate 80.
In addition to RIE, ion beam etching or the like can be used.

  Here, the conditions are set so that the difference between the etching rate of the compound semiconductor and the etching rate of the resist patterns 91 and 92 becomes small. Then, the compound semiconductor is etched, and the resist patterns 91 and 92 are etched. That is, in the resist pattern 92 having a tapered side surface, the side surface of the resist pattern 92 disappears from the tapered skirt portion, and the tapered side surface shifts inward. The newly exposed compound semiconductor portion is also etched. In this way, the cross-sectional shape of the resist pattern 92 is transferred to the cross-sectional shape of the compound semiconductor. That is, the side surface of the island transfer portion 101 is tapered.

  On the other hand, in the resist pattern 91 whose side surface is not tapered, the side surface does not shift. Therefore, the side surface is not tapered in the light emitting portion 102 of the island.

FIGS. 9D1 and 9D2 are cross-sectional views of the light-emitting chip C after the resist removing process for removing the resist patterns 91 and 92. FIG.
The resist patterns 91 and 92 are removed by a predetermined method.

FIGS. 9E1 and 9E2 are views showing a cross section of the light emitting chip C after the insulating layer forming step of forming the insulating layer 86 on the light emitting chip C on which the p-type ohmic electrode and the n-type ohmic electrode are formed. .
An n-type ohmic electrode (such as n-type ohmic electrodes 321 and 322) made of AuGe or the like and a p-type ohmic electrode (such as p-type ohmic electrode 331) made of AuZn are formed by a predetermined method.
Then, an insulating layer 86 made of an insulating material that transmits light emitted from the light-emitting thyristor L, such as silicon dioxide, is deposited on the surface of the light-emitting chip C by a predetermined method.

FIGS. 9F1 and 9F2 are views showing a cross-section of the light-emitting chip C after a wiring formation step in which a through hole is provided in the insulating layer 86 to form a wiring.
A through hole is provided in the insulating layer 86 so that the central portions of the p-type ohmic electrode and the n-type ohmic electrode are exposed. Next, for example, a metal film such as aluminum or gold is deposited and processed into a wiring by a predetermined method (step of forming a wiring).
By doing in this way, the light emitting chip C shown in FIG. 6 is manufactured.

  As described above, in the first embodiment, the side surface of the portion corresponding to the transfer unit 101 where the island wiring intersects is tapered, and the side surface of the light emitting unit 102 where the wiring does not intersect is not tapered. In this way, the wiring resistance is increased and the wiring disconnection probability is reduced. Thereby, the light emitting thyristors L are arranged at high density while suppressing the area of the light emitting surface 311 of the light emitting thyristor L in the light emitting unit 102 from being reduced.

In the first embodiment, the light emitting thyristor L1, the transfer thyristor T1, and the coupling diode Dx1 are formed on the first island 301. However, the light emitting thyristor L1, the transfer thyristor T1, and the coupling diode Dx1 may be formed on different islands. At this time, in the island where the light emitting thyristor L1 is formed, the side surface where the trunk portion 75a of the lighting signal line 75 intersects may be tapered.
That is, for example, even if the first island 301 shown in FIGS. 6A and 6B is divided into a plurality of islands, the side portion where the island wiring intersects may be tapered.

[Second Embodiment]
In the first embodiment, as shown in FIGS. 6A and 6B, the side surface of the island corresponding to the transfer unit 101 is tapered, and the power supply line 71 and the first transfer are formed on the tapered side surface. Wirings such as the signal line 72 and the second transfer signal line 73 are crossed.
In the second embodiment, a portion where the wiring on the side surface of the island intersects is tapered. Since the other configuration is the same as that of the first embodiment, different parts will be described, and the same parts are denoted by the same reference numerals, and description thereof will be omitted.

  FIG. 10 is an example of a plan layout view and a cross-sectional view of the light-emitting chip C in the second embodiment. FIG. 10A is a plan layout diagram of the light-emitting chip C, and shows a portion centering on the light-emitting thyristors L1 to L4 and the transfer thyristors T1 to T4. FIG. 10B is a cross-sectional view taken along line XB-XB shown in FIG. Therefore, similarly to FIG. 6B, FIG. 10B shows a cross section of the light emitting thyristor L1, the transfer thyristor T1, the coupling diode Dx1, and the power supply line resistance Rgx1 from the bottom in the figure.

In FIG. 10, in the first island 301, the side portion where the first transfer signal line 72, the second transfer signal line 73, and the connection wirings 76, 77, 78 intersect is tapered. Similarly, in the second island 302, a side surface portion where the power supply line 71 and the connection wiring 76 intersect is tapered. The same applies to other islands.
In the first embodiment, since the side surface of the part corresponding to the island transfer unit 101 is tapered, the area occupied by elements such as the transfer thyristor T, the coupling diode Dx, and the start diode Dx0 is reduced. However, in the second embodiment, it is not necessary to reduce the area occupied by these elements except for a portion intersecting with the wiring. Therefore, by increasing the size of these elements, the operation of these elements becomes more stable.

  In the second embodiment, as in the first embodiment, since the side surface of the island where the wiring intersects can be selectively tapered, the side surface of the island such as the light-emitting thyristor L that does not intersect with the wiring can be formed. It does not need to be tapered. Therefore, the light emitting thyristors L can be arranged with high density.

  In the first and second embodiments, the thyristor (transfer thyristor T, light-emitting thyristor L) has been described as an anode common in which the anode terminal is connected to the substrate 80. The thyristor (transfer thyristor T, light-emitting thyristor L) may be a cathode common whose cathode terminal is connected to the substrate 80 by changing the polarity of the circuit.

Further, in the first embodiment and the second embodiment, the self-scanning light-emitting element array (SLED) including the light-emitting thyristor L and the transfer thyristor T has been described, but the self-scanning light-emitting element array ( SLED) may include other members such as a control thyristor, a diode, and a resistor in addition to the light emitting thyristor L and the transfer thyristor T.
In the first embodiment and the second embodiment, the transfer thyristor T is connected by the coupling diode Dx. However, a member that can transmit a change in potential such as a resistance may be used.

  In the first embodiment and the second embodiment, the light emitting element is the light emitting thyristor L. The light emitting element is a light emitting diode (LED) in which a p-type semiconductor layer and an n-type semiconductor layer are stacked. ).

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 10 ... Image formation process part, 11, 11Y, 11M, 11C, 11K ... Image formation unit, 12 ... Photosensitive drum, 14 ... Print head, 30 ... Image output control part, 40 ... Image processing part , 62 ... circuit board, 63 ... light source section, 64 ... rod lens array, 65 ... light emitting device, 71 ... power supply line, 72 ... first transfer signal line, 73 ... second transfer signal line, 75 ... lighting signal line, 90 DESCRIPTION OF SYMBOLS ... Photoresist, 91, 92 ... Resist pattern, 95 ... Photomask, 97 ... Exposure light, 101 ... Transfer part, 102 ... Light emission part, 110 ... Signal generation circuit, 120 ... Transfer signal generation part, 140 ... Lighting signal generation part 160 ... reference potential supply unit, 170 ... power supply potential supply unit, 401, 402 ... mask pattern, 401a, 402a ... light-shielding region, 401b, 402b ... gray scale (half Over) region, φ1 ... first transfer signal, φ2 ... second transfer signal, φI (φI1-φI40) ... lighting signal, C (C1-C40) ... light emitting chip, L ... light emitting thyristor, T ... transfer thyristor, Dx ... Coupling diode, Vga: power supply potential, Vsub: reference potential

Claims (4)

A substrate,
A plurality of semiconductor layers having different conductivity types are stacked on the substrate, and a plurality of islands each provided with a light emitting element and a driving element that is provided corresponding to the light emitting element and drives the light emitting element ;
A lighting signal line that is provided on the substrate and is connected to the light emitting element of each of the plurality of islands and supplies a current for lighting, and a driving signal line that drives the driving element of each of the plurality of islands And comprising
Each of the plurality of islands includes a first side surface and a second side surface having an inclination angle smaller than that of the first side surface, and the lighting signal line and the drive signal line intersect the second side surface. A light emitting component characterized by being provided.   2. The light emitting component according to claim 1, wherein a side surface adjacent to a light emitting surface that emits light is configured by the first side surface in the island provided with the light emitting element. A plurality of islands each having a substrate and a plurality of semiconductor layers having different conductivity types stacked on the substrate, each provided with a light emitting element and a driving element provided corresponding to the light emitting element and driving the light emitting element ; A lighting signal line that is provided on the substrate and supplies a current for lighting to the light emitting element of each of the plurality of islands; and a drive signal line that drives the driving element of each of the plurality of islands; Each of the plurality of islands includes a first side surface and a second side surface having an inclination angle smaller than that of the first side surface, and the lighting signal line and the drive signal line are the second side surface. A light emitting means provided to intersect with
And a print head including an optical unit that forms an image of light emitted from the light emitting unit. An image carrier,
Charging means for charging the image carrier;
A plurality of islands each having a substrate and a plurality of semiconductor layers having different conductivity types stacked on the substrate, each provided with a light emitting element and a driving element provided corresponding to the light emitting element and driving the light emitting element ; A lighting signal line that is provided on the substrate and supplies a current for lighting to the light emitting element of each of the plurality of islands; and a drive signal line that drives the driving element of each of the plurality of islands; Each of the plurality of islands includes a first side surface and a second side surface having an inclination angle smaller than that of the first side surface, and the lighting signal line and the drive signal line are the second side surface. And an exposure unit that exposes the image carrier charged by the charging unit via an optical unit,
Developing means for developing the electrostatic latent image exposed by the exposure means and formed on the image carrier;
An image forming apparatus comprising transfer means for transferring an image developed on the image holding member to a transfer target.

Images