JP7351149B2 - Light emitting device, optical scanning device - Google Patents

Description

The present invention relates to a light emitting device and an optical scanning device.

Patent Document 1 discloses that in a light emitting device including 40 light emitting chips each having a plurality of light emitting thyristors, these 40 light emitting chips are divided into two groups (#a, #b) of 20 each. It is also described that the light emitting chips are divided into 20 groups (#1 to #20) of two each including the light emitting chips of each group. Further, in Patent Document 1, a first transfer signal φ1a, a second transfer signal φ2a, a lighting signal φIa, and an enable signal φRa are commonly supplied to the light emitting chip group #a, and the light emitting chip group #b is The first transfer signal φ1b, the second transfer signal φ2b, the lighting signal φIb, and the permission signal φRb are commonly supplied, and the corresponding setting signals φW1 to φW1 to each of the 20 groups #1 to #20 are supplied in common. It is described that φW20 is supplied.

Further, Patent Document 2 describes a light emitting device including 57 odd number of light emitting chips each having a plurality of light emitting thyristors.

Japanese Patent Application Publication No. 2015-139894 Japanese Patent Application Publication No. 2010-120261

For example, if the total number of light emitting chips is an odd number and the chips are grouped into sets of two, one chip will be left over. Now, let us consider a case where a configuration is adopted in which a setting signal is supplied to a set of two light emitting chips and a set of one light emitting chip, with each set as a unit. Then, if an abnormal voltage (noise) such as a surge is applied to the wiring that supplies setting signals to the former group and the wiring that supplies setting signals to the latter group, the light-emitting chips that make up the latter group A larger current (approximately twice as much in this case) will flow through the light-emitting chips that make up the former group. As a result, the light emitting chips forming the latter group may have a higher probability of electrical failure than the light emitting chips forming the former group.

An object of the present invention is to suppress failure of some electronic circuits due to noise in a light emitting device or the like that includes a plurality of electronic circuits each having a plurality of light emitting elements.

The invention according to claim 1 provides x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements. and y sets (y is an integer of 1 or more) of second circuits each including n electronic circuits (n is an integer of 1 or more but less than m) and x sets of the first circuits. x number of first wirings that supply a first signal to each of said second circuits; y number of second wirings that supply a second signal to each of y sets of said second circuits; and x sets of said first circuits. a common wiring commonly connected to the y groups of the second circuits; and a noise filter connected between the common wiring and the y number of the second wirings; The light emitting device is characterized in that it does not include a noise filter between the light emitting device and the first wiring .
The invention according to claim 2 is the light emitting device according to claim 1, wherein the noise filter includes a capacitor or a coil.
The invention according to claim 3 is the light emitting device according to claim 2, wherein the noise filter includes a capacitor, and the capacitor has a capacitance of 5 pF or more.
The invention according to claim 4 includes a printed wiring board in which the common wiring, x number of the first wirings, and y number of the second wirings are formed as a wiring pattern, and a plurality of the electronic circuits are formed of semiconductors. 2. The light emitting device according to claim 1, wherein the light emitting device is configured of an integrated circuit and is mounted on the printed wiring board, and the noise filter is mounted on the printed wiring board.
The invention according to claim 5 is mounted on the printed wiring board, and the common wiring, x number of the first wirings, and y number of the second wirings are connected, and the common wiring and the x number of the second wirings are connected. The first signal is outputted to each of the x sets of the first circuits via the first wiring, and the y set of the second circuits is outputted via the common wiring and the y second wirings. 5. The light emitting device according to claim 4, further comprising a signal output circuit for outputting the second signal to each of the light emitting devices.
The invention according to claim 6 is characterized in that each of the electronic circuits has a plurality of light emitting thyristors as the light emitting elements, and further includes a plurality of control thyristors that control lighting of the plurality of light emitting thyristors. 2. A light emitting device according to claim 1.
According to a seventh aspect of the invention, the first signal is output to the control thyristor provided in the electronic circuit constituting x sets of the first circuits via the common wiring and the first wiring. , the control thyristor provided in the electronic circuit constituting the second circuit of group y further includes a signal output circuit that outputs the second signal via the common wiring and the second wiring. 7. A light emitting device according to claim 6.
The invention according to claim 8 provides x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements. and y sets (y is an integer of 1 or more) of second circuits each including n electronic circuits (n is an integer of 1 or more but less than m) and x sets of the first circuits. x first wirings that supply signals to each of the first circuits; y second wirings that supply signals to each of the y sets of the second circuits; a wiring board to which x sets of the first circuits and y sets of the second circuits are attached; In the wiring board, a second capacitance that is a capacitance between the first wiring and the common wiring is larger than a first capacitance that is a capacitance between the first wiring and the common wiring. The light emitting device is characterized in that the area of the second wiring is larger than the area of the first wiring .
The invention according to claim 9 provides x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements. and y sets (y is an integer of 1 or more) of second circuits each including n electronic circuits (n is an integer of 1 or more but less than m) and x sets of the first circuits. x first wirings that supply signals to each of the first circuits; y second wirings that supply signals to each of the y sets of the second circuits; a wiring board to which x sets of the first circuits and y sets of the second circuits are attached; A second capacitance, which is a capacitance between the first wiring and the common wiring, is larger than a first capacitance, which is a capacitance between the first wiring and the common wiring. The light emitting device is characterized in that two wirings are connected via a capacitor , and the common wiring and the first wiring are not connected via a capacitor .
The invention according to claim 10 provides x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements. and y sets (y is an integer of 1 or more) of second circuits each including n electronic circuits (n is an integer of 1 or more but less than m) and x sets of the first circuits. x number of first wirings that supply a first signal to each of the corresponding second circuits; y number of second wirings that supply a second signal to each of the corresponding second circuits of the y group; A common wiring connected in common to y groups of said second circuits, and a noise filter connected between said common wiring and y said said second wirings, and using a plurality of said light emitting elements. comprising an exposure means for exposing an image carrier, and an imaging means for forming an image of light output from the exposure means on the image carrier, and between the common wiring and the x number of the first wirings. This is an optical scanning device characterized in that it does not include a noise filter .
The invention according to claim 11 provides x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements. and y sets (y is an integer of 1 or more) of second circuits each including n electronic circuits (n is an integer of 1 or more but less than m) and x sets of the first circuits. x number of first wirings that supply signals to each of the corresponding second circuits, y number of second wirings that supply signals to each of the y sets of the corresponding second circuits, and the a common wiring that is commonly connected to the second circuit, and a wiring board to which x sets of the first circuits and y sets of the second circuits are attached; The size of the second capacitance, which is the capacitance between the first wiring and the common wiring, is set larger than the first capacitance, which is the capacitance between the first wiring and the common wiring, and The wiring board includes an exposure means for exposing an image carrier to light using an element, and an imaging means for forming an image on the image carrier with light output from the exposure means, and the wiring board includes The optical scanning device is characterized in that the area is larger than the area of the first wiring .

According to the invention described in claim 1, in a light emitting device including a plurality of electronic circuits each having a plurality of light emitting elements, it is possible to suppress failure of some of the electronic circuits due to noise. I can do it.
According to the invention set forth in claim 2, it is possible to suppress failure of the noise filter due to noise, compared to a case where the noise filter is configured with active elements.
According to the third aspect of the present invention, it is possible to reduce the amount of current flowing through some electronic circuits due to noise, compared to a case where the capacitance of the capacitor is less than 5 pF.
According to the fourth aspect of the present invention, the printed wiring board and the noise filter can be connected more easily than when the noise filter is not mounted on the printed wiring board.
According to the invention set forth in claim 5, it is possible to reduce noise superimposed on various signals compared to a case where the signal output circuit is not mounted on a printed wiring board.
According to the sixth aspect of the invention, the light emission of the light emitting element can be controlled more easily than in the case where the light emitting thyristor and the control thyristor are not used.
According to the seventh aspect of the invention, the light emission of the light emitting element can be controlled more easily than in the case where the light emitting thyristor and the control thyristor are not used.
According to the invention set forth in claim 8 , a state in which a noise filter is present can be realized without providing a separate noise filter .
According to the invention described in claim 9 , the capacitance of the capacitor provided between the common wiring and the second wiring can be reduced compared to the case where the capacitor is provided between the common wiring and the first wiring. can.
According to the tenth aspect of the invention, in an optical scanning device including a plurality of electronic circuits each having a plurality of light emitting elements, failure of some of the electronic circuits due to noise is suppressed. be able to.
According to the invention described in claim 11 , in an optical scanning device including a plurality of electronic circuits each having a plurality of light emitting elements, failure of some of the electronic circuits due to noise is suppressed. be able to.

1 is a diagram showing an example of the overall configuration of an image forming apparatus to which this embodiment is applied. FIG. 2 is a cross-sectional view showing the configuration of a print head. FIG. 3 is a top view of the light emitting device. FIG. 3 is a diagram for explaining the arrangement of light emitting chips in a light source section, and the grouping and grouping of each light emitting chip. FIG. 2 is a block diagram for explaining the configuration of a signal generation circuit. FIG. 2 is a top view for explaining the configuration of a light emitting chip. FIG. 3 is a diagram for explaining the configuration of various wirings on a wiring board. 3 is a diagram for explaining the electrical connection relationship between a wiring board, a light source section, and a signal generation circuit in the light emitting device of Embodiment 1. FIG. FIG. 3 is a diagram for explaining the relationship between each grouped and grouped light emitting chips constituting a light source section and various signals supplied to each light emitting chip. FIG. 2 is a diagram for explaining a circuit configuration of a self-scanning light emitting element array provided on a light emitting chip. (a) to (c) are diagrams for explaining the current flowing through each set forming the light source section when an IEC 61000-4-2 test is performed. FIG. 7 is a diagram for explaining an electrical connection relationship between a wiring board, a light source section, and a signal generation circuit in a light emitting device according to a second embodiment. 7 is a diagram for explaining the relationship between each setting wiring (first setting wiring to eighth setting wiring) and grounding wiring in the wiring board of the second embodiment. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<Embodiment 1>
[Image forming device]
FIG. 1 is a diagram showing an example of the overall configuration of an image forming apparatus 1 to which this embodiment is applied.
The image forming apparatus 1 shown in FIG. 1 is generally referred to as a tandem type. The image forming apparatus 1 includes an image forming process section 10 that forms an image in accordance with image data of each color, an image output control section 30 that controls the image forming process section 10, and, for example, a personal computer (PC) 2 or an image reading device. The image processing unit 40 is connected to the PC 3 and performs predetermined image processing on image data received from the PC 2 or the image reading device 3.

The image forming process section 10 includes an image forming unit 11 including a plurality of engines arranged in parallel at predetermined intervals. This image forming unit 11 is provided for each color of yellow (Y), magenta (M), cyan (C), and black (K). , M, C, K.

The image forming units 11Y, 11M, 11C, and 11K each include a photoreceptor drum 12 that forms an electrostatic latent image and holds a toner image, and a charger 13 that charges the surface of the photoreceptor drum 12 with a predetermined potential. , a print head 14 that exposes the photoreceptor drum 12 charged by a charger 13, and a developer 15 that develops an electrostatic latent image obtained by the print head 14. Here, each of the image forming units 11Y, 11M, 11C, and 11K has the same configuration except for the toner stored in the developing device 15. The image forming units 11Y, 11M, 11C, and 11K form yellow (Y), magenta (M), cyan (C), and black (K) toner images, respectively.

The image forming process section 10 also transports the recording paper in order to multiple-transfer the toner images of each color formed on the photoreceptor drums 12 of the image forming units 11Y, 11M, 11C, and 11K onto the recording paper. A paper conveyance belt 21, a drive roll 22 that is a roll that drives the paper conveyance belt 21, a transfer roll 23 that transfers the toner image on the photoreceptor drum 12 onto recording paper, and a fixing device 24 that fixes the toner image on the recording paper. It is equipped with

[Operation of image forming apparatus]
In this image forming apparatus 1, an image forming process section 10 performs image forming operations based on various control signals supplied from an image output control section 30.

Under the control of the image output control section 30 , image data received from the PC 2 or the image reading device 3 is subjected to image processing by the image processing section 40 and supplied to the image forming unit 11 . For example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged to a predetermined potential by the charger 13 while rotating in the direction of the arrow, and image data supplied from the image processing section 40 is charged. The print head 14 emits light based on the image. As a result, an electrostatic latent image regarding a black (K) color image is formed on the photoreceptor drum 12.

The electrostatic latent image formed on the photoreceptor drum 12 is developed by a developing device 15, and a black (K) toner image is formed on the photoreceptor drum 12. In the image forming units 11Y, 11M, and 11C, toner images of yellow (Y), magenta (M), and cyan (C) are formed, respectively.

Each color toner image formed on the photoreceptor drum 12 by each image forming unit 11 is transferred to the recording paper fed by the movement of the paper conveyance belt 21 moving in the direction of the arrow, by the transfer electric field applied to the transfer roll 23. As a result, the toner of each color is sequentially electrostatically transferred to form a composite toner image on the recording paper in which the toner of each color is superimposed.

Thereafter, the recording paper onto which the composite toner image has been electrostatically transferred is conveyed to the fixing device 24. The composite toner image on the recording paper conveyed to the fixing device 24 is fixed on the recording paper through a fixing process using heat and pressure by the fixing device 24, and is ejected from the image forming apparatus 1.

[Print head]
FIG. 2 is a cross-sectional view showing the configuration of the print head 14. As shown in FIG. The print head 14 includes a housing 61 , a light emitting device 62 including a light source section 72 made up of a plurality of light emitting elements (light emitting thyristors in this embodiment) that exposes the photosensitive drum 12 , and light emitted from the light source section 72 . and a rod lens array 63 for forming an image on the surface of the photoreceptor drum 12.

Further, the light emitting device 62 includes a wiring board 71 on which the above-described light source section 72 and a signal generation circuit 73 (see FIG. 3 described later) for driving the light source section 72 are mounted.

The housing 61 is made of metal, for example. The housing 61 supports the light emitting device 62 via the wiring board 71 and also supports the rod lens array 63. At this time, the housing 61 holds the light emitting device 62 so that the light emitting point of the light emitting element of the light source section 72 and the focal plane of the rod lens array 63 coincide with each other. Further, the rod lens array 63 is arranged along the axial direction of the photosensitive drum 12 (the main scanning direction, which is the X direction in FIGS. 3 and 4, which will be described later).

(Light emitting device)
FIG. 3 is a top view of the light emitting device 62 shown in FIG. 2, viewed from the photosensitive drum 12 side.
As described above, this light emitting device 62 includes a wiring board 71 on which various wirings are formed, a light source part 72 mounted on the wiring board 71, and a light source part 72 mounted on the same wiring board 71 to drive the light source part 72. It also includes a signal generation circuit 73 that generates various signals. The light source section 72 and the signal generation circuit 73 are electrically connected via various wirings provided on the wiring board 71.

The light emitting device 62 of the present embodiment is generally an elongated device whose length in the X direction, which is the main scanning direction of the image forming apparatus 1, is larger than the length in the Y direction, which is the sub scanning direction of the image forming apparatus 1. It has the shape of Therefore, the wiring board 71 constituting the light emitting device 62 has a rectangular shape in which the length in the X direction is longer than the length in the Y direction. A signal generation circuit 73 is attached to one end side (upstream side) in the X direction of the wiring board 71, and a light source section 72 is attached to the other end side (downstream side) in the X direction of the wiring board 71. It looks like this.

However, the signal generation circuit 73 is not an essential component of the light emitting device 62 and may be provided outside the wiring board 71. In other words, the light source section 72 and the signal generation circuit 73 may be provided separately. In this case, the light source section 72 and the signal generation circuit 73 are electrically connected, for example, via a harness or the like. Note that the following description will be given assuming that the light emitting device 62 includes both the light source section 72 and the signal generation circuit 73.

[Wiring board]
As the wiring board 71, various wiring patterns can be formed by combining an insulator and a conductor, and for example, a so-called printed wiring board is used. Note that the detailed configuration of the wiring board 71 will be described later.

[Light source section]
The light source section 72 has a plurality of (15 in this example) light emitting chips C. In this example, the light source section 72 is configured by arranging 15 light emitting chips C in two rows in a staggered manner in the X direction. To explain more specifically, in this example, a pre-stage light emitting chip group #a including eight light emitting chips C (Ca1 to Ca8) arranged side by side along the X direction on one end side of the Y direction, and A light source section 72 is constituted by a rear light emitting chip group #b including seven light emitting chips C (Cb1 to Cb7) arranged side by side along the X direction on the other end side.

FIG. 4 is a diagram for explaining the arrangement of the light emitting chips C in the light source section 72, and the grouping and grouping of each light emitting chip C. The following description will be made with reference to FIG. 4 in addition to FIG. 3 described above.

As described above, the light source section 72 includes a front light emitting chip group #a including eight light emitting chips C (Ca1 to Ca8) and a rear light emitting chip group #b including seven light emitting chips C (Cb1 to Cb7). It is composed of Here, in the front light emitting chip group #a, from the upstream side in the X direction, the first front light emitting chip Ca1, the second front light emitting chip Ca2, the third front light emitting chip Ca3, the fourth front light emitting chip Ca4, and the fifth front light emitting chip The light emitting chips C are lined up in the following order: chip Ca5, sixth light emitting chip Ca6 in the front stage, seventh light emitting chip Ca7 in the front stage, and eighth light emitting chip Ca8 in the front stage. On the other hand, in the rear-stage light-emitting chip group #b, from the upstream side in the X direction, the rear-stage first light-emitting chip Cb1, the rear-stage second light-emitting chip Cb2, the rear-stage third light-emitting chip Cb3, the rear-stage fourth light-emitting chip Cb4, and the rear-stage fifth light-emitting chip. The light emitting chips C are lined up in the following order: light emitting chip Cb5, second stage sixth light emitting chip Cb6, and second stage seventh light emitting chip Cb7. In the present embodiment, these 15 light-emitting chips C, that is, the first front-stage light-emitting chip Ca1 to the front-stage eighth light-emitting chip Ca8 and the second-stage first light-emitting chip Cb1 to the second-stage seventh light-emitting chip Cb7 share a common circuit. It has a structure.

In addition, in the light source section 72, the first light emitting chip Ca1 of the front stage is arranged so that the downstream end in the X direction of the first light emitting chip Ca1 and the upstream end of the first light emitting chip Cb1 of the rear stage in the X direction partially overlap. The chip Ca1 and the second-stage first light emitting chip Cb1 are positioned. In addition, in the light source section 72, the downstream first light emitting chip Cb1 is arranged such that the downstream end in the X direction of the downstream first light emitting chip Cb1 and the upstream end in the X direction of the upstream second light emitting chip Ca2 partially overlap. The chip Cb1 and the preceding second light emitting chip Ca2 are positioned. Although a detailed explanation will be omitted below, adjacent light emitting chips C are positioned with respect to each other in the same manner. Finally, in the light source section 72, the downstream end of the seventh light emitting chip Cb7 in the rear stage in the X direction partially overlaps with the upstream end in the X direction of the eighth light emitting chip Ca8 in the front stage. The seventh light emitting chip Cb7 and the preceding eighth light emitting chip Ca8 are being positioned.

Furthermore, in the light source section 72 of the present embodiment, as described above, in addition to grouping the 15 light emitting chips C into the front stage light emitting chip group #a and the rear stage light emitting chip group #b, Basically, two light emitting chips C are grouped into one set. At this time, in each set, basically, one is selected from the front-stage light-emitting chip group #a, and the other is selected from the rear-stage light-emitting chip group #b.

In this example, first, the front-stage first light-emitting chip Ca1 and the rear-stage first light-emitting chip Cb1 having the same number, that is, adjacent to each other, form a first set #1. Furthermore, the adjacent front-stage second light-emitting chip Ca2 and rear-stage second light-emitting chip Cb2 having the same number form a second set #2. Further, the adjacent front-stage third light-emitting chip Ca3 and rear-stage third light-emitting chip Cb3 having the same number form a third set #3. Furthermore, the adjacent front-stage fourth light-emitting chip Ca4 and rear-stage fourth light-emitting chip Cb4, which have the same number, form a fourth set #4. Furthermore, the adjacent front-stage fifth light-emitting chip Ca5 and rear-stage fifth light-emitting chip Cb5 having the same number form a fifth set #5. Further, next, the adjacent front-stage sixth light-emitting chip Ca6 and rear-stage sixth light-emitting chip Cb6, which have the same number, form a sixth set #6. Furthermore, the next front-stage seventh light-emitting chip Ca7 and the rear-stage seventh light-emitting chip Cb7, which are adjacent to each other and have the same number, form a seventh set #7.

However, in this example, the number of light emitting chips C that constitute the light source section 72 is 15 in total, so if two chips are made into one set, the remaining light emitting chips C (in this example, the eighth light emitting chip in the previous stage) Ca8) will be generated. In this example, the remaining front-stage eighth light emitting chip Ca8 alone forms the eighth group #8.

[Signal generation circuit]
FIG. 5 is a block diagram for explaining the configuration of the signal generation circuit 73. Although the actual signal generation circuit 73 is composed of, for example, an ASIC (Application Specific Integrated Circuit), the signal generation circuit 73 is shown here as a functional block.

The signal generation circuit 73 includes an image data development section 111, a reference clock generation section 112, and a timing generation section 113. Further, the signal generation circuit 73 includes a lighting time setting section 114, a transfer signal generation section 120, a permission signal generation section 130, a lighting signal generation section 140, and a setting signal generation section 150. Further, the signal generation circuit 73 includes a reference potential supply section 160 and a power supply potential supply section 170.

{Connection relationship of each part}
First, a description will be given of the connection relationship of each part constituting the signal generation circuit 73.
First, the input side of the image data development section 111 is connected to the output sides of the image processing section 40 and the timing generation section 113. Further, the output side of the image data development section 111 is connected to the input side of the lighting time setting section 114.
Next, the output side of the image output control section 30 is connected to the input side of the reference clock generation section 112. Further, the output side of the reference clock generation section 112 is connected to each input side of the timing generation section 113 and the lighting time setting section 114.
Subsequently, the output side of the image output control section 30 is connected to the input side of the timing generation section 113. Further, the output side of the timing generation section 113 is connected to each input side of the image data development section 111, the lighting time setting section 114, the transfer signal generation section 120, the permission signal generation section 130, and the lighting signal generation section 140.
Next, to the input side of the lighting time setting section 114, the output sides of the image data development section 111, the reference clock generation section 112, and the timing generation section 113 are connected. Further, the output side of the lighting time setting section 114 is connected to the input side of the setting signal generation section 150.
The output side of the timing generation section 113 is connected to the input side of the transfer signal generation section 120. Further, the output side of the transfer signal generating section 120 is connected to the light source section 72 (see FIG. 3).
Next, the output side of the timing generation section 113 is connected to the input side of the permission signal generation section 130. Further, the output side of the permission signal generating section 130 is connected to the light source section 72 (see FIG. 3).
Subsequently, the output side of the timing generation section 113 is connected to the input side of the lighting signal generation section 140. Further, the output side of the lighting signal generating section 140 is connected to the light source section 72 (see FIG. 3).
Next, the output side of the lighting time setting section 114 is connected to the input side of the setting signal generation section 150. Further, the output side of the setting signal generating section 150 is connected to the light source section 72 (see FIG. 3).
The input side of the reference potential supply section 160 is connected to the ground side of a power supply device (not shown). Further, the output side of the reference potential supply section 160 is connected to the light source section 72 (see FIG. 3).
The input side of the power supply potential supply section 170 is connected to the power supply voltage side of a power supply device (not shown). Further, the output side of the power supply potential supply section 170 is connected to the light source section 72 (see FIG. 3).
The functions of each part constituting the signal generation circuit 73 will be explained below.

{Image data expansion section}
The image data expansion unit 111 receives serialized image data from the image processing unit 40. Further, the image data development unit 111 develops and parallelizes the received image data, and divides it into a plurality of chip image data corresponding to each light emitting chip C, respectively. Here, each chip image data includes element image data corresponding to the number of light emitting elements included in the light emitting chip C (128 in this example, as described later). Then, the image data development unit 111 divides the obtained plurality of (15 in this example) chip image data into the above-mentioned eight groups (first group #1 to eighth group #8). Then, a plurality of (in this example, eight) sets of image data are created. Then, the image data development section 111 outputs the plurality of (eight) sets of image data obtained in this way to the lighting time setting section 114. At this time, each of the seven sets of image data corresponding to the first set #1 to the seventh set #7 includes 256 element image data. On the other hand, one set of image data corresponding to the eighth set #8 includes 128 element image data.

{Reference clock generator}
The reference clock generation section 112 includes a PLL circuit (not shown), and operates based on instructions input from the image output control section 30 to generate a standard that serves as a reference for the operation of each section constituting the signal generation circuit 73. Generate a clock signal. Then, the reference clock generation section 112 outputs the reference clock signal generated by itself to the timing generation section 113 and the lighting time setting section 114.

{Timing generator}
The timing generation section 113 operates based on instructions input from the image output control section 30 and the reference clock signal input from the reference clock generation section 112, so that each section constituting the signal generation circuit 73 operates. Generates a timing signal that serves as a reference for starting the operation. Then, the timing generation section 113 outputs the timing signal generated by itself to the lighting time setting section 114, the transfer signal generation section 120, the permission signal generation section 130, and the lighting signal generation section 140. Here, the reference clock signal generated by the reference clock generation section 112 described above is common regardless of the output destination, but the timing signal generated by the timing generation section 113 is unique depending on the output destination. It has become a thing.

{Lighting time setting section}
The lighting time setting section 114 includes a first lighting time setting section 114-1, a second lighting time setting section 114-2, a third lighting time setting section 114-3, and a fourth lighting time setting section 114-4. , a fifth lighting time setting section 114-5, a sixth lighting time setting section 114-6, a seventh lighting time setting section 114-7, and an eighth lighting time setting section 114-8. However, the description of the third lighting time setting section 114-3 to the sixth lighting time setting section 114-6 is omitted in FIG. The first lighting time setting section 114-1 to the eighth lighting time setting section 114-8 correspond to the first group #1 to the eighth group #8 (see FIG. 4) in the light source section 72, respectively. ing.

The first lighting time setting section 114-1 to the eighth lighting time setting section 114-8 receive a reference clock signal from the reference clock generation section 112 and a timing signal from the timing generation section 113, respectively. Ru. Furthermore, the set image data corresponding to the first set #1 is input from the image data development unit 111 to the first lighting time setting unit 114-1. Furthermore, the set image data corresponding to the second set #2 is input from the image data development unit 111 to the second lighting time setting unit 114-2. Although not shown, each of the third lighting time setting section 114-3 to the sixth lighting time setting section 114-6 receives data from the image data development section 111 from the third group #3 to the sixth group #3. Image data for combination corresponding to each of 6 is input. Further, the set image data corresponding to the seventh set #7 is input from the image data development unit 111 to the seventh lighting time setting unit 114-7. The set image data corresponding to the eighth set #8 is input from the image data development unit 111 to the eighth lighting time setting unit 114-8.

Furthermore, these first lighting time setting section 114-1 to eighth lighting time setting section 114-8 set each light emitting element (each pixel ) Create a control signal (assembly control signal) to set the lighting time. The first lighting time setting section 114-1 to the eighth lighting time setting section 114-8 output a total of eight combination control signals created by each of them to the setting signal generation section 150.

{Transfer signal generation section}
The transfer signal generation section 120 includes a first-stage transfer signal generation section 120a and a second-stage transfer signal generation section 120b. Of these, the front-stage transfer signal generating section 120a corresponds to the front-stage light emitting chip group #a in the light source section 72, and the rear-stage transfer signal generating section 120b corresponds to the rear-stage light emitting chip group #b in the light source section 72, respectively. (See Figure 4).

A timing signal for a transfer signal is input from the timing generation section 113 to the first-stage transfer signal generation section 120a and the second-stage transfer signal generation section 120b.

The pre-stage transfer signal generating section 120a generates the pre-stage first transfer signal φ1a and the pre-stage second transfer signal φ2a based on the input timing signal. Then, the pre-stage transfer signal generating section 120a outputs the first pre-stage transfer signal φ1a and the second pre-stage transfer signal φ2a generated by itself to the pre-stage light emitting chip group #a (see FIG. 4) that constitutes the light source section 72. .

On the other hand, the subsequent-stage transfer signal generating section 120b generates the subsequent-stage first transfer signal φ1b and the subsequent-stage second transfer signal φ2b based on the input timing signal. Then, the subsequent-stage transfer signal generation section 120b outputs the subsequent-stage first transfer signal φ1b and the subsequent-stage second transfer signal φ2b generated by itself to the subsequent-stage light emitting chip group #b (see FIG. 4) that constitutes the light source section 72. .

In the following description, the first transfer signal φ1a at the front stage and the first transfer signal φ1b at the rear stage may be collectively referred to as the first transfer signal φ1, if necessary. Furthermore, the first-stage second transfer signal φ2a and the second-stage second transfer signal φ2b may be collectively referred to as a second transfer signal φ2.

{Permission signal generator}
The permission signal generation section 130 includes a first-stage permission signal generation section 130a and a second-stage permission signal generation section 130b. Of these, the front-stage permission signal generating section 130a corresponds to the front-stage light emitting chip group #a in the light source section 72, and the rear-stage permission signal generating section 130b corresponds to the rear-stage light emitting chip group #b in the light source section 72, respectively. (See Figure 4).

A timing signal for a permission signal is input from the timing generation section 113 to the first-stage permission signal generation section 130a and the second-stage permission signal generation section 130b.

The pre-stage permission signal generating section 130a generates the pre-stage permission signal φEa based on the input timing signal. The pre-stage permission signal generating section 130a outputs the pre-stage permission signal φEa generated by itself to the pre-stage light emitting chip group #a (see FIG. 4) that constitutes the light source section 72.

On the other hand, the subsequent-stage permission signal generating section 130b generates the subsequent-stage permission signal φEb based on the input timing signal. Subsequent-stage permission signal generating section 130b outputs the subsequent-stage permission signal φEb generated by itself to subsequent-stage light emitting chip group #b (see FIG. 4) that constitutes light source section 72.

Note that in the following description, the front-stage permission signal φEa and the second-stage permission signal φEb may be collectively referred to as the permission signal φE, if necessary.

{Lighting signal generator}
The lighting signal generation section 140 includes a front stage lighting signal generation section 140a and a rear stage lighting signal generation section 140b. Of these, the front stage lighting signal generating section 140a corresponds to the front stage light emitting chip group #a in the light source section 72, and the rear stage lighting signal generating section 140b corresponds to the rear stage light emitting chip group #b in the light source section 72, respectively. (See Figure 4).

A timing signal for a lighting signal is input from the timing generating section 113 to the preceding stage lighting signal generating section 140a and the subsequent stage lighting signal generating section 140b.

The pre-stage lighting signal generating section 140a generates the pre-stage lighting signal φIa based on the input timing signal. The pre-stage lighting signal generating section 140a outputs the pre-stage lighting signal φIa generated by itself to the pre-stage light emitting chip group #a (see FIG. 4) that constitutes the light source section 72.

On the other hand, the second-stage lighting signal generating section 140b generates the second-stage lighting signal φIb based on the input timing signal. Then, the rear-stage lighting signal generating section 140b outputs the rear-stage lighting signal φIb generated by itself to the rear-stage light emitting chip group #b (see FIG. 4) that constitutes the light source section 72.

In the following description, the front stage lighting signal φIa and the rear stage lighting signal φIb may be collectively referred to as the lighting signal φI, if necessary.

{Setting signal generator}
A total of eight group control signals are input to the setting signal generating section 150 from each of the first lighting time setting section 114-1 to the eighth lighting time setting section 114-8 that constitute the lighting time setting section 114. It's coming. Further, the setting signal generation unit 150 sets the lighting start timing for each group, and creates a setting signal φW that associates the lighting start timing for each group with the group control signal for each group. Here, the setting signal φW is created for each group, and in this example, a total of eight first setting signals φW1 to eight setting signals φW8 are created. Then, the setting signal generating section 150 outputs the setting signal φW generated by itself to the light source section 72. At this time, the setting signal generating section 150 sends the first setting signal φW1 to the first set #1 of the light source section 72, the second setting signal φW2 to the second set #2 of the light source section 72, and the third setting signal φW3. The fourth setting signal φW4 is sent to the third set #3 of the light source unit 72, the fifth setting signal φW5 is sent to the fifth set #5 of the light source unit 72, and the sixth setting signal φW6 is sent to the third set #3 of the light source unit 72. output to the sixth set #6 of the light source section 72, the seventh setting signal φW7 to the seventh set #7 of the light source section 72, and the eighth setting signal φW8 to the eighth set #8 of the light source section 72, respectively. do. However, the description of the third setting signal φW3 to the sixth setting signal φW6 in FIG. 5 is omitted.

{Reference potential supply section}
The reference potential supply unit 160 is set to a potential (reference potential) on the ground side of a power supply device (not shown). Then, the reference potential supply unit 160 supplies a reference potential Vsub (GND potential) having the same potential to a plurality of (15 in this example) light emitting chips C forming the light source unit 72.

{Power supply potential supply section}
The power supply potential supply unit 170 is set to a potential on the power supply voltage side (power supply potential) of a power supply device (not shown). Then, the power supply potential supply unit 170 supplies a power supply potential Vga having the same potential to a plurality of (15 in this example) light emitting chips C forming the light source unit 72.

[Schematic configuration of light emitting chip]
Here, the schematic configuration of the light emitting chip C that constitutes the light source section 72 in the light emitting device 62 will be explained.
FIG. 6 is a top view for explaining the configuration of the light emitting chip C. More specifically, FIG. 6 shows the light emitting chip C when the light emitting device 62 shown in FIG. 3 is viewed from the front side in the figure.

The light emitting chip C includes an element substrate 80, a terminal group 81, and a light emitting section 82. Further, the terminal group 81 includes a φE terminal 81a, a φ1 terminal 81b, a Vga terminal 81c, a φ2 terminal 81d, a φW terminal 81e, a φI terminal 81f, and a Vsub terminal 81g.

The element substrate 80 has a compound semiconductor substrate made of, for example, GaAs, and a plurality of light emitting elements constituting the terminal group 81 and the light emitting section 82 are integrated on this compound semiconductor substrate. In other words, the light emitting chip C is composed of an integrated circuit (IC).
The element substrate 80 has a rectangular shape when viewed from above, and the length in the X direction is longer than the length in the Y direction. Hereinafter, the X direction on the element substrate 80 may be referred to as the longitudinal direction, and the Y direction on the element substrate 80 may be referred to as the lateral direction.

Next, seven terminals (electrodes) forming the terminal group 81 in the light emitting chip C will be explained.
First, the φE terminal 81a, the φ1 terminal 81b, and the Vga terminal 81c are arranged in this order on one end side in the longitudinal direction (upstream side in the X direction) on the surface of the element substrate 80. The φE terminal 81a functions as an input terminal for the enable signal φE, the φ1 terminal 81b functions as an input terminal for the first transfer signal φ1, and the Vga terminal 81c functions as an input terminal for the power supply potential Vga.
Further, the φ2 terminal 81d, the φW terminal 81e, and the φI terminal 81f are arranged in this order on the other longitudinal end side (downstream side in the X direction) of the surface of the element substrate 80. The φ2 terminal 81d functions as an input terminal for the second transfer signal φ2, the φW terminal 81e functions as an input terminal for the setting signal φW, and the φI terminal 81f functions as an input terminal for the lighting signal φI.
Further, the Vsub terminal 81g is provided on the back surface (not shown) of the light emitting chip C over the entire surface thereof. This Vsub terminal 81g functions as an input terminal for the reference potential Vsub.

In the following description, the φE terminal 81a, the φ1 terminal 81b, and the Vga terminal 81c provided at one end of the element substrate 80 may be collectively referred to as a one-end terminal group. Further, the φ2 terminal 81d, the φW terminal 81e, and the φI terminal 81f provided on the other end side of the element substrate 80 may be collectively referred to as the other end side terminal group.

Next, the light emitting section 82 provided in the light emitting chip C will be explained.
The light emitting section 82 is provided on the upper surface of the element substrate 80 between the one end terminal group and the other end terminal group. The light-emitting section 82 is configured by arranging a plurality of (128 in this example) light-emitting elements along the longitudinal direction. In this embodiment, the plurality of light emitting elements constituting the light emitting section 82 are composed of light emitting thyristors having a pnpn structure. Therefore, in the following description, the light emitting element that constitutes the light emitting section 82 will be referred to as a light emitting thyristor. In addition, the 128 light emitting thyristors constituting the light emitting section 82 are listed in order from the upstream side in the X direction: the first light emitting thyristor L1, the second light emitting thyristor L2, the third light emitting thyristor L3, ..., the 126th light emitting thyristor L126. , a 127th light emitting thyristor L127, and a 128th light emitting thyristor L128.
Note that the light emitting chip C has a built-in circuit for controlling the light emission (lighting) of each of the first light emitting thyristor L1 to the 128th light emitting thyristor L128 constituting the light emitting section 82, but the details thereof are as follows. will be described later.

[Electrical connection relationship in light emitting device]
Next, the electrical connections in the light emitting device 62 will be explained. More specifically, the connection relationship between the wiring board 71, the light source section 72, and the signal generation circuit 73 will be explained.

FIG. 7 is a diagram for explaining the configuration of various wirings on the wiring board 71. Here, in addition to the wiring board 71, FIG. 7 also shows a plurality of light emitting chips C constituting the light source section 72 and a signal generation circuit 73. However, regarding the light source section 72, some of the 15 light emitting chips C constituting the light source section 72 (front stage first light emitting chip Ca1 to front stage fifth light emitting chip Ca5 and rear stage first light emitting chip Cb1 to rear stage fifth light emitting chip A total of 10 light emitting chips Cb5) are extracted and shown.

Further, FIG. 8 is a diagram for explaining the electrical connection relationship between the wiring board 71, the light source section 72, and the signal generation circuit 73 in the light emitting device 62 of the first embodiment. Here, FIG. 8 shows the grouping (two groups of front-stage light-emitting chip group #a and the rear-stage light-emitting chip group #b) and grouping (eight groups of first group #1 to eighth group #8) in the light source section 72. It also shows the relationship between However, in FIG. 8, the third group #3 to the sixth group #6 (the third front light emitting chip Ca3 to the sixth front light emitting chip Ca6 constituting the front light emitting chip group #a, and the rear light emitting chip group #b) The description of the constituent third light emitting chip Cb3 to sixth light emitting chip Cb6) is omitted.

The wiring board 71 includes a base material layer 91 made of an insulator, various kinds of wiring made of a conductor such as metal formed on the base material layer 91, and a plurality of (in this example, the number of light emitting chips C) The current limiting resistors RI (same as 15) (see FIG. 7) and a single (one) noise filter 92 (see FIG. 8) are provided.
Here, the wiring board 71 includes a ground wiring 200a and a power supply wiring 200b. Further, the wiring board 71 includes a first transfer wiring 201a on the front side and a first transfer wiring 201b on the rear side. Further, the wiring board 71 includes a first-stage second transfer wiring 202a and a second-stage second transfer wiring 202b. Further, the wiring board 71 includes a front-side permission wiring 203a and a rear-side permission wiring 203b. Further, the wiring board 71 includes a front-stage lighting wiring 204a and a rear-stage lighting wiring 204b.
The wiring board 71 includes a first setting wiring 301, a second setting wiring 302, a third setting wiring 303, a fourth setting wiring 304, a fifth setting wiring 305, and a sixth setting wiring 302. It further includes a setting wiring 306, a seventh setting wiring 307, and an eighth setting wiring 308.
However, in FIG. 8, the description of the ground wiring 200a, the power supply wiring 200b, and each current limiting resistor RI is omitted.

{Noise filter}
The noise filter 92 is mounted on the wiring board 71 so as to be connected in parallel with the preceding eighth light emitting chip Ca8 forming the eighth group #8 among the 15 light emitting chips C forming the light source section 72. . Here, the eighth group #8 to which the front-stage eighth light emitting chip Ca8 belongs is configured such that each of the other first group #1 to seventh group #7 includes two light emitting chips C. The difference is that the structure includes only one light emitting chip C. By adopting such a connection method, the eighth group #8 appears to have two elements (one light emitting chip C and one electric element (noise filter 92)) like the other groups. ).

Here, as the noise filter 92, a passive filter including passive elements such as a capacitor, a coil, and a resistor may be used as long as it is capable of removing the target noise, or a passive filter including various active elements may be used. An active filter may also be used. However, from the viewpoint of simplifying the configuration and suppressing the occurrence of electrostatic damage, it is preferable that the noise filter 92 be configured by a passive element, and further preferably use a capacitor or a coil alone. When a capacitor is used as the noise filter 92, it is preferable to use a capacitor whose capacitance value is set to 5 pF or more.

{Grounding wiring and power wiring}
One end of the ground wiring 200a provided on the wiring board 71 is connected to the output side of the reference potential supply section 160 provided in the signal generation circuit 73. Further, the other end of the grounding wiring 200a is connected in parallel to a Vsub terminal 81g (see FIG. 6) provided in each of all (15) light emitting chips C constituting the light source section 72. A reference potential Vsub is supplied to the ground wiring 200a from a reference potential supply unit 160 provided in the signal generation circuit 73.

One end of the power supply wiring 200b provided on the wiring board 71 is connected to the output side of the power supply potential supply section 170 provided in the signal generation circuit 73. Further, the other end of the power supply wiring 200b is connected in parallel to a Vga terminal 81c (see FIG. 6) provided in each of all (15) light emitting chips C constituting the light source section 72. A power supply potential Vga is supplied to the power supply wiring 200b from a power supply potential supply section 170 provided in the signal generation circuit 73.

{First transfer wiring}
One end of the first forward transfer wiring 201a provided on the wiring board 71 is connected to the output side of the forward transfer signal generating section 120a provided in the signal generating circuit 73. Further, the other end of the first forward-stage transfer wiring 201a is connected to the eight light-emitting chips C (first-stage first light-emitting chip Ca1 to eighth light-emitting chip Ca8) constituting the front-stage light-emitting chip group #a in the light source section 72. They are connected in parallel to the respective φ1 terminals 81b. The first forward transfer signal φ1a is supplied to the first forward transfer wiring 201a from the forward transfer signal generating section 120a provided in the signal generation circuit 73.

One end of the second-stage first transfer wiring 201b provided on the wiring board 71 is connected to the output side of the second-stage transfer signal generation section 120b provided on the signal generation circuit 73. In addition, the other end of the rear-stage first transfer wiring 201b is connected to the seven light-emitting chips C (the rear-stage first light-emitting chip Cb1 to the rear-stage seventh light-emitting chip Cb7) constituting the rear-stage light-emitting chip group #b in the light source section 72. They are connected in parallel to the respective φ1 terminals 81b (see FIG. 6). Then, the second-stage first transfer signal φ1b is supplied to the second-stage first transfer wiring 201b from the second-stage transfer signal generation section 120b provided in the signal generation circuit 73.

{Second transfer wiring}
One end of the first-stage second transfer wiring 202a provided on the wiring board 71 is connected to the output side of the first-stage transfer signal generation section 120a provided in the signal generation circuit 73. Further, the other end of the second forward-stage transfer wiring 202a is connected to the eight light-emitting chips C (first-stage first light-emitting chip Ca1 to eighth light-emitting chip Ca8) forming the front-stage light-emitting chip group #a in the light source section 72. They are connected in parallel to the respective φ2 terminals 81d (see FIG. 6). The pre-stage second transfer signal φ2a is supplied to the pre-stage second transfer wiring 202a from the pre-stage transfer signal generating section 120a provided in the signal generation circuit 73.

One end of the second transfer wiring 202b provided on the wiring board 71 is connected to the output side of the subsequent transfer signal generation section 120b provided in the signal generation circuit 73. Further, the other end of the second transfer wiring 202b on the rear stage side is connected to the seven light emitting chips C (first light emitting chip Cb1 to seventh light emitting chip Cb7 on the rear stage) constituting the rear stage light emitting chip group #b in the light source section 72. They are connected in parallel to the respective φ2 terminals 81d (see FIG. 6). Then, the second subsequent transfer signal φ2b is supplied to the second second transfer wiring 202b from the second transfer signal generation section 120b provided in the signal generation circuit 73.

{Permission wiring}
One end of the upstream permission wiring 203a provided on the wiring board 71 is connected to the output side of the upstream permission signal generation section 130a provided in the signal generation circuit 73. The other end of the front-side permission wiring 203a is connected to each of the eight light-emitting chips C (the first front-stage light-emitting chip Ca1 to the eighth front-stage light-emitting chip Ca8) constituting the front-stage light-emitting chip group #a in the light source section 72. It is connected in parallel to the provided φE terminal 81a (see FIG. 6). The preceding stage permission signal φEa is supplied to the preceding stage permission wiring 203a from the preceding stage permission signal generating section 130a provided in the signal generating circuit 73.

One end of the subsequent-stage permission wiring 203b provided on the wiring board 71 is connected to the output side of the subsequent-stage permission signal generation section 130b provided on the signal generation circuit 73. The other end of the rear-stage permission wiring 203b is connected to each of the seven light-emitting chips C (the first rear-stage light-emitting chip Cb1 to the seventh rear-stage light-emitting chip Cb7) constituting the rear-stage light-emitting chip group #b in the light source section 72. It is connected in parallel to the provided φE terminal 81a (see FIG. 6). The subsequent-stage permission signal φEb is supplied to the subsequent-stage permission wiring 203b from the subsequent-stage permission signal generating section 130b provided in the signal generation circuit 73.

{Wiring for lighting}
One end of the pre-stage lighting wiring 204a provided on the wiring board 71 is connected to the output side of the pre-stage lighting signal generating section 140a provided in the signal generating circuit 73. The other end of the front-stage lighting wiring 204a is connected to each of the eight light-emitting chips C (first-stage first light-emitting chip Ca1 to eighth front-stage light-emitting chip Ca8) constituting the front-stage light-emitting chip group #a in the light source section 72. They are connected in parallel to the provided φI terminal 81f (see FIG. 6) via the respective provided current limiting resistors RI. The preceding stage lighting signal φIa is supplied to the preceding stage lighting wiring 204a from the preceding stage lighting signal generating section 140a provided in the signal generating circuit 73.

One end of the rear-stage lighting wiring 204b provided on the wiring board 71 is connected to the output side of the rear-stage lighting signal generating section 140b provided on the signal generating circuit 73. The other end of the rear-stage lighting wiring 204b is connected to each of the seven light-emitting chips C (the first rear-stage light-emitting chip Cb1 to the seventh rear-stage light-emitting chip Cb7) constituting the rear-stage light-emitting chip group #b in the light source section 72. They are connected in parallel to the provided φI terminal 81f (see FIG. 6) via the respective provided current limiting resistors RI. The subsequent lighting signal φIb is supplied to the subsequent lighting wiring 204b from the subsequent lighting signal generating section 140b provided in the signal generating circuit 73.

{Wiring for first setting}
One end of the first setting wiring 301 provided on the wiring board 71 is connected to the output side of the setting signal generating section 150 provided in the signal generating circuit 73. Further, the other end of the first setting wiring 301 is provided to each of the two light emitting chips C (the first light emitting chip Ca1 at the front stage and the first light emitting chip Cb1 at the rear stage) constituting the first group #1 in the light source section 72. is connected in parallel to the φW terminal 81e (see FIG. 6). A first setting signal φW1 is supplied to the first setting wiring 301 from a setting signal generating section 150 provided in the signal generating circuit 73.

{Second setting wiring}
One end of the second setting wiring 302 provided on the wiring board 71 is connected to the output side of the setting signal generating section 150 provided on the signal generating circuit 73. Further, the other end of the second setting wiring 302 is provided to each of the two light emitting chips C (front stage second light emitting chip Ca2 and rear stage second light emitting chip Cb2) constituting the second group #2 in the light source section 72. is connected in parallel to the φW terminal 81e (see FIG. 6). A second setting signal φW2 is supplied to the second setting wiring 302 from a setting signal generating section 150 provided in the signal generating circuit 73.

{Wiring for third setting}
One end of the third setting wiring 303 provided on the wiring board 71 is connected to the output side of the setting signal generating section 150 provided on the signal generating circuit 73. Further, the other end of the third setting wiring 303 is provided to each of the two light emitting chips C (front third light emitting chip Ca3 and rear third light emitting chip Cb3) constituting the third group #3 in the light source section 72. is connected in parallel to the φW terminal 81e (see FIG. 6). A third setting signal φW3 is supplied to the third setting wiring 303 from a setting signal generating section 150 provided in the signal generating circuit 73.

{Wiring for 4th setting}
One end of the fourth setting wiring 304 provided on the wiring board 71 is connected to the output side of the setting signal generating section 150 provided in the signal generating circuit 73. Further, the other end of the fourth setting wiring 304 is provided to each of the two light emitting chips C (front stage fourth light emitting chip Ca4 and rear stage fourth light emitting chip Cb4) constituting the fourth group #4 in the light source section 72. is connected in parallel to the φW terminal 81e (see FIG. 6). A fourth setting signal φW4 is supplied to the fourth setting wiring 304 from a setting signal generating section 150 provided in the signal generating circuit 73.

{Wiring for 5th setting}
One end of the fifth setting wiring 305 provided on the wiring board 71 is connected to the output side of the setting signal generating section 150 provided on the signal generating circuit 73. Further, the other end of the fifth setting wiring 305 is provided to each of the two light emitting chips C (front stage fifth light emitting chip Ca5 and rear stage fifth light emitting chip Cb5) constituting the fifth group #5 in the light source section 72. is connected in parallel to the φW terminal 81e (see FIG. 6). A fifth setting signal φW5 is supplied to the fifth setting wiring 305 from a setting signal generating section 150 provided in the signal generating circuit 73.

{6th setting wiring}
One end of the sixth setting wiring 306 provided on the wiring board 71 is connected to the output side of the setting signal generating section 150 provided on the signal generating circuit 73. Further, the other end of the sixth setting wiring 306 is provided to each of the two light-emitting chips C (the sixth light-emitting chip Ca6 in the front stage and the sixth light-emitting chip Cb6 in the rear stage) constituting the sixth group #6 in the light source section 72. is connected in parallel to the φW terminal 81e (see FIG. 6). The sixth setting wiring 306 is supplied with a sixth setting signal φW6 from a setting signal generating section 150 provided in the signal generating circuit 73.

{7th setting wiring}
One end of the seventh setting wiring 307 provided on the wiring board 71 is connected to the output side of the setting signal generating section 150 provided on the signal generating circuit 73. Further, the other end of the seventh setting wiring 307 is provided to each of the two light emitting chips C (first stage seventh light emitting chip Ca7 and second stage seventh light emitting chip Cb7) constituting the seventh group #7 in the light source section 72. is connected in parallel to the φW terminal 81e (see FIG. 6). A seventh setting signal φW7 is supplied to the seventh setting wiring 307 from a setting signal generating section 150 provided in the signal generating circuit 73.

{8th setting wiring}
One end of the eighth setting wiring 308 provided on the wiring board 71 is connected to the output side of the setting signal generating section 150 provided on the signal generating circuit 73. Further, the other end of the eighth setting wiring 308 is connected to a φW terminal 81e (see FIG. 6 ) and one end of the noise filter 92. That is, the other end of the eighth setting wiring 308 is connected in parallel to the eighth light emitting chip Ca8 and the noise filter 92 in the previous stage. Note that the other end of the noise filter 92 is connected to a Vsub terminal 81g (see FIG. 6) provided on the light emitting chip C (the eighth light emitting chip Ca8 in the previous stage). The eighth setting wiring 308 is supplied with the eighth setting signal φW8 from the setting signal generating section 150 provided in the signal generating circuit 73.

{Summary of connections}
FIG. 9 is a diagram for explaining the relationship between the light-emitting chips C that are grouped and grouped and make up the light source section 72, and various signals supplied to each light-emitting chip C.
Here, FIG. 9 shows the name of the group to which it belongs, the name of the light-emitting chip C that belongs to each group, the name of the group to which each light-emitting chip C belongs, the setting signal φW supplied to each light-emitting chip C, the permission signal φE, and the number The relationship between the first transfer signal φ1, the second transfer signal φ2, and the lighting signal φI is shown.
Note that since the contents of FIG. 9 are as described above, detailed explanation thereof will be omitted here.

[Circuit configuration of light emitting chip]
Next, the circuit configuration of the above-mentioned light emitting chip C will be explained. Here, in the light source section 72 of the present embodiment, the first light emitting chip Ca1 to the eighth light emitting chip Ca8 (8 pieces) constitute the front light emitting chip group #a, and the rear light emitting chip group #b. The first rear light emitting chip Cb1 to the seventh rear light emitting chip Cb7 (seven pieces) are all composed of light emitting chips C having a common structure.

FIG. 10 is a diagram for explaining the circuit configuration of a self-scanning light emitting device (SLED) provided in the light emitting chip C. Here, in order to facilitate understanding, FIG. 10 exemplifies the first light emitting chip Ca1 as the light emitting chip C, and in addition to the first light emitting chip Ca1, the first light emitting chip Ca1 of the signal generating circuit 73 Components related to driving the light emitting chip Ca1 are extracted and shown.

Here, in the connection between the signal generation circuit 73 and the first light emitting chip Ca1 in the front stage, the front lighting signal generating section 140a provided in the signal generation circuit 73 and the φI terminal 81f provided in the first light emitting chip Ca1 in the front stage are as follows. As described above, they are connected via the current limiting resistor RI. Although details will not be described, the pre-stage lighting signal generating section 140a and each φI terminal 81f provided in the pre-stage second light emitting chip Ca2 to pre-stage eighth light emitting chip Ca8 are connected via a current limiting resistor RI. . Further, the rear-stage lighting signal generating section 140b and each φI terminal 81f provided in the rear-stage first light emitting chip Cb1 to rear-stage seventh light emitting chip Cb7 are connected via a current limiting resistor RI (see also FIG. 7). .

As described above, the light emitting chip C including the first front light emitting chip Ca1 includes the element substrate 80, the terminal group 81, and the light emitting section 82. In addition to these, the light emitting chip C further includes a transition section 83 and a setting section 84. In other words, the light emitting chip C includes the element substrate 80 and the terminal group 81, the light emitting section 82, the transition section 83, and the setting section 84, which are formed on the element substrate 80. In the light emitting chip C, the transition section 83 and the setting section 84 operate in conjunction with each other, so that the light emitting thyristors (first light emitting thyristor L1 to 128th light emitting thyristor L128) constituting the light emitting section 82 emit light (turn on and off). ) is designed to control the behavior. Here, among the elements constituting the light emitting chip C, the element substrate 80 and the terminal group 81 have already been explained, so the light emitting section 82, the transition section 83, and the setting section 84 will be explained in detail here. conduct.

The element substrate 80 constituting the light emitting chip C also includes various wiring such as a power supply line 100, a first transfer signal line 101, a second transfer signal line 102, a setting signal line 103, a lighting signal line 104, a permission signal line, and A ground wire (not shown) is provided.

{Light emitting part}
The light emitting section 82 includes a plurality of light emitting thyristors L1, L2, L3, L4, . . . . In this embodiment, the number of light emitting thyristors constituting the light emitting section 82 is 128 (L1 to L128) as shown in FIG. 6.

In the light emitting section 82, the anodes of the light emitting thyristors L1 to L128 are connected to the Vsub terminal 81g via a ground line (not shown). Further, the cathodes of each of the light emitting thyristors L1 to L128 are connected to the φI terminal 81f via the lighting signal line 104. Further, the gates Gl1 to Gl128 of the respective light emitting thyristors L1 to L128 are connected to the Vga terminal 81c via the respective connecting resistors Rz1 to Rz128 and the power line 100.

{Transition part}
The transition section 83 includes a plurality of transfer thyristors T1, T2, T3, T4, ..., one start diode D0, a plurality of coupling diodes D1, D2, D3, D4, ..., and two current limiting resistors R1, R2. It is equipped with Here, when the number of light emitting thyristors forming the light emitting section 82 is 128, the number of transfer thyristors forming the transition section 83 is 128 (T1 to T128), which is the same as the light emitting thyristors. Further, when the number of light emitting thyristors forming the light emitting section 82 is 128, the number of coupling diodes forming the transition section 83 is 127 (D1 to D127), which is one less than the light emitting thyristor.

In the transition section 83, the anodes of each of the transfer thyristors T1 to T128 are connected to the Vsub terminal 81g via a ground line (not shown). Further, the cathodes of the odd-numbered transfer thyristors T1, T3, . . . , T127 are connected to the φ1 terminal 81b via the first transfer signal line 101 and the current limiting resistor R1. On the other hand, the cathodes of the even numbered transfer thyristors T2, T4, ..., T128 and the anode of the start diode D0 are connected to the φ2 terminal 81d via the second transfer signal line 102 and the current limiting resistor R2. There is. Further, the cathode of the start diode D0 is connected to the gate Gt1 of the first transfer thyristor T1. Further, the anodes of each of the coupling diodes D1 to D127 are connected to the gates Gt1 to Gt127 of each transfer thyristor T1 to T127. Furthermore, the cathodes of the respective coupling diodes D1 to D127 are connected to the gates Gt2 to Gt128 of the respective transfer thyristors T2 to T128.

{Settings section}
The setting section 84 includes one setting permission thyristor S0 and a plurality of setting thyristors S1, S2, S3, S4, . . . . Further, the setting unit 84 sets the plurality of connection resistances Rx1, Rx2, Rx3, Rx4, ..., the plurality of connection resistances Ry1, Ry2, Ry3, Ry4, ..., and the plurality of connection resistances Rz1, Rz2, Rz3, Rz4, ... It is equipped with Further, the setting section 84 includes two current limiting resistors RE and RW. Here, when the number of light emitting thyristors forming the light emitting section 82 is 128, the number of setting thyristors forming the setting section 84 is 128 (S1 to S128), which is the same as the light emitting thyristors. Further, the number of each connection resistance is 128 (Rx1 to Rx128, Ry1 to Ry128, Rz1 to Rz128).

In the setting section 84, the anode of the setting permission thyristor S0 and the anode of each setting thyristor S1 to S128 are connected to the Vsub terminal 81g via a grounding wire (not shown). Further, the cathode of the setting permission thyristor S0 and the cathodes of each of the setting thyristors S1 to S128 are connected to the φW terminal 81e via the setting signal line 103 and the current limiting resistor RW. Furthermore, the gate Gs0 of the setting permission thyristor S0 is connected to the φE terminal 81a via the permission signal line 105 and the current limiting resistor RE. On the other hand, the gates Gs0 to Gs128 of each setting thyristor S1 to S128 are connected to the gates Gt1 to Gt128 of each transfer thyristor T1 to T128 via each connection resistor Rx1 to Rx128, and the gates Gs0 to Gs128 of each setting thyristor S1 to S128 are are connected to the gates Gl1 to Gl128 of the respective light emitting thyristors L1 to L128 via.

Although the explanation has been given here assuming that the connection resistances Rx1 to Rx128, Ry1 to Ry128, and Rz1 to Rz128 are all components of the setting section 84, for example, regarding the connection resistances Rx1 to Rx128, For example, the connection resistors Ry1 to Ry128 and Rz1 to Rz128 can be considered to be components of the light emitting section 82.

[Correspondence]
Here, in this embodiment, the print head 14 is an example of an optical scanning device, and the light emitting device 62 is an example of a light emitting device.
Further, in the present embodiment, the photosensitive drum 12 is an example of an image carrier, the light emitting device 62 is an example of an exposure means, and the rod lens array 63 is an example of an image forming means.
Further, in this embodiment, the SLED provided in each light emitting chip C is an example of an electronic circuit.
Further, in the present embodiment, each of the first set #1 to the seventh set #7 is an example of the first circuit. Therefore, in the case of this embodiment, x=7 and m=2.
Further, in this embodiment, the eighth set #8 is an example of the second circuit. Therefore, in the case of this embodiment, y=1 and n=1.
Further, in this embodiment, 128 light emitting thyristors L1 to L128 provided in each light emitting chip C are an example of light emitting elements.
Further, in this embodiment, the 128 transfer thyristors T1 to T128 and the 128 setting thyristors S1 to S128 provided in each light emitting chip C are examples of control thyristors.
Further, in this embodiment, the wiring board 71 that constitutes the light emitting device 62 is an example of a printed wiring board and a wiring board.
Further, in this embodiment, each light emitting chip C forming the light source section 72 in the light emitting device 62 is an example of a semiconductor integrated circuit.
Further, in this embodiment, the signal generation circuit 73 that constitutes the light emitting device 62 is an example of a signal output circuit.
Further, in this embodiment, the first setting wiring 301 to the seventh setting wiring 307 (7 pieces: x=7) provided on the wiring board 71 are an example of the first wiring. Therefore, the first setting signal φW1 to the seventh setting signal φW7 in the setting signal φW are examples of the first signal.
Further, in this embodiment, the eighth setting wiring 308 (one piece: y=1) provided on the wiring board 71 is an example of the second wiring. Therefore, the eighth setting signal φW8 in the setting signal φW is an example of the second signal.
Further, in this embodiment, the grounding wiring 200a provided on the wiring board 71 is an example of a common wiring.
In this embodiment, the noise filter 92 attached to the wiring board 71 is an example of a noise filter.

[Print head operation]
Now, the operation of the print head 14 executed during the operation of the image forming apparatus 1 described above will be explained.
In the print head 14, a signal generation circuit 73 provided in the light emitting device 62 controls the light emitting (lighting/non-lighting) operation of the light source section 72. At this time, in the light source section 72, the 128 light emitting thyristors L1 to L128 (1920 light emitting thyristors in total) provided in each of the 15 light emitting chips C constituting the light source section 72 are activated in the main scanning direction (X lighting/non-lighting is set for each line (direction). Of the 1,920 thyristors that make up the light source section 72, the light output from the light-emitting thyristor set to the lit state is irradiated onto the photoreceptor drum 12 via the rod lens array 63 in an image-formed state. Ru. By repeating such operations, an electrostatic latent image is formed on the surface of the photosensitive drum 12 rotating along the sub-scanning direction (Y direction).

[Operation of light emitting device]
Next, the operation of the light emitting device 62, which is executed during the operation of the print head 14 described above, will be explained.

In the signal generation circuit 73 provided in the light emitting device 62, the power supply potential supply section 170 and the reference potential supply section 160 connect all (15) light emitting chips C (first stage first light emitting chip Ca1 to front stage) constituting the light source section 72. The power supply potential Vga is supplied to each of the eighth light emitting chip Ca8 and the first to second light emitting chips Cb1 to seventh light emitting chip Cb7.

Further, in the signal generation circuit 73, a pre-stage transfer signal generation section 120a and a reference potential supply section 160 provided in the transfer signal generation section 120 are used to control the eight light-emitting chips C constituting the pre-stage light-emitting chip group #a in the light source section 72. The first front-stage transfer signal φ1a and the second front-stage transfer signal φ2a are supplied to each of the first light-emitting chip Ca1 to the eighth front-stage light emitting chip Ca8.
Furthermore, in the signal generation circuit 73, the subsequent stage transfer signal generating section 120b and the reference potential supply section 160 provided in the transfer signal generating section 120 are used to control the seven light emitting chips C constituting the second stage light emitting chip group #b in the light source section 72. The first subsequent transfer signal φ1b and the second second transfer signal φ2b are supplied to each of the first second light emitting chip Cb1 to the seventh second light emitting chip Cb7.

In addition, in the signal generation circuit 73, the pre-stage permission signal generation section 130a and the reference potential supply section 160 provided in the permission signal generation section 130 are used to control the eight light-emitting chips C constituting the pre-stage light-emitting chip group #a in the light source section 72. A pre-stage enable signal φEa is supplied to each of (first pre-stage light emitting chip Ca1 to eighth pre-stage light emitting chip Ca8).
Furthermore, in the signal generation circuit 73, the rear-stage permission signal generation section 130b and the reference potential supply section 160 provided in the permission signal generation section 130 are used to generate the seven light-emitting chips C constituting the rear-stage light-emitting chip group #b in the light source section 72. A subsequent-stage enable signal φEb is supplied to each of the second-stage first light-emitting chip Cb1 to the second-stage seventh light-emitting chip Cb7.

Further, in the signal generation circuit 73, a pre-stage lighting signal generation section 140a and a reference potential supply section 160 provided in the lighting signal generation section 140 are used to control the eight light-emitting chips C constituting the pre-stage light-emitting chip group #a in the light source section 72. A pre-stage lighting signal φIa is supplied to each of (pre-stage first light emitting chip Ca1 to pre-stage eighth light emitting chip Ca8).
Further, in the signal generation circuit 73, a rear-stage lighting signal generation section 140b and a reference potential supply section 160 provided in the lighting signal generation section 140 are connected to the seven light-emitting chips C constituting the rear-stage light-emitting chip group #b in the light source section 72. A rear stage lighting signal φIb is supplied to each of the rear stage first light emitting chip Cb1 to the rear stage seventh light emitting chip Cb7.

The signal generating circuit 73 also receives group control signals (first group control signals to eighth group control signals) inputted from the first lighting time setting section 114-1 to the eighth lighting time setting section 114-8, respectively. The setting signal generating section 150 generates the first setting signal φW1 to the eighth setting signal φW8 based on the control signal). The setting signal generating section 150 and the reference potential supplying section 160 supply signals to the two light emitting chips C (the first light emitting chip Ca1 at the front stage and the first light emitting chip Cb1 at the rear stage) constituting the first group #1 in the light source section 72. , supplies the first setting signal φW1. Further, the setting signal generation section 150 and the reference potential supply section 160 are connected to the two light emitting chips C (first stage second light emitting chip Ca2, second stage second light emitting chip Cb2) constituting the second group #2 in the light source section 72. , supplies the second setting signal φW2. Further, the setting signal generating section 150 and the reference potential supplying section 160 are connected to the two light emitting chips C (first stage third light emitting chip Ca3, second stage third light emitting chip Cb3) constituting the third group #3 in the light source section 72. , supplies the third setting signal φW3. Further, the setting signal generating section 150 and the reference potential supplying section 160 are connected to the two light emitting chips C (first stage fourth light emitting chip Ca4, second stage fourth light emitting chip Cb4) constituting the fourth group #4 in the light source section 72. , supplies the fourth setting signal φW4. Further, the setting signal generation section 150 and the reference potential supply section 160 are connected to the two light emitting chips C (first stage fifth light emitting chip Ca5, second stage fifth light emitting chip Cb5) constituting the fifth group #5 in the light source section 72. , supplies the fifth setting signal φW5. Further, the setting signal generation section 150 and the reference potential supply section 160 are connected to the two light emitting chips C (first stage sixth light emitting chip Ca6, second stage sixth light emitting chip Cb6) constituting the sixth group #6 in the light source section 72. , supplies the sixth setting signal φW6. Further, the setting signal generating section 150 and the reference potential supplying section 160 are connected to the two light emitting chips C (the seventh light emitting chip Ca7 at the front stage and the seventh light emitting chip Cb7 at the rear stage) constituting the seventh group #7 in the light source section 72. , supplies the seventh setting signal φW7. Then, the setting signal generating section 150 and the reference potential supplying section 160 supply the eighth setting signal φW8 to one light emitting chip C (previous stage eighth light emitting chip Ca8) constituting the eighth group #8 in the light source section 72. supply.

Here, the signal generation circuit 73 generates a setting signal φW (first setting signal φW1 to eighth setting signal φW8), an enable signal φE (first stage enable signal φEa, second stage enable signal φEb), a first transfer signal φ1 (first stage first stage enable signal φEb), and a first transfer signal φ1 (first stage first stage enable signal φEb). transfer signal φ1a, second stage first transfer signal φ1b), second transfer signal φ2 (first stage second transfer signal φ2a, second stage second transfer signal φ2b), and lighting signal φI (first stage lighting signal φIa, second stage lighting signal φIb). By setting using a known method (for example, see Patent Document 1), it is possible to light up a target light-emitting thyristor among the plurality of (1920 in this example) light-emitting thyristors that constitute the light source section 72. It becomes like this.

At this time, in this embodiment, the 15 light-emitting chips C constituting the light source section 72 are divided into two groups (front-stage light-emitting chip group #a, rear-stage light-emitting chip group #b), and eight Since these 15 light emitting chips C are driven in a matrix by dividing into groups (first group #1 to eighth group #8), these 15 light emitting chips C are individually driven. The number of wires (more specifically, the number of wires for supplying various signals) provided on the wiring board 71 that connects the signal generation circuit 73 and the light source section 72 is reduced compared to the case of the present invention. becomes possible.

[EMC test]
Next, the EMC (Electromagnetic Compatibility) test will be explained.
The image forming apparatus 1 equipped with the print head 14 of this embodiment is generally used by a person. The electromagnetic noise immunity test for electronic equipment against electrostatic discharge (ESD) generated from a charged human body is based on International Electrotechnical Committee (IEC) 61000-4-2 (hereinafter referred to as IEC 61000-4-2). 4-2). This ESD test simulates the phenomenon in which ESD from a metal object held by a human body affects electronic devices placed on a table or on the floor. The light emitting device 62 constituting the print head 14 is required to pass IEC 61000-4-2.

FIG. 11 is a diagram for explaining the current flowing through each set forming the light source section 72 when the light emitting device 62 forming the print head 14 is tested according to IEC 61000-4-2.

(For the 1st group)
FIG. 11(a) shows that when the print head 14 (light emitting device 62) is tested according to IEC 61000-4-2, the first light emitting chip Ca1 in the front stage and the first light emitting chip Ca1 in the rear stage of the light source section 72. FIG. 3 is a diagram for explaining the current flowing through the first set #1 configured by Cb1.

When a test voltage Vs of about several kV is applied to the first set #1, a test current Is flows through the first set #1 via the first setting wiring 301 and the grounding wiring 200a. Here, in the first set #1, since the first light emitting chip Ca1 in the front stage and the first light emitting chip Cb1 in the rear stage are connected in parallel, the first light emitting chip Ca1 in the front stage receives the front chip current Isa, and the first light emitting chip Ca1 in the rear stage A subsequent chip current Isb flows through each of the light emitting chips Cb1. At this time, "test current Is=front-stage chip current Isa+second-stage chip current Isb". In this example, since the first light emitting chip Ca1 in the front stage and the first light emitting chip Cb1 in the rear stage have a common structure, the front chip current Isa≒back chip current Isb≒test current Is/2. Become.

Although the details will not be explained, the other six groups (specifically, the second group #2 to the seventh group #7), which are made up of two light emitting chips C, are also similar to the first group described above. Similar to #1, the test current Is is divided into the front-stage chip current Isa and the rear-stage chip current Isb, and the front-stage chip current Isa and the rear-stage chip current Isb are approximately equal.

(For group 8)
FIG. 11(b) shows that when the print head 14 (light emitting device 62) is tested according to IEC 61000-4-2, the eighth light emitting chip Ca8 in the front stage and the noise filter 92 in the light source section 72 FIG. 8 is a diagram for explaining the current flowing through the eighth set #8.

When the test voltage Vs of several kV, which is the same as that of the first set #1, is applied to the eighth set #8, the test voltage Vs is applied to the eighth set #8 via the eighth setting wiring 308 and the grounding wiring 200a. Then, the test current Is flows. Here, in the eighth set #8, the pre-stage eighth light-emitting chip Ca8 and the noise filter 92 are connected in parallel, so the pre-stage chip current Isa is applied to the pre-stage eighth light-emitting chip Ca8, and the noise filter 92 receives the pre-stage chip current Isa. Branch currents Isc flow respectively. At this time, "test current Is=previous chip current Isa+filter branch current Isc". Further, in this example, when a capacitor is used as the noise filter 92 and the capacitance value of this capacitor is about 5 pF, the pre-chip current Isa≒chip branch current Isc≒test current Is/2.

(For conventional 8th group)
Here, in the conventional print head 14 (light-emitting device 62), one light-emitting chip C constituting the eighth group #8 was allowed to exist alone without being connected to the noise filter 92.
FIG. 11(c) shows that when the conventional print head 14 (light emitting device 62) is tested according to IEC 61000-4-2, the light source section 72 is composed of only the eighth light emitting chip Ca8 in the front stage. FIG. 8 is a diagram for explaining the current flowing through the eighth set #8.

When a test voltage Vs of about several kV, which is the same as that of the first group #1 described above, is applied to the conventional eighth group #8, the eighth setting wiring 308 and the grounding wire 308 are applied to the conventional eighth group #8. A test current Is flows through the wiring 200a. Here, in the conventional eighth group #8, since the front-stage eighth light-emitting chip Ca8 is connected alone, the test current Is flows directly through the front-stage eighth light-emitting chip Ca8.

Therefore, when testing according to IEC61000-4-2, the eighth light-emitting chip Ca8 in the front stage that constitutes the eighth group #8 in FIG. 11(c) has the eighth group #8 in FIG. A larger current flows than in the preceding eighth light emitting chip Ca8. As a result, it can be said that the pre-stage eighth light emitting chip Ca8 constituting the conventional eighth group #8 is susceptible to failure due to overcurrent flowing in the IEC 61000-4-2 test.

On the other hand, in this embodiment, unlike the first set #1 to the seventh set #7 in which two light emitting chips C constitute one set, only one light emitting chip C constitutes one set. In the eighth set #8, by connecting the noise filter 92 in parallel to the light emitting chip C (the eighth light emitting chip Ca8 in the previous stage), the current flowing through one light emitting chip C can be reduced in the IEC 61000-4-2 test. It becomes possible to reduce the size. As a result, in the IEC 61000-4-2 test, it is possible to suppress the occurrence of a situation in which the eighth light-emitting chip Ca8 in the preceding stage is likely to fail.

<Embodiment 2>
In the first embodiment, in the wiring board 71 of the light emitting device 62, the noise filter 92 is connected in parallel to one light emitting chip C (previous eighth light emitting chip Ca8) constituting the eighth group #8. Ta. In other words, an electronic component called a noise filter 92 is mounted on the wiring board 71. In contrast, in this embodiment, the function of a noise filter (capacitor) is realized by utilizing the shapes of various wiring patterns formed on the base material layer 91 of the wiring board 71 instead of mounting electronic components. This is what I did. Note that in this embodiment, the same parts as in Embodiment 1 are given the same reference numerals, and detailed explanation thereof will be omitted.

[Electrical connection relationship in light emitting device]
FIG. 12 is a diagram for explaining the electrical connection relationship between the wiring board 71, the light source section 72, and the signal generation circuit 73 in the light emitting device 62 of the second embodiment. Here, FIG. 12 shows the grouping (two groups of front-stage light-emitting chip group #a and the rear-stage light-emitting chip group #b) and grouping (eight groups of first group #1 to eighth group #8) in the light source section 72. It also shows the relationship between However, in FIG. 12, the third group #3 to the sixth group #6 (the third front light emitting chip Ca3 to the sixth front light emitting chip Ca6 constituting the front light emitting chip group #a, and the rear light emitting chip group #b) The description of the constituent third light emitting chip Cb3 to sixth light emitting chip Cb6) is omitted.

The basic configuration of the light emitting device 62 in this embodiment is the same as that described in Embodiment 1 (see FIG. 8). However, as described above, the eighth set #8 does not include the noise filter 92, in other words, the eighth set #8 is composed only of the light emitting chip C (the eighth light emitting chip Ca8 in the previous stage). This is different from the first embodiment in this point.

FIG. 13 is a diagram for explaining the relationship between each setting wiring (first setting wiring 301 to eighth setting wiring 308) and grounding wiring 200a in wiring board 71 of the second embodiment.

In the example shown in FIG. 13, the wiring board 71 is constituted by, for example, a so-called double-sided board, and the first setting wiring 301 to the eighth setting wiring 308 are arranged on one surface (upper surface) of the base material layer 91. Furthermore, grounding wiring 200a is provided on the other surface (lower surface) of the base material layer 91, respectively. Furthermore, while the grounding wiring 200a is formed on substantially the entire lower surface of the base layer 91, the first setting wiring 301 to the eighth setting wiring 308 are substantially parallel to the upper surface of the base material layer 91. They are arranged in such a way that

Among the first setting wiring 301 to the eighth setting wiring 308, the widths of the first setting wiring 301 to the seventh setting wiring 307 are approximately equal, whereas The width of the wiring 308 is larger (wider) than the first setting wiring 301 to the seventh setting wiring 307. In other words, the eighth setting wiring 308 has a larger area facing the grounding wiring 200a than the first setting wiring 301 to the seventh setting wiring 307.

In the wiring board 71, by making the first setting wiring 301 to the eighth setting wiring 308 and the grounding wiring 200a have the above-mentioned positional relationship and shape, the first setting wiring 301 to the seventh setting wiring 307 can be connected to each other. The electrostatic capacitance values (stray capacitances) generated between the ground wiring 200a and the ground wiring 200a are approximately equal. On the other hand, the capacitance value (stray capacitance) generated between the eighth setting wiring 308 and the grounding wiring 200a is larger than these.

Here, in this embodiment, the capacitance values generated between the first setting wiring 301 to the seventh setting wiring 307 and the grounding wiring 200a correspond to the first capacitance. , the capacitance value generated between the eighth setting wire 308 and the grounding wire 200a corresponds to the second capacitance.

As a result, a capacitor with a larger capacitance than the other groups (first group #1 to seventh group #7) appears to be connected in parallel to the front-stage eighth light emitting chip Ca8 constituting the eighth group #8. Becomes connected. As a result, as in the first embodiment, it is possible to suppress the occurrence of a situation in which the eighth light-emitting chip Ca8 in the front stage is likely to fail in the IEC 61000-4-2 test.

<Others>
Note that in the first and second embodiments described above, the element substrate 80 constituting each light emitting chip C (Ca1 to Ca8 and Cb1 to Cb7) is a light emitting circuit (self-contained) including a light emitting section 82, a transition section 83, and a setting section 84. Although the case where one scanning light emitting element array (scanning type light emitting element array) is provided has been described, the present invention is not limited to this. For example, each of the element substrates 80 constituting each light emitting chip C may be provided with a plurality of (for example, two) light emitting circuits.

Furthermore, in the first and second embodiments described above, the number of light emitting chips Cb1 constituting the light source section 72 is 15, and the number of light emitting chips C constituting the pre-stage light emitting chip group #a is eight (Ca1 to Ca8). The number of light emitting chips C constituting the rear stage light emitting chip group #b was set to seven (Cb1 to Cb7). In addition, these 15 light-emitting chips C are divided into eight groups, and each group is made up of two light-emitting chips C for the seven groups 1st group #1 to 7th group #7, and the 8th group #8 is divided into 8 groups. Each of these groups was made up of one light emitting chip C. However, it is not limited to this.

For example, the number of light emitting chips C constituting the light source section 72 may be other than 15 (an even number or an odd number may be used). Further, the number of groups constituting the light source section 72 can be other than 2 (3 or more). Furthermore, the number of pairs constituting the light source section 72 can be other than 8 (it may be 7 or less or 9 or more).

Generalizing the above-mentioned matters, this embodiment includes x sets (x is an integer of 1 or more) each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements. a first circuit of a set of y (where y is an integer of 1 or more) comprising n electronic circuits (n is an integer of 1 or more but less than m); and a first circuit of a set of x x first wirings that supply a first signal to each of the circuits; y second wirings that supply a second signal to each of the y sets of second circuits; It can be applied to a light emitting device that includes a common wiring that is commonly connected to the circuit and the second circuit of the y group, and a noise filter that is connected between the common wiring and the second wiring of the y group. be.

Further, in the first embodiment described above, among the eight groups constituting the light source section 72, the eighth group #8 having one light emitting chip C is provided with the noise filter 92, while the noise filter 92 is provided in the eighth group #8 having one light emitting chip C. Although the noise filter 92 is not provided in the first set #1 to the seventh set #7 having the above, the present invention is not limited to this. For example, the noise filter 92 may be provided in all groups (first group #1 to eighth group #8). In this case, the noise filters 92 provided in the first group #1 to the seventh group #7 may be different from the noise filters 92 provided in the eighth group #8. Specifically, when using a capacitor as the noise filter 92, for example, the capacitance value of the capacitor provided in the 8th group #8 is the capacitance value of the capacitor provided in the 1st group #1 to the 7th group #7. You can make it larger than .

DESCRIPTION OF SYMBOLS 1... Image forming device, 14... Print head, 61... Housing, 62... Light emitting device, 63... Rod lens array, 71... Wiring board, 72... Light source part, 73... Signal generation circuit, 91... Base material layer, 92... Noise filter, 200a... Wiring for grounding, 200b... Wiring for power supply, 201a... Wiring for first transfer on the former stage side, 201b... Wiring for first transfer on the latter stage side, 202a... Wiring for second transfer on the former stage side, 202b... Wiring for second transfer on the latter stage side 2 transfer wiring, 203a... Wiring for front side permission, 203b... Wiring for back side permission, 204a... Wiring for front side lighting, 204b... Wiring for back side lighting, 301... Wiring for first setting, 302... Second setting 303... Wiring for third setting, 304... Wiring for fourth setting, 305... Wiring for fifth setting, 306... Wiring for sixth setting, 307... Wiring for seventh setting, 308... Wiring for eighth setting. , C... light emitting chip, #a... front light emitting chip group, #b... rear light emitting chip group, #1... first group, #2... second group, #3... third group, #4... fourth group, #5...5th group, #6...6th group, #7...7th group, #8...8th group

Claims (11)

x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements;
a y-set (y is an integer of 1 or more) of second circuits comprising n electronic circuits (n is an integer of 1 or more and less than m);
x first wirings that supply a first signal to each of the x sets of first circuits;
y second wirings that supply a second signal to each of the y sets of second circuits;
a common wiring commonly connected to the x group of the first circuits and the y group of the second circuits;
a noise filter connected between the common wiring and y of the second wirings ;
A light emitting device characterized in that a noise filter is not provided between the common wiring and the x number of first wirings . The light emitting device according to claim 1, wherein the noise filter includes a capacitor or a coil. 3. The light emitting device according to claim 2, wherein the noise filter includes a capacitor, and the capacitor has a capacitance of 5 pF or more. A printed wiring board in which the common wiring, x number of the first wirings, and y number of the second wirings are formed as a wiring pattern;
The plurality of electronic circuits are configured of semiconductor integrated circuits and are mounted on the printed wiring board,
The light emitting device according to claim 1, wherein the noise filter is mounted on the printed wiring board. Mounted on the printed wiring board, the common wiring is connected to the x number of the first wirings and the y number of the second wirings, via the common wiring and the x number of the first wirings, The first signal is output to each of the x sets of the first circuits, and the second signal is output to each of the y sets of the second circuits via the common wiring and y of the second wirings. 5. The light emitting device according to claim 4, further comprising a signal output circuit. 2. The light-emitting device according to claim 1, wherein each of the electronic circuits has a plurality of light-emitting thyristors as the light-emitting elements, and further includes a plurality of control thyristors that control lighting of the plurality of light-emitting thyristors. The first signal is outputted to the control thyristor provided in the electronic circuit constituting the x group of the first circuits through the common wiring and the first wiring, and the y group of the second circuits is connected to the control thyristor. 7. The light emitting device according to claim 6, wherein the control thyristor provided in the electronic circuit is further provided with a signal output circuit that outputs the second signal via the common wiring and the second wiring. Device. x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements;
a y-set (y is an integer of 1 or more) of second circuits comprising n electronic circuits (n is an integer of 1 or more and less than m);
x first wirings that supply signals to each of the x sets of the first circuits; y second wirings that supply signals to each of the y sets of the second circuits; a common wiring commonly connected to the first circuit and the second circuit of the y group, and a wiring board to which the first circuit of the x group and the second circuit of the y group are attached. ,
The second capacitance, which is the capacitance between the second wiring and the common wiring, is larger than the first capacitance, which is the capacitance between the first wiring and the common wiring. Also big,
In the wiring board, the light emitting device is characterized in that the area of the second wiring is larger than the area of the first wiring . x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements;
a y-set (y is an integer of 1 or more) of second circuits comprising n electronic circuits (n is an integer of 1 or more and less than m);
x first wirings that supply signals to each of the x sets of the first circuits; y second wirings that supply signals to each of the y sets of the second circuits; A wiring board provided with a common wiring that is commonly connected to the first circuit of the group and the second circuit of the group y, and to which the first circuit of the group x and the second circuit of the group y are attached;
Equipped with
The second capacitance, which is the capacitance between the second wiring and the common wiring, is larger than the first capacitance, which is the capacitance between the first wiring and the common wiring. Also large,
the common wiring and the second wiring are connected via a capacitor ,
A light emitting device characterized in that the common wiring and the first wiring are not connected via a capacitor . x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements; n is an integer of 1 or more and less than m), and supplies the first signal to each of y sets (y is an integer of 1 or more) of second circuits and x sets of the first circuits. y number of first wirings, y number of second wirings that supply a second signal to each of y sets of the relevant second circuits, x sets of the relevant first circuits, and y sets of the relevant second circuits. an exposure means for exposing an image carrier to light using a plurality of said light emitting elements, comprising a common wiring connected in common and a noise filter connected between said common wiring and y said second wirings; ,
an imaging means for forming an image of the light output from the exposure means on the image carrier;
An optical scanning device characterized in that a noise filter is not provided between the common wiring and the x number of first wirings . x sets (x is an integer of 1 or more) of first circuits each including m electronic circuits (m is an integer of 2 or more) each having a plurality of light emitting elements; n is an integer greater than or equal to 1 and less than m), y sets (y is an integer greater than or equal to 1) of second circuits, and x sets of x circuits that supply signals to each of the first circuits. A first wiring, y second wirings that supply signals to each of the y groups of the second circuits, and are commonly connected to the x group of the first circuits and the y group of the second circuits. and a wiring board to which x sets of the first circuits and y sets of the second circuits are attached, and a capacitance between the second wiring and the common wiring. 2. The size of the capacitance is set to be larger than the first capacitance that is the capacitance between the first wiring and the common wiring, and the image carrier is exposed using a plurality of the light emitting elements. an exposure means for
an imaging means for forming an image of the light output from the exposure means on the image carrier;
An optical scanning device characterized in that, in the wiring board, the area of the second wiring is larger than the area of the first wiring .