JP5653669B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and more particularly to a technique for suppressing variation in gate-source capacitance of a thin film transistor disposed for each pixel.

  In a conventional liquid crystal display device, a thin film transistor and a storage capacitor (storage capacitor) connected in parallel to a pixel electrode are formed for each pixel, the thin film transistor is used as a switching element, and the thin film transistor is turned off from the on period to the next on period. A structure in which a desired grayscale voltage is applied to the pixel electrode by holding the charge in the period (one frame period) in the storage capacitor.

  As a liquid crystal display device having such a configuration, Patent Document 1 discloses a technique in which two thin film transistors are formed for each pixel and the formation positions thereof are orthogonal to each other across the corners of the pixel electrodes. The technique described in Patent Document 1 makes it possible to form two thin film transistors with an area equivalent to that of a conventional thin film transistor formation region.

Japanese Patent Laid-Open No. 5-241197

  In a liquid crystal display device mounted on a portable information terminal such as a cellular phone, an increase in the number of pixels and an improvement in display luminance are made due to a demand for higher definition and higher image quality. In particular, in portable information terminals and the like, the size of the housing is limited, so as the number of pixels increases, the area occupied by one pixel decreases, and the aperture ratio and transmittance of each pixel improve. Is desired. For this reason, in the conventional liquid crystal display device, as shown in Patent Document 1, a reduction in the pixel area is suppressed by reducing the area of a region that does not contribute to display by thinning the drain line or the gate line. In addition, the area of the thin film transistor in each pixel region is reduced, and the transmittance in the transmission region of each pixel is improved. As a technique for improving the transmittance, an insulating film in a region where a pixel electrode is formed is thinned.

  A conventional liquid crystal display device such as an IPS system has a configuration in which a storage capacitor is formed by a pixel electrode and a common electrode that are arranged so as to overlap with an insulating film interposed therebetween. For this reason, the capacitance value of the storage capacitor is reduced by reducing the thickness of the insulating film formed between the pixel electrode and the common electrode and reducing the pixel area. In particular, regarding the relationship between the jump voltage (feedthrough voltage) and the holding capacitor, the smaller the holding capacitor, the relatively larger the gate-source capacitance of the thin film transistor, and the holding voltage margin (margin) with respect to the jump voltage is increased. There is a concern that when the insulating film is further thinned to improve the transmittance, flicker due to the jump voltage occurs and display quality is deteriorated.

  Since the gate-source capacitance of the thin film transistor is proportional to the overlapping area of the semiconductor layer and the source electrode, it may be possible to reduce the overlapping area of the semiconductor layer and the source electrode, but the driving capability of the thin film transistor is reduced. There is a problem. Further, it is known that the gate-source capacitance varies due to the interlayer shift caused by the alignment accuracy when forming the semiconductor layer and the source electrode. For this reason, in the conventional liquid crystal display device, it is necessary to reduce the thickness of the insulating film in consideration of the variation in gate-source capacitance due to the interlayer shift. In order to further reduce the thickness of the insulating film and improve the transmittance, Therefore, there is a strong demand for a technique that can suppress variations in gate-source capacitance due to interlayer displacement.

  The liquid crystal display panel described in Patent Document 1 aims to improve pixel defects due to manufacturing defects of thin film transistors. What is the relationship between the gate-source capacitance and the storage capacitance due to interlayer displacement and the influence of the jump voltage? It has not been taken into account, nor is it described.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a technique capable of suppressing variations in gate-source capacitance of a thin film transistor in a manufacturing process.

In order to solve the above problem, a drain line extending in the X direction and juxtaposed in the Y direction, a gate line extending in the Y direction and juxtaposed in the X direction, the drain line and the gate line A pixel electrode formed for each of the enclosed pixel regions; and a thin film transistor formed for each of the pixel regions and supplying a video signal from the drain line to the pixel electrode in response to a scanning signal from the gate line. The thin film transistor includes a first corner and a second corner formed at diagonal positions, a first side on which the first corner is formed, and the second side. A semiconductor layer formed to overlap with a gate electrode connected to the gate line through a gate insulating film, and a third corner sharing a second side where the corner is formed; A portion of the drain line is formed to extend from the drain line. A drain electrode that overlaps with the third corner, a first source electrode that has one end overlapped with the first corner of the semiconductor layer, and the other end connected to the pixel electrode; A second source electrode having one end overlapped with the second corner of the semiconductor layer and the other end connected to the pixel electrode , the first and second source electrodes having one end have two or more corners on the side, is a display device in which only each of the one corner of the first and second source electrodes Ru is overlapped with the first and second corners of said semiconductor layer .

  According to the present invention, variation in gate-source capacitance of a thin film transistor in a manufacturing process can be suppressed.

  Other effects of the present invention will become apparent from the description of the entire specification.

It is a figure for demonstrating the whole structure of the liquid crystal display device which is a display apparatus of Embodiment 1 of this invention. It is a top view for demonstrating schematic structure for 1 pixel in the liquid crystal display device of Embodiment 1 of this invention. FIG. 3 is a cross-sectional view taken along line a-a ′ illustrated in FIG. 2. It is a figure for demonstrating the detailed structure of the thin-film transistor in the liquid crystal display device of the conventional Embodiment 1. FIG. It is a figure for demonstrating the detailed structure of the thin-film transistor in the liquid crystal display device of Embodiment 1 of this invention. It is a figure for demonstrating schematic structure of the liquid crystal display device which is a display apparatus of Embodiment 2 of this invention. It is a figure for demonstrating schematic structure of the liquid crystal display device which is a display apparatus of Embodiment 3 of this invention. It is a figure for demonstrating schematic structure of the liquid crystal display device which is a display apparatus of Embodiment 4 of this invention. It is a figure for demonstrating schematic structure of the thin-film transistor in the liquid crystal display device which is a display apparatus of Embodiment 5 of this invention.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. However, in the following description, the same components are denoted by the same reference numerals, and repeated description is omitted. Further, X, Y, and Z shown in the figure indicate an X axis, a Y axis, and a Z axis, respectively.

<Embodiment 1>
<overall structure>
FIG. 1 is a diagram for explaining the overall configuration of a liquid crystal display device that is a display device according to a first embodiment of the present invention. Hereinafter, the overall configuration of the display device according to the first embodiment will be described with reference to FIG. However, in the following description, a case where the present invention is applied to a liquid crystal display device called an IPS (IPS-Lite) method or a horizontal electric field method will be described. However, an IPS-Pro liquid crystal display device, a VA method, etc. The present invention can also be applied to a TN liquid crystal display device.

  As shown in FIG. 1, in the liquid crystal display device of Embodiment 1, a first substrate SUB1 on which pixel electrodes and the like are formed, a color filter and a black matrix (not shown) are formed, and are arranged to face the first substrate SUB1. A liquid crystal display panel PNL composed of a second substrate SUB2 and a liquid crystal layer (not shown) sandwiched between the first substrate SUB1 and the second substrate SUB2, and a back (not shown) serving as a light source of the liquid crystal display panel PNL A liquid crystal display device is configured by combining with a light unit (backlight device). The first substrate SUB1 and the second substrate SUB2 are fixed and the liquid crystal is sealed with a sealing material SL applied to the periphery of the second substrate in an annular shape, and the liquid crystal is also sealed. Further, the second substrate SUB2 has a smaller area than the first substrate SUB1, and the lower side of the first substrate SUB1 in the drawing is exposed. A drive circuit DR composed of a semiconductor chip is mounted on the side of the first substrate SUB1. This drive circuit DR drives each pixel in the display area AR described in detail later. In the following description, the liquid crystal display panel PNL is also referred to as a liquid crystal display device.

  In addition, as the first substrate SUB1 and the second substrate SUB2, for example, a well-known glass substrate is generally used as a base material. However, the substrate is not limited to the glass substrate, and is not limited to quartz glass or plastic (resin). Other insulating substrates such as For example, when quartz glass is used, since the process temperature can be increased, a gate insulating film of a thin film transistor TFT described later can be densified, so that reliability can be improved. On the other hand, when a plastic (resin) substrate is used, a liquid crystal display device that is lightweight and excellent in impact resistance can be provided.

  In the liquid crystal display device according to the first embodiment, a region where display pixels (hereinafter abbreviated as pixels) are formed in a region in which liquid crystal is sealed becomes a display region AR. Therefore, even in the region where the liquid crystal is sealed, a region where pixels are not formed and which is not involved in display is not the display region AR.

  In the liquid crystal display device according to the first embodiment, a scanning signal line (gate line) that extends in the X direction in FIG. 1 and is arranged in parallel in the Y direction in the display area AR on the liquid crystal side surface of the first substrate SUB1. GL is formed. Further, a video signal line (drain line) DL extending in the Y direction in FIG. 1 and arranged in parallel in the X direction is formed. A rectangular region surrounded by the drain line DL and the gate line GL constitutes a region in which pixels are formed, whereby each pixel is arranged in a matrix in the display region AR. Each pixel includes, for example, two thin film transistors TFT1 and TFT2 that are turned on / off by a scanning signal from the gate line GL, as shown in an equivalent circuit diagram A ′ of a circle A in FIG. The pixel electrode PX to which the video signal from the drain line DL is supplied via the TFT 2 is formed at least on the entire surface of the display region, and is common from one end of the left and right (end portion of the first substrate SUB1) in the X direction or from both sides. A common electrode CT to which a common signal having a reference potential with respect to the potential of the video signal is supplied via a line CL.

  An electric field having a component parallel to the main surface of the first substrate SUB1 is generated between the pixel electrode PX and the common electrode CT, and liquid crystal molecules are driven by this electric field. Such a liquid crystal display device is known to be capable of so-called wide viewing angle display, and is called an IPS system or a lateral electric field system because of the peculiarity of applying an electric field to liquid crystal. Further, in the liquid crystal display device having such a configuration, normally black which minimizes the light transmittance when no electric field is applied to the liquid crystal (black display) and improves the light transmittance by applying the electric field. The display is performed in the display form.

  Each drain line DL and each gate line GL extend over the seal material SL at the ends thereof, and are supplied to a drive circuit DR that generates a drive signal such as a video signal or a scanning signal based on a video signal from an external system. Connected. However, in the liquid crystal display device of the first embodiment, the drive circuit DR is formed of a semiconductor chip and mounted on the first substrate SUB1, but the video signal drive circuit that outputs the video signal and the scan signal drive that outputs the scan signal are used. One or both of the drive circuits may be mounted on the flexible printed circuit board FPC by a tape carrier method or a COF (Chip On Film) method and connected to the first substrate SUB1.

  In the liquid crystal display device according to the first embodiment, the common electrode CT is formed at least over the entire display region. However, the present invention is not limited to this. For example, as shown in an equivalent circuit diagram A ′, A configuration may be adopted in which a common signal is input via a common line CL to a common electrode CT formed independently for each time.

<Pixel configuration>
FIG. 2 is a top view for explaining a schematic configuration of one pixel in the liquid crystal display device of Embodiment 1 of the present invention, and FIG. 3 is a cross-sectional view taken along the line aa ′ shown in FIG. Hereinafter, the pixel structure in the liquid crystal display device of Embodiment 1 will be described with reference to FIGS. However, in order to simplify the description, only the first substrate is shown in FIGS. 2 and 3, and a well-known alignment film or the like is omitted. Further, since each thin film can be formed by a known photolithography technique, a detailed description of the forming method is omitted. The thin film transistors TFT1 and TFT2 are thin film transistors having a so-called inverted stagger structure, and are driven so that the drain electrode and the source electrode are interchanged by application of a bias. The side connected to the drain electrode DT and the side connected to the pixel electrode PX are referred to as source electrodes ST1 and ST2.

  As shown in FIG. 2, in the liquid crystal display device according to the first embodiment, gate lines GL extending in the X direction and juxtaposed in the Y direction, and drain lines DL extending in the Y direction and juxtaposed in the X direction. A region surrounded by is a pixel region. For each pixel region, a flat pixel electrode PX made of a transparent conductive material such as ITO (Indium-Tin-Oxide), and thin film transistors TFT1 and TFT2 are formed. In the liquid crystal display device of Embodiment 1, a planar common electrode CT made of a transparent conductive material such as ITO is formed on the liquid crystal side surface (opposing surface) of the first substrate SUB1. As will be described in detail later, the common electrode CT is formed in a planar shape in the display area AR, and a plurality of slits that are openings extending in the Y direction are formed in areas corresponding to the pixel areas. (Slit SLT in FIG. 5 described later) is formed. With this configuration, a linear (comb-like) electrode overlapping the pixel electrode PX is formed in the pixel region. The common electrode CT is formed so as to overlap the common line CL at the side portion of the first substrate SUB1, and is thereby electrically connected to the common line CL. The drain line DL (including the drain electrode DT), the gate line GL (including the gate electrode GT), and the source electrodes ST1 and ST2 are formed of a metal thin film such as AL (aluminum).

  In addition, the thin film transistors TFT1 and TFT2 of the first embodiment are configured to be formed in the vicinity of the gate line GL and the drain line DL (the lower left portion of the pixel area in FIG. 2) for supplying a driving signal corresponding to the pixel. Yes. At this time, the two thin film transistors TFT1 and TFT2 have a common configuration of the gate electrode GT and the drain electrode DT, and the source electrode ST1 of one thin film transistor TFT1 is formed at the corner (first corner) of the rectangular semiconductor layer AS. The source electrode ST2 of the other thin film transistor TFT2 is formed at a corner portion (second corner portion) opposite to the corner portion where the source electrode ST1 is formed. At this time, the drain electrodes DT of the thin film transistors TFT1 and TFT2 are formed at one of the remaining corners (third corner). That is, in the first embodiment, among the corners of the rectangular semiconductor layer AS, the source electrode ST1 is formed at one corner of the corner adjacent to the corner where the drain electrode DT is formed, and the other A source electrode ST2 is formed at the corner.

  At this time, in the liquid crystal display device of Embodiment 1, as described in detail later, a partial region of the source electrodes ST1 and ST2 of each thin film transistor TFT1 and TFT2 and a partial region of the semiconductor layer AS are overlapped. As a result, it is possible to suppress variations in the gate-source capacitances of the thin film transistors TFT1 and TFT2 due to alignment errors caused by interlayer alignment between the semiconductor layer AS and the source electrodes ST1 and ST2.

  In the liquid crystal display device according to the first embodiment, the pixel electrode PX is formed in the pixel region excluding the formation region of the thin film transistors TFT1 and TFT2, and the pixel electrode PX adjacent to the formation region of the thin film transistors TFT1 and TFT2 is formed on the side portion. A connecting portion CNN is formed along the line. The connection portion CNN is a region where a conductive metal thin film extending from the source electrodes ST1 and ST2 overlaps with a side portion of the pixel electrode PX. That is, the connection portion CNN of Embodiment 1 is an overlapping region of the conductive metal thin film formed in the same process as the source electrodes ST1 and ST2 and the pixel electrode PX extended to the region to be the connection portion CNN. Thus, the source electrodes ST1, ST2 and the pixel electrode PX are electrically connected directly. By adopting such a configuration, the thin film transistor TFT1 and the thin film transistor TFT2 are connected in parallel, and a video signal input via the two thin film transistors TFT1 and TFT2 is efficiently output to the pixel electrode PX.

  In the liquid crystal display device of Embodiment 1, as will be described in detail later, the extending portion of the source electrode ST1 and the extending portion of the source electrode ST2 extend in the X direction, and the direction overlapping the semiconductor layer AS is the same. A source electrode ST1 and a source electrode ST2 are formed so as to face each other. In particular, a part of the drain line DL extending in the Y direction extends toward the thin film transistors TFT1 and TFT2 to form the drain electrode DT, and the extending direction is X as in the extending direction of the source electrodes ST1 and ST2. Stretching in the direction. With such a configuration, in the liquid crystal display device according to the first embodiment, the drain electrode DT and the source electrode ST1 constituting the thin film transistor TFT1 are disposed to face each other on the upper layer of the semiconductor layer AS, and the thin film transistor TFT2 is configured. The drain electrode DT and the source electrode ST2 to be arranged are arranged to face each other on the upper layer of the semiconductor layer AS.

  Furthermore, in the liquid crystal display device according to the first embodiment, the gate line GL extends to the thin film transistors TFT1 and TFT2, and the extended portion overlaps the semiconductor layer AS as the gate electrode GT. At this time, in the liquid crystal display device of Embodiment 1, the gate electrode GT is larger than the semiconductor layer AS, and occupies a region smaller than the region of the gate electrode GT on the upper layer side of the region where the gate electrode GT is formed. A semiconductor layer AS is formed.

  In the liquid crystal display device according to the first embodiment having such a configuration, as shown in FIG. 3, a base film IN for protecting the thin film transistors TFT1 and TFT2 is formed on the surface of the first substrate SUB1, and the base film IN A gate line GL (including the gate electrode GT) is formed in the upper layer. In the liquid crystal display device according to the first embodiment, as will be described in detail later, the common electrode CT is formed so as to cover the display region. However, the wiring (common line CL) that connects the drive circuit DR and the common electrode CT. Is formed in the same layer as the gate line GL, for example.

  An insulating film (gate insulating film) GI is formed on the upper layer so as to cover the gate line GL and the common line CL. This insulating film GI functions as a gate insulating film of the thin film transistors TFT1 and TFT2 in the formation region of the thin film transistors TFT1 and TFT2, and the film thickness and the like are set accordingly.

  A semiconductor layer AS made of, for example, amorphous silicon is formed on the upper surface of the insulating film GI and overlaps with a part of the gate line GL. This semiconductor layer AS is a semiconductor layer of the thin film transistors TFT1 and TFT2. Further, when the semiconductor layer AS is formed, for example, an amorphous silicon layer AS 'is formed in a region where the drain signal line DL and the gate line GL intersect so that the step can be formed with a small level difference. The semiconductor layer AS is not limited to amorphous silicon, and may be low-temperature polysilicon, microcrystalline silicon, or the like.

  In the liquid crystal display device according to the first embodiment, a part of the drain line DL extends as a drain electrode DT to the upper layer of the semiconductor layer AS, and a part of the drain line DL overlaps with a corner of the semiconductor layer AS. In addition, the source electrodes ST1 and ST2 that are simultaneously formed when the drain line DL and the drain electrode DT are formed are formed so that a partial region thereof is overlapped with an adjacent corner portion of the semiconductor layer AS. As a result, FIG. As shown, the source electrode ST2 is disposed on the semiconductor layer AS so as to face the drain electrode DT, thereby forming a thin film transistor TFT2. Similarly, in the thin film transistor TFT1, the source electrode ST1 is disposed on the semiconductor layer AS so as to face the drain electrode DT, thereby forming the thin film transistor TFT1. As is clear from FIG. 3, the source electrode ST2 extending from the upper layer of the semiconductor layer AS is extended to a region where the end portion overlaps the pixel electrode PX (region of the connection portion CNN), and the pixel The electrode PX is overlapped and electrically connected. Similarly, the end portion of the source electrode ST1 extending from the upper layer of the semiconductor layer AS is also overlapped with and electrically connected to the pixel electrode PX. With such a configuration, a video signal input via the drain line DL via the two thin film transistors TFT1 and TFT2 connected in parallel is supplied to the pixel electrode PX.

  Further, a protective film PAS made of an insulating film covering the thin film transistors TFT1, TFT2, and the pixel electrode PX is formed on the surface of the first substrate SUB1, that is, the upper layer of the drain line DL, the source line SL, the pixel electrode PX, and the like. . This protective film PAS prevents the thin film transistors TFT1, TFT2 and the pixel electrode PX from contacting the common electrode CT. In the liquid crystal display device of Embodiment 1, the protective film PAS functions as a dielectric film of the capacitive element, and the common electrode CT is formed on the upper layer via the protective film PAS. Accordingly, the protective film PAS is formed to extend to the entire surface of the liquid crystal side surface of the first substrate SUB1, that is, the region reaching the edge. A planar common electrode CT is formed on the protective film PAS.

<Detailed configuration of thin film transistor>
Next, FIG. 4 is a diagram for explaining the detailed configuration of the thin film transistor in the conventional liquid crystal display device, and FIG. 5 is a diagram for explaining the detailed configuration of the thin film transistor in the liquid crystal display device of Embodiment 1 of the present invention. Based on FIGS. 4 and 5, the detailed configuration of the thin film transistor according to the first embodiment and the effect of suppressing variations in gate-source capacitance will be described in detail.

  First, as shown in FIG. 4, in the conventional IPS liquid crystal display device, as shown in FIG. 4, a region surrounded by the drain line DL and the gate line GL becomes a pixel region, and a gate is formed in this pixel region. A rectangular semiconductor layer AS is formed so as to overlap with the gate electrode GT extended from the line GL. A drain electrode DT formed by extending a part of the drain line DL is formed to overlap with an end portion of the semiconductor layer AS near the gate line GL, and from the gate line GL of the semiconductor layer AS. One end of the source electrode ST is formed at the far end, and the other end of the source electrode ST forms a connection portion CNN and is electrically connected to the pixel electrode. In this conventional thin film transistor, the overlapping area of the source electrode ST and the semiconductor layer AS indicated by the dotted line frame K is proportional to the gate-source capacitance of the thin film transistor. For this reason, when the relative position of the semiconductor layer AS and the source electrode ST due to the interlayer shift varies in the Y direction, the gate-source capacitance of the thin film transistor varies with the variation of the overlapping area. .

  On the other hand, as shown in FIG. 5, the thin film transistors TFT1 and TFT2 of the first embodiment are configured such that the source electrodes ST1 and ST2 and the drain electrode DT are formed in a region including the corners of the rectangular semiconductor layer AS. Yes. In particular, in the thin film transistors TFT1 and TFT2 of the first embodiment, the shape of the source electrodes ST1 and ST2 and the drain electrode DT on the semiconductor layer AS side is also formed in a rectangular shape, and a partial region of the tip thereof overlaps with the semiconductor layer AS. It becomes the composition which is done. That is, in the pixel of Embodiment 1, the thin film transistors TFT1 and TFT2 are formed in the vicinity of the intersection of the drain line DL extending in the Y direction and the gate line GL extending in the X direction. At this time, a part of the drain line DL extending in the Y direction extends in the formation direction of the thin film transistors TFT1 and TFT2, that is, the X direction to form the drain electrode DT, and the gate line GL extending in the X direction. A part of the gate electrode GT extends in the formation direction of the thin film transistors TFT1 and TFT2, that is, the Y direction, to form the gate electrode GT.

  Further, in the thin film transistors TFT1 and TFT2 of the first embodiment, the semiconductor layer AS having sides smaller than the lengths in the X direction and the Y direction of the gate electrode GT is formed via the insulating film (gate insulating film) GI. It is formed in the upper layer of the gate electrode GT. At this time, the rectangular drain electrode DT extending from the drain line DL has two corners perpendicular to the tip side, and one of the corners is the corner of the semiconductor layer AS. The other corner is not overlapped with the semiconductor layer AS. On the other hand, the two corners on the front end side of the drain electrode DT are configured to overlap the gate electrode GT. With such a configuration, in the thin film transistors TFT1 and TFT2 of the first embodiment, the thin film transistors TFT1 and TFT2 are caused by a shift in the formation position accompanying the alignment when forming the semiconductor layer AS formed in a layer different from the drain electrode DT. The area of the overlapping region of the drain electrode DT acting as the drain region of the semiconductor layer AS and the semiconductor layer AS is variable.

  In the thin film transistors TFT1 and TFT2 of the first embodiment, the source electrodes ST1 and ST2 formed in the same layer as the drain line DL and the drain electrode DT are formed at corners adjacent to the corner where the drain electrode DT is formed. It becomes the composition which is done. In addition, source electrodes ST1 and ST2 are formed at corners located diagonally of the semiconductor layer AS. That is, the thin film transistor TFT1 and the thin film transistor TFT2 of Embodiment 1 are configured to write a video signal to the pixel electrode PX by two thin film transistors connected in parallel. In order to achieve such a configuration, in the thin film transistors TFT1 and TFT2 of the first embodiment, the source electrode ST1 of the thin film transistor TFT1 and the source electrode ST2 of the thin film transistor TFT2 are formed in the same layer as the source electrodes ST1 and ST2, that is, The connection is made with a conductive thin film formed together with the source electrodes ST1 and ST2. That is, in the first embodiment, the connection portion CNN that connects the source electrode ST1 and the source electrode ST2 is provided so as to overlap with the side portion of the pixel electrode PX that is formed so as not to overlap with the formation region of the thin film transistors TFT1 and TFT2. It is configured. With such a configuration, the connection portion CNN also electrically connects the pixel electrode PX made of a transparent conductive film formed in the upper layer of the source electrodes ST1 and ST2 and the source electrodes ST1 and ST2. .

  Further, in the thin film transistors TFT1 and TFT2 of the first embodiment, the source indicated by the dotted line frame B formed at the corner on the side far from the gate line GL among the source electrodes ST1 and ST2 formed diagonally of the semiconductor layer AS. The electrode ST1 includes a rectangular electrode thin film serving as a second extending portion extending in the Y direction from the connection portion CNN and a rectangular serving as a first extending portion extending in the X direction from the second extending portion. It has a substantially L-shaped electrode shape made of an electrode thin film. At this time, in the source electrode ST1, the second extension portion does not overlap with either the gate electrode GT or the semiconductor layer AS, and only the first extension portion overlaps with the gate electrode GT and the semiconductor layer AS. Has been. On the distal end side of the first extending portion, that is, the side overlapping with the semiconductor layer AS, the corner near the drain electrode DT is formed so as to overlap with the region including the corner of the semiconductor layer AS, and the corner on the far side is formed. The portion is not superimposed on the semiconductor layer AS, but is superimposed only on the gate electrode GT. The source electrode ST2 is formed of a rectangular electrode thin film serving as a third extending portion extending in the X direction from the connection portion CNN, and is far from the gate line GL on the tip side, that is, the side overlapping with the semiconductor layer AS. The corner portion on the side is formed so as to overlap with the region including the corner portion of the semiconductor layer AS, and the corner portion on the side close to the gate line GL is not overlapped with the semiconductor layer AS, and is overlapped only on the gate electrode GT. ing. At this time, the first extending portion and the third extending portion have the same Y-direction length (electrode width) when there is no displacement, and further, the gate electrode GT and the source electrodes ST1, ST2 The superposition length (superposition amount) and the superposition amount with the semiconductor layer AS are also formed to have the same size.

  By adopting such a configuration, in the thin film transistors TFT1 and TFT2 of the first embodiment, as will be described in detail later, the misalignment caused by the interlayer misalignment between the semiconductor layer AS and the source electrodes ST1 and ST2 occurs. In addition, the area of the source electrodes ST1 and ST2 overlapping the semiconductor layer AS is constant. That is, the gate-source capacitances of the thin film transistors TFT1 and TFT2 that are affected by the total area of the source electrodes ST1 and ST2 overlapping the semiconductor layer AS are made constant. Furthermore, the total area of the source electrode ST1 and the source electrode ST2 overlapping the gate electrode GT is constant. As a result, a change in gate-source capacitance due to increase or decrease in the total area is suppressed.

  Next, a case where an interlayer shift occurs between the semiconductor layer AS and the source electrodes ST1 and ST2 based on the enlarged view B ′ of the dotted line frame B and the enlarged view C ′ of the dotted line frame C in FIG. To do. However, since the interlayer displacement between the semiconductor layer AS and the source electrodes ST1 and ST2 is a relative displacement between the respective layers, in the following description, it is apparent that the formation positions of the source electrodes ST1 and ST2 are used as a reference. A case will be described in which misalignment between layers occurs only in the semiconductor layer AS.

  First, the area S1 of the region where the source electrode ST1 and the semiconductor layer AS overlap with each other when there is no misalignment between layers is S1 = Y1 · X1 (where “·” indicates multiplication). The area S2 of the region where ST2 and the semiconductor layer AS overlap is S2 = Y2 · X2. Therefore, the total area S of the thin film transistors TFT1 and TFT2 that drive the pixel electrode PX is S = S1 + S2 = Y1 · X1 + Y2 · X2.

  Next, the case where the semiconductor layer AS is displaced by X0 only in the X direction indicated by the arrow with respect to the drain electrode DT and the source electrodes ST1 and ST2 as shown in the enlarged views B ′ and C ′ will be described. . At this time, since the source electrode ST1 and the source electrode ST2 are formed of the same conductive film formed in the same process, the amount of positional deviation between the source electrode ST1 and the source electrode ST2 with respect to the semiconductor layer AS is the same. It becomes quantity.

  Therefore, when only a positional shift in the X direction of the positional shift amount X0 indicated by the arrow in FIG. 5 occurs, the area S1 ′ of the region where the source electrode ST1 and the semiconductor layer AS overlap is S1 ′ = Y1 · (X1−X0), and the area S2 ′ of the region where the source electrode ST2 and the semiconductor layer AS overlap is S2 ′ = Y2 · (X2 + X0). Therefore, the total area S ′ of the thin film transistors TFT1 and TFT2 that drive the pixel electrode PX is S ′ = S1 ′ + S2 ′ = Y1 · (X1−X0) + Y2 · (X2 + X0) = S−Y1 · X0 + Y2 · X0. Become. At this time, in the liquid crystal display device of Embodiment 1, Y1 = Y2, that is, the overlapping length in the Y direction has the same value, so S ′ = S, and the source electrodes ST1, ST2 and the semiconductor accompanying the positional deviation in the X direction. The area of the overlapping region with the layer AS is the same even when a positional shift occurs. As a result, the total gate-source capacitance of the thin film transistor TFT1 and the thin film transistor TFT2 is the same even if a positional shift occurs only in the X direction.

  Similarly, when a positional shift amount Y0 occurs only in the Y direction indicated by the arrow in FIG. 5, the area S1 ′ of the region where the source electrode ST1 and the semiconductor layer AS overlap is S1 ′ = ( Y1−Y0) · X1, and the area S2 ′ of the region where the source electrode ST2 and the semiconductor layer AS overlap is S2 ′ = (Y2 + Y0) · X2. Therefore, the total area S ′ of the overlapping areas of the semiconductor layer AS and the source electrodes ST1 and ST2 in the thin film transistors TFT1 and TFT2 that drive the pixel electrode PX is S ′ = S1 ′ + S2 ′ = (Y1−Y0) · X1 + ( Y2 + Y0) · X2 = S−Y0 · X1 + Y0 · X2. At this time, in the liquid crystal display device of Embodiment 1, since X1 = X2, S ′ = S, and the area of the overlapping region of the source electrodes ST1, ST2 and the semiconductor layer AS due to the displacement in the Y direction is Even when a positional shift caused by the interlayer shift occurs, the area is the same. As a result, the sum of the gate-source capacitances of the thin film transistors TFT1 and TFT2 is the same even when a positional shift occurs only in the Y direction, and the total capacitance is constant.

  Next, as shown by the arrows in FIG. 5, when both the positional deviation of the deviation amount X0 in the X direction and the positional deviation of the deviation amount Y0 in the Y direction occur, that is, in the oblique direction in FIG. A case where a displacement occurs will be described. In this case, the area S1 ′ of the region where the source electrode ST1 and the semiconductor layer AS overlap is S1 ′ = (Y1−Y0) · (X1−X0), and the source electrode ST2 and the semiconductor layer AS overlap each other. The area S2 ′ is S2 ′ = (Y2 + Y0) · (X2 + X0). Therefore, the total area S ′ of the thin film transistors TFT1 and TFT2 that drive the pixel electrode PX is S ′ = S1 ′ + S2 ′ = (Y1−Y0) · (X1−X0) + (Y2 + Y0) · (X2−X0). = S + 2 · Y0 · X0. At this time, since Y0 · X0 << Y1 · X1 and Y0 · X0 << Y2 · X2, S ′ = S, and the source electrodes ST1 and ST2 and the semiconductor layer AS due to displacement in the Y and X directions. The area of the overlap region with the same area is the same even when a positional shift occurs. As a result, the total gate-source capacitance of the thin film transistor TFT1 and the thin film transistor TFT2 is the same even when a positional shift occurs in the Y direction and the X direction, and the total capacitance is constant.

  At this time, the source electrodes ST1 and ST2 are also overlapped with the gate electrode GT via the insulating film GI. However, in the thin film transistor TFT1 and TFT2 of the first embodiment, the first extension portion of the source electrode ST1 and the source The region on the semiconductor layer AS side of the third extension portion of the electrode ST2 overlaps with the gate electrode GT, and the Y direction of the first extension portion of the source electrode ST1 and the third extension portion of the source electrode ST2 The length (electrode width) is formed with the same size. Therefore, even when a shift in the X direction occurs, even when an interlayer shift in the X direction occurs between the gate electrode GT and the source electrodes ST1 and ST2, the insulating film GI is interposed therebetween. Thus, the total parasitic capacitance associated with the overlapping of the gate electrode GT and the source electrodes ST1 and ST2 can be held at a constant capacitance. At this time, regarding the interlayer displacement in the Y direction between the gate electrode GT and the source electrodes ST1, ST2, the gate electrode GT and the source electrodes ST1, ST2 do not change in the overlapping state in the Y direction, so that the parasitic capacitance No change will occur.

  As described above, the thin film transistor in the display device according to the first embodiment includes the semiconductor layer that is disposed so as to overlap the gate electrode with the gate insulating film interposed therebetween, and the first corner portion in which the semiconductor layer is formed at the diagonal position. And a second corner portion, and a third corner portion sharing a first side where the first corner portion is formed and a second side where the second corner portion is formed. The drain line is formed so as to partially extend from the drain line, overlapped with the third corner, formed with one end overlapped with the first corner, and connected with the pixel electrode at the other end. And a second source electrode having one end overlapped with the second corner and the other end connected to the pixel electrode. Even when a relative displacement occurs between the semiconductor layer and the first and second source electrodes. The semiconductor layer of the two thin film transistors and the sum of the overlapping area between the first and second source electrode can be kept constant, it is possible to suppress the variation of the gate-source capacitance of the thin film transistor in the manufacturing process. Therefore, the combined characteristics of the two thin film transistors can be kept constant, and fluctuations in the characteristics of the thin film transistor due to interlayer displacement can be suppressed. As a result, even when the insulating film is further thinned in order to improve the transmittance, it is possible to increase the margin of the holding voltage with respect to the jump voltage, such as flicker caused by the jump voltage. Occurrence can be significantly suppressed, and display image quality and display quality can be improved.

<Embodiment 2>
FIG. 6 is a diagram for explaining a schematic configuration of a liquid crystal display device which is a display device according to the second embodiment of the present invention, and in particular, an enlarged view for explaining a detailed configuration of the thin film transistor of the second embodiment. However, the configuration other than the thin film transistor of the second embodiment is the same as that of the liquid crystal display device of the first embodiment. Therefore, in the following description, the structure of the thin film transistor will be described in detail.

  As is apparent from FIG. 6, each pixel of the second embodiment is also configured to supply a video signal to the pixel electrode PX using two thin film transistors TFT1 and TFT2. At this time, in the thin film transistor TFT1 and the thin film transistor TFT2 of the second embodiment, the gate electrode GT extending from the gate line GL in the direction of the pixel electrode PX is formed as in the first embodiment, and is not shown in the upper layer of the gate electrode GT. A rectangular semiconductor AS is formed so as to overlap with a gate insulating film interposed therebetween. The shape of the semiconductor layer AS at this time is also formed in a rectangular shape as in the first embodiment, and one of the two opposing sides is the first direction of the pixels arranged in the extending direction of the drain lines DL, that is, in a matrix. The configuration matches the arrangement direction. The other two opposite sides of the rectangular semiconductor layer AS are configured to coincide with the extending direction of the gate lines GL, that is, the second arrangement direction of the pixels arranged in a matrix.

  Further, the drain electrode DT formed by extending a part of the drain line DL is formed in a region including a corner closest to the intersection region between the drain line DL and the gate line GL among the corners of the semiconductor layer AS. Is formed. That is, the drain electrode DT of the second embodiment is also one of the corners located at both ends of the edge on the semiconductor layer AS side of the drain electrode extending in the X direction, like the drain electrode DT of the first embodiment. A portion is formed on the upper surface side of the semiconductor layer AS so as to overlap with a region including the corner of the semiconductor layer AS, and the other corner is not overlapped with the semiconductor layer AS.

  Similarly to the first embodiment, the source electrodes ST1 and ST2 of the two thin film transistors TFT1 and TFT2 are also formed at the corners located at the opposite corners of the semiconductor layer AS. At this time, as shown by the two dotted frames, in the thin film transistors TFT1 and TFT2 of the second embodiment, the thin film transistors TFT1 and TFT2 are independent from each other, that is, the conductive thin films forming the source electrode ST1 and the source electrode ST2 are the same. The layers are not connected by the conductive thin film. That is, the source electrode ST1 of the thin film transistor TFT1 extends in the drain line direction (Y direction) from the connection portion CNN1 electrically connected to the pixel electrode PX formed on the lower layer side of the pixel electrode PX. And a first extension portion extending from the second extension portion in the gate line GL direction (X direction) and overlapping with the corner portion of the semiconductor layer AS. On the other hand, the source electrode ST2 of the thin film transistor TFT2 is connected to the pixel electrode PX formed on the lower layer side of the pixel electrode PX, and is connected to the pixel electrode PX in the gate line GL direction (X direction) from the connection portion CNN2. The third extending portion extends and overlaps with the corner portion of the semiconductor layer AS.

  As described above, also in the liquid crystal display device of the second embodiment, the semiconductor layer AS and the drain electrode DT are formed in common, and other than the corners of the semiconductor layer AS where the drain electrode DT is formed, Thus, since the source electrode ST1 is formed at one of the pair of corners forming the diagonal and the source electrode ST2 is formed at the other corner, the same effect as in the first embodiment can be obtained. it can.

  At this time, the source electrodes ST1 and ST2 of the two thin film transistors TFT1 and TFT2 are electrically connected via an ITO thin film which is a light-transmitting conductive thin film forming the pixel electrode PX. At this time, since the pixel electrode PX has an electric resistance per unit area larger than that of the metal thin film forming the source electrodes ST1 and ST2, the two thin film transistors TFT1 and TFT2 supply video signals to the pixel electrode PX independently. It becomes composition.

<Embodiment 3>
FIG. 7 is a diagram for explaining a schematic configuration of a liquid crystal display device which is a display device according to the third embodiment of the present invention. In particular, FIG. 7 is an enlarged view for explaining detailed configurations of the thin film transistor and the pixel electrode according to the third embodiment. is there. However, in the liquid crystal display device of the third embodiment, the configuration other than the pixel electrodes PX1 and PX2 is the same as that of the liquid crystal display device of the second embodiment. Therefore, in the following description, the configuration of the pixel electrodes PX1 and PX2 will be described in detail.

  As is apparent from FIG. 7, the liquid crystal display device according to the third embodiment has a configuration in which one pixel region surrounded by the drain line DL and the gate line GL is divided into two regions D and E. Is formed with a pixel electrode PX1, and in the region E, a pixel electrode PX2 is formed. At this time, in the third embodiment, the source electrode ST1 of the thin film transistor TFT1 is electrically connected to the pixel electrode PX1 formed on the lower layer side of the pixel electrode PX1, and the drain line direction (from the connection portion CNN1) A second extension portion extending in the Y direction), and a first extension portion extending in the gate line GL direction (X direction) extending from the first extension portion and overlapping the corner portion of the semiconductor layer AS. Thus, the video signal is supplied to the pixel electrode PX1.

  On the other hand, the source electrode ST2 of the thin film transistor TFT2 is connected to the pixel electrode PX2 formed on the lower layer side of the pixel electrode PX2, and is connected to the pixel electrode PX2 and from the connection portion CNN2 to the gate line GL direction (X direction). The third extending portion that extends and overlaps with the corner portion of the semiconductor layer AS is configured to supply a video signal to the pixel electrode PX1.

  Thus, also in the liquid crystal display device of the third embodiment, the thin film transistor TFT1 and the thin film transistor TFT2 are formed with the gate electrode GT extending from the gate line GL in the direction of the pixel electrode PX, as in the first and second embodiments. A rectangular semiconductor AS is formed above the gate electrode GT via a gate insulating film (not shown). The shape of the semiconductor layer AS at this time is also formed in a rectangular shape as in the first and second embodiments, and one of the two opposing sides thereof is arranged in the extending direction of the drain line DL, that is, in a matrix. The configuration coincides with the first arrangement direction of the pixels. Further, the other two opposite sides of the rectangular semiconductor layer AS are configured to coincide with the extending direction of the gate lines GL, that is, the second arrangement direction of the pixels arranged in a matrix, so that the first embodiment 2 can be obtained.

<Embodiment 4>
FIG. 8 is a diagram for explaining a schematic configuration of a liquid crystal display device which is a display device according to a fourth embodiment of the present invention, and in particular, an enlarged view for explaining a detailed configuration of the thin film transistor of the fourth embodiment. However, the liquid crystal display device of the fourth embodiment has the same configuration as that of the liquid crystal display device of the second embodiment except for the configuration of the thin film transistors TFT1 and TFT2 and the configuration of the pixel electrode PX. Therefore, in the following description, the configuration of the thin film transistors TFT1 and TFT2 and the configuration of the pixel electrode PX will be described in detail.

  As is apparent from FIG. 8, in the two thin film transistors TFT1 and TFT2 in the liquid crystal display device according to the fourth embodiment, as in the thin film transistors TFT1 and TFT2 according to the first to third embodiments, one gate electrode GT, the semiconductor layer AS, and , A drain electrode DT and two source electrodes ST1 and ST2. At this time, a corner portion of the semiconductor layer AS where neither the drain electrode DT nor the source electrodes ST1 and ST2 are formed (inserted) is removed, and an interlayer shift between the gate electrode GT and the source electrodes ST1 and ST2 is removed at the removed corner portion. It is the structure which forms the electroconductive thin film for correct | amending. That is, the thin film transistors TFT1 and TFT2 of the fourth embodiment have a pentagonal semiconductor layer AS in which three orthogonal corners are adjacently arranged. In particular, in the thin film transistors TFT1 and TFT2 of the fourth embodiment, Of the three orthogonal corners, two corners are arranged along the extending direction of the drain line DL, and two corners are arranged along the extending direction of the gate line GL. ing. In particular, the drain electrode DT is formed so as to overlap the corner disposed near the intersection of the drain line DL and the gate line GL among the corners disposed along the extending direction of the drain line DL. The configuration is such that the source electrode ST1 is formed so as to overlap the corner portion disposed on the far side. Of the corners arranged along the extending direction of the gate line GL, the corner formed near the intersection of the drain line DL and the gate line GL, that is, the corner formed by overlapping the drain electrode DT. The portion has the same configuration as that of the thin film transistor TFT2, and the source electrode ST2 is formed so as to overlap the corner portion arranged on the far side. By adopting such a configuration, the thin film transistors TFT1 and TFT2 of the fourth embodiment can obtain the same effects as those of the first to third embodiments.

  In the thin film transistors TFT1 and TFT2 of the fourth embodiment, the drain electrode DT extends between the source electrode ST1 and the source electrode ST2 from a corner portion disposed near the intersection of the drain line DL and the gate line GL. It has a structure that extends to the side facing the corner. With such a configuration, the overlapping area between the drain electrode DT and the semiconductor layer AS can be increased, and the driving performance of the thin film transistors TFT1 and TFT2 can be improved.

  Furthermore, in the thin film transistor TFT1 of the fourth embodiment, as in the first embodiment, the connection portion CNN1 in which the source electrode ST1 is electrically connected to the pixel electrode PX1 formed on the lower layer side of the pixel electrode PX1, and the connection A second extending portion extending from the portion CNN1 in the drain line direction (Y direction), and extending from the first extending portion in the gate line GL direction (X direction) to be overlapped with a corner portion of the semiconductor layer AS. The first extending portion is configured to supply a video signal to the pixel electrode PX1.

  On the other hand, the source electrode ST2 of the thin film transistor TFT2 extends in the fourth extending portion extending in the extending direction (Y direction) of the drain line DL and in the gate line GL direction (X direction) from the fourth extending portion. The semiconductor layer AS includes a fifth extension portion that overlaps the corner portion of the semiconductor layer AS, and the extension portion that extends from the pixel electrode PX is overlapped and electrically connected in a partial region of the fourth extension portion. The connection portion CNN2 is formed, and the video signal is supplied to the pixel electrode PX. At this time, the gate electrode GT of the fourth embodiment has a configuration in which the entire region of the first extension portion of the source electrode ST1 is overlapped and the partial region of the second extension portion is also overlapped. Yes. Furthermore, the gate electrode GT is configured to avoid the connection region CNN2 of the source electrode ST2 extending from the pixel electrode PX and the formation region of the pixel electrode PX. That is, in the gate electrode GT of the fourth embodiment, a partial region of the gate line GL protrudes in the formation direction (Y-axis direction) of the pixel electrode PX to form the gate electrode GT, and the gate in the protruding region. A concave region where the electrode GT is not formed is formed. In particular, in the gate electrode GT of the fourth embodiment, the opening (opening side) of the concave region is in a direction perpendicular to the extending direction of the fourth extending portion of the source electrode ST2, and the concave region, that is, the gate A connection portion CNN2 is formed in a region where the electrode GT is not formed, and the extension portion from the pixel electrode PX and the fourth extension portion of the source electrode ST2 are electrically connected. At this time, one end side of the fourth extending portion of the source electrode ST2 extends in the Y direction beyond the concave region of the gate electrode GT, and is overlapped with the gate electrode GT again. Further, the other end side of the fourth extension portion of the source electrode ST2 extends in the Y direction beyond the gate electrode GT, and the end portion is not overlapped with the gate electrode GT. Furthermore, the thin film transistor of Embodiment 4 is formed such that the X-direction width of the second extension portion of the source electrode ST1 and the X-direction width of the fourth extension portion of the source electrode ST2 have the same wiring width. ing.

  With such a configuration, in the region where the fourth extension portion of the source electrode ST2 and the gate electrode GT overlap, as shown by a dotted line H in FIG. And the rectangular gate wiring GL are orthogonal to each other. With this configuration, the fourth extension of the source electrode ST2 occurs even when a relative displacement in the X direction and the Y direction occurs between the gate line GL (including the gate electrode GT) and the source electrode ST2. The overlapping area between the portion and the gate electrode GT is kept constant. As a result, even when a relative positional shift occurs in the X direction and the Y direction between the gate line GL (including the gate electrode GT) and the source electrode ST2, the gate line GL (including the gate electrode GT) is generated. ) And the source electrode ST2 can be made to have a constant capacitance value due to the superposition of the source electrode ST2 via an insulating film (gate insulating film) (not shown).

  Further, in the thin film transistors TFT1 and TFT2 of Embodiment 4, as shown by a dotted frame G in FIG. 8, a region in which one end side of the fourth extending portion of the source electrode ST2 overlaps with a part of the gate electrode GT is provided. In addition, the wiring width (X direction width) of the fourth extending portion of the source electrode ST2 is the same as the wiring width (X direction width) of the first extending portion of the source electrode ST1. Therefore, as a relative positional shift in the Y direction between the gate electrode GT and the source electrodes ST1 and ST2, for example, when the gate electrode GT is shifted downward in FIG. 8, a dotted frame F in FIG. In the region where the second extending portion of the source electrode ST1 and the gate electrode GT overlap each other, the overlapping area of the first extending portion of the source electrode ST1 and the gate electrode GT is reduced. On the other hand, in the region where the fourth extending portion of the source electrode ST2 and the gate electrode GT overlap each other as indicated by the dotted frame G in FIG. 8, the overlapping area of the fourth extending portion of the source electrode ST2 and the gate electrode GT. Will increase. At this time, in the fourth embodiment, since the wiring widths of the extending portion of the source electrode ST1 and the extending portion of the source electrode ST2 are the same, the source electrode ST1 accompanying the downward shift of the gate electrode GT is formed. The decrease in the overlap area between the first extension portion and the gate electrode GT coincides with the increase in the overlap area between the fourth extension portion of the source electrode ST2 and the gate electrode GT. As a result, the total overlapping area of the overlapping area of the first extending portion of the source electrode ST1 and the gate electrode GT and the overlapping area of the fourth extending portion of the source electrode ST2 and the gate electrode GT does not change. It will be. Therefore, the parasitic capacitance between the gate and the source of the thin film transistors TFT1 and TFT2 due to the source electrodes ST1 and ST2 and the gate electrode GT being overlapped can be kept constant, and the gate electrode GT (including the gate line) is maintained. And the source electrode ST1 and ST2 can greatly suppress the deterioration in display quality due to variations in interlayer alignment.

  In the liquid crystal display device according to the fourth embodiment, one pixel electrode is formed in one pixel region. For example, as shown in the third embodiment, the pixel electrode PX1 corresponding to the thin film transistor TFT1 and the thin film transistor TFT2 are provided. The pixel electrode PX2 corresponding to may be formed.

<Embodiment 5>
FIG. 9 is an enlarged view for explaining a schematic configuration of a thin film transistor in a liquid crystal display device which is a display device according to the fifth embodiment of the present invention. The configuration other than the configuration of the source electrode ST1 of the thin film transistor TFT1 is the same as that of the first embodiment. The same as the liquid crystal display device.

  As is clear from FIG. 9, the source electrode ST1 of the thin film transistor TFT1 of the fifth embodiment is connected to the drain line DL from the connection portion CNN formed along the side portion of the pixel electrode PX, like the source electrode ST2 of the thin film transistor TFT2. The first extending portion extends in the extending direction (Y direction), and one corner portion of the end portion of the first extending portion is overlapped with the corner portion of the semiconductor layer AS to form a source region. It has a configuration.

  As described above, also in the thin film transistors TFT1 and TFT2 of the fifth embodiment, the first extension part for forming the source electrode ST1 and the third extension part for forming the source electrode ST2 are formed in the same process. The connection electrodes CNN are connected by the same conductive thin film, and the source electrodes ST1 and ST2 are formed.

  By adopting such a configuration, even in the thin film transistors TFT1 and TFT2 of the fourth embodiment, even when a misalignment occurs between the layers when forming the semiconductor layer AS and the source electrodes ST1 and ST2, the first embodiment. The same effect can be obtained. Further, in the thin film transistor TFT1 of the fifth embodiment, since the first extending portion extends from the connection portion CNN, it is possible to obtain a special effect that the formation region of the thin film transistors TFT1 and TFT2 can be reduced. .

  In the fifth embodiment, the thin film transistor TFT1 and the thin film transistor TFT2 are connected in parallel through the connection portion CNN. However, as in the second embodiment, the first connection portion corresponding to the thin film transistor TFT1 and the thin film transistor The second connection portion corresponding to the TFT 2 may be formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment of the invention, and various modifications can be made without departing from the scope of the invention. It can be changed.

PNL: Liquid crystal display panel, SUB1: First substrate, SUB2: Second substrate SL: Seal material, DR: Drive circuit, FPC: Flexible printed circuit board AR: Display area, DL: Drain line, GL: Gate line, CT: Common electrode TFT1, 2: Thin film transistor, CL: Common line, GT ... Gate electrode DT ... Drain electrode, AS ... Semiconductor layer, ST1, 2 ... Source electrode AS ' ...... Amorphous silicon, IN ... Base film, SLT ... Slit GI ... Insulating film (gate insulating film), PAS ... Protective film CNN, CNN1, CNN2 ... Connection, PX, PX1, PX2 ... Pixel electrode

Claims (5)

A drain line extending in the X direction and juxtaposed in the Y direction, a gate line extending in the Y direction and juxtaposed in the X direction, and a pixel region surrounded by the drain line and the gate line A display device comprising: a pixel electrode to be formed; and a thin film transistor that is formed for each pixel region and supplies a video signal from the drain line to the pixel electrode in response to a scanning signal from the gate line,
The thin film transistor includes a first corner and a second corner formed at diagonal positions, a first side where the first corner is formed, and a first corner formed with the second corner. A semiconductor layer having a third corner portion sharing the two sides, and overlapping with a gate electrode connected to the gate line through a gate insulating film;
A drain electrode formed partially extending from the drain line and overlapping the third corner of the semiconductor layer;
A first source electrode having one end overlapped with the first corner of the semiconductor layer and the other end connected to the pixel electrode;
A second source electrode having one end overlapped with the second corner of the semiconductor layer and the other end connected to the pixel electrode ;
The first and second source electrodes have two or more corners on one end side, and only one corner of each of the first and second source electrodes is the first and second corners of the semiconductor layer. display device is corner between superimposed characterized Rukoto. The first and second source electrodes are formed so that one end side overlapping with the semiconductor layer overlaps with the gate electrode, and the electrode width in the region overlapping with the gate electrode is the same electrode width . The display device according to claim 1. The other end of the first source electrode and the other end of the second source electrode are electrically connected by a conductive thin film formed in the same layer as the first and second source electrodes. The display device according to claim 1, wherein the display device is a display device. The pixel electrode, wherein a first pixel electrode connected the first source electrode and electrically, the Rukoto such from said second source electrode electrically connected to the Ru second pixel electrode The display device according to claim 1 or 2 . One end of the first source electrode is overlapped with the semiconductor layer, extends in the gate line direction, and extends in the drain line direction from the other end of the first extension part. And the other end side comprises a second extending portion connected to the pixel electrode ,
The second source electrode, one end of which overlaps the semiconductor layer, any of the other end extending to the gate line direction of claims 1 to 4, characterized in Rukoto connected to the pixel electrode The display device described in 1.

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