JPH0812923B2 - Pixel drive transistor - Google Patents

Description

The present invention relates to a transistor used for, for example, an active flat panel display and driving a pixel thereof.

"Prior Art" In a conventional active liquid crystal display device, transparent substrates 11 and 12 such as glass are provided in close proximity to each other, as shown in FIG. A liquid crystal 14 is sealed between the substrates 11 and 12. A plurality of display electrodes 15 are formed on the inner surface of one transparent substrate 11, and a thin film transistor 16 is formed in contact with each display electrode 15 as a switching element.
The drain of is connected to the display electrode 15. A transparent common electrode 17 is formed on the inner surface of the other transparent substrate 12 so as to face the plurality of display electrodes 15.

The display electrodes 15 are, for example, pixel electrodes, and as shown in FIG. 9, square ones are arranged on the transparent substrate 11 in rows and columns, that is, in a matrix form. And, along with this, each gate bus
18 are formed, and a source bus (data line) 19 is formed in the vicinity of each column array of the display electrodes 15 along the array. A thin film transistor 16 is provided at the intersection of each gate bus 18 and source bus 19, a gate of each thin film transistor 16 is connected to the gate bus 18 at an intersection position of both buses, and each source is connected to a source bus 19 respectively. The drain is connected to the display electrode 15.

Each of the gate bus 18 and the source bus 19 is selected and a voltage is applied between them, and only the thin film transistor 16 to which the voltage is applied becomes conductive, and a display connected to the drain of the conductive thin film transistor 16 is displayed. The charge is accumulated in the electrode 15 and the liquid crystal 14 in the portion between the display electrode 15 and the common electrode 17
A voltage is applied to only the display electrode 15 so that only the portion of the display electrode 15 is transparent or light-shielded, and selective display is performed. The display can be erased by discharging the charges accumulated in the display electrode 15.

The thin film transistor 16 has been conventionally configured as shown in FIGS. 10 and 11, for example. That is, the transparent substrate 11
A display electrode 15 and a source bus 19 are formed on the top by a transparent conductive film such as ITO, and a semiconductor such as amorphous silicon is spread over the portions of the display electrode 15 and the source bus 19 which are in parallel and close to each other. A layer 21 is formed, and a gate insulating film 22 such as silicon nitride is further formed thereon. A gate electrode 23 is formed on the gate insulating film 22 so as to partially overlap the display electrode 15 and the source bus 19 via the semiconductor layer 21. One end of the gate electrode 23 is connected to the gate bus 18. In this way, the display electrode 15 and the source bus 19 that face the gate electrode 23 are respectively the drain electrode 15
a, the source electrode 19a is formed, and the thin film transistor 16 is composed of the electrodes 15a and 19a, the semiconductor layer 21, the gate insulating film 22, and the gate electrode 23. The gate electrode 23 and the gate bus 18 are formed at the same time and are made of, for example, aluminum.

"Problems to be Solved by the Invention" In this conventional liquid crystal display element, the gate electrode 23, the drain electrode 15a, and the source electrode 1 of each thin film transistor 16 are
Electrostatic (parasitic) capacitances Cgd and Csg exist between the gate electrode 23 and the drain electrode 15, respectively.
a, the semiconductor layer 21 between the opposing portions of the source electrode 19a
There is a parasitic resistance Rs whose resistance value changes depending on the area of. These capacitances Cgd, Csg and parasitic resistance Rs are
However, if the position of the gate electrode 23 is slightly deviated when the gate electrode 23 is formed, the capacitance Cgd or the like directly changes, which causes variations in the characteristics of the thin film transistor 16. For example, if the design value of the overlapping width of these electrodes is 3 microns and the channel width is w, then the capacitances Cgd and Csg are each three times w if they are as designed.
Although it is proportional to
Is shifted to the source electrode 19a side, Cgd and Csg are proportional to w of 2 times and w of 4 times respectively, and when the gate electrode 23 is shifted to the source electrode 19a side by 2 microns, Cgd, Csg
Are proportional to 1 times w and 5 times w, respectively.
Therefore, the displacement of the gate electrode 23 has a great influence on the characteristics of the thin film transistor 16. When the characteristics of the thin film transistors 16 in the liquid crystal display element vary, display unevenness occurs.

From this point of view, it was considered that the second thin film transistor is connected to each display electrode at a position opposite to the thin film transistor connected thereto, and these two thin film transistors are connected in parallel with each other.

FIG. 12 schematically shows an example of the liquid crystal display element in that case. The display electrodes 15 are arranged in a matrix and are shown in FIG.
Similar to the case of FIG. 10, source buses 19a are formed on one side corresponding to each column of the display electrodes 15,
The source bus 19a and the display electrode 15 in that column are connected by a thin film transistor 16. Further, for each display electrode 15, a thin film transistor 25 is connected to the display electrode 15 on the side opposite to the side to which the thin film transistor 16 is connected, and on the left side in the drawing. The thin film transistor 25, which corresponds to each array of the display electrodes 15, has its source electrode connected to the source bus 26, and each column array of the display electrodes 15 has both ends of the corresponding pair of source buses 19 and 26 connected to each other. Connected in a loop. Although not shown, the gate electrode of the thin film transistor 25 is connected to the gate bus 18 to which the gate electrode of the thin film transistor 16 connected to the display electrode 15 is connected. Therefore, for each display electrode, both thin film transistors 16 and 25 are connected in parallel with each other.

As shown in FIGS. 13 and 14 corresponding to FIGS. 8, 10, and 11 with the same reference numerals, a source bus 26 is formed on the side opposite to the source bus 19 of each display electrode 15. Is
A semiconductor layer 27 such as amorphous silicon is formed between the source bus 26 and the display electrode 15, and the semiconductor layer 27 is further formed.
A gate insulating film 22 is formed on the gate electrode 28, and a gate electrode 28 is formed on the gate insulating film 22.
Are formed to form the thin film transistor 25. The gate electrode 28 is connected to the gate bus 18.

Also in the thin film transistor 25 of this configuration, as shown in FIG. 15, the overlapping portion of the gate electrode 28 and the display electrode 15, that is, the electrostatic capacitance Cgd ₂ between the drain electrode 15b, the overlapping portion with the source bus 26, That is, the capacitance Csg ₂ exists between the source electrode 26a and the source electrode 26a. However, since the two thin film transistors 16 and 25 are formed on both sides of one display electrode 15 respectively and these are connected in parallel with each other, the gate electrode 23 and the display electrode are
15, the capacitance with the source bus 19 is Cgd ₁ , Csg ₁ ,
Capacitances Cgd ₁ and Cgd ₂ , and Csg ₁ and Csg ₂ are connected in parallel, respectively.

Therefore, when the gate electrodes 23 and 28 are overlapped as designed, the electrostatic capacitances Cgd ₁ + Cgd ₂ and Csg ₁ + Csg ₂ are 3 respectively.
It is assumed to be double w. That is, the overlapping width of each gate electrode, the drain electrode, and the source electrode is 3 μm, and the channel width is w / 2. At this time, for example, FIG. 13, FIG. 14, and FIG.
When the gate electrode 23 is displaced to the right side in the figure, the gate electrode 23 and the gate electrode 28 of the thin film transistor 25 are formed by the same mask, so that the gate electrode 28 is also displaced to the right side by the same amount, so that the source of the thin film transistor 16 is shifted. The capacitance Csg ₁ between the gates increases, but the capacitance between the source and gate of the thin film transistor 25 is increased by the same amount as the increase.
Csg ₂ is reduced, and the capacitance between the source and gate of both thin film transistors 16 and 25 is three times w, which is the same as the design value. This is the capacitance between the gate and drain of the thin film transistor 16.
The same is true between Cgd ₁ and the electrostatic capacitance Cgd ₂ between the gate and drain of the thin film transistor 25. When one increases, the other decreases and the sum is always constant. Therefore, the capacitance is always as designed even if there is a mask shift. Therefore, even if the mask shift at the time of forming the gate electrode in each part of the display surface of the liquid crystal display element is not uniform, the thin film transistors having the same characteristics can be obtained. As for the parasitic resistance Rs, if the thin-film transistor 16 side increases, the parasitic-resistor 25 side decreases, and the sum is always constant.

However, in the display element in which the two thin film transistors are connected in parallel, since the two thin film transistors connected in parallel to each other are provided separately from each other, the bus length for supplying the source or gate signal is increased. It becomes longer, requires a distance of about twice, and the distance between source buses or gate buses adjacent to each other is narrower, which causes a high rate of defects such as disconnection and short circuit in manufacturing, and the yield is high. It will be bad.

Therefore, an object of the present invention is to provide a pixel driving transistor which is not easily affected by mask misalignment during manufacturing, has uniform transistor characteristics, and does not require a particularly long source bus or gate bus, and is easy to manufacture. Especially.

[Means for Solving Problems] According to the present invention, the source electrode and the drain electrode are
Sets are provided, and these two sets are arranged such that the directions of the source electrode and the drain electrode viewed from each other are opposite to each other, and these two sets are arranged substantially at right angles to the arrangement direction of the one set of source and drain electrodes. The two sets of source electrodes and the drain electrodes are connected to each other, and a common gate insulating film and a common gate electrode are provided for all the source electrodes and the drain electrodes,
The widths of the respective channels formed by the source electrode and the drain electrode and the common gate electrode in each set are almost equal to each other.

A source electrode and two drain electrodes sandwiching the source electrode are provided, and a common gate insulating film and a common gate electrode are provided for the source electrode and the two drain electrodes. The source electrode and the two drains are provided. The widths of the respective channels formed by the electrodes and the common gate electrode are substantially equal to each other.

Further, a plurality of sets of a source electrode and two drain electrodes sandwiching the source electrode are provided, and the arrangement directions of the drain electrodes of these sets are parallel to each other, and the plurality of source electrodes and the drain electrodes are connected to each other. A common gate insulating film and a common gate electrode are provided for the source electrode and the two drain electrodes of the plurality of sets, and in each set, the source electrode and the two drain electrodes and the common gate electrode are provided. The widths of the channels respectively constituted by are substantially equal to each other. Further, a plurality of sets of drain electrodes and two source electrodes sandwiching the drain electrodes are provided, and the source electrodes of each set are arranged in substantially parallel to each other, and the plurality of source electrodes are connected to each other and the drain electrodes are connected to each other. Connected to each other, a common gate insulating film and a common gate electrode are provided for a plurality of sets of drain electrodes and two source electrodes.
The widths of the respective channels formed by the drain electrode and the two source electrodes and the common gate electrode are substantially equal to each other. With such a configuration, the gate-source capacitance is always constant and the gate-drain capacitance is always constant as a whole even if a mask shift occurs during manufacturing. Further, since the gate electrode is common to a plurality of source electrodes and drain electrodes, it is not necessary to extend the source bus or gate bus for a long time, and it is not necessary to increase the number of source buses or gate buses, and a short circuit occurs between adjacent buses. It is also possible to reduce the number of accidents in which the bus is disconnected.

"Embodiment" FIG. 1 is a view corresponding to FIG. 10 and FIG. 13 when a pixel driving thin film transistor according to the constitution of claim 1 of the present invention is applied to an active matrix liquid crystal display device. , The corresponding parts are designated by the same reference numerals. In this example, each display electrode 15 is formed adjacent to one side edge that is perpendicular to the source bus 19, along which a branch pattern 31 is formed by being connected to the source bus 19, and one half of the side edge of the display electrode 15 is formed. The branch pattern 31 is formed by being shifted, and the branch pattern 31 is bent and extended on the retracted side edge and the bent extension portion.
An extension pattern 33 is extended from the display electrode 15 so as to surround and surround 32. The display electrode 15 and the branch pattern 31 are partially opposed to each other, and the extension 32 and the extension pattern 33 are provided.
A gate bus 18 is formed so as to face a part of each of them via a gate insulating film 22. The portions of the display electrode 15 and the extension pattern 33 that face the gate bus 18 act as drain electrodes 15a and 15b, respectively, and the branch pattern 31 and the extension 3
2 is the source electrode 1 in the part facing the gate bus 18
Acts as 9a, 19b. That is, the arrangement direction of the drain electrode 15a and the source electrode 19a, and the drain electrode 15b and the source electrode 19a.
The electrodes 15a, 15b, 19a, and 19b are parallel to but opposite to the array direction of b, and these electrodes 15a, 15b, 19a, and 19b have a common gate electrode (gate bus 1
8) is facing. The channel length and channel width between the electrodes 15a and 19a are made equal to the channel length and channel width between the electrodes 15b and 19b, respectively.

According to this configuration, the drain electrode 15a, the source electrode 19a,
The gate bus 18 constitutes the thin film transistor 16, and the drain electrode 15b, the source electrode 19b, and the gate bus 18 form the thin film transistor 34.
Are connected in parallel and operate as one transistor. Even if the gate bus 18 is displaced in the arrangement direction of the drain electrode 15a and the source electrode 19a due to a mask displacement during manufacturing, the gate and source capacitances, the gate and drain capacitances of the thin film transistors 16 and 34 as parallel transistors are respectively It will be easily understood that the value is a constant value.

Further, in this case, the gate bus 18 and the source bus 19 have almost the same length as in the case shown in FIG. 10, and it is not necessary to extend them long, and in the case of FIG. 13, the source bus 19 is between the display electrodes. Although two lines are arranged, only one line is required in FIG. 1, and it is possible to reduce the number of disconnection of the source bus 19 and no short circuit in the manufacturing process.

FIG. 2 shows the structure of the second aspect of the present invention. As shown in FIG.
The extension pattern 33 is formed over the entire length of one side edge of the display electrode 15 so as to sandwich the branch pattern 31, and the gate bus 18 is divided into the branch pattern 31, a part of the display electrode 15, and the extension pattern 33. It may be provided so as to face the section. In this case, one side edge of the branch pattern 31 acts as the source electrode 19a and the other side edge acts as the source electrode 19b.

The source electrode and the drain electrode may be provided in the same number in which the arrangement directions are opposite to each other, and are not limited to one set each. FIG. 3 shows the configuration of the third aspect of the present invention, and is an example in which two sets are provided for each. That is, facing the gate bus 18, the drain electrode 15a, the source electrode 19a,
A source electrode 19b and a drain electrode 15b are arranged in the width direction of the gate bus 18, and are arranged in the length direction of the gate bus 18 with respect to them, and the drain electrode 15c, the source electrode 19c,
The source electrode 19d and the drain electrode 15d are arranged in the width direction of the gate bus 18 and formed so as to face the gate bus 18, and the drain electrodes 15a and 15c are side edge portions of the display electrode 15, and the drain electrodes 15b are provided at both ends thereof. , 15d are connected to each other, and source electrodes 19a to
19d is composed of a pattern 32 along one side edge of the display electrode 15, and the pattern 32 is connected to the branch pattern 31 at an intermediate portion.

FIG. 4 shows the structure according to the fourth aspect of the present invention, and shows the case where the gate bus 18 is formed so as to be displaced in the width direction with respect to the electrode pattern arrangement similar to that of FIG. FIG. 5 shows a structure according to the third aspect of the present invention. The electrodes 15b and 15d in FIG. 3 and the display electrode 15 are commonly connected at an intermediate portion of one side edge of the display electrode 15. , The source electrodes 19a and 19b are common, and the source electrode 19a
This is the case where c and 19d are connected to the source bus 31 at each end.
FIG. 6 shows the structure according to the fourth aspect of the present invention, which is the case where the gate buses 18 are provided so as to be shifted in the width direction in FIG. FIG. 7 shows an example in which a larger number of sets of source electrodes and drain electrodes are provided in the structure corresponding to one of the structures according to claims 1 to 4 of the present invention, for example, the structure corresponding to item 3. Is.

[Advantages of the Invention] As described above, according to the present invention, a plurality of transistors are provided with a common gate electrode, and the directions in which the drain electrodes are viewed from the source electrodes are mutually opposite at least one set at a time. Therefore, even if there is a mask shift at the time of manufacturing, transistors having the same characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing a transistor and a display electrode array when an example of a pixel driving transistor according to the present invention is applied to an active matrix liquid crystal display element, and FIGS. 2 to 7 are plan views showing other examples. FIG. 8 is a cross-sectional view showing a part of a general structure of a liquid crystal display element,
FIG. 9 is an electric circuit diagram of the active matrix liquid crystal display device, FIG. 10 is a plan view showing the arrangement of the display electrodes 15 and the transistors 16 of the liquid crystal display device of FIG. 8, and FIG. 11 is A- of FIG. FIG. 12 is a cross-sectional view taken along the line A, and FIG.
13 is a plan view corresponding to FIG. 10 of the liquid crystal display device shown in FIG. 12, FIG. 14 is a sectional view taken along the line BB of FIG. 13, and FIG.
It is a figure which shows the weight of the gate electrode of FIG. 13, a source electrode, and a drain electrode. 15a, 15b, 15c, 15d: drain electrode, 16, 34: transistor,
18: Gate bus (gate electrode), 19: Source bus, 19a, 19
b, 19c, 19d: source electrode, 21, 27: semiconductor layer, 22: gate insulating layer.

Claims (4)

[Claims] 1. Two sets of a source electrode and a drain electrode are provided, and these two sets are opposite to each other when viewed from the source electrode to the drain electrode, and these two sets are one set of the source electrode and the drain electrode. The source electrodes and drain electrodes are arranged in a direction substantially perpendicular to the direction of arrangement of the drain electrodes, and the two sets of source electrodes are connected to each other, and the drain electrodes are connected to each other. A pixel driving transistor, wherein a gate electrode is provided, and widths of respective channels respectively constituted by the source electrode and the drain electrode in each set and the common gate electrode are substantially equal to each other. 2. A source electrode and two drain electrodes sandwiching the source electrode are provided, the drain electrodes are connected to each other, and a common gate insulating film and a common gate electrode are provided for the source electrode and the two drain electrodes. A pixel driving transistor, wherein the widths of the respective channels which are provided and are respectively constituted by the source electrode, the two drain electrodes, and the common gate electrode are substantially equal to each other. 3. A plurality of sets of a source electrode and two drain electrodes sandwiching the source electrode are provided, and the arrangement directions of the drain electrodes of these sets are substantially parallel to each other, and the plurality of source electrodes are The drain electrodes are connected to each other, a common gate insulating film and a common gate electrode are provided for the plurality of sets of source electrodes and two drain electrodes, and in each of the sets, the source electrode and the two drains are provided. The pixel driving transistor is characterized in that the widths of the respective channels formed by the electrodes and the common gate electrode are substantially equal to each other. 4. A plurality of sets of drain electrodes and two source electrodes sandwiching the drain electrodes are provided, and the source electrodes of these sets are arranged substantially parallel to each other. The drain electrodes are connected to each other, a common gate insulating film and a common gate electrode are provided for the plurality of sets of drain electrodes and two source electrodes, and in each of the sets, the drain electrode and the two source electrodes are provided. The pixel driving transistor is characterized in that the widths of the respective channels constituted by the common gate electrode and the common gate electrode are substantially equal to each other.