JP5645855B2 - プリント基板の作製手法 - Google Patents
プリント基板の作製手法 Download PDFInfo
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- JP5645855B2 JP5645855B2 JP2012014686A JP2012014686A JP5645855B2 JP 5645855 B2 JP5645855 B2 JP 5645855B2 JP 2012014686 A JP2012014686 A JP 2012014686A JP 2012014686 A JP2012014686 A JP 2012014686A JP 5645855 B2 JP5645855 B2 JP 5645855B2
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- Prior art keywords
- power supply
- circuit
- circuit board
- printed circuit
- impedance
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- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 title description 9
- 239000003990 capacitor Substances 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000004458 analytical method Methods 0.000 description 17
- 238000005259 measurement Methods 0.000 description 14
- 238000013461 design Methods 0.000 description 7
- 239000000523 sample Substances 0.000 description 5
- 230000005672 electromagnetic field Effects 0.000 description 4
- 238000002847 impedance measurement Methods 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 3
- 238000012938 design process Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- Structure Of Printed Boards (AREA)
Description
LSI電源等価回路とプリント基板電源等価回路とを統合し、電源供給系全体(チップ+パッケージ+ボード)のインピーダンス解析を行なうためのLSI電源等価回路を作製するものであって、LSIは汎用BGAパッケージのFPGA(Field-Programmable GateArray)とCPU(Central Processing Unit)のコア電源を対象とした。
図1に示すように、前記LSIが搭載された実製品を用意し、プリント基板電源回路に実装されたコンデンサを取り外し、コンデンサ実装部位からプロービングし、ベクトル・ネットワークアナライザE5071A (Agilent Technologies社製)にてインピーダンス測定を行なった。
LSI電源回路のインピーダンス測定の際、全てのコンデンサを取り外すことが困難な場合がある。その場合、図7に示すように、LSI搭載部位直下のコンデンサを取り外した状態で測定を行なう。
前記CPUの電源等価回路を用いた解析例を示す。図10に示すシミュレーション回路にて、CPUチップ内のDie端子からみたインピーダンスを解析した。プリント基板電源等価回路は平面電磁界解析(Ansys社SIWave)より抽出した。
Claims (1)
- 電源供給配線およびそれに接続されるコンデンサを備え、半導体集積回路が実装されるプリント基板の作製手法であって、
前記半導体集積回路が搭載されたプリント基板の実製品を用意し、該実製品の電源回路に実装されたコンデンサおよびコイルを全て取り外すか、または、前記半導体集積回路搭載部位直下のコンデンサを取り外して、前記実製品の電源回路のインピーダンスを測定し、
前記半導体集積回路の電源回路を除く前記実製品のプリント基板電源回路のインピーダンスを解析して、前記測定した実製品の電源回路のインピーダンスから差し引くことで、前記半導体集積回路の電源等価回路を作製し、
該作製した前記半導体集積回路の電源等価回路と前記プリント基板の電源等価回路とを統合して、前記半導体集積回路のパッケージの配線及びチップのキャパシタンスを含む当該プリント基板の電源供給系全体のインピーダンス解析を行うことで、前記半導体集積回路の電源等価回路と前記プリント基板の電源等価回路による反共振点を求め、
前記半導体集積回路の動作周波数が前記反共振点の周波数と一致しないように、前記コンデンサ若しくは前記電源供給配線を設定することを特徴とするプリント基板の作製手法。
Priority Applications (1)
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JP2012014686A JP5645855B2 (ja) | 2012-01-27 | 2012-01-27 | プリント基板の作製手法 |
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JP2012014686A JP5645855B2 (ja) | 2012-01-27 | 2012-01-27 | プリント基板の作製手法 |
Publications (2)
Publication Number | Publication Date |
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JP2013156711A JP2013156711A (ja) | 2013-08-15 |
JP5645855B2 true JP5645855B2 (ja) | 2014-12-24 |
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JP2012014686A Active JP5645855B2 (ja) | 2012-01-27 | 2012-01-27 | プリント基板の作製手法 |
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Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008070924A (ja) * | 2006-09-12 | 2008-03-27 | Nec Electronics Corp | 半導体集積回路設計方法、半導体集積回路設計プログラム、及び半導体集積回路設計装置 |
US7957150B2 (en) * | 2008-02-21 | 2011-06-07 | Hitachi, Ltd. | Support method and apparatus for printed circuit board |
JP2010009179A (ja) * | 2008-06-25 | 2010-01-14 | Elpida Memory Inc | 半導体装置もしくはプリント配線基板の設計方法および設計支援システム |
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- 2012-01-27 JP JP2012014686A patent/JP5645855B2/ja active Active
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