JP5635036B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5635036B2 JP5635036B2 JP2012129804A JP2012129804A JP5635036B2 JP 5635036 B2 JP5635036 B2 JP 5635036B2 JP 2012129804 A JP2012129804 A JP 2012129804A JP 2012129804 A JP2012129804 A JP 2012129804A JP 5635036 B2 JP5635036 B2 JP 5635036B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating resin
- resin layer
- substrate
- semiconductor chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
- Dicing (AREA)
Description
Claims (6)
- 一方の主面に複数の突出電極が設けられた半導体ウエハを用意する第1工程と、
前記一方の主面上に絶縁性樹脂層を形成して、前記複数の突出電極を前記絶縁性樹脂層内に埋め込む第2工程と、
ダイシングテープを前記半導体ウエハの他方の主面及び環状のダイシングフレームに貼付けて、前記半導体ウエハが前記ダイシングフレームに固定された状態とする第3工程と、
前記一方の主面側から前記半導体ウエハ及び前記絶縁性樹脂層をダイシングすることで、複数の半導体チップに個片化する第4工程と、
前記半導体チップを前記ダイシングテープから剥離してピックアップする第5工程と、
前記第5工程でピックアップされた前記半導体チップを位置合わせヘッドによって保持した状態で、当該半導体チップの突出電極と基板上の回路電極との位置合わせを行い、前記位置合わせヘッドを用いて当該半導体チップと前記基板とを仮固定する第6工程と、
接続ヘッド及び接続ステージを用いて当該半導体チップと前記基板とを加熱圧着することで、当該半導体チップの前記突出電極と前記基板の前記回路電極とを電気的に接続する第7工程とを備え、
前記突出電極は、Auを含む金属により形成されており、
前記回路電極は、Snを含む金属により形成されており、
前記第7工程では、前記接続ヘッド及び前記接続ステージの少なくとも一方を、前記位置合わせヘッドよりも高温で、且つ、SnとAuとの共晶温度以上の300℃以上に設定することを特徴とする半導体装置の製造方法。 - 前記基板は、ポリイミド基板である、請求項1に記載された半導体装置の製造方法。
- 前記絶縁性樹脂層の可視光に対する光透過率が10%以上であることを特徴とする、請求項1又は2に記載された半導体装置の製造方法。
- 前記半導体チップと前記基板とを加熱接続する際の温度が300℃以上であるときに、前記絶縁性樹脂層に発泡が生じないことを特徴とする、請求項1〜3のいずれか一項に記載された半導体装置の製造方法。
- 前記第2工程では、表面に絶縁性樹脂組成物が設けられたフィルムを前記一方の主面に貼付けることで前記一方の主面上に絶縁性樹脂層を形成して、前記複数の突出電極を前記絶縁性樹脂層内に埋め込むことを特徴とする、請求項1〜4のいずれか一項に記載された半導体装置の製造方法。
- 前記絶縁性樹脂層を構成する絶縁性樹脂組成物が、ポリイミド樹脂、エポキシ樹脂及び硬化剤を含有することを特徴とする、請求項1〜5のいずれか一項に記載された半導体装置の製造方法。
Priority Applications (1)
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JP2012129804A JP5635036B2 (ja) | 2008-03-21 | 2012-06-07 | 半導体装置の製造方法 |
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JP2008073458 | 2008-03-21 | ||
JP2008073458 | 2008-03-21 | ||
JP2012129804A JP5635036B2 (ja) | 2008-03-21 | 2012-06-07 | 半導体装置の製造方法 |
Related Parent Applications (1)
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JP2008246572A Division JP2009260224A (ja) | 2008-03-21 | 2008-09-25 | 半導体ウエハのダイシング方法及び半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2012165031A JP2012165031A (ja) | 2012-08-30 |
JP5635036B2 true JP5635036B2 (ja) | 2014-12-03 |
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JP2008246572A Pending JP2009260224A (ja) | 2008-03-21 | 2008-09-25 | 半導体ウエハのダイシング方法及び半導体装置の製造方法 |
JP2012129804A Expired - Fee Related JP5635036B2 (ja) | 2008-03-21 | 2012-06-07 | 半導体装置の製造方法 |
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JP2008246572A Pending JP2009260224A (ja) | 2008-03-21 | 2008-09-25 | 半導体ウエハのダイシング方法及び半導体装置の製造方法 |
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Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2004349561A (ja) * | 2003-05-23 | 2004-12-09 | Kyocera Chemical Corp | 半導体装置の接着方法とそれに使用される接着剤 |
JP4170839B2 (ja) * | 2003-07-11 | 2008-10-22 | 日東電工株式会社 | 積層シート |
JP2005089660A (ja) * | 2003-09-18 | 2005-04-07 | Nitto Denko Corp | 半導体封止用樹脂組成物 |
JP4168887B2 (ja) * | 2003-09-18 | 2008-10-22 | 日立化成工業株式会社 | 半導体装置の製造方法 |
TWI393758B (zh) * | 2005-06-06 | 2013-04-21 | Toray Industries | 半導體用黏著組成物、用它之半導體裝置及半導體裝置之製法 |
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2008
- 2008-09-25 JP JP2008246572A patent/JP2009260224A/ja active Pending
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2012
- 2012-06-07 JP JP2012129804A patent/JP5635036B2/ja not_active Expired - Fee Related
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JP2012165031A (ja) | 2012-08-30 |
JP2009260224A (ja) | 2009-11-05 |
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