JP5626847B2 - Nanostructure and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nanostructure and a manufacturing method thereof, and more particularly to a nanostructure in which a core / shell type semiconductor nanowire is formed on a substrate and a manufacturing method thereof.

  In recent years, with an increase in environmental awareness on a global scale, devices that help save energy resources such as solar cells and light-emitting diodes are rapidly spreading. In particular, the development of devices using direct transition type compound semiconductors has been actively conducted because of its high energy efficiency.

  For example, among solar cells, a multi-junction solar cell in which a plurality of diodes (cells) having different band gaps are superimposed is divided and absorbs light of a wide wavelength band of sunlight for each cell. It is expected that conversion efficiency can be achieved, and active development has been made. As one of such multi-junction solar cells, it has been reported that an extremely high conversion efficiency of 41% was obtained in a three-junction solar cell in which three cells, a GaInP cell, a GaInAs cell, and a Ge cell are joined. (For example, refer nonpatent literature 1).

  A solar cell using a core / shell type semiconductor nanowire has also been reported (for example, see Non-Patent Document 2). In the solar cell using the core-shell type semiconductor nanowire, the light absorption region can be elongated in the axial direction, and a thin film is formed so that the influence of recombination is reduced within the minority carrier diffusion length in the radial direction. Therefore, further improvement in absorption efficiency can be expected as compared with the conventional one. Further, even when there is a difference in the lattice constants of the semiconductor nanowire materials to be laminated, the semiconductor nanowires are connected to each other, so that it is effective in that there is little distortion and there is little electric loss.

  As a method for producing a core / shell type semiconductor nanowire, for example, a VLS (Vapor-Liquid-Solid) method using a metal catalyst may be mentioned. The crystal growth method by the VLS method has been confirmed in the 1960s using Au fine particles and Si semiconductors (for example, see Non-Patent Document 3). When Au and Si are alloyed, the melting point of Si is significantly lower than that of a simple substance, and particularly at the eutectic point, the melting point of Si is lowered to nearly 400 ° C. For this reason, in the vicinity of the Au fine particles, Si is converted into a liquid and Si as a raw material is efficiently decomposed, and Si is supersaturated to cause epitaxial growth similar to LPE (Liquid Phase Epitaxy). doing.

  This VLS method is not limited to the case of growing semiconductor nanowires made of silicon, but can be applied to the case of growing compound semiconductor nanowires made of a compound. In addition to the VLS method, a method for growing compound semiconductor nanowires includes, for example, a selective growth method. Either method can produce compound semiconductor nanowires with a core-shell structure by growing crystals in the axial and radial directions by changing the growth conditions. However, compound semiconductor nanowires are stacked in multiple layers. In this case, the selective growth method cannot be used, and it is necessary to grow the compound semiconductor nanowire by the VLS method.

W. Guter et al. , Appl. Phys. Lett. 94 (2009) 223504. B. M.M. Kays et al. , J. et al. Appl. Phys. 97 (2005) 114302. R. S. Wagner and W.W. C. Ellis, APL 4 (1964) 89.

  By the way, when it is going to manufacture devices, such as a multi-junction type solar cell and a multi-junction type light emitting diode, by laminating semiconductor nanowires, for example, core-shell type semiconductor nanowire (cell), the following problems arise. That is, it is necessary to provide a tunnel junction film 330 having a high carrier concentration at a portion where two semiconductor nanowires 320 and 340 are joined, but the tunnel junction film 330 is in electrical contact with the substrate 310 as shown in FIG. As a result, a leak current flows from the tunnel junction film 330 to the substrate 310. In this case, the cells below the tunnel junction film 330 among the cells constituting the device, that is, the semiconductor nanowires 320 do not function, and the intention of stacking the semiconductor nanowires is lost.

  Then, an object of this invention is to provide the nanostructure suitable for manufacture of the device which consists of laminated | stacked semiconductor nanowire, and its manufacturing method.

  A nanostructure according to the present invention includes a substrate, a semiconductor nanowire formed perpendicularly to the substrate on the substrate, and an insulator covering a part of the semiconductor nanowire, and the upper portion of the semiconductor nanowire includes: It is not covered with the insulator.

  In the nanostructure according to the present invention, the semiconductor nanowire may be a core-shell type semiconductor nanowire.

  Furthermore, in the nanostructure according to the present invention, the semiconductor nanowire may constitute a diode.

Further, the nanostructure according to the present invention, the semiconductor nanowires are respectively the semiconductor nanowires comprising one diode and semiconductor nanowires assemblies and a plurality of serially connected via a tunnel junction film, before Symbol plurality of diodes , ing from materials of different band gap from each other.

Furthermore, in the nanostructure according to the present invention, the insulator may have a resistivity of 1.0 × 10 ⁸ [Ω · m] or more and a refractive index of 2.0 or less.

  In the nanostructure according to the present invention, the insulator may be made of at least one of silicon, an oxide or a nitride of titanium.

  The method of manufacturing a nanostructure according to the present invention includes a first step of forming a semiconductor nanowire on a substrate perpendicularly to the substrate by a VLS method, and covering the semiconductor nanowire with an insulator except for an upper portion of the semiconductor nanowire. And a second step.

In the method for producing nano-structure according to the present invention, have a row the first step alternating with said second step, a semiconductor nanowire, a semiconductor nanowire including each one diode through a tunnel junction film more A series of semiconductor nanowires connected in series is formed, and a plurality of diodes are formed of materials having different band gaps .

  Furthermore, in the method for manufacturing a nanostructure according to the present invention, the second step includes a step of covering the semiconductor nanowire with an insulator, and a step of removing a part of the insulator to expose a part of the semiconductor It is good also as having.

According to the present invention, since the upper part of the semiconductor nanowire formed perpendicularly to the substrate is exposed on the substrate, a nanostructure in which another semiconductor nanowire is laminated on the upper part can be manufactured. . At this time, since the semiconductor nanowire is covered with the insulator except for the upper portion thereof, it is possible to suppress the semiconductor nanowire from being accidentally short-circuited with other parts.
In addition, since the semiconductor nanowires are stacked in the axial direction, even if there is a difference in the lattice constant of the stacked semiconductors, the interface has an area defined by the diameter of the semiconductor nanowires at most. Therefore, it is possible to connect well while suppressing strain generated in the semiconductor crystal.
Furthermore, when a plurality of semiconductor nanowires are stacked to produce a device such as a solar cell or a light-emitting diode having a multi-stage structure, the generation of leakage current is suppressed by the insulating film, so that light of multiple wavelengths can be electrically High-performance devices such as solar cells that can be converted and light-emitting diodes that can emit light of a plurality of wavelengths can be obtained.

It is sectional drawing which shows one structural example of the solar cell which concerns on Embodiment 1 of this invention. It is a figure which shows the band structure of the solar cell which concerns on Embodiment 1 of this invention. It is a perspective view which shows one structure of the solar cell which concerns on Embodiment 1 of this invention. It is process drawing which shows the manufacturing method of the solar cell which concerns on Embodiment 1 of this invention. It is process drawing which shows the manufacturing method of the solar cell which concerns on Embodiment 1 of this invention. It is process drawing which shows the manufacturing method of the solar cell which concerns on Embodiment 1 of this invention. It is process drawing which shows the manufacturing method of the solar cell which concerns on Embodiment 1 of this invention. It is the SEM photograph image | photographed when forming the 1st diode when manufacturing the solar cell which concerns on Embodiment 1 of this invention. It is the SEM photograph image | photographed when forming the 1st diode and the 2nd diode when manufacturing the solar cell which concerns on Embodiment 1 of this invention. It is sectional drawing which shows one structural example of the light emitting diode which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the example of 1 structure of the solar cell by which the conventional semiconductor nanowire was laminated | stacked.

In the nanostructure according to the present invention, the first semiconductor nanowire grown on the substrate is once covered with a silicon insulating film, and then a part of the silicon insulating film is removed to expose the upper portion of the first semiconductor nanowire. Then, a new semiconductor nanowire (second semiconductor nanowire) is further grown on the exposed first semiconductor nanowire. Semiconductor nanowires can be grown using the VLS method.
Hereinafter, as Embodiments 1 and 2 of the present invention, a case where nanostructures are respectively used for a solar cell and a light emitting element will be described in detail with reference to the drawings.

[Embodiment 1]
First, the solar cell according to Embodiment 1 of the present invention has a structure in which core-shell type semiconductor nanowires are stacked on a substrate in the axial direction. FIG. 1 is a cross-sectional view along the axial direction of a semiconductor nanowire of a solar cell.
As shown in FIG. 1, the solar cell according to the present embodiment includes a substrate 110, a first semiconductor nanowire 120 formed on the substrate 110, and the first semiconductor nanowire via the tunnel junction film 130. , A second semiconductor nanowire 140 connected thereto, a silicon resin film 114 (corresponding to an insulator) covering these, a transparent electrode 150, an electrode 160, and an external load 170.
Among these, the first semiconductor nanowire 120 and the second semiconductor nanowire 140 are both core-shell type semiconductor nanowires, as will be described later, and form the first diode 120 and the second diode 140, respectively. .
Note that Au fine particles 112 are disposed on the second semiconductor nanowire 140. The Au fine particles 112 are fine particles having a diameter of about 20 nm made of Au, and are used when the semiconductor nanowires 120 and 140 and the tunnel junction film 130 are formed by the VLS method.

Here, the substrate 110 is a substrate made of a p-InP semiconductor, and the surface thereof faces the (111) B direction.
The first semiconductor nanowire (first diode) 120 is a core-shell type nanowire, and includes a p-InP layer 120a, an i-InAsP layer 120b, and an n-InP layer 120c in order from the center toward the outside. , A pin structure diode.
Similarly, the second semiconductor nanowire (second diode) 140 is a core-shell type nanowire, and the p-GaP layer 140a, the i-GaAsP layer 140b, and the n-GaP layer sequentially from the center toward the outside. This is a diode having a pin structure having 140c.
The tunnel junction film 130 includes an n ⁺ -InP layer 130 a and a p ⁺ -GaP layer 130 b having a relatively high impurity concentration, and the n − InP layer 120 c of the first diode 120 and the p − of the second diode 140. It plays the role of electrically connecting the GaP layer 140a.
The silicon resin film 114 is made of silicon resin, and its insulating action prevents each component, for example, the tunnel junction film 130 from conducting with the substrate 110 or the like. Further, since the silicon resin film 114 is optically transparent, light that has reached from the outside can reach the first diode 120 and the second diode 140 without being blocked by the silicon resin film 114. .
The transparent electrode 150 is made of an ITO (indium tin oxide) film, and is connected to an external load 170 as a cathode of the solar cell.
The electrode 160 is made of a metal that is in ohmic contact with the substrate 110, and is connected to the external load 170 as an anode of the solar cell.

  FIG. 2 is a diagram showing a band structure of the solar cell according to the above-described embodiment. As shown in FIG. 2, the first diode 120 made of an InP-based material can convert light having a relatively long wavelength into electricity, while the second diode 140 made of a GaP-based material is relatively short. Wavelength light can be converted into electricity. Further, since the generation of leakage current is suppressed by the silicon resin film 114, the plurality of diodes function as a component of one solar cell. Therefore, the conversion efficiency of the whole solar cell is improved by having these two diodes.

  In the above description, the description has focused on one solar cell made of a plurality of semiconductor nanowires (diodes) connected in series. However, as a solar cell using the nanostructure according to the present invention, FIG. It goes without saying that a plurality of solar cells 116 may be arranged on a substrate to form a solar cell array as shown in FIG.

  Next, a method for manufacturing a nanostructure according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 4A, Au fine particles 112 are formed on the substrate 110. Specific methods include, for example, a method of self-forming by vapor deposition and annealing of Au, a method of patterning using electron beam drawing, and a method of applying a solution containing Au fine particles 112.

Next, as illustrated in FIG. 4B, a p-InP layer 120 a is formed under the Au fine particles 112. This can be performed using a well-known VLS method. For example, the substrate 110 is placed in a metal organic vapor phase epitaxy (MOVPE) apparatus, and TMIn (trimethylindium) is 1 × 10 ° C. at 380 ° C. ^-5 mol / min, PH ₃ (phosphine) 6 × 10 ⁻⁴ mol / min and DEZn (diethyl zinc) are introduced at a rate of 1 × 10 ⁻⁶ mol / min for 5 minutes to grow p-InP nanowires be able to.

  Subsequently, as shown in FIG. 4C, a silicon resin film 114a covering a part of the columnar p-InP layer 120a that is a semiconductor nanowire and at least the surface of the substrate 110 in the vicinity thereof is formed. At this time, a portion including the upper portion of the p-InP layer 120a is exposed from the silicon resin film 114a. For example, a silicon resin is applied to the substrate 110 taken out from the MOVPE apparatus, the p-InP layer 120a is embedded, heated to 200 ° C. and solidified, and then silicon is etched using an organic solvent such as acetone or by etching. This can be realized by removing the surface portion of the resin and exposing the upper portion of the p-InP layer 120a.

Next, as shown in FIG. 5D, the i-InAsP layer 120b and the n-InP layer 120c are formed using the p-InP layer 120a exposed from the silicon resin film 114a as a core, and the pin-type first diode 120 is formed. To complete.
Specifically, the substrate 110 is placed in the MOVPE apparatus again, the temperature is set to 430 ° C., TMIn is 1 × 10 ⁻⁵ mol / min, PH ₃ is 5 × 10 ⁻⁴ mol / min, AsH _3. The i-InAsP layer 120b can be formed by waiting for 5 minutes while introducing at a rate of 1 × 10 ⁻⁴ mol / min. Thereafter, TMIn is introduced at a rate of 1 × 10 ⁻⁵ mol / min, PH ₃ is introduced at a rate of 6 × 10 ⁻⁴ mol / min, and Si ₂ H ₆ (disilane) is introduced at a rate of 1 × 10 ⁻⁶ mol / min. As a result, the n-InP layer 120c can be grown in the radial direction.
FIG. 8 is an SEM photograph of the first diode 120 formed as described above. From FIG. 8, it can be seen that the first diode 120 is formed perpendicular to the substrate 110.
In the pin-type first diode 120 formed as described above, the p-InP layer 120a is connected to the substrate 110, while the i-InAsP layer 120b and the n-InP layer 120c are made of silicon. It is insulated from the substrate 110 by the resin film 114a.

  Subsequently, as shown in FIG. 5E, a silicon resin film 114b covering the first diode 120 is formed. At this time, the upper part of the first diode 120 is exposed from the silicon resin film 114b. As described above, this may be a combination of application of silicon resin and removal by organic solvent or etching.

Next, as illustrated in FIG. 5F, a tunnel junction film 130 including an n ⁺ -InP layer 130 a and a p ⁺ -GaP layer 130 b is formed on the first diode 120. For example, in a MOVPE apparatus, TMIn is 1 × 10 ⁻⁵ mol / min, PH ₃ is 6 × 10 ⁻⁴ mol / min, and Si ₂ H ₆ is 1 × 10 ⁻⁴ mol / min at 550 ° C. Then, after waiting for 20 seconds, the n ⁺ -InP layer 130a is formed. Thereafter, TMGa is introduced at a rate of 1 × 10 ⁻⁵ mol / min, PH ₃ is introduced at a rate of 6 × 10 ⁻⁴ mol / min, DEZn is introduced at a rate of 1 × 10 ⁻⁴ mol / min, and then waiting for 20 seconds, p ⁺ -GaP Layer 130b can be formed.
The tunnel junction film 130 formed in this way is insulated from the substrate 110 by the silicon resin films 114a and 114b.

Subsequently, as illustrated in FIG. 6G, a p-GaP layer 140 a is formed on the tunnel junction film 130. For example, the substrate 110 is placed in a MOVPE apparatus, TMGa is 1 × 10 ⁻⁵ mol / min, PH ₃ is 6 × 10 ⁻⁴ mol / min, and DEZn is 1 × 10 ⁻⁶ mol / min at 490 ° C. The p-GaP layer 140a can be formed by introducing at a rate and waiting for 5 minutes.

  Next, as shown in FIG. 6H, a silicon resin film 114c is formed to cover the tunnel junction film 130 and a part (root part) of the p-GaP layer 140a. At this time, the portion including the upper portion of the p-GaP layer 140a is exposed from the silicon resin film 114c. As described above, this may be a combination of application of silicon resin and removal by organic solvent or etching.

Subsequently, as shown in FIG. 7I, the i-GaAsP layer 140b and the n-GaP layer 140c are formed using the p-GaP layer 140a exposed from the silicon resin film 114c as a core, and a pin-type second diode is formed. 140 is completed.
Specifically, the substrate 110 is again placed in the MOVPE apparatus, the temperature is set to 530 degrees, TMGa is 1 × 10 ⁻⁵ mol / min, PH ₃ is 5 × 10 ⁻⁴ mol / min, AsH _3. Can be formed at a rate of 1 × 10 ⁻⁴ mol / min and wait for 5 minutes to form the i-GaAsP layer 140b. Thereafter, TMGa is introduced at 1 × 10 ⁻⁵ mol / min, PH ₃ is introduced at 6 × 10 ⁻⁴ mol / min, Si ₂ H ₆ is introduced at 1 × 10 ⁻⁶ mol / min, and n-GaP is waited for 5 minutes. The layer 140c can be grown in the radial direction.
FIG. 9 is an SEM photograph of the first diode 120 and the second diode 140 formed as described above. From FIG. 9, it can be seen that the first diode 120 and the second diode 140 are stacked.
In the pin-type second diode 140 formed as described above, the p-GaP layer 140a is connected to the tunnel junction film 130, while the i-GaAsP layer 140b and the n-GaP layer 140c are The silicon resin films 114a, 114b, and 114c are insulated from the substrate 110, the first diode 120, and the tunnel junction film 130.
Further, since the silicon resin films 114a, 114b, and 114c have a refractive index smaller than 2.0, light can reach the semiconductor nanowires that form the diode.

  Finally, as shown in FIG. 7 (j), the transparent electrode 150 and the electrode 160 are formed to obtain a solar cell. An external load 170 is connected between these electrodes.

  As described above, according to the solar cell according to the present embodiment, a structure having the second diode 140 laminated on the first diode 120 via the tunnel junction film 130 has a relatively long wavelength. Since light can be converted into electricity by the first diode 120 and light having a relatively short wavelength can be converted into electricity by the second diode 140, the conversion rate can be improved. At this time, since the silicon resin film 114 is formed everywhere between the substrate 110, the first diode 120, the tunnel junction film 130, and the second diode 140, it is possible to suppress an accidental short circuit. In addition, since both the first diode 120 and the second diode 140 are core / shell type semiconductor nanowires, even when there is a difference in the lattice constant of the stacked semiconductors, the semiconductor nanowires are connected to each other, so It is possible to connect well without generating.

  In the above-described embodiment, the two-stage junction solar cell in which two diodes, the first diode 120 and the second diode 140, are stacked. However, three or more diodes may be stacked. .

  In the above-described embodiment, the substrate 110 is used as it is. However, only the substrate 110 is removed by a method such as etching, and the remaining members are a glass substrate with a conductive film, a PET (polyethylene terephthalate) substrate, or the like. It is also possible to paste on.

  Furthermore, in the above-described embodiment, the solar cell is described. However, the semiconductor nanowire may be formed on the substrate and may be a nanostructure covered with an insulator.

[Embodiment 2]
Next, a light emitting diode according to Embodiment 2 of the present invention will be described.
The light emitting diode according to the present embodiment includes a diode made of a core / shell type semiconductor nanowire. FIG. 10 is a cross-sectional view along the axial direction of the semiconductor nanowire of the light emitting diode according to the present embodiment. As shown in FIG. 10, the light-emitting diode according to the present embodiment includes a core / shell type first semiconductor nanowire (first diode) 220, a second semiconductor nanowire (second diode) 240, and a third semiconductor nanowire (second diode) 240. A three-junction structure in which semiconductor nanowires (third diodes) 260 are stacked is formed, and these three diodes are joined by tunnel junction films 230 and 250. In the solar cell according to Embodiment 1, the external load 170 is connected, whereas in the light emitting diode according to the present embodiment, the power source 290 is connected.
By changing the composition of the first diode 220, the second diode 240, and the third diode 260, when current is supplied from the power supply 290, light having different wavelengths can be emitted from these three diodes.

Next, an example of a method for manufacturing the light emitting diode according to the present embodiment will be described.
First, Au fine particles 212 are coated on a p-InP (111) B substrate 210, and then the substrate 210 is placed in a MOVPE apparatus, and TMIn is 1 × 10 ⁻⁵ mol / min and PH ₃ is 6 at 380 ° C. The p-InP layer 220a is grown for 5 minutes by introducing × 10 ⁻⁴ mol / min and DEZn at a rate of 1 × 10 ⁻⁶ mol / min.

  Next, the substrate 210 is taken out, a silicon oxide film 214a is formed by a plasma sputtering apparatus and the p-InP layer 220a is embedded, and an upper portion of the p-InP layer 220a is exposed by fluorine ions by a reactive ion etching apparatus.

Again, the substrate 210 was placed in the MOVPE apparatus, the temperature was set to 430 ° C., TMIn 1 × 10 ⁻⁵ was introduced at a rate of mol / min, and PH ₃ was introduced at a rate of 6 × 10 ⁻⁴ mol / min for 5 minutes. By waiting, the i-InP layer 220b, followed by TMIn at a rate of 1 × 10 ⁻⁵ mol / min, PH ₃ at 3 × 10 ⁻⁴ mol / min, and AsH ₃ at a rate of 3 × 10 ⁻⁴ mol / min. Then, TMIn is introduced at a rate of 1 × 10 ⁻⁵ mol / min and PH ₃ at a rate of 6 × 10 ⁻⁴ mol / min for 5 minutes to grow an InP / InAsP / InP layer 220b of the first active layer, TMIn was introduced at a rate of 1 × 10 ⁻⁵ mol / min, PH ₃ at a rate of 6 × 10 ⁻⁴ mol / min, and Si ₂ H ₆ at a rate of 1 × 10 ⁻⁶ mol / min to form the n-InP layer 220c for 5 minutes. The first diode 220 was fabricated by growing in the radial direction.
In the first diode 220, the p-InP layer 220a is connected to the substrate 210, while the i-InAsP layer 220b and the n-InP layer 220c are insulated from the substrate 210 by the silicon oxide film 214a.

  Next, the substrate 220 is taken out, a silicon oxide film 214b is deposited by a plasma sputtering apparatus to embed the first diode 220, and an upper portion of the first diode 220 is exposed by fluorine ions by a reactive ion etching apparatus.

Subsequently, TMIn was introduced into the MOVPE apparatus at a rate of 1 × 10 ⁻⁵ mol / min, PH ₃ at 6 × 10 ⁻⁴ mol / min, and Si ₂ H ₆ at a rate of 1 × 10 ⁻⁴ mol / min at 550 ° C. Waiting for 20 seconds, introducing TMGa at a rate of 1 × 10 ⁻⁵ mol / min, PH ₃ at a rate of 6 × 10 ⁻⁴ mol / min, and DEZn at a rate of 1 × 10 ⁻⁴ mol / min, and growing for 20 seconds. As a result, an n ⁺ / p ⁺ tunnel junction film 230 is formed.

The second diode 240, the tunnel junction film 250, and the third diode 260 are formed by repeating the same procedure. Here, the raw material supply amount of the i-InAsP layer 240b as the second active layer is as follows: TMIn is 1 × 10 ⁻⁵ mol / min, PH ₃ is 4 × 10 ⁻⁴ mol / min, and AsH ₃ is 2 × 10. ^-4 mol / min, in the i-InAsP layer 260b as the third active layer, TMIn is 1 × 10 ⁻⁵ mol / min, PH ₃ is 5 × 10 ⁻⁴ mol / min, and AsH ₃ is 1 × 10 ^{− What} is necessary is just ⁴ mol / min.

  Finally, a transparent electrode 270 is manufactured by covering the surface with an ITO (indium tin oxide) film, and a power supply 290 is provided between the transparent electrode 280 and the three-junction light-emitting diode according to this embodiment is obtained. It is done. The i-InAsP layer 220b as the first active layer, the i-InAsP layer 240b as the second active layer, and the i-InAsP layer 260b as the third active layer have different compositions. The peak wavelength is different. Accordingly, the entire light emission has a wide characteristic with a wavelength band of 1.1 to 1.7 mm. Here, the InAsP system is used as the material, but III-V group compounds or II-VI group compounds in which the group III is changed to Al, Ga, In, the group V is changed to N, P, As, Sb, etc. Good. Since the silicon oxide films 214a to 214e have a refractive index smaller than 2.0, light emitted from the diode can pass through the silicon oxide film 214.

In the first and second embodiments described above, the silicon resin film 114 and the silicon oxide film 214 are used as the insulators. However, any material can be used as long as it has an insulating function and transmits light. Oxides, nitrides, and the like containing bismuth may be used. In this case, it is desirable to use one having a resistivity of 1.0 × 10 ⁸ [Ω · m] or more and a refractive index of 2.0 or less.

  The present invention can be used in the manufacturing industry of solar cells and light emitting diodes.

DESCRIPTION OF SYMBOLS 110 ... Board | substrate, 112 ... Au fine particle, 114, 114a-c ... Silicone resin film, 116 ... Solar cell, 120 ... 1st diode (1st semiconductor nanowire), 120a ... p-InP layer, 120b ... i-InAsP Layer, 120c ... n-InP layer, 130 ... tunnel junction film, 130a ... n ⁺ -InP layer, 130b ... p ⁺ -GaP layer, 140 ... second diode (second semiconductor nanowire), 140a ... p-GaP layer 140b ... i-GaAsP layer, 140c ... n-GaP layer, 150 ... transparent electrode, 160 ... electrode, 170 ... external load, 210 ... substrate, 212 ... Au fine particles, 214, 214a to e ... silicon oxide film, 220 ... First diode, 220a ... p-InP layer, 220b ... i-InAsP layer, 220c ... n-InP layer, 230 ... tunnel junction film 230a ... n ⁺ -InP layer, 230b ... p ⁺ -InP layer, 240 ... second diode, 240a ... p-InP layer, 240b ... i-InAsP layer, 240c ... n-InP layer, 250 ... tunnel junction film, 260 3rd diode 260a ... p-InP layer 260b ... i-InAsP layer 260c ... n-InP layer 270 ... transparent electrode 280 ... electrode 290 ... power source 310 ... substrate 320,340 ... nanowire 330 ... tunnel coupling film.

Claims (6)

A substrate,
Semiconductor nanowires formed perpendicular to the substrate on the substrate;
An insulator covering a part of the semiconductor nanowire,
A plurality of the semiconductor nanowires each including one diode connected in series via a tunnel junction film, and an assembly of the semiconductor nanowires,
The plurality of diodes are made of materials having different band gaps,
The top of the semiconductor nanowire is not covered with the insulator. Nanostructure characterized by the above-mentioned. The nanostructure of claim 1, wherein
The said semiconductor nanowire is a core-shell type semiconductor nanowire. The nanostructure characterized by the above-mentioned. The nanostructure according to claim 1 or 2 ,
The insulator resistivity of ^{1.0 × 10 8 [Ω · m} ] or more, and wherein a refractive index of 2.0 or less to Luna Bruno structure. The nanostructure according to any one of claims 1 to 3 ,
The insulator is silicon, features and be Luna Roh structure that consists of at least one of oxides or nitrides of titanium. A first step of forming semiconductor nanowires perpendicular to the substrate on the substrate by a VLS method;
A second step of covering the semiconductor nanowire with an insulator except for the top of the semiconductor nanowire;
Equipped with a,
Alternately performing the first step and the second step;
The semiconductor nanowires are formed as an assembly of semiconductor nanowires in which a plurality of semiconductor nanowires each including one diode are connected in series via a tunnel junction film, and the plurality of diodes are formed in a state made of materials having different band gaps. method for producing a nano-structure, characterized in that. The method for producing a nanostructure according to claim 5 , wherein
The second step includes
Covering the semiconductor nanowire with an insulator;
And a step of removing a part of the insulator to expose a part of the semiconductor.