JP5607289B2 - タイミング制御回路及び半導体記憶装置 - Google Patents

タイミング制御回路及び半導体記憶装置 Download PDF

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Publication number
JP5607289B2
JP5607289B2 JP2007233001A JP2007233001A JP5607289B2 JP 5607289 B2 JP5607289 B2 JP 5607289B2 JP 2007233001 A JP2007233001 A JP 2007233001A JP 2007233001 A JP2007233001 A JP 2007233001A JP 5607289 B2 JP5607289 B2 JP 5607289B2
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Japan
Prior art keywords
signal
clock
clock signal
timing
circuit
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Expired - Fee Related
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JP2007233001A
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Japanese (ja)
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JP2009064526A (ja
JP2009064526A5 (enExample
Inventor
昭 井出
康浩 高井
知紀 関口
理一郎 竹村
悟 秋山
浩晃 中谷
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PS4 Luxco SARL
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PS4 Luxco SARL
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Priority to JP2007233001A priority Critical patent/JP5607289B2/ja
Priority to US12/205,668 priority patent/US7973582B2/en
Publication of JP2009064526A publication Critical patent/JP2009064526A/ja
Publication of JP2009064526A5 publication Critical patent/JP2009064526A5/ja
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/15033—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of bistable devices

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
JP2007233001A 2007-09-07 2007-09-07 タイミング制御回路及び半導体記憶装置 Expired - Fee Related JP5607289B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007233001A JP5607289B2 (ja) 2007-09-07 2007-09-07 タイミング制御回路及び半導体記憶装置
US12/205,668 US7973582B2 (en) 2007-09-07 2008-09-05 Timing control circuit and semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007233001A JP5607289B2 (ja) 2007-09-07 2007-09-07 タイミング制御回路及び半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2009064526A JP2009064526A (ja) 2009-03-26
JP2009064526A5 JP2009064526A5 (enExample) 2011-07-21
JP5607289B2 true JP5607289B2 (ja) 2014-10-15

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JP2007233001A Expired - Fee Related JP5607289B2 (ja) 2007-09-07 2007-09-07 タイミング制御回路及び半導体記憶装置

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Country Link
US (1) US7973582B2 (enExample)
JP (1) JP5607289B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009152658A (ja) * 2007-12-18 2009-07-09 Elpida Memory Inc 半導体装置
KR20130057855A (ko) * 2011-11-24 2013-06-03 에스케이하이닉스 주식회사 반도체 메모리 장치
DE102012216002B3 (de) * 2012-05-18 2013-09-12 Leica Microsystems Cms Gmbh Schaltung und Verfahren zum Erzeugen von periodischen Steuersignalen sowie Mikroskop und Verfahren zum Steuern eines Mikroskops
JP5717897B2 (ja) * 2014-03-14 2015-05-13 キヤノン株式会社 情報処理装置又は情報処理方法
US12088296B2 (en) * 2021-12-17 2024-09-10 Advanced Micro Devices, Inc. Clock gating using a cascaded clock gating control signal
CN116758971B (zh) * 2023-06-09 2024-02-02 合芯科技有限公司 一种寄存器堆的时序测试电路及芯片

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819929A (ja) * 1981-07-29 1983-02-05 Nec Corp デイジタル装置
JP2704203B2 (ja) * 1988-02-24 1998-01-26 日本電信電話株式会社 タイミング発生装置
JPH04196813A (ja) * 1990-11-28 1992-07-16 Asia Electron Inc 遅延回路
JPH0677789A (ja) * 1992-06-24 1994-03-18 Verisys Inc タイミング信号遅延装置
US6154821A (en) * 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
JP3560319B2 (ja) * 1998-04-03 2004-09-02 松下電器産業株式会社 位相調整回路
US6895522B2 (en) * 2001-03-15 2005-05-17 Micron Technology, Inc. Method and apparatus for compensating duty cycle distortion in a data output signal from a memory device by delaying and distorting a reference clock
US7154978B2 (en) * 2001-11-02 2006-12-26 Motorola, Inc. Cascaded delay locked loop circuit
JP2004110490A (ja) 2002-09-19 2004-04-08 Renesas Technology Corp タイミング制御回路装置
US7218158B2 (en) * 2004-08-27 2007-05-15 Micron Technology, Inc. Self-timed fine tuning control
JP3821825B2 (ja) 2004-12-27 2006-09-13 Ｎｔｔエレクトロニクス株式会社 タイミング発生回路
KR100644127B1 (ko) * 2005-01-03 2006-11-10 학교법인 포항공과대학교 무한의 위상 이동 기능을 가지는 전압 제어 지연 라인을기반으로 하는 듀얼 루프 디엘엘
KR20080037233A (ko) * 2006-10-25 2008-04-30 삼성전자주식회사 지연 동기 루프 회로
KR100868015B1 (ko) * 2007-02-12 2008-11-11 주식회사 하이닉스반도체 지연 장치, 이를 이용한 지연 고정 루프 회로 및 반도체메모리 장치
KR100985413B1 (ko) * 2008-10-14 2010-10-06 주식회사 하이닉스반도체 지연회로 및 그를 포함하는 지연고정루프회로

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Publication number Publication date
JP2009064526A (ja) 2009-03-26
US20090066390A1 (en) 2009-03-12
US7973582B2 (en) 2011-07-05

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