JP5597120B2 - メモリアクセス装置 - Google Patents
メモリアクセス装置 Download PDFInfo
- Publication number
- JP5597120B2 JP5597120B2 JP2010276730A JP2010276730A JP5597120B2 JP 5597120 B2 JP5597120 B2 JP 5597120B2 JP 2010276730 A JP2010276730 A JP 2010276730A JP 2010276730 A JP2010276730 A JP 2010276730A JP 5597120 B2 JP5597120 B2 JP 5597120B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- address
- output
- bits
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Memory System (AREA)
- Dram (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010276730A JP5597120B2 (ja) | 2010-12-13 | 2010-12-13 | メモリアクセス装置 |
| US13/311,985 US20120147690A1 (en) | 2010-12-13 | 2011-12-06 | Memory accessing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010276730A JP5597120B2 (ja) | 2010-12-13 | 2010-12-13 | メモリアクセス装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012128478A JP2012128478A (ja) | 2012-07-05 |
| JP2012128478A5 JP2012128478A5 (https=) | 2014-01-23 |
| JP5597120B2 true JP5597120B2 (ja) | 2014-10-01 |
Family
ID=46199267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010276730A Expired - Fee Related JP5597120B2 (ja) | 2010-12-13 | 2010-12-13 | メモリアクセス装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20120147690A1 (https=) |
| JP (1) | JP5597120B2 (https=) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5949639A (ja) * | 1982-09-16 | 1984-03-22 | Hitachi Ltd | 記憶回路の語長変更回路 |
| JPS61139866A (ja) * | 1984-12-11 | 1986-06-27 | Toshiba Corp | マイクロプロセツサ |
| JPH05210572A (ja) * | 1992-01-30 | 1993-08-20 | Casio Comput Co Ltd | メモリ制御装置 |
| JP2002063791A (ja) * | 2000-08-21 | 2002-02-28 | Mitsubishi Electric Corp | 半導体記憶装置およびメモリシステム |
| JP4052878B2 (ja) * | 2002-05-28 | 2008-02-27 | 松下電器産業株式会社 | 情報処理装置 |
| JP2007164415A (ja) * | 2005-12-13 | 2007-06-28 | Sony Corp | データ転送制御装置 |
-
2010
- 2010-12-13 JP JP2010276730A patent/JP5597120B2/ja not_active Expired - Fee Related
-
2011
- 2011-12-06 US US13/311,985 patent/US20120147690A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US20120147690A1 (en) | 2012-06-14 |
| JP2012128478A (ja) | 2012-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7529139B2 (en) | N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof | |
| US8358557B2 (en) | Memory device and method | |
| JP2009015832A (ja) | アクセス間調停回路、半導体装置およびアクセス間調停方法 | |
| CN101876946A (zh) | 存储器控制装置和存储器控制方法 | |
| US11625196B2 (en) | Semiconductor memory device and operating method thereof | |
| JP4947395B2 (ja) | 半導体試験装置 | |
| JP5597120B2 (ja) | メモリアクセス装置 | |
| JP7591901B2 (ja) | ディジタル信号処理装置及びディジタル信号処理装置の制御方法 | |
| JP3967559B2 (ja) | 制御回路及び半導体記憶装置 | |
| US20130100757A1 (en) | Dual-Port Memory and a Method Thereof | |
| JP2013182373A (ja) | 記憶装置及びその制御方法 | |
| JP4019757B2 (ja) | 記憶装置 | |
| JP2004280924A (ja) | メモリテスト回路 | |
| JP2005259266A (ja) | 試験装置及び試験方法 | |
| JP6461831B2 (ja) | メモリ検査装置 | |
| JP4866194B2 (ja) | 集積回路及びリコンフィギュラブル回路の入力データ制御方法 | |
| JP2011238331A (ja) | 半導体装置のアドレス出力タイミング制御回路 | |
| JP2016118950A (ja) | 半導体装置、メモリアクセス制御方法、及び半導体装置システム | |
| JP2010287150A (ja) | データ転送回路 | |
| JP2008077418A (ja) | メモリアクセス装置 | |
| JP4811909B2 (ja) | アドレス生成回路およびデータ記憶装置 | |
| US9251887B2 (en) | Static random access memory system and operation method thereof | |
| KR20090011250A (ko) | 단일 포트 메모리를 이용하여 다중 포트 메모리를 구현하는방법 및 장치 | |
| JP2008299704A (ja) | アドレス変換回路、ベクトル処理装置、ベクトル処理システム、および、アドレス変換方法 | |
| EP2587485A1 (en) | A dual-port memory and a method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20130404 |
|
| RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20130521 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131128 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20131128 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20140411 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140422 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140623 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140716 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140808 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 5597120 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| LAPS | Cancellation because of no payment of annual fees |