JP5596582B2 - Class D amplifier - Google Patents

Description

  The present invention relates to a circuit technique for driving and controlling a transistor of an output stage of a class D amplifier, and more particularly to a circuit technique effective when a transistor of an output stage is a DMOS (Double Diffused MOS) transistor.

  A half-bridge or bridge-type class D amplifier includes a push-pull output stage in which power MOS transistors are connected in series. This output stage needs to control the power MOS transistor with a control signal having a dead time in order to prevent the power MOS transistors connected in series from being simultaneously turned on. However, when the dead time is increased, there is a problem that the distortion rate of the analog output through the LC type low-pass filter is deteriorated. For this reason, it is necessary to make the dead time as small as possible. As the dead time is smaller, the distortion of the output waveform of the class D amplifier is reduced and the sound quality is improved.

  As described above, in the class D amplifier, it is necessary to provide a dead time in order to reduce the through current of the output stage and suppress the heat generation amount and the reactive power consumption. However, the dead time can be increased in order to improve the distortion rate of the analog output signal. Must be as small as possible.

  In recent years, by using a BCD (bipolar CMOS-DMOS) process technology, a module portion (modulation portion) requiring high integration is formed by a CMOS process technology, and a driver portion requiring high breakdown voltage is formed by a DMOS process technology. It has become possible to form a class D amplifier on one chip. However, in a DMOS transistor, the maximum voltage that can be applied between the gate and source of the transistor is lower than the maximum voltage that can be applied between the drain and source for structural reasons. For this reason, when the power supply voltage of the transistor in the output stage is set to the maximum voltage value, there is a problem that a voltage equal to the power supply voltage cannot be applied between the gate and the source.

  FIG. 6 shows a block circuit diagram of a conventional class D amplifier. A conventional class D amplifier includes a modulator, an output transistor driving circuit having a function of generating a dead time, and two series-connected NMOS transistors (NH, NL) that are turned on with an H level gate voltage. It is comprised by the push pull type output stage which consists of. In this way, in the half-bridge type class D amplifier configured to convert the PWM signal into an analog output signal through the LC low-pass filter and sound the load speaker (SPK), the upper NMOS transistor (NH) of the output stage A through current is eliminated by providing a dead time between the switching signal applied to the gate and the switching signal applied to the gate of the lower NMOS transistor (NL).

  The output transistor drive circuit shown in FIG. 6 inputs the PWM signal output from the modulator, the signal inverted by the inverter circuit, and the signal obtained by delaying each signal by the delay circuit including the resistor R and the capacitor C to the AND circuit. As a result, the gate signals SH and SL are generated. For this reason, the dead time is determined by the values of the resistor R and the capacitor C.

  FIG. 5 shows a driver circuit having a dead time disclosed in Patent Document 1. In FIG. A high-side gate switch 101, a low-side gate switch 102, and a driver circuit 100 that controls on / off of the gate switch are provided. The high-side gate switch 101 is controlled based on the upper control input, and the low-side gate switch 102 is controlled based on the lower control input. In the high-side gate switch 101 and the low-side gate switch 102, the conductivity of the gate switch is detected by the first conductivity detection circuit 105 and the second conductivity detection circuit 106, respectively. AND logic circuits (103, 104) are provided so that the other control input is enabled in the conductive state. This prevents the high-side and low-side gate switches from being turned on simultaneously.

JP 2004-166207 A

  In the method of generating a dead time using a delay circuit composed of a resistor and a capacitor as shown in FIG. 6, it is difficult to obtain a highly accurate dead time because the values of the resistor and the capacitor vary due to manufacturing variations.

  Further, the gate switch of the invention according to Patent Document 1 is configured by a normal MOS transistor. As described above, a normal MOS transistor can apply a voltage equal to the maximum drain-source voltage between the gate and source of the transistor, but in a DMOS transistor, the maximum voltage that can be applied between the gate and source. Is lower than the maximum drain-source voltage. Therefore, if the MOS transistor at the output stage of the circuit of FIG. 5 is configured by a DMOS transistor, the power supply voltage at the output stage cannot be the maximum voltage between the drain and source of the DMOS transistor. As described above, the driver circuit according to Patent Document 1 has a problem in that the function of the DMOS transistor having a high breakdown voltage characteristic cannot be sufficiently exhibited.

In order to solve this problem, the invention according to claim 1 includes a high-side P-channel DMOS transistor and a low-side N-channel DMOS transistor connected in series between a high power supply voltage and a low power supply voltage, and the high power supply voltage. A high-side driving circuit for driving the high-side P-channel DMOS transistor based on a high-side control signal, a second intermediate power-supply voltage, and the low power-supply voltage. disposed between, and a low-side drive circuit for driving the low-side N-channel DMOS transistor based on the low side control signal, the high-side drive circuit, when the low-side N-channel DMOS transistor is non-conductive, the Corresponds to the first intermediate power supply voltage based on the high-side control signal A low-side drive circuit that corresponds to the second intermediate power supply voltage based on the low-side control signal when the high-side P-channel DMOS transistor is non-conductive. In the class D amplifier including a second voltage conversion circuit that generates a voltage to be generated , the first voltage conversion circuit includes a first PMOS transistor and a first voltage between the high power supply voltage and the low power supply voltage. A parallel connection circuit of resistors, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor that is conductive when the low-side N-channel DMOS transistor is non-conductive are connected in series from the high power supply voltage side. Connect the gates of the first PMOS transistor and the first NMOS transistor to a common input terminal. The second PMOS transistor has a configuration in which the gate of the second PMOS transistor is connected to the first intermediate power supply voltage, and the second voltage conversion circuit includes the high side voltage between the high power supply voltage and the low power supply voltage. A third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, and a parallel connection circuit of the fourth NMOS transistor and the second resistor that are turned on when the P-channel DMOS transistor is non-conductive are connected in series. Are connected in order from the high power supply voltage side, the gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to a common input terminal, and the gate of the third NMOS transistor is connected to the second intermediate power supply. It is characterized by comprising a configuration connected to a voltage .

According to a second aspect of the present invention, in the class D amplifier according to the first aspect, the first voltage conversion circuit has a gate commonly connected to a gate of the low-side N-channel DMOS transistor, and a source connected to the low power supply voltage. The first N-channel DMOS transistor to be connected and one end connected to the drain of the first N-channel DMOS transistor and the other end connected directly or via the first switch means to the second intermediate power supply voltage. A first input level detection circuit configured by a third resistor, the output of which is a connection point between the drain of the first N-channel DMOS transistor and the third resistor; and the second voltage conversion circuit includes: A first P channel having a gate commonly connected to the gate of the high side P-channel DMOS transistor and a source connected to the high power supply voltage. And a fourth resistor having one end connected to the drain of the first P-channel DMOS transistor and the other end connected directly or via the second switch means to the first intermediate power supply voltage. And a second input level detection circuit that outputs a connection point between the drain of the first P-channel DMOS transistor and the fourth resistor, the threshold voltage of the first N-channel DMOS transistor and the low side The threshold voltage of the N channel DMOS transistor is equal, and the threshold voltage of the first P channel DMOS transistor is equal to the threshold voltage of the high side P channel DMOS transistor .

According to a third aspect of the present invention, in the class D amplifier circuit according to the first or second aspect, switching means for switching a gate input of the second PMOS transistor to the high power supply voltage, and the third NMOS It has switching means for switching the gate connection of the transistor to the low power supply voltage .

  The driver drive circuit of the class D amplifier of the present invention can be formed of any MOS transistor. In particular, when the output transistor is formed of a DMOS transistor, the power supply voltage of the output stage is increased to the maximum power supply voltage. be able to. Further, the total harmonic distortion can be lowered by minimizing the dead time.

1 is a circuit diagram of a first embodiment of a class D amplifier according to the present invention. FIG. It is a circuit diagram of a second embodiment of a class D amplifier according to the present invention. FIG. 5 is a circuit diagram of a third embodiment of a class D amplifier according to the present invention. It is a wave form diagram which shows the gate input signal of the MOS transistor of the output stage of this invention. It is a circuit diagram of the drive circuit which has a dead time concerning a prior art. It is a block circuit diagram of the class D amplifier concerning a prior art.

(Embodiment 1) FIG. 1 is a circuit diagram of a class D amplifier according to claim 1 of the present invention. Although the output stage of the conventional class D amplifier is two NMOS transistors connected in series, in the present invention, a PMOS transistor QPH and an NMOS transistor QNL are connected in series between the high power supply voltage VHH and the low power supply voltage VLL. It is configured to connect to. In order to drive the PMOS transistor QPH, a high side drive circuit 21 is provided between the high power supply voltage VHH and the first intermediate power supply voltage VHL, and the second intermediate power supply voltage VLH is used to drive the NMOS transistor QNL. And the low power supply voltage VLL are provided with a low side drive circuit 31. By adopting this circuit configuration, the gate-source voltage of the output stage PMOS transistor QPH and NMOS transistor QNL can be made lower than the drain-source voltage.

  The relationship among the high power supply voltage VHH, the low power supply voltage VLL, the first intermediate power supply voltage VHL, and the second intermediate power supply voltage VLH is as follows: low power supply voltage VLL <first intermediate power supply voltage VHL <high power supply voltage VHH Low power supply voltage VLL <second intermediate power supply voltage VLH <high power supply voltage VHH.

  Between the level shift circuit 11 and the high side drive circuit 21, the first voltage conversion circuits (20a, 20b) are arranged. In this circuit, a parallel connection circuit of a PMOS transistor QP1 and a resistor R1, an NMOS transistor QN1, a PMOS transistor QP2, and an NMOS transistor QN2 are connected in series from the high power supply voltage side between the high power supply voltage VHH and the low power supply voltage VLL. ing. The gates of the PMOS transistor QP1 and the NMOS transistor QN1 are connected in common and used as the input of the first voltage conversion circuit (20a, 20b). The gate of the PMOS transistor QP2 is connected to the first intermediate power supply voltage VHL. The gate of the NMOS transistor QN2 inputs the gate input of the NMOS transistor QNL in the output stage via the inverter circuit 25. The output of the first voltage conversion circuit (20a, 20b) is the other end of the parallel connection circuit of the PMOS transistor QP1 and the resistor R1, which has one end connected to the high power supply voltage VHH.

  Similarly, a second voltage conversion circuit (30a, 30b) is disposed between the level shift circuit 12 and the low-side drive circuit 31. In this circuit, a parallel connection circuit of a PMOS transistor QP3, an NMOS transistor QN3, a PMOS transistor QP4, an NMOS transistor QN4 and a resistor R2 is connected in series from the high power supply voltage side between the high power supply voltage VHH and the low power supply voltage VLL. ing. The gates of the PMOS transistor QP4 and the NMOS transistor QN4 are connected in common and used as the input of the second voltage conversion circuit (30a, 30b). The gate of the NMOS transistor QN3 is connected to the second intermediate power supply voltage VLH. The gate of the PMOS transistor QP3 inputs the gate input of the PMOS transistor QPH in the output stage via the inverter circuit 24. The output of the second voltage conversion circuit (30a, 30b) is the other end of the parallel connection circuit of the NMOS transistor QN4 and the resistor R2, which has one end connected to the low power supply voltage VLL.

  The resistors R3 and R4 are resistors for fixing the gate so that the output stage transistor is not turned on before each power supply voltage rises.

  Next, the operation of the circuit of the present invention will be described. First, consider the case where the voltage at the input terminal IN is at L level. Assuming that the polarity is not changed by the level shift circuit 11 and the level shift circuit 12, the voltage level of the node n1 is converted to the power supply voltage (voltage VHH, voltage VHL) of the high side drive circuit 21 and is L level (voltage VHL). Thus, the voltage of the node n2 is converted to the power supply voltage (voltage VLH, voltage VLL) of the low side drive circuit 22 and becomes L level (voltage VLL).

  Since the node n1 is at the L level (voltage VHL), the PMOS transistor QP1 is turned on and the NMOS transistor QN1 is turned off. Therefore, the node n3 is at the H level (voltage VHH), and the node n5 at the output of the buffer 22 is at the H level (voltage VHH). Therefore, the PMOS transistor QPH is turned off.

  At this time, the PMOS transistor QP3 is turned on because the voltage of the node n5 is inverted by the inverter circuit 24 and the L level (voltage VHL) is input. The PMOS transistor QP4 is on because the node n2 is at the L level (voltage VLL). Therefore, a current flows from the power supply voltage VHH toward the power supply voltage VLL through the current paths of the PMOS transistor QP3, the NMOS transistor QN3, the PMOS transistor QP4, and the resistor R2. At this time, since the gate voltage of the NMOS transistor QN3 is the voltage VLH, a current flows until the voltage of the source terminal of the NMOS transistor QN3 becomes the voltage VLH−Vth (Vth is the threshold voltage of the NMOS transistor QN3). Thereby, the potential of the node n4 becomes a voltage (voltage VLH−Vth) corresponding to the H level. Then, the output node n6 of the buffer 23 becomes H level (voltage VLH), and the NMOS transistor QNL in the output stage is turned on.

  At this time, the NMOS transistor QN2 is turned off because the voltage of the node n6 is inverted by the inverter circuit 25 and the L level (voltage VLL) is input.

  Consider the case where the signal input to the input terminal IN changes to H level from this state. The node n1 becomes H level (voltage VHH), and the node n2 also changes to H level (voltage VLH). As a result, the NMOS transistor QN4 of the second voltage conversion circuit (30a, 30b) is turned on and the PMOS transistor QP4 is turned off. For this reason, the node n4 becomes L level (voltage VLL) and the node n6 of the output of the buffer 23 becomes L level (voltage VLL), so that the NMOS transistor QNL in the output stage changes from on to off.

  On the other hand, when the NMOS transistor QN2 is turned on, the first voltage conversion circuit (20a, 20b) has a voltage corresponding to the potential of the node n3 of L level (potential VHL + Vth (Vth is the threshold voltage of the PMOS transistor QP2)). ). As a result, the output node n5 of the buffer 22 becomes L level (voltage VHL), and the PMOS transistor QPH in the output stage changes from OFF to ON.

  Thus, when the signal input to the input terminal IN changes from the L level to the H level, the NMOS transistor QNL in the output stage is turned off, and then the PMOS transistor QPH is turned on after a dead time (DT) (see FIG. 4). ).

  Similarly, consider a case where the signal input to the input terminal IN changes from H level to L level. The node n1 becomes L level (voltage VHL), and the node n2 also changes to L level (voltage VLL). As a result, the PMOS transistor QP1 of the first voltage conversion circuit (20a, 20b) is turned on and the NMOS transistor QN1 is turned off. For this reason, the node n3 becomes H level (voltage VHH), and the output node n5 of the buffer 22 becomes H level (voltage VHH), so that the PMOS transistor QPH in the output stage changes from on to off.

  On the other hand, when the PMOS transistor QP3 is turned on, the second voltage conversion circuit (30a, 30b) has a voltage corresponding to the H level of the potential of the node n4 (potential VLH−Vth (Vth is a threshold value of the NMOS transistor QN3). Voltage)). As a result, the output node n6 of the buffer 23 becomes H level (voltage VLH), and the output stage NMOS transistor QNL changes from OFF to ON.

  As described above, when the signal input to the input terminal IN changes from the H level to the L level, the PMOS transistor QPH in the output stage is turned off, and then the NMOS transistor QNL is turned on after a dead time (DT) (see FIG. 4). ).

  As described above, according to this embodiment, it is possible to automatically set the optimum dead time so as not to turn on the transistors in the output stage at the same time, and to lower the gate-source voltage of the output stage transistor than the drain-source voltage. Therefore, it is suitable for a class D amplifier whose output stage is composed of DMOS transistors.

It shows a circuit diagram of a class D amplifier according to claim 2 of the present invention in FIG. 2 (Embodiment 2). The difference from the circuit of FIG. 1 is that a first input level detection circuit 50 is added in the first voltage conversion circuit (20a, 20b ′), and the second voltage conversion circuit (30a, 30b ′) is second. The input level detection circuit 60 is added.

  The first input level detection circuit 50 has an NMOS transistor QN5 whose gate and source are commonly connected to the NMOS transistor QNL at the output stage, one end connected to the drain of the NMOS transistor QN5, and the other end connected to the drain of the PMOS transistor QP5. A resistor R5, a PMOS transistor QP5 having a gate connected to the NMOS transistor QN5, a drain connected to one end of the resistor R5, and a source connected to the second intermediate power supply voltage (VLH), and a drain and a resistor of the NMOS transistor QN5 It is composed of an inverter 27 for polarity inversion with the connection point with R5 as an input.

  The second input level detection circuit 60 has a PMOS transistor QP6 whose gate and source are commonly connected to the PMOS transistor QPH at the output stage, one end connected to the drain of the PMOS transistor QP6, and the other end connected to the drain of the NMOS transistor QN6. The resistor R6, the gate is commonly connected to the PMOS transistor QP6, the drain is connected to one end of the resistor R6, the source is connected to the first intermediate power supply voltage (VHL), the drain and the resistor of the PMOS transistor QP6 It is composed of an inverter 26 for polarity inversion with the connection point with R6 as an input.

  A feature of the present embodiment is that the NMOS transistor QN5 of the first input level detection circuit 50 and the NMOS transistor QNL in the output stage are configured by N-channel DMOS transistors that are the same process, and the thresholds of both N-channel DMOS transistors. The voltage value is made the same, and the PMOS transistor QP6 of the second input level detection circuit 60 and the PMOS transistor QPH of the output stage are configured by P channel DMOS transistors which are the same process, and the thresholds of both P channel DMOS transistors are configured. The voltage value is the same.

  Next, operations of the input level detection circuit 50 and the input level detection circuit 60 will be described. First, when the potential of the node n6 changes from the H level (voltage VLH) to the L level (voltage VLL) (see FIG. 4), the NMOS transistor QNL in the output stage changes from on to off, and at the same time, the input level detection. The NMOS transistor QN5 of the circuit 50 also changes from on to off. At this time, since the PMOS transistor QP5 is turned on, the input potential of the inverter 27 becomes H level (voltage VLH). Therefore, the output of the inverter 27 is L level (voltage VLL), the output of the inverter 25 is H level (voltage VLH), and the NMOS transistor QN2 is turned on. As a result, the power supply voltage VLL is supplied to the circuit 20a of the first voltage conversion circuit.

  Next, when the potential of the node n5 changes from the L level (voltage VHL) to the H level (voltage VHH) (see FIG. 4), the output stage PMOS transistor QPH changes from on to off, and at the same time the input level. The PMOS transistor QP6 of the detection circuit 60 also changes from on to off. At this time, since the NMOS transistor QN6 is turned on, the input potential of the inverter 26 becomes L level, the output of the inverter 26 becomes H level (voltage VHH), the output of the inverter 24 becomes L level (voltage VHL), and the PMOS Transistor QP3 is turned on. As a result, the power supply voltage VHH is supplied to the circuit 30a of the second voltage conversion circuit.

  In the above-described operation, the NMOS transistor QNL and the NMOS transistor QN5 in the output stage are composed of DMOS transistors by the same process, and the threshold voltages of both transistors are the same, so the timing when both transistors change from on to off is the same. It becomes. Similarly, the PMOS transistor QPH and the PMOS transistor QP6 in the output stage are configured by DMOS transistors by the same process, and the threshold voltages of both transistors are the same. Therefore, the timing when both transistors change from OFF to ON is the same. . Therefore, variation in dead time is suppressed, and more accurate dead time control is possible.

  Note that the PMOS transistor QP5 and the NMOS transistor QN6 are switching means for cutting the DC path from the power source to the NMOS transistor QN5 and the PMOS transistor QP5, respectively, and suppressing current consumption, and are not necessarily required. That is, one end of the resistor R5 may be directly connected to the second intermediate voltage (voltage VLH) without being connected to the drain of the PMOS transistor QP5. Similarly, the first intermediate voltage (voltage VHL) may be directly connected without connecting one end of the resistor R6 to the drain of the NMOS transistor QN6.

  In order to suppress current consumption, it is preferable that the resistors R5 and R6 have values sufficiently larger than the on-resistances of the NMOS transistor QN5 and the PMOS transistor QP6, respectively.

It shows a circuit diagram of a class D amplifier according to claim 3 of the present invention in FIG. 3 (Embodiment 3). An enable terminal EN is newly provided to set the H level (voltage VHH) to the gate of the PMOS transistor QP2 of the first voltage conversion circuit (20a, 20b), and the NMOS transistor QN3 of the second voltage conversion circuit (30a, 30b). By inputting the L level (voltage VLL) to the gate, the voltage conversion circuit is set in the standby state. By setting the voltage conversion circuit to the standby state, the through current of the voltage conversion circuit is eliminated, and both the two transistors in the output stage can be turned off. In FIG. 3, the case where the enable terminal EN is newly provided for the class D amplifier described in FIG. 1 has been described. However, the enable terminal is also newly provided for the class D amplifier previously described in FIG. Needless to say, EN may be provided.

11, 12, 13, 14: level shift circuits 20a, 20b, 20b ': first voltage conversion circuits 30a, 30b, 30b': second voltage conversion circuit 21: high side drive circuit 31: low side drive circuit 22, 23: Buffers 24, 25, 26, 27, 28: Inverter circuits 50, 60: Input level detection circuits QP1, QP2, QP3, QP4, QP5, QP6: PMOS transistors QN1, QN2, QN3, QN4, QN5, QN6: NMOS Transistor QPH: PMOS transistor QNL: NMOS transistors R1, R2, R3, R4, R5, R6: resistors

Claims (3)

A high-side control is provided between a high-side P channel DMOS transistor and a low-side N-channel DMOS transistor connected in series between a high power supply voltage and a low power supply voltage, and between the high power supply voltage and the first intermediate power supply voltage. A high-side driving circuit for driving the high-side P-channel DMOS transistor based on a signal, and a second intermediate power-supply voltage and the low power-supply voltage, and the low-side N-channel based on a low-side control signal. A low side driving circuit for driving the DMOS transistor ,
The high-side drive circuit includes a first voltage conversion circuit that generates a voltage corresponding to the first intermediate power supply voltage based on the high-side control signal when the low-side N-channel DMOS transistor is non-conductive. ,
The low-side drive circuit includes a second voltage conversion circuit that generates a voltage corresponding to the second intermediate power supply voltage based on the low-side control signal when the high-side P-channel DMOS transistor is non-conductive . In class D amplifier,
The first voltage conversion circuit includes a parallel connection circuit of a first PMOS transistor and a first resistor, a first NMOS transistor, and a second PMOS transistor between the high power supply voltage and the low power supply voltage. And a second NMOS transistor that is conductive when the low-side N-channel DMOS transistor is non-conductive is connected in series from the high power supply voltage side, and the gates of the first PMOS transistor and the first NMOS transistor Are connected to a common input terminal, and the gate of the second PMOS transistor is connected to the first intermediate power supply voltage,
The second voltage conversion circuit includes a third PMOS transistor, a third NMOS transistor, which are turned on when the high-side P-channel DMOS transistor is non-conductive between the high power supply voltage and the low power supply voltage. , A fourth PMOS transistor, a fourth NMOS transistor, and a parallel connection circuit of a second resistor are connected in series from the high power supply voltage side, and the fourth PMOS transistor and the fourth NMOS transistor A class D amplifier comprising a configuration in which a gate is connected to a common input terminal, and a gate of the third NMOS transistor is connected to the second intermediate power supply voltage . The first voltage conversion circuit has a gate commonly connected to the gate of the low-side N-channel DMOS transistor, a source connected to the low power supply voltage, and one end connected to the first N-channel. A third resistor connected to the drain of the DMOS transistor and having the other end connected directly or via the first switch means to the second intermediate power supply voltage; and the drain of the first N-channel DMOS transistor A first input level detection circuit that outputs a connection point of the third resistor;
The second voltage conversion circuit has a gate commonly connected to the gate of the high-side P-channel DMOS transistor, a source connected to the high power supply voltage, and one end connected to the first P-channel DMOS transistor. The drain of the first P-channel DMOS transistor is connected to the drain of the channel DMOS transistor, and the other end is connected to the first intermediate power supply voltage directly or via the second switch means. And a second input level detection circuit that outputs a connection point of the fourth resistor,
The threshold voltage of the first N-channel DMOS transistor is equal to the threshold voltage of the low-side N-channel DMOS transistor, and the threshold voltage of the first P-channel DMOS transistor is equal to the threshold voltage of the high-side P-channel DMOS transistor. 2. The class D amplifier according to claim 1, wherein the hold voltages are equal . 2. The switching means for switching the gate input of the second PMOS transistor to the high power supply voltage and the switching means for switching the gate connection of the third NMOS transistor to the low power supply voltage. The class D amplifier circuit according to claim 2.

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