WO2008101548A1

WO2008101548A1 - Level shift circuit

Info

Publication number: WO2008101548A1
Application number: PCT/EP2007/051731
Authority: WO
Inventors: Peter Seesink
Original assignee: Mueta B.V.
Priority date: 2007-02-22
Filing date: 2007-02-22
Publication date: 2008-08-28

Abstract

A level shift circuit for transferring an input signal (60, 90) referenced to a first reference voltage (Vsshs, Vssls) to an output signal (65, 66, 95, 96) referenced to a second reference voltage (Vssls, Vsshs). The circuit comprises a first pull-up transistor (42), a first shielding transistor (43), and a first pull-down transistor (44) connected in series between the first reference voltage and the second reference voltage, and a second pull-up transistor (45), a second shielding transistor (46), and a second pull-down transistor (47) connected in series between the first reference voltage and the second reference voltage. The first pull-up transistor is controlled by the input signal, and the second pull-up transistor controlled by an inverted signal derived from the input signal. The gate terminals of the first and second shielding transistors are connected through gate series resistors (50, 51) to a third voltage (Vddls) having a fixed difference from the second reference voltage. The output signal is taken from a first node (62) between the first shielding transistor and the first pull-down transistor or a second node (64) between the second shielding transistor and the second pull-down transistor.

Description

LEVEL SHIFT CIRCUIT

BACKGROUND OF THE INVENTION

[0001] The invention relates to level shift circuits for converting a signal referenced to a first voltage reference to a signal referenced to a second reference voltage, and to switching amplifiers using such level shift circuits.

[0002] Linear amplifiers, such as class A and class AB amplifiers, for example, whose amplifier stage is essentially operated as a controllable series resistor, have a very low efficiency, since high heat dissipation occurs in the output stage when the amplifier is not driven to full load. An amplifier circuit comprising a switched output stage, on the other hand, such as a class D amplifier, exhibits only a small degree of heat dissipation, since the current through the output stage is zero when the output switching transistors are switched off, and the voltage across the output stage is practically zero when the switching transistors are on. Switching amplifiers, or class D amplifiers, have a very high energy efficiency, often over 90% in practice.

[0003] In a class D amplifier circuit a block wave signal is generated which has a frequency which is much higher than the highest frequency of the input signal to be amplified. The pulse width ratio of the block wave signal is modulated so that the average value of the block wave signal is proportional to the input signal, but increased by an amplification factor. By applying the block wave signal to a low-pass filter or resonator circuit, with a cut-off frequency ranging between the highest signal frequency and the frequency of the block wave signal, an output signal is produced from which the switching frequency or block wave frequency and higher frequencies of the block wave signal have been removed. The output signal represents the average value of the block wave signal, and thus represents an amplified version of the input signal. The amplification factor is determined by the electrical characteristics of the modulator, the correction signal, the supply source and the switching means. Usually, switching transistors such as MOSFET's (Metallic Oxide Semiconductor Field Effect Transistors) are used as the switching means. [0004] The switching transistors have a limited response time, which is mainly caused by parasitic capacitances. Transistors connected in a so-called half-bridge circuit, wherein two switching transistors are arranged in series and the block wave signal is generated at the junction of the transistors, must never be "on" at the same time, as this would result in a short- circuit path for the supply voltage which would damage the switching transistors. For this reason a "dead time" is maintained during the switching of the transistors, the time required for switching one transistor off and subsequently switching the other transistor on. This dead time results in non-linearities in the transfer function of the amplifier circuit which is especially significant at small amplitudes, and consequently the dead time must not be too large. In order to co-ordinate the switching of the switching transistors to reduce the dead time as much as possible while ensuring the switching transistors do not short the supply voltage, the amplifier must be able to send control signals to the switching transistors with a minimum of propagation delay in the circuits. [0005] For amplifier circuits having high power output, the switching transistors are required to switch a high voltage, typically 20 to 100V. The switching transistors must be designed to withstand this high voltage. However, this increases the size and cost of the transistors, and it is preferable to limit the number of high voltage circuit components and operate as much of the amplifier circuitry at low voltage as possible. However, this requires that signals must be conveyed from low voltage control circuits operating at one voltage level to circuit components operating a much higher or lower voltage level. Level shift circuits are used for this purpose. These level shift circuits are able to transfer control signals between the different voltage levels extremely quickly in order to minimize the propagation delay in the amplifier to reduce the dead time. [0006] Furthermore, the high voltage block wave signal generated by the switching means can have a very high rate of change (dV/dt), which can be transferred to the output signal of the level shift circuit. SUMMARY OF THE INVENTION

[0007] In accordance with the invention, a level shift circuit is provided for transferring an input signal referenced to a first reference voltage to an output signal referenced to a second reference voltage. The circuit comprises a first pull-up transistor, a first shielding transistor, and a first pull-down transistor connected in series between the first reference voltage and the second reference voltage, and a second pull-up transistor, a second shielding transistor, and a second pull-down transistor connected in series between the first reference voltage and the second reference voltage. The first pull-up transistor is controlled by the input signal, and the second pull-up transistor controlled by an inverted signal derived from the input signal. The gate terminals of the first and second shielding transistors are connected through gate series resistors to a third voltage having a fixed difference from the second reference voltage. The output signal is taken from a first node between the first shielding transistor and the first pulldown transistor or a second node between the second shielding transistor and the second pulldown transistor. [0008] The pull-down transistors may be connected with the gate terminal of the first pulldown transistor coupled to the drain terminal of the second pull-down transistor, and the gate terminal of the second pull-down transistor coupled to the drain terminal of the first pull-down transistor. The resistance of the gate series resistors is preferably at least ten times the on resistance of the pull-down transistors. [0009] In a particular configuration, the source terminals of the first and second pull-up transistors are coupled to the first reference voltage and the source terminals of the first and second pull-down transistors are coupled to the second reference voltage. [0010] The level shift circuit may also include inverter circuits to improve the common mode rejection ratio of the level shift circuit. A first inverter circuit comprises a third pull-up transistor for inverting the second node voltage, and a fourth pull-up transistor for inverting the first node voltage, and a second inverter circuit comprises a fifth pull-up transistor for inverting the inverted first node voltage to generate a first filtered output, and a sixth pull-up transistor for inverting the inverted second node voltage to generate a second filtered output. - A -

The third and fourth pull-up transistors are turned off by a positive spike at the first and second nodes, and the fifth and sixth pull-up transistors are turned off by a negative spike at the first and second nodes, and the output signal is derived from the first filtered output or the second filtered output. [0011] In a particular configuration, the first inverter circuit includes third and fourth pulldown transistors, the gate terminal of the third pull-down transistor being coupled to the drain terminal of the fourth pull-down transistor, and the gate terminal of the fourth pull-down transistor being coupled to the drain terminal of the third pull-down transistor. [0012] The invention also relates to a switching amplifier employing the level shift circuit. The switching amplifier comprises a modulator, a switching circuit, and an output filter. The modulator receives a filtered analog input signal and generates a pulse wave shaped signal. The switching circuit comprises a switching control circuit for receiving the pulse wave shaped signal and generating switching control signals, a plurality of switching transistors for generating an amplified block wave signal, a plurality of gate driver circuits for receiving the switching control signals and driving the switching transistors, and one or more level shift circuits for transferring at least one switching control signal between the switching control circuit and at least one of the gate driver circuits. The output filter receives the amplified block wave signal and generates an amplified analog output signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Further aspects, features and advantages of the invention will become apparent from the following description, given by way of example only, of preferred embodiments of the invention, referring to the accompanying drawings, wherein:

Figure 1 is a simplified diagram of a switching amplifier; Figure 2 is a simplified diagram of the switching circuit of Figure 1;

Figure 3 is a circuit diagram of the high-to-low level shift circuit of the switching circuit of

Figure 2;

Figure 4 shows the variation in voltage at various nodes of the level shift circuit of Figure 3; Figure 5 is a circuit diagram of the high-to-low level shift circuit of Figure 3 including circuits to avoid voltage spikes propagating to the output; and

Figure 6 is a circuit diagram of the low-to -high level shift circuit.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0014] Elements or components which are indicated by the same numerals throughout the various drawings have an identical or equivalent function.

[0015] Figure 1 is a simplified diagram of a switching amplifier or class D amplifier 10. Amplifier 10 comprises a filter/control circuit 11, modulator 12, switching circuit 13, and output filter 14. An analog input signal 16 which is to be amplified is applied to an input of the filter/control circuit 11. The filtered analog input signal is then supplied to modulator 12. [0016] The modulator 12 usually comprises a comparator circuit having two stable (binary) output states. An oscillator signal, which is generally triangular or sawtoothed, is applied to a first input of the comparator circuit, and the filtered analog input signal is applied to a second input. The binary output state of the comparator circuit indicates whether the analog input signal is larger or smaller than the oscillator signal. Consequently, the output signal from the modulator 12 is a pulse wave shaped control signal 17, whose pulse width ratio is modulated by the analog input signal 16 in such a manner that the average value of the pulse wave shaped signal 17 is proportional to the analog input signal 16 at each instant. This modulation principle is known as "sine-triangle" modulation. Besides sine-triangle modulation, also the "sigma-delta" modulation principle may be used. According to the sigma-delta modulation principle, the modulator comprises a hysteresis control circuit. An integrating component is used, which integrates the difference between the output voltage of the switching circuit and a desired value. This integrated signal is in turn applied to an input of the hysteresis control circuit. Other modulating circuits may be employed as is well known to those of skill in the art.

[0017] The switching circuit 13 comprises controllable switching means, such as switching transistors, to generate a block wave signal 18. The switching circuit 13 shown in Figure 1 uses a half-bridge circuit with two switching transistors 20 and 21 connected in series between a first (positive) supply voltage +V and a second (negative) supply voltage -V. MOSFET's (Metallic Oxide Semiconductor Field Effect Transistors) are suitable for this circuit, although other types of switching devices may also be used. The output of the switching circuit 13 is taken from the junction between the two switching transistors. The switching transistors 20 and 21 are switched in turn to alternately connect the output of the switching circuit to the first and second supply voltages, generating a block wave signal 18 ranging between the first and second supply voltages. The two switching transistors 20 and 21 must not be "on" at the same time, as this would result in a short-circuit path for the supply voltage. [0018] The switching circuit may use a full-bridge or H-bridge circuit instead of the half- bridge circuit shown in Figure 1. When no positive or negative supply voltages are available, a full-bridge circuit can be used, wherein two half-bridge circuits are connected in parallel between a first (positive) supply voltage and a second (zero) supply voltage value. The output of the switching circuit is taken between the two mid-point junctions of the two bridge branches in this configuration. Another possibility is an H-bridge circuit comprising two complementary mode controlled branches. As regards waveforms and functionality, this circuit produces a result which is comparable to that of the half-bridge circuit, but requiring only half the supply voltage. Other configurations are also possible to produce a two level or three level block wave signal 18, as is well known to those of skill in the art. [0019] The block wave signal 18 is supplied to output filter 14, generally a passive low pass filter which may comprise, for example, a self inductance 27 and a capacitance 28, although other types of filter circuits known to those of skill in the art may be used. An output signal 19 is obtained at the output of the output filter 14 which is corresponds to the input signal 16 amplified by an amplification factor. The output filter 14 (also called resonating means) provides for the removal of the switching or block wave frequency and higher frequencies from the switched block wave signal 18 of the switching circuit 13. A feedback signal may also be provided, for example from the output filter 14 to the control filter 11. [0020] The switching circuit 13 includes gate driver circuits 22 and 23 for controlling the switching transistors 20 and 21 respectively. Switching control circuitry 24 receives the pulse wave shaped signal 17 from the modulator 17 and generates signals to control the gate driver circuits 22 and 23 in order to control the switching of transistors 20 and 21. Where a Ml- bridge or H-bridge switching circuit is used, additional circuits will generally be used to independently drive each switching transistor.

[0021] For amplifier circuits having high power output, the voltage +V to -V is generally high. This requires the use of high voltage switching transistors able to withstand this high voltage. However, due to the size and cost of designing high voltage transistors, it is preferable to use low voltage circuits where possible.

[0022] The two switching transistors 20 and 21 must not be on at the same time, as this would result in a short-circuit path for the supply voltage. The time required for switching one transistor off and subsequently switching the other transistor on is called the dead time. This dead time results in non-linearities in the transfer function of the amplifier circuit 10, and consequently the dead time must not be too large.

[0023] Figure 2 is a simplified diagram showing additional details of the switching circuit 13 of Figure 1. The circuit of Figure 2 includes a "low-side" 30 and a "high-side" 31. The switching control 24 and the gate driver 23 comprise low voltage circuits operating on supply voltages V_ssi_s and Vddk, where V_ssi_s is connected to supply voltage -V, and Vddk is a fixed voltage, typically 5V, above V_ssi_s. The circuits 23 and 24 and supply voltages V_ssi_s and Vddk form the low-side circuits of the switching circuit 13. The gate driver 22 also comprises low voltage circuits, operating on supply voltages V_ssh_s and Vddhs, where V_ssh_s is connected to the node between switching transistors 20 and 21, which is the switching circuit output at which the block wave signal 18 is formed. Vddhs is a fixed voltage, typically 5V, above V_ssh_s. The circuit 22 and supply voltages V_ssh_s and Vddhs form the "high-side" circuits of the switching circuit 13.

[0024] The switching transistors 20 and 21 are controlled by the gate driving circuits 22 and 23 which apply a voltage to the gates of the transistors. Switching transistors 20 and 21 are connected across the supply voltage +V to -V. This voltage is selected to be sufficiently high to provide the output voltage required for the amplifier circuit. In the following description, the supply voltages +V and -V are assumed to be +30V and -30V, respectively, generally suitable for an amplifier of 450W rms output power into a 40hm load. Many other voltages are of course possible.

[0025] The class D amplifier operates by generating a block wave signal 18 at the output of the switching circuit 13 that is switched between +30V and -30V. When switching transistor 20 is on and switching transistor 21 is off, the voltage at the source of transistor 20 and the drain of transistor 21 (i.e. the output of the switching circuit 13, the block wave signal 18) will be almost equal to +30V, and transistor 21 will have approximately 60V from source to drain terminal. When switching transistor 20 is off and switching transistor 21 is on, the voltage at the source of transistor 20 and the drain of transistor 21 will be almost equal to - 30V, and transistor 20 will have approximately 60V from source to drain terminal. [0026] For n-type MOS transistors, the transistor will turn on when the voltage applied to its gate terminal is sufficiently above the voltage at its source terminal. A gate voltage 5 V above the source voltage will typically be sufficient to turn on a high voltage MOS transistor. The low-side gate driver circuit 23 controls switching transistor 21 by generating a control voltage on the gate terminal of transistor 21 referenced to the voltage at the source terminal of transistor 21. The source terminal of transistor 21 is fixed at the supply voltage -V which is connected to the low-side supply voltage V_ssi_s. The high-side gate driver circuit 22 controls switching transistor 20 by generating a control voltage on the gate terminal of transistor 20 which is referenced to the voltage at the source terminal of transistor 20, which is connected to high-side supply voltage V_ssh_s. The source terminal of switching transistor 20 is the switching circuit output, which switches between supply voltages +V and -V to form the block wave output signal 18.

[0027] The gate driver circuits may both be low voltage circuits, but while the low-side gate driver circuit 23 is referenced to the fixed low-side supply voltages V_ssi_s and Vddk, the high-side gate driver circuit 22 is referenced to the high-side supply voltages V_ssh_s and Vddhs which fluctuate with the high voltage supply voltages +V and -V. The switching control circuit 24 is referenced to the fixed low-side supply voltages, but must send control signals to both the low-side gate driver circuit 23 and high-side gate driver circuit 22. In addition, the gate driver circuits send control signals back to the switching control circuit 24 in order to turn on the low-side switching transistor 21 as soon as the off-state of the high-side switching transistor 20 is detected, and vice versa. While the switching control circuit 24 and low-side gate driver circuit 23 can directly send signals to each other, level shift circuits are required to transfer control signals between switching low-side control circuit 24 and high-side gate driver circuit 22 and vice-versa. Level shift circuit 25 transfers signals from low-side control circuit 24 to high-side gate driver circuit 22, and level shift circuit 26 transfers signals from high-side gate driver circuit 22 to low-side control circuit 24.

[0028] Figure 3 is a circuit diagram of level shift circuit 26 of Figure 2 for transferring signals from the high-side circuits (at high-side input 60) to the low-side circuits (at low-side output 65). Pull-up transistor 42, shielding transistor 43, and pull-down transistor 44 are connected in series between high-side supply voltage Vddhs and low-side supply voltage V_ssi_s. Pull-up transistor 45, shielding transistor 46 and pull-down transistor 47 are similarly connected in series between Vddhs and V_ssi_s. The source of transistor 42 is connected to Vddhs, and the drain of transistor 42 is connected to the drain of transistor 43 at node 61. Similarly, the source of transistor 45 is connected to Vddhs, and drain of transistor 45 is connected to the drain of transistor 46 at node 63.

[0029] High-side input 60 is inverted by inverter 48 and connected to the gate of transistor 42. The inverted high-side input is inverted again by inverter 49 and then connected to the gate of transistor 45. Inverters 48 and 49 are powered by high-side supply voltages Vddhs and V_ssh_s. The gates of transistor 43 and 46 are connected to low-side supply voltage Vddis through resistors 50 and 51 respectively. The gate of transistor 44, the source of transistor 46, and the drain of transistor 47, are all connected together at node 64. Similarly, the gate of transistor 47, the source of transistor 43, and the drain of transistor 44, are all connected together at node 62. Node 62 is connected to low-side output 65 through inverters 52 and 53, and to inverted low-side output 65 through only inverter 52. Inverters 52 and 53 are powered by low-side supply voltages Vddk and V_ssi_s. Nodes 62 and 64 are connected to low-side supply voltage Vddk through diodes 54 and 55 respectively.

[0030] In operation, a logical high signal (i.e. a logical "1" at or near voltage Vddhs) at high-side input 60 will turn pull-up transistor 42 on and pull-up transistor 45 off. The voltage at node 61 will rise to approximately Vddhs and the voltage at node 63 will float. The transistors 43 and 46 act as high voltage shielding transistors, preventing the voltage at nodes 62 and 64 from rising above Vddk - V_th, where V_th is the threshold voltage of the shielding transistors. Diodes 54 and 55 provide additional backup to ensure that the voltage at nodes 62 and 64 do not rise above Vddk + Vd (low-side supply voltage plus the diode voltage drop).

Thus, the voltage at node 62 will rise to Vddk - Vth, causing pull-down transistor 47 to turn on. This will pull the voltage at node 64 down to approximately V_ssi_s, turning pull-down transistor 44 off and turning shielding transistor 46 on. The voltage at node 63 will drop to approximately equal to the voltage at node 64. The voltage Vddk - Vth at node 62 will result in a logical high output at low-side output 65. Thus, the logical high signal at high-side input 60 will be transferred to the low-side output 65.

[0031] A logical low signal (i.e. a logical "0") at high-side input 60 will turn pull-up transistor 42 off and pull-up transistor 45 on. The voltage at node 63 will rise to approximately Vddhs and the voltage at node 61 will float. The voltage at node 64 will rise to Vddk - Vth, causing pull-down transistor 44 to turn on. This will pull the voltage at node 62 down to approximately V_ssi_s, turning pull-down transistor 47 off and turning shielding transistor 43 on. The voltage at node 61 will drop to approximately V_ssi_s, the voltage at node 62. The voltage V_ssi_s at node 62 will result in a logical low output at low-side output 65. Thus, the logical low signal at high-side input 60 will be transferred to the low-side output 65. [0032] The pull-up transistors 42 and 45, and the shielding transistors 43 and 46, must be designed to withstand a drain-source voltage of the full supply voltage, i.e. Vddhs- V_ssk when Vsshs is equal to +V. As an example, assume the supply voltages +V and -V shown in Figure 2 are +30V and -30V respectively, and Vdd was fixed at 5V above V_ss. The low-side supply voltage Vssis would be -30V and Vddk would be -25 V, and high-side supply voltage V_ssh_s would vary from -30V to +30V and Vddhs would vary between -25V to +35V. When V_ssh_s is at +30V and Vddhs is at +35 V, and transistor 42 is on and shielding transistor 43 is off, then the voltage at node 61 will be approximately +35 V (Vddhs) and the voltage at node 62 will be approximately -26V (Vddk - V_th, assuming a threshold voltage of IV). Thus, the maximum voltage across source-drain of shielding transistor 43 will be approximately 61V. When pull- up transistor 42 is off, and shielding transistor 43 and pull-down transistor 47 are on, then the voltage at node 61 will be approximately -30V (V_ssi_s). Thus, the maximum voltage across source-drain of pull-up transistor 42 will be approximately 65 V. Transistors 45 and 46 will experience similarly high voltages. BCDMOS (bipolar CMOS and DMOS) transistors, with an 80V drain-to-source breakdown voltage, may be suitable for use in this application. [0033] Pull-up transistors 42 and 45 also must have a higher current capacity than the pull-down transistors 44 and 47, so that the pull-up transistors will predominate in competition with the pull-down transistors to control the voltages at nodes 61-64. The pull-down transistors may be low voltage devices as the voltages at nodes 62 and 64 are limited by the shielding transistors 43 and 46 and diodes 54 and 55. However, the weaker pull-down transistors must be able to quickly pull down the voltages at nodes 62 and 64 if the level shift circuit is to quickly transfer the high-side input 60 to the low-side output 65. The time taken for the pull-down transistors to pull down the voltage at nodes 62 and 64 results in time delay in the level shift circuit to transfer a change in the high-side input signal to the low-side output signal. In a class D amplifier, this delay will necessitate increasing the dead time between turning one of the switching transistors off and turning the other switching transistor on, to ensure that the transistors are not both on at the same time, resulting in a short-circuit path for the supply voltage. This increase in dead time results in greater non-linearities in the transfer function of the amplifier circuit.

[0034] The shielding transistors 43 and 46 each have an internal parasitic capacitance C_gs across their gate-source terminals. To pull down the voltage at nodes 62 and 64, the pulldown transistors 44 and 47 must charge this capacitance C_gs. As the pull-down transistors must be relatively small to enable the circuit to operate correctly, they do not have a large current capacity and time taken to charge C_gs will drastically slow the operation of the level shift circuit.

[0035] The series gate resistors 50 and 51 connected to the gates of shielding transistors 43 and 46 respectively are provided to address this problem. These resistors function by taking a large voltage drop across the resistor when the voltage at node 62 or 64 suddenly drops, permitting a rapid change in the voltage at nodes 62 or 64, even when the parasitic capacitance C_gs of transistor 43 or 46 has not been charged. [0036] Figure 4 shows the variation in voltage at various points in the level shift circuit of Figure 3, at node 62, at the gate of shielding transistor 43, across resistor 50, and across the parasitic capacitance C_gs of transistor 43. Initially, the high-side input is a logical high, transistor 42 is on and pull-down transistor 44 is off. The voltage at node 62 is maintained at Vddis - Vth (i.e. -26V for the supply voltage values discussed above) by the shielding transistor 43, and the low-side output 65 is a logical high. The voltage across resistor 50 is essentially zero and the gate of shielding transistor 43 is at the same voltage as supply voltage Vddis (- 25V). Thus, the gate-source voltage of transistor 43, which is the voltage across the parasitic capacitance C_gs, is Vth (IV).

[0037] When the high-side input changes to a logical low, transistor 42 turns off and pulldown transistor 44 turns on, shorting node 62 to supply voltage V_ssi_s. The voltage at node 62 drops immediately to V_ssi_s (a drop of 4V to -30V). The capacitance C_gs has not been charged and still has a voltage Th (IV) across it, so the voltage at the gate of transistor 43 also drops the same amount, to V_ssi_s + Vth (a drop of 4 V to -29V). The resistor 50 now has a voltage drop of Vddis - Vssis - Vth (4 V) across it. The parasitic capacitance C_gs now starts to charge as a result of current flowing through pull-down transistor 44. Capacitance C_gs charges to Vddis - Vssis (5V) and the voltage across resistor 50 correspondingly falls to OV.

[0038] Thus, the pull-down transistor 44 is able to immediately pull the voltage at node 62 down without the delay required to charge the parasitic capacitance C_gs of transistor 43. The low voltage at node 62 results in a logical low signal as the low-side output 65. [0039] The series gate resistors 50 and 51 preferably have a high resistance value to assume as much voltage drop as possible, since the each resistor 50 and 51 will form a voltage divider circuit with the corresponding pull-down transistor 44 and 47. The resistance of resistors 50 and 51 is preferably at least ten times the resistance across the corresponding pull- down transistor when turned on, and the resistance is preferably chosen to be as high as possible but not so high that the gate voltage becomes too sensitive to cross-talk effects. If the pull-down transistors have an on resistance of 2k Ohm, the series gate resistors should have resistance of at least 20k Ohm. In practice, the addition of 50k Ohm series gate resistors to the circuit of Figure 3 operates to increase the switching time of the level shift circuit from about 50 nanoseconds to about 2 nanoseconds.

[0040] As mentioned above, the high-side supply voltages in the level shift circuit of Figure 3 are tied to the node between the two switching transistors 20 and 21, as shown in Figure 2. The high-side supply voltages V_ssh_s and Vddhs thus switch between +V and -V very rapidly. For example, a class D amplifier design switching +30V and -30V, the high-side supply voltages will also switch between +30V and -30V, generating voltage swin_gs of 25,000V per microsecond (25kV/μsec). Under these conditions, the parasitic capacitive coupling between the high-side and low-side circuits will create voltage spikes at nodes 62 and 64 when the switching transistors 20 and 21 switch, resulting in the level shift circuit having a poor common mode rejection ratio. [0041] In Figure 5, the level shift circuit of Figure 3 includes additional circuitry to address this problem. Eight transistors 71-78 are arranged into two sets of balanced inverters. The circuit of transistors 71-74 form a balanced inverter arranged to prevent positive-going spikes with at nodes 62 and 64 from propagating to the outputs 65 and 66, and the circuit of transistors 75-78 form a second balanced inverter to prevent negative-going spikes at nodes 62 and 64 from propagating to the outputs 65 and 66.

[0042] The source terminals of transistors 71, 73, 75, and 77 are connected to low-side supply voltage Vddk, the source terminals of transistors 72, 74, 76, and 78 are connected to low-side supply voltage V_ssi_s. Node 62 is connected to the gate of transistor 73, and node 64 is connected to the gate of transistor 71. The drain terminals of transistors 71 and 72, and the gate terminal of transistor 74 are connected together at node 81. The drain terminals of transistors 73 and 74, and the gate terminal of transistor 72 are connected together at node 82. The drain terminals of transistors 75 and 76, and the gate terminal of transistor 78 are connected together at low-side output 65. The drain terminals of transistors 77 and 78, and the gate terminal of transistor 76 are connected together at low-side inverted output 66. [0043] In operation, when the voltage at node 62 is high (a logical high at Vddk - V_th) and the voltage at node 64 is low (a logical low at V_ssi_s), then transistor 71 will turn on and transistor 73 will turn off. As a result, node 81 will be high, transistor 74 will turn on, node 82 will be low, and transistor 72 will turn off. The voltages at nodes 81 and 82 will turn transistor 75 on and transistor 77 off. As a result, low-side output 65 will be high, transistor 78 will turn on, low-side inverted output 66 will be low, and transistor 76 will turn off. Transistors 71 and 73 should have greater current capacity than transistors 72 and 74, so that transistors 71 and 73 predominate over transistors 72 and 74 to control the voltages at nodes 81 and 82. Similarly, transistors 75 and 77 should have greater current capacity than transistors 76 and 78, so that transistors 75 and 77 predominate over transistors 76 and 78 to control the voltages at outputs 65 and 66.

[0044] Similarly, when the voltage at node 62 is low and node 64 is high, transistor 71 will turn off and transistor 73 will turn on. Node 82 will be high, transistor 72 will turn on, node 81 will be low, and transistor 74 will turn off. The voltages at nodes 81 and 82 will turn transistor 75 off and transistor 77 on. As a result, low-side output 65 will be low, transistor 78 will turn off, low-side inverted output 66 will be high, and transistor 76 will turn on. [0045] If a positive spike occurs in the voltage at nodes 62 and 64, then both transistors 71 and 73 will turn off (the one that was previously on will turn off and the other will remain off). The voltages at nodes 81 and 82 will remain at their previous values. The gate-source capacitance of transistors 72, 74, 75 and 77 will act to maintain the voltages present at nodes 81 and 82 for the short time duration of the spike, resulting in transistors 72 and 74 maintaining their state. For example, if the voltage at node 62 had been a logical high, transistor 71 will turn off and the voltage at node 81 will float. The gate-source capacitance will maintain node 81 high, keeping transistor 74 on, so that node 82 remains low, and transistor 72 remains off. Because there is no change to the voltages at nodes 81 and 82, transistors 75-78 will maintain their previous state, and outputs 65 and 66 will remain unchanged.

[0046] If a negative spike occurs in the voltage at nodes 62 and 64, then both transistors 71 and 73 will turn on (the one that was previously on will stay on and the other will turn on). The voltages at nodes 81 and 82 will rise to a logical high (Vddk), and as a result transistors 75 and 77 will both turn off (the one that was previously on will turn off and the other will remain off). The voltages at outputs 65 and 66 will remain at their previous values, maintained by the gate-source capacitance of transistors 76 and 78 and by the capacitive load at outputs 65 and 66 if applicable for the short time duration of the spike, resulting in transistors 76 and 78 maintaining their state. If a purely resistive load is present at outputs 65 and 66, then an inverter or buffer would be required at the outputs to prevent the gate-source capacitance of transistors 76 and 78 being discharged.

[0047] Both positive and negative spikes at nodes 62 and 64 will be filtered out by the inverter circuits of transistors 71-78, making the level shifter insensitive to even the most extreme voltage spikes with very high dV/dt, resulting in more reliable operation of the level shift circuit. [0048] Figure 6 shows a level shift circuit with the same design as the circuit of Figure 5, but configured for transferring signals from the low-side to the high-side. The level shift circuit of Figure 6 transfers a low-side input signal 90 to high-side outputs 95 and 96. The circuit components in Figure 6 have been given the same reference numbers as the corresponding circuit components in Figure 5 which perform the same function. A detailed explanation of the low-to-high level shift circuit of Figure 6 is omitted, as it will be appreciated that this circuit functions in the same manner as the circuit of Figure 5, except that the high-side and low-side supply voltages have been swapped. It should be noted that the terminology "pull-up" used in the description of the high-to-low level shift circuit of Figures 3-5 should be understood as referring to moving a voltage down (to V_ssi_s for example) in relation to the low-to -high level shift circuit of Figure 6. Similarly, the terminology "pull-down" used in the description of Figures 3-5 should be understood as referring to moving a voltage up (to Vddhs for example) in relation to Figure 6. [0049] The level shift circuit may be implemented in discrete components, in integrated circuits, or using any other suitable technique known to one of skill in the field. The circuit may be applied for use in class-D amplifiers, switching power supplies, motor driving circuits, and other applications where it is necessary to transmit signals from one voltage level to another. [0050] It should be understood that any feature described in relation to one embodiment may also be used in other of the embodiments. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the invention, which is defined in the accompanying claims.

Claims

CLAIMS:

1. A circuit for transferring an input signal (60, 90) referenced to a first reference voltage (Vsshs, Vssis) to an output signal (65, 66, 95, 96) referenced to a second reference voltage (V_ssi_s, V_Sshs), the circuit comprising: a first pull-up transistor (42), a first shielding transistor (43), and a first pull-down transistor (44) connected in series between the first reference voltage and the second reference voltage; and a second pull-up transistor (45), a second shielding transistor (46), and a second pulldown transistor (47) connected in series between the first reference voltage and the second reference voltage; wherein: the first pull-up transistor is controlled by the input signal, and the second pull-up transistor is controlled by an inverted signal derived from the input signal; the gate terminals of the first and second shielding transistors are connected through gate series resistors (50, 51) to a third voltage (Vaais) having a fixed difference from the second reference voltage; and the output signal is derived from a first node (62) between the first shielding transistor and the first pull-down transistor, or a second node (64) between the second shielding transistor and the second pull-down transistor.

2. The circuit of claim 1, wherein the gate terminal of the first pull-down transistor (62) is coupled to the drain terminal of the second pull-down transistor (64), and the gate terminal of the second pull-down transistor (64) is coupled to the drain terminal of the first pull-down transistor (62).

3. The circuit of claim 1 or claim 2, wherein the resistance of the gate series resistors (50, 51) is at least ten times the on resistance of the pull-down transistors (44, 47).

4. The circuit of any of the preceding claims, wherein the source terminals of the first and second pull-up transistors are coupled to the first reference voltage and the source terminals of the first and second pull-down transistors are coupled to the second reference voltage.

5. The circuit of any of the preceding claims, further comprising; a first inverter circuit comprising a third pull-up transistor (71) for inverting the second node voltage (64), and a fourth pull-up transistor (73) for inverting the first node voltage (62); and a second inverter circuit comprising a fifth pull-up transistor (75) for inverting the inverted first node voltage to generate a first filtered output, and a sixth pull-up transistor (77) for inverting the inverted second node voltage to generate a second filtered output; wherein: the third and fourth pull-up transistors (71, 73) are turned off by a positive spike at the first and second nodes (62, 64), the fifth and sixth pull-up transistors (75, 77) are turned off by a negative spike at the first and second nodes (62, 64), and the output signal is derived from the first filtered output or the second filtered output.

6. The circuit of claim 5, wherein the first inverter circuit is for switching between the second reference voltage (V_ssi_s, V_sshs) and a fourth voltage (Vaais, Vdd_hs) having a fixed difference from the second reference voltage, and the second inverter circuit is for switching between the second reference voltage and the fourth voltage.

7. The circuit of claim 5 or claim 6, wherein the first inverter circuit further comprises a third pull-down transistor (72) and a fourth pull-down transistor (74), the gate terminal of the third pull-down transistor being coupled to the drain terminal of the fourth pull-down transistor, and the gate terminal of the fourth pull-down transistor being coupled to the drain terminal of the third pull-down transistor.

8. A switching amplifier comprising: a modulator for receiving a filtered analog input signal and generating a pulse wave shaped signal; a switching circuit comprising: a switching control circuit for receiving the pulse wave shaped signal and generating switching control signals; a plurality of switching transistors for generating an amplified block wave signal; a plurality of gate driver circuits for receiving the switching control signals and driving the switching transistors; and one or more level shift circuits according to any one of the preceding claims, for transferring at least one switching control signal between the switching control circuit and at least one of the gate driver circuits; and an output filter receiving the amplified block wave signal and generating an amplified analog output signal.