JP5576754B2 - Radiation imaging device - Google Patents

Description

The present invention relates to a radiation imaging equipment.

  In recent years, in the field of digital radiation imaging devices, instead of image intensifiers, large-area flat panels with equal-magnification optical systems that use photoelectric conversion elements to improve resolution, reduce volume, and suppress image distortion Type sensors are widespread. Imaging devices using photoelectric conversion elements include amorphous silicon type, CCD type, and CMOS type. An image sensor using an amorphous silicon semiconductor on a glass substrate is easy to create a large screen. On the other hand, however, amorphous silicon is difficult to finely process a semiconductor substrate on a glass substrate as compared with a single crystal silicon semiconductor substrate, and as a result, the semiconductor characteristics such as an increase in the capacity of an output signal line are not sufficient. The CCD type imaging device is fully depleted and highly sensitive. However, as a large screen imaging device, the number of charge transfer stages is increased, and the power consumption is more than 10 times larger than that of a CMOS type imaging device. It is not suitable for making a large screen.

  In Patent Document 1, as a large area flat panel sensor, a CMOS image sensor is used as a photoelectric conversion element, and a rectangular image sensor obtained by cutting out a CMOS photoelectric converter from a silicon semiconductor wafer into a rectangular shape is tiled. This realizes large area imaging. The CMOS type image pickup device can be read at higher speed than amorphous silicon by fine processing, and higher sensitivity can be obtained. In addition, the CMOS image sensor has no problem in the number of transfer stages and power consumption of charge transfer like the CCD image sensor, and can be easily increased in area, and is known to be highly advantageous as a large area flat panel sensor. It has been.

  Patent Document 2 discloses a configuration using a pixel addition circuit and a sensitivity changeover switch in a CMOS image sensor.

JP 2002-344809 A JP 2006-319529 A

  However, in a CMOS image pickup device that achieves both pixel addition and sensitivity switching, for example, when driving in the high sensitivity mode, the sensitivity switching switch is turned off, and one end of the dynamic range expansion capacitor is opened and floats. Since the charge accumulated in the floating capacitor is indefinite, an indefinite potential is generated in the circuit of the CMOS image sensor. If an indefinite potential exists in the CMOS image sensor circuit during moving image shooting, a small amount of leak between the gate and the source of the MOS transistor in the CMOS image sensor circuit becomes indeterminate, which affects random noise in each frame.

  Further, the CMOS image sensor has an offset value, and each pixel outputs a non-zero value as an optical signal even if it is not irradiated with light. There is a method of subtracting the FPN pattern from the optical signal data obtained when acquiring a moving image, using optical signal data acquired without irradiating light as a fixed pattern noise (FPN) pattern of a CMOS image sensor. However, since the potential of the floating portion for each moving image changes with time, the potential of the floating portion in the CMOS image sensor obtained before capturing the FPN pattern and the potential of the floating portion when the moving image is actually acquired. There is also a difference. For this reason, a difference in noise component due to an indefinite potential of the floating portion occurs between the FPN pattern and the moving image data to be subjected to FPN correction, and correct FPN correction cannot be performed.

  Therefore, in the present invention, in order to fix the indefinite potential of the floating part in the pixel circuit of the CMOS type image pickup device, driving is performed to fix the indefinite potential with a predetermined voltage of the power source at the timing before imaging by the imaging unit (potential Fixed drive). An object of the present invention is to provide a radiation imaging apparatus that can fix an indefinite potential of a floating portion in a pixel circuit by fixed potential driving and reduce noise components.

A radiation imaging apparatus according to one aspect of the present invention that achieves the above object is as follows:
A pixel amplifier for outputting a voltage corresponding to the charge generated in the photodiode; a signal sample-and-hold switch for causing the signal hold capacitor to sample and hold the charge corresponding to the voltage; and the pixel amplifier and the photodiode an imaging unit in which a plurality of pixel circuits are arranged, each having a switching means for supplying a predetermined voltage, the between,
Imaging control means for controlling the operations of the plurality of pixel circuits so as to perform imaging a plurality of times for causing the plurality of pixel circuits to output a signal corresponding to the electric charge held in the signal hold capacitor ;
A time measuring means for measuring time;
Storage means for storing a time at which a control signal is transmitted from the imaging control means in order to operate the switch means when performing the first imaging among the plurality of times of imaging ,
A voltage is supplied to the pixel circuit, and before the imaging , the imaging control unit operates the pixel amplifier, the signal sample hold switch, and the switching unit to respond to the predetermined voltage. Sampled and held in the signal hold capacitor,
When the second imaging is performed after the first imaging, the imaging control unit causes the elapsed time from the time stored in the storage unit to the current time obtained by the timing unit to exceed a threshold time In this case, before the second imaging, the pixel amplifier, the signal sample hold switch, and the switch means are operated,
If the elapsed time from the time stored in the storage means to the current time obtained by the time measuring means is within a threshold time, before the second imaging, the pixel amplifier, the signal sample hold switch, The switch means is not operated .

  According to the present invention, it is possible to fix the indefinite potential of the floating portion in the pixel circuit at a predetermined voltage of the power source at a timing before imaging by the imaging unit, and reduce the noise component.

FIG. 5 is a diagram illustrating driving timing of the pixel circuit according to the first embodiment. The figure which shows the drive timing of the pixel circuit in 2nd Embodiment. The figure which shows schematic structure of the radiation imaging device concerning 3rd Embodiment. The figure which shows schematic structure of the radiation imaging device concerning 4th Embodiment. It is a figure which shows the flow of the drive procedure of the imaging control part in the radiation imaging device concerning 4th Embodiment. The figure which illustrates the structure of the pixel circuit of a CMOS image sensor. The drive timing chart of the pixel circuit of a CMOS image sensor. (A) The figure which illustrates the structure of the addition circuit in the pixel circuit of a CMOS type image sensor, (b) The typical block diagram of the CMOS type image sensor connected by the addition circuit. (A) The figure which illustrates the structure of the radiation imaging device concerning 1st Embodiment, (b) The figure which shows the function structure of the pixel circuit for 1 pixel of a CMOS type image pick-up element.

(First embodiment)
The configuration of the radiation imaging apparatus 204 according to the embodiment of the present invention is shown in FIGS. The radiation imaging apparatus 204 illustrated in FIG. 9A includes an imaging unit 210 configured by a plurality of CMOS imaging devices 202 and an imaging control unit 201 that controls the operations of the plurality of CMOS imaging devices 202. . FIG. 9B is a diagram illustrating a functional configuration of a pixel circuit for one pixel of a CMOS image sensor used for tiling a rectangular image sensor obtained by cutting out a CMOS photoelectric conversion element into a rectangular shape. The imaging unit 210 is configured by arranging pixel circuits in m rows and n columns (m and n are natural numbers of 2 or more) in a two-dimensional region. The switch unit 910 of the pixel circuit is connected to a power supply that supplies a predetermined voltage during operation, and disconnects from the power supply during non-operation. The accumulation unit 920 accumulates a signal for one pixel corresponding to the input radiation signal. The removal unit 930 removes noise from the signal accumulated in the accumulation unit 920. The holding unit 940 can hold and output the signal from which noise has been removed by the removing unit 930. The adder 950 performs addition processing of the signal held in the holding unit 940 and the signal held in the holding unit of another pixel circuit adjacent to a (a is a natural number of 2 or more). The imaging control unit 201 can control the operation of each pixel circuit constituting the imaging unit 210. The imaging control unit 201 operates the switch unit 910, the storage unit 920, the removal unit 930, the holding unit 940, and the addition unit 950 that constitute the pixel circuit at a timing before imaging by the imaging unit 210. Then, the imaging control unit 201 sets a predetermined voltage of a power source connected via the switch unit 910 in the storage unit 920, the removal unit 930, the holding unit 940, and the addition unit 950 (potential fixed drive). By fixing the potential, the indeterminate potentials of the storage unit 920, the removal unit 930, the holding unit 940, and the addition unit 950 in the pixel circuit are fixed at a predetermined voltage of the power source at a timing before imaging of the imaging unit 210, and the noise component is The fixed pattern noise can be corrected with high accuracy. The potential fixing drive will be described below with reference to a specific circuit configuration of the CMOS image sensor.
(Circuit configuration example of CMOS image sensor)
FIG. 6 is a diagram illustrating an example of a pixel circuit for one pixel of a CMOS image sensor used for tiling a rectangular image sensor obtained by cutting out a CMOS photoelectric conversion element into a rectangular shape. In FIG. 6, PD is a photodiode that performs photoelectric conversion. Cfd is a capacitance of a floating diffusion (floating diffusion region) that accumulates electric charges according to an optical signal converted from a radiation signal by a photodiode (PD). M2 is a reset MOS transistor (reset switch) for discharging the charge accumulated in the floating diffusion. The reset switch (M2) is connected to a first power supply that supplies a reset voltage (VRES) as a predetermined voltage during operation, and is disconnected from the first power supply during non-operation.

  M1 is a sensitivity switching MOS transistor (sensitivity switching switch) for switching and setting between the high dynamic range mode and the high sensitivity mode. C1 is a capacity for expanding the dynamic range. When the sensitivity changeover switch (M1) is turned on, charge can be accumulated. When the sensitivity changeover switch (M1) is turned on, the capacitance (Cfd) of the charge storage unit (floating diffusion) increases, and the dynamic range can be expanded although the sensitivity is lowered. For example, the sensitivity changeover switch (M1) is turned off during fluoroscopic imaging that requires high sensitivity, and the sensitivity changeover switch (M1) is turned on during DSA imaging that requires a high dynamic range. M4 is an amplifying MOS transistor (first pixel amplifier) that operates as a source follower. M3 is a selection MOS transistor (selection switch 1) for bringing the first pixel amplifier (M4) into an operating state.

  A clamp circuit (noise removal circuit) that removes reset noise (kTC noise) generated by connection with the reset voltage (VRES) when the reset switch (M2) is turned on is provided at the subsequent stage of the first pixel amplifier (M4). It has been. Ccl is a clamp capacitor, and M5 is a clamp MOS transistor (clamp switch). The clamp switch (M5) is connected to a second power supply that supplies a clamp voltage (VCL) as a predetermined voltage during operation, and is disconnected from the second power supply during non-operation. M7 is an amplification MOS transistor (second pixel amplifier) that operates as a source follower. M6 is a selection MOS transistor (selection switch 2) for bringing the second pixel amplifier (M7) into an operating state.

  Two sample-and-hold circuits are provided after the second pixel amplifier (M7). M8 is a sample and hold MOS transistor (sample and hold switch S) that constitutes a sample and hold circuit (first sample and hold circuit) for storing optical signals. CS is an optical signal hold capacitor. M11 is a sample hold MOS transistor (sample hold switch N) that constitutes a sample hold circuit (second sample hold circuit) for accumulating noise signals. CN is a noise signal hold capacitor. M10 is an optical signal amplification MOS transistor (pixel amplifier S) that operates as a source follower. The pixel amplifier S (third pixel amplifier) outputs the optical signal voltage held in the sample hold circuit (first sample hold circuit) for storing optical signals.

  M9 is an analog switch (transfer switch S) for outputting the optical signal amplified by the pixel amplifier S (M10) to the S signal output line. M13 is an amplifying MOS transistor (pixel amplifier N) for a noise signal that operates as a source follower. The pixel amplifier N (fourth pixel amplifier) outputs the noise signal voltage held in the sample and hold circuit (second sample and hold circuit) for storing the noise signal. M12 is an analog switch (transfer switch N) for outputting the noise signal amplified by the pixel amplifier N (M13) to the N signal output line.

  An EN signal input unit is connected to the gates of the selection switch 1 (M3) and the selection switch 2 (M6), and the first pixel amplifier (M4) and the second pixel amplifier ( The operating state of M7) is controlled. When the EN signal is at a high level, the first pixel amplifier (M4) and the second pixel amplifier (M7) are simultaneously operated. On the other hand, when the EN signal is at a low level, the first pixel amplifier (M4) and the second pixel amplifier (M7) are simultaneously stopped. The WIDE signal input unit is connected to the gate of the sensitivity switching switch (M1), and sensitivity switching is controlled by the WIDE signal input from the WIDE signal input unit. When the WIDE signal is at a low level, the sensitivity selector switch is turned off and the high sensitivity mode is set. On the other hand, when the WIDE signal is at a high level, the sensitivity changeover switch is turned on to enter the low sensitivity mode. The PRES signal is a reset signal that turns on the reset switch (M2) to discharge the charge accumulated in the floating diffusion capacitor (Cfd). The PCL signal is a signal for controlling the clamp switch (M5). When the PCL signal is at a high level, the clamp switch (M5) is turned on, and the clamp capacitor (Ccl) is set to a clamp voltage (VCL) as a reference voltage. The TS signal is an optical signal sample / hold control signal. When the TS signal is set to high level and the sample / hold switch S (M8) is turned on, the optical signal is collectively transferred to the capacitor CS through the second pixel amplifier (M7). The

  Next, the TS signal is set to the low level for all the images at the same time, and the sample switch S (M8) is turned off to complete the holding of the optical signal charge in the sample hold circuit. The TN signal is a noise signal sample / hold control signal. When the TN signal is set to a high level and the sample / hold switch N (M11) is turned on, the noise signal is collectively transferred to the capacitor CN through the second pixel amplifier (M7). . Next, the TN signal is set to the low level for all the images and the sample switch N (M11) is turned off, whereby the holding of the noise signal charge in the sample hold circuit is completed.

(Example of driving a CMOS image sensor)
FIG. 7 is a timing chart illustrating drive timing at the time of moving image capturing when the potential fixing drive is not executed in the pixel circuit of FIG. Hereinafter, the timing of rising and falling of the control signal until charge is sampled and held in the optical signal hold capacitor CS and the noise signal hold capacitor CN in moving image capturing will be described with reference to FIG.

  Accumulation start driving starts at time (t0). The accumulation start drive is a drive for resetting and clamping. First, at time (t0), the EN signal is changed from a low level to a high level, and the first pixel amplifier (M4) and the second pixel amplifier (M7) are set in an operating state. Next, the signal PRES is changed from the low level to the high level, and the photodiode PD is connected to the reset voltage (VRES) to perform resetting. Next, the PRES signal is changed from the high level to the low level to complete the reset, and the reset voltage (VRES) is set on the first pixel amplifier (M4) side of the clamp capacitor (Ccl).

  Next, the clamp switch (M5) is turned on by changing the PCL signal from the low level to the high level at time (t1), and the clamp voltage (VCL) is applied to the second pixel amplifier (M7) side of the clamp capacitor (Ccl). Is set. At time (t2), the clamp switch (M5) is turned off by changing the PCL signal from the high level to the low level. The electric charge corresponding to the voltage difference between the clamp voltage (VCL) and the reset voltage (VRES) is accumulated in the clamp capacitor (Ccl), and the clamp is finished. The accumulation start drive ends at time (t2).

  The accumulation start drive is terminated, and accumulation of the photoelectric conversion unit (floating diffusion capacitor (Cfd)) is started from time (t2). The tiled CMOS image sensor collects all the pixels of each tiled image sensor at one time in order to prevent image misalignment caused by temporal switching deviation between image sensors and between scanning lines during moving image capturing. Thus, the accumulation start drive is performed at the same timing and the same period. Thereafter, photoelectric charges generated in the photodiode PD are accumulated in the floating diffusion capacitor (Cfd). In the accumulation start drive from time (t0) to (t2), reset noise (kTC noise) is generated by connection with the reset voltage (VRES) by turning on the reset switch (M2). The reset noise (kTC noise) is eliminated by fixing the clamp capacitor (Ccl) of the clamp circuit on the second pixel amplifier (M7) side with the clamp voltage (VCL).

  Next, initial driving starts at time (t3). The EN signal is changed from low level to high level, and the selection switch 1 (M3) and the selection switch 2 (M6) are turned on. As a result, the charge accumulated in the floating diffusion capacitor (Cfd) is subjected to charge / voltage conversion, and the converted voltage is output from the first pixel amplifier (M4) operating as a source follower to the clamp capacitor (Ccl). The voltage output from the first pixel amplifier (M4) includes reset noise. Since the second pixel amplifier (M7) side is set to the clamp voltage (VCL) at the time of reset by the clamp circuit, the voltage including the reset noise becomes an optical signal voltage from which the reset noise is removed, and the second pixel. It is output to the amplifier (M7). Next, the sample hold control signal TS is set to the high level and the sample hold switch S (M8) is turned on, so that the optical signal voltage is transferred to the optical signal hold capacitor (CS) through the second pixel amplifier (M7). Is done.

  By changing the TS signal from the high level to the low level at time (t4) and turning off the sample hold switch S (M8), the optical signal hold capacitor (CS) has a charge corresponding to the optical signal voltage (optical signal charge). ) Is sampled and held.

  Next, at time (t4), the reset signal PRES is changed from low level to high level, the reset switch (M2) is turned on, and the floating diffusion capacitor (Cfd) is reset at a potential corresponding to the reset voltage (VRES). At time (t5), the reset signal PRES is changed from the high level to the low level to complete the reset. At this time, the reset voltage (VRES) is set on the first pixel amplifier (M4) side of the clamp capacitor (Ccl).

  Next, at time (t5), the PCL signal is changed from low level to high level. As a result, the clamp switch (M5) is turned on, and the clamp voltage (VCL) is set on the second pixel amplifier (M7) side of the clamp capacitor (Ccl). Charges corresponding to the voltage difference between the clamp voltage (VCL) and the reset voltage (VRES) are accumulated in the clamp capacitor (Ccl).

  At time (t5), the TN signal is changed from low level to high level, and the sample hold switch N (M11) is turned on, so that the noise signal voltage generated when the clamp voltage (VCL) is set is held for the noise signal. Transfer to capacity (CN).

  At time (t6), the TN signal is changed from the high level to the low level, and the sample hold switch N (M11) is turned off, so that the noise signal holding capacitor (CN) of the noise signal has a charge (in accordance with the noise signal voltage). Noise signal charge) is sampled and held. At time (t6), the EN signal and the PCL signal are changed from the high level to the low level, and the initial driving is finished. Initial driving is performed for all pixels at once.

  After the initial drive, accumulation start drive is performed again at time (t7), and accumulation of the photodiode PD in the next frame (N + 1 frame) of the current frame (N frame (N: natural number)) is started. The scanning of the optical signal and the noise signal is performed for each pixel. By turning on the transfer switch S (M9) and the transfer switch N (M12), the optical signal voltage corresponding to the charge of the optical signal hold capacitor (CS) and the charge of the noise signal hold capacitor (CN) And a noise signal voltage corresponding to the output. The optical signal voltage corresponding to the charge of the optical signal hold capacitor (CS) is transferred to the optical signal output line via the pixel amplifier S (M10). The noise signal voltage corresponding to the charge of the noise signal holding capacitor (CN) is transferred to the noise signal output line via the pixel amplifier N (M13).

  The optical signal voltage transferred to the optical signal output line and the noise signal voltage transferred to the noise signal output line are subtracted by an operation input amplifier (not shown) connected to the optical signal output line and the noise signal output line. The difference between the two is obtained. The noise signal voltage corresponds to fixed pattern noise (FPN) due to, for example, thermal noise, 1 / f noise, temperature difference, and process variation in the pixel amplifier. The fixed pattern noise (FPN) is removed from the optical signal voltage by the subtraction processing in the operation input amplifier. The period during which the noise signal voltage and the optical signal voltage relating to the current frame can be transferred is from the time when the sample and hold ends (t6) to the time (t9) when the optical signal charge relating to the next frame is sampled and held.

  In the circuit of FIG. 6, the timing for starting the accumulation of the floating diffusion capacitor (Cfd) is when the clamping is completed by setting the PCL signal to the low level at time (t2) or time (t8) in FIG. Further, the accumulation end timing is the time when the optical signal voltage is sampled and held at the time (t4) or the time (t10) when the TS signal is changed from the high level to the low level. The storage time can be limited by inserting a storage start drive or an initial drive for starting the storage time between the initial drive 701 and the initial drive 702 that sample and hold the optical signal voltage and the noise signal voltage. In the example of FIG. 7, the storage start drive 703 is inserted at the timing of time (t7). The optical signal voltage sample and hold period is from time (t4) to time (t10), while the storage time is the same time from time (t2) to time (t4). The time is limited to (t10).

  The pixel circuit connects an optical signal storage sample-hold circuit (first sample-hold circuit) and an optical signal storage sample-hold circuit (third sample-hold circuit) of another pixel circuit to generate an optical signal voltage. A first adding circuit for adding is provided. The pixel circuit connects a noise signal sample and hold circuit (second sample and hold circuit) to a noise signal sample and hold circuit (fourth sample and hold circuit) of another pixel circuit, and adds a noise signal voltage. The addition circuit is provided.

  FIG. 8A is a diagram illustrating the configuration of an adder circuit (first adder circuit, second adder circuit) in a pixel circuit of a CMOS image sensor. FIG. 8A illustrates a circuit configuration in which an addition circuit (a first addition circuit and a second addition circuit) is inserted into a circuit configuration in which pixel circuits 801 and 802 for two circuits are simply displayed. Each of the photodiodes 160 and 161 corresponds to the photodiode PD in FIG. Reference numerals 162, 163, 166, 167, 172, and 173 denote amplification MOS transistors (pixel amplifiers) that operate as source followers in the respective circuits. The pixel amplifiers 162 and 163 correspond to the first pixel amplifier (M4) in FIG. 6, and the pixel amplifiers 166 and 167 correspond to the second pixel amplifier (M7) in FIG. The pixel amplifiers 172 and 173 correspond to the pixel amplifier S (M10: third pixel amplifier) and the pixel amplifier N (M13: fourth pixel amplifier) in FIG. Reference numerals 164 and 165 denote clamp capacitors of the respective pixel circuits, which correspond to the clamp capacitors (Ccl) in FIG. Reference numerals 168 and 169 denote sample MOS transistors (sample hold switches) constituting a sample hold circuit for accumulating the optical signal voltage or noise signal voltage of each pixel circuit. The sample hold switches 168 and 169 correspond to the sample hold switch S (M8) or the sample hold switch N (M11) in FIG. Reference numerals 170 and 171 denote optical signal hold capacitors or noise signal hold capacitors, which correspond to the optical signal hold capacitor (CS) or noise signal hold capacitor (CN) in FIG. The adder circuit 150 connects the optical signal hold capacitor (noise signal hold capacitor) on the pixel circuit 801 side and the adder circuit 151. The adder circuit 151 connects the adder circuit 150 to the optical signal hold capacitor (noise signal hold capacitor) on the pixel circuit 802 side. For the sake of simplicity, the adder circuits 150 and 151 are shown as one circuit element in FIG. 8A, but a first adder circuit that adds an optical signal voltage and a second adder that adds a noise signal voltage. Circuit elements corresponding to the adder circuit are arranged.

  FIG. 8B is a diagram showing a schematic configuration of a CMOS type image sensor connected by an adder circuit (first adder circuit, second adder circuit). The pixel circuit shown in FIG. ". A portion surrounded by a dotted line in FIG. 8A and a portion surrounded by a dotted line in FIG. 8B indicate the same circuit portion.

  As shown in FIG. 8B, an optical signal hold capacitor or a noise signal hold capacitor for each adjacent pixel is connected to perform pixel addition. As a result, the number of pixels to be scanned is reduced without discarding the pixel information, and signals can be read at a higher frame rate. When the addition signal is changed from the low level (low level) to the high level (high level), all of the addition MOS transistors connected to the addition signal line are operable (ON). In FIG. 8B, when the ADD signal is at a high level and the ADD1 signal is at a low level, pixel addition with a pixel size of 2 × 2 can be performed. Further, when the ADD signal is set to the high level and the ADD1 signal is set to the high level, 4 × 4 pixel addition can be performed. Further, when the ADD signal, the ADD signal 1 and the ADD2 signal are set to the high level, 8 × 8 pixel addition can be performed.

(Drive control of CMOS image sensor)
Next, drive control of a CMOS image sensor that performs fixed potential drive, which is a feature of the present invention, will be described with reference to the timing chart of FIG. FIG. 1 shows a timing chart of drive waveforms when the first to second images are taken at the time of moving image capturing in the pixel circuit for one pixel of the CMOS image sensor shown in FIGS. . The pixel circuit is set with high sensitivity and no pixel addition, and the driving shown in FIG. 1 is performed for all pixels in a CMOS image sensor.

  The timing chart of FIG. 1 will be described in time series. In the present embodiment, in order to fix the indefinite potential of the floating portion in the pixel circuit of the CMOS type image sensor, driving is performed to fix the indeterminate potential with a predetermined voltage of the power supply at the timing before imaging by the imaging unit (potential fixing). Drive). First, at time (t11), the EN signal, TS signal, PRES signal, PCL signal, TN signal, and WIDE signal are changed from low level to high level. Accordingly, the reset switch (M2), clamp switch (M5), sample hold switch S (M8), sample hold switch N (M11), sensitivity changeover switch (M1), selection switch 1 (M3), selection switch 2 (M6) Turns on. In FIG. 6, stable potentials are respectively applied to the floating portions on the output side from the input side of the pixel circuit to the transfer switch S (M9) and the transfer switch N (M12). After fixing all the floating portions of the pixel circuit with stable potentials, at time (t12), the EN signal, TS signal, PRES signal, PCL signal, TN signal, and WIDE signal are changed from high level to low level. Accordingly, the reset switch (M2), clamp switch (M5), sample hold switch S (M8), sample hold switch N (M11), sensitivity changeover switch (M1), selection switch 1 (M3), selection switch 2 (M6) Turns off. Thereby, in FIG. 6, all floating parts on the output side from the input side of the pixel circuit to the transfer switch S (M9) and the transfer switch N (M12) are fixed (clamped) at a stable potential.

  Further, at time (t12), ADD, ADD1, and ADD2 are changed from the low level to the high level, and the addition circuit 150 and the addition circuit 151 (FIG. 8B) are turned on. Thereby, a stable potential is set in all the floating portions of the pixel circuit shown in FIG. In order to fix all the floating portions of the pixel circuit shown in FIG. 8B with a stable potential, ADD, ADD1, and ADD2 are changed from the high level to the low level at time (t13). As a result, the floating portion of the pixel circuit shown in FIG. 8B is fixed at a stable potential. All floating portions of the pixel circuit in the CMOS image sensor have a fixed potential. The potential fixing drive is executed from time (t11) to time (t12) in FIG.

  Next, accumulation start driving is performed. The accumulation start drive is a drive that performs reset and clamp from time (t14) to time (t16) in FIG. First, at time (t14), the EN signal is changed from a low level to a high level, and the first pixel amplifier (M4) and the second pixel amplifier (M7) are set in an operating state. Next, when the reset signal (PRES signal) is changed from low level to high level and the reset switch is turned on, the floating diffusion capacitor (Cfd) is reset by connection with the reset voltage (VRES). At time (t15), the PRES signal is changed from the high level to the low level to complete the reset, and the reset voltage (VRES) is set on the first pixel amplifier (M4) side of the clamp capacitor (Ccl).

  At time (t15), the clamp switch (M5) is turned on by changing the PCL signal from the low level to the high level, and the clamp voltage (VCL) is set on the second pixel amplifier (M7) side of the clamp capacitor (Ccl). Is done.

  When the PCL signal is changed from the high level to the low level at time (t16), the clamp switch (M5) is turned off, and the electric charge corresponding to the difference voltage between the clamp voltage (VCL) and the reset voltage (VRES) is transferred to the clamp capacitor ( Ccl) is accumulated and the clamping is completed. The accumulation start drive ends at time (t16).

  On the other hand, accumulation of the floating diffusion capacitor (Cfd) is started from time (t16). The tiled CMOS image sensor collects all the pixels of each tiled image sensor at one time in order to prevent image misalignment caused by temporal switching deviation between image sensors and between scanning lines during moving image capturing. Thus, the accumulation start drive is performed at the same timing and the same period. Thereafter, photoelectric charges generated in the photodiode PD are accumulated in the floating diffusion capacitor (Cfd). In the accumulation start drive from time (t14) to time (t16), reset noise (kTC noise) is generated by connection with the reset voltage (VRES) by turning on the reset switch (M2). The reset noise (kTC noise) is eliminated by fixing the clamp capacitor (Ccl) of the clamp circuit on the second pixel amplifier (M7) side with the clamp voltage (VCL).

  The initial drive starting at time (t17) will be described. The EN signal is changed from the low level to the high level, and the selection switch 1 (M3) and the selection switch 2 (M6) are turned on. As a result, the charge accumulated in the floating diffusion capacitor (Cfd) is subjected to charge / voltage conversion, and the converted voltage is output from the first pixel amplifier (M4) operating as a source follower to the clamp capacitor (Ccl). . The voltage output from the first pixel amplifier (M4) includes reset noise, but the reset noise is removed by fixing the second pixel amplifier (M7) side with the clamp voltage (VCL). The optical signal voltage from which the set noise has been removed is output to the second pixel amplifier (M7).

  At time (t17), the sample hold control signal TS is changed from the low level to the high level, and the sample hold switch S (M8) is turned on, so that the optical signal voltage passes through the second pixel amplifier (M7) and the optical signal hold capacitance ( CS).

  By changing the TS signal from high level to low level at time (t18) and turning off the sample hold switch S (M8), the optical signal charge corresponding to the optical signal voltage is sampled and held in the optical signal hold capacitor (CS). The

  Next, at time (t18), the reset signal PRES is changed from the low level to the high level, the reset switch (M2) is turned on, and the floating diffusion capacitor (Cfd) is reset with charges according to the reset voltage (VRES). At time (t19), the reset signal PRES is changed from the high level to the low level to complete the reset. A reset voltage (VRES) is set on the first pixel amplifier (M4) side of the clamp capacitor (Ccl).

  Next, at time (t19), the PCL signal is changed from low level to high level. As a result, the clamp switch (M5) is turned on, and the clamp voltage (VCL) is set on the second pixel amplifier (M7) side of the clamp capacitor (Ccl). Charges corresponding to the voltage difference between the clamp voltage (VCL) and the reset voltage (VRES) are accumulated in the clamp capacitor (Ccl).

  At time (t19), the TN signal is changed from low level to high level, and the sample hold switch N (M11) is turned on, so that the noise signal voltage generated when the clamp voltage (VCL) is set is used for the noise signal. Transfer to hold capacitor (CN).

  At time (t20), the TN signal is changed from the high level to the low level, and the sample hold switch N (M11) is turned off, whereby the noise signal holding capacitor (CN) for the noise signal corresponds to the noise signal voltage. The charge is sampled and held. Further, at time (t20), the EN signal and the PCL signal are changed from the high level to the low level, and the initial driving ends. Initial driving is performed for all pixels at once.

  After the initial drive, accumulation start drive is performed again at time (t21), and accumulation of the floating diffusion capacity (Cfd) in the next frame (N + 1 frame) of the current frame (N frame (N: natural number)) is started. . The scanning of the optical signal and the noise signal is performed for each pixel. By turning on the transfer switch S (M9) and the transfer switch N (M12), the optical signal voltage of the optical signal hold capacitor (CS) and the noise signal voltage of the noise signal hold capacitor (CN) are reduced. Is output. That is, the optical signal voltage of the optical signal hold capacitor (CS) is transferred to the optical signal output line via the pixel amplifier S (M10: third pixel amplifier). Further, the noise signal voltage of the noise signal holding capacitor (CN) is transferred to the noise signal output line via the pixel amplifier N (M13: fourth pixel amplifier).

  The noise signal voltage transferred to the noise signal output line and the optical signal voltage transferred to the optical signal output line are subtracted by an operation input amplifier (not shown) connected to the noise signal output line and the optical signal output line, The difference between the two is obtained. The noise signal voltage corresponds to fixed pattern noise (FPN) due to, for example, thermal noise, 1 / f noise, temperature difference, and process variation in the pixel amplifier. The fixed pattern noise (FPN) is removed from the optical signal voltage by the subtraction processing in the operation input amplifier.

  During the transfer period of the noise signal voltage and the optical signal voltage of the current frame, the optical signal charge of the next frame is sampled and held again in the optical signal hold capacitor (CS) from the end of the sample hold (t20) ( until t23).

  The optical signal obtained by the subtraction processing by the differential input amplifier is further subjected to FPN correction by the FPN pattern of the optical signal acquired in advance under the condition that no light is irradiated.

  Since the pixel addition is not performed with the high sensitivity setting in the drive of FIG. 1, the sensitivity changeover switch (M1), the adder circuit 150, and the adder circuit 151 are not turned on after the accumulation start drive, and the capacitor (C1) and the adder circuit 150 are added. The floating portion remains between the circuits 151. However, by fixing the capacitance (C1) and the potential between the addition circuit 150 and the addition circuit 151 before capturing a moving image, random noise generated in the background of the captured image due to an indefinite potential in the circuit. The part is fixed. By fixing a part of the random noise, there is no difference between the potential of the floating portion in the CMOS image sensor circuit when the FPN pattern is acquired and the potential of the floating portion when the moving image is actually acquired. , Accurate FPN correction can be performed.

  In the circuit of FIG. 6, the timing for starting the accumulation of the floating diffusion capacitor (Cfd) is when the clamping is completed by setting the PCL signal to the low level at time (t16) or (t22) in FIG. Further, the accumulation end timing is the time when the optical signal is sampled and held at the low level of the TS signal at time (t18) or (t24). The storage time can be limited by inserting a storage start drive or an initial drive for starting the storage time between the initial drive 101 and the initial drive 102 for sample-holding the optical signal and the noise signal.

  In the example of FIG. 1, the storage start drive 103 is inserted at the timing of time (t21). The optical signal sample and hold period is from time (t18) to time (t24), while the accumulation time is the same time from time (t16) to time (t18) to time (t24). ) Is limited to the time until. However, when the initial drive is inserted at the timing of time (t21), the scanning period is limited from (t20) to the time (t21) before the initial drive starts and the optical signal charge is sampled and held. . When the requested accumulation time and the sample period are the same, the accumulation start drive from time (t21) to time (t22) is not inserted, and the initial drive is started from time (t21).

(Low sensitivity mode, no pixel addition)
Next, an operation mode (low sensitivity mode (high dynamic range mode)) of the pixel circuit when the sensitivity setting of the pixel circuit is lowered and the dynamic range is expanded will be described. It is assumed that pixel addition is not performed. Since operations other than the WIDE signal are performed at the same drive timing as the timing chart shown in FIG. 1, differences from FIG. 1 will be described with reference to FIGS. 1 and 6. At time (t14), the WIDE signal is changed from low level to high level, and the sensitivity changeover switch (M1) is turned on. As a result, the floating diffusion capacitor (Cfd) and the capacitor (C1) are connected in parallel, the capacity of the floating node portion increases, and the dynamic range is expanded instead of decreasing the sensitivity. The WIDE signal stays at the high level until imaging is completed after it changes from the low level to the high level at time (t14) in FIG. As a result, the sensitivity is always low during imaging, but the dynamic range is expanded. When the sensitivity is lowered, the floating portion is between the addition circuit 150 and the addition circuit 151. However, before capturing a moving image, it is possible to reduce the noise component by fixing the indefinite potential of the floating portion in the pixel circuit with a predetermined voltage of the power supply at a timing before imaging by the imaging unit.

(High sensitivity mode, with pixel addition)
Next, as an example of pixel addition, 2 × 2 pixel addition will be described as an example. The sensitivity is assumed to be a high sensitivity mode. Since an example of 2 × 2 pixel addition is the same as the timing chart shown in FIG. 1 except for the ADD signal, differences from FIG. 1 will be described with reference to FIGS. 1, 6, and 8. At time (t20), the imaging control unit 201 changes the TN signal from the high level to the low level, turns off the sample hold switch N (M11), and accumulates the noise signal component in the noise signal hold capacitor (CN). Ends. Thereafter, the ADD signal is set to high level, and the addition circuit 150 and the addition circuit 151 are turned on. At this time, all the MOS transistors connected to the ADD signal line in FIG. 8B are also turned on. As a result, 2 × 2 pixel addition is performed for the noise signal that has been accumulated in the noise signal hold capacitor (CN) together with the optical signal that has been accumulated in the optical signal hold capacitor (CS) at time (t18). Is called. The imaging control unit 201 changes the ADD signal from the high level to the low level at time (t23). In the scanning period of the optical signal and the noise signal, adjacent 2 × 2 pixels are in the pixel addition state.

  When performing 2 × 2 pixel addition in the high sensitivity mode in accordance with the timing chart of FIG. 7, the addition circuit used for the capacitance (C1), 4 × 4 pixel addition and 8 × 8 pixel addition of FIG. 8B is floating. Part. However, it is possible to fix the indefinite potential of the floating portion in the pixel circuit and reduce the noise component by performing the potential fixing drive before capturing the moving image according to the timing chart of FIG.

  Similarly, when 4 × 4 pixel addition is performed, the imaging control unit 201 changes the ADD signal and ADD1 signal from low level to high level at time (t20), and the MOS transistors connected to the ADD signal line and ADD1 signal line. Also turn on all. As a result, 4 × 4 pixel addition is performed for the noise signal that has been accumulated in the noise signal hold capacitor (CN) together with the optical signal that has been accumulated in the optical signal hold capacitor (CS) at time (t18). Is called. At time (t23), the imaging control unit 201 changes the ADD signal and the ADD1 signal from high level to low level. When performing 4 × 4 pixel addition in the high sensitivity mode in accordance with the timing chart of FIG. 7, the capacitor (C1) and the 8 × 8 pixel addition circuit of FIG. However, it is possible to fix the indefinite potential of the floating portion in the pixel circuit and reduce the noise component by performing the potential fixing drive before capturing the moving image according to the timing chart of FIG.

  Similarly, when pixel addition is performed at 8 × 8, the imaging control unit 201 changes the ADD signal, ADD1 signal, and ADD2 signal from low level to high level at time (t20). All MOS transistors connected to the ADD signal line, the ADD1 signal line, and the ADD2 signal line are also turned on. As a result, 8 × 8 pixel addition is performed on the optical signal that has been accumulated in the optical signal hold capacitor (CS) at time (t18) and the noise signal that has been accumulated in the noise signal hold capacitor (CN). Is called. The imaging control unit 201 changes the ADD signal line, the ADD1 signal line, and the ADD2 signal from high level to low level at time (t23). In the 8 × 8 pixel addition in the high sensitivity mode according to the timing chart of FIG. 7, the capacitor (C1) becomes the floating portion. However, it is possible to fix the indefinite potential of the floating portion in the pixel circuit and reduce the noise component by performing the potential fixing drive before capturing the moving image according to the timing chart of FIG. Furthermore, FPN correction can be performed with high accuracy.

  In the high sensitivity mode, the capacitance (C1) becomes a floating part, but when the sensitivity is lowered, the imaging control unit 201 changes the WIDE signal from low level to high level and turns on the sensitivity changeover switch (M1). As a result, the floating diffusion capacitor (Cfd) and the capacitor (C1) are connected in parallel, the capacity of the floating node portion increases, and the dynamic range is expanded instead of decreasing the sensitivity. When the sensitivity is lowered and 2 × 2, 4 × 4, and 8 × 8 pixel addition is performed, the capacitor (C1) does not become a floating portion.

  When 2 × 2 pixel addition is performed with low sensitivity, an addition circuit used for 4 × 4 pixel addition and 8 × 8 pixel addition becomes a floating portion. When 4 × 4 pixel addition is performed with low sensitivity, an addition circuit used for 8 × 8 pixel addition becomes a floating portion. Also in these cases, it is possible to fix the indefinite potential of the floating portion in the pixel circuit and reduce the noise component by performing the potential fixing drive (FIG. 1) before capturing the moving image. Furthermore, FPN correction can be performed with high accuracy.

  In the potential fixing drive, the EN signal, TS signal, PRES signal, PCL signal, TN signal, WIDE signal, ADD signal, ADD1 signal, and ADD2 signal are changed from low level to high level. As long as the object of making all the floating portions have stable potentials can be achieved, the timing at which each signal changes from low level to high level and the timing from high level to low level may be changed. For example, the EN signal, TS signal, PRES signal, PCL signal, and TN signal in the fixed potential drive may be changed to the low level timing and the high level timing of each signal so as to have the same drive pattern as the initial drive. . Further, high-level to low-level conversion may be repeatedly performed on one signal.

  In addition, the accumulation start drive and the initial drive shown in FIG. 1 have different drive patterns. However, the drive pattern is not necessarily limited to this example. For example, the accumulation start drive can be performed with the same drive pattern as the initial drive. As a result, only one drive pattern needs to be mounted, leading to simplification of mounting. Further, the accumulation start drive from (t21) and the initial drive from (t23) may not be performed. Thereby, it is possible to capture only one frame.

  According to the present embodiment, the indefinite potential of the floating part in the pixel circuit is fixed at a predetermined voltage of the power supply at the timing before imaging by the imaging unit, the noise component is reduced, and the fixed pattern noise is accurately corrected. It becomes possible.

(Second Embodiment)
Next, drive control of the CMOS image sensor according to the second embodiment of the present invention will be described with reference to the timing chart of FIG. FIG. 2 shows the driving waveform when the first to second images are taken at the time of moving image pick-up in the pixel circuit for one pixel of the CMOS type image pickup device shown in FIGS. A timing chart is shown. The pixel circuit is set with high sensitivity and no pixel addition. The driving shown in FIG. 2 is performed for all pixels in a CMOS image sensor.

  The timing chart of FIG. 2 is different from the timing chart of FIG. 1 in that the potential fixing drive includes the first accumulation start drive for moving image imaging start. Hereinafter, FIG. 2 will be described in time series. As in the first embodiment, the driving (potential fixing driving) for making all the floating portions each have a stable potential (fixed potential) is performed. At time (t25), the EN signal, TS signal, PRES signal, PCL signal, TN signal, and WIDE signal are changed from low level to high level. Accordingly, the reset switch (M2), clamp switch (M5), sample hold switch S (M8), sample hold switch N (M11), sensitivity changeover switch (M1), selection switch 1 (M3), selection switch 2 (M6) Turns on. In FIG. 6, stable potentials are respectively applied to all portions on the output side from the input side of the pixel circuit to the transfer switch S (M9) and the transfer switch N (M12).

  After all the potentials in the CMOS image sensor are fixed, at time (t26), the TS signal, the PCL signal, the TN signal, and the WIDE signal are changed from the high level to the low level. The selection switch 1 (M3) and the reset switch (M2) are turned on, and the accumulation start drive is started from time (t26).

  At time (t26), the ADD signal, ADD1 signal, and ADD2 signal are changed from low level to high level, and the potential of the pixel addition circuit shown in FIG. 8B is fixed.

  At time (t27), the PRES signal is changed from the high level to the low level to complete the reset, and the reset voltage (VRES) is set on the first pixel amplifier (M4) side of the clamp capacitor (Ccl). At time (t27), the clamp switch (M5) is turned on by changing the PCL signal from the low level to the high level, and the clamp voltage (VCL) is applied to the second pixel amplifier (M7) side of the clamp capacitor (Ccl). Set. The electric charge corresponding to the voltage difference between the clamp voltage (VCL) and the reset voltage (VRES) is accumulated in the clamp capacitor (Ccl), and the clamp is finished.

  At time (t28), the EN signal, the PCL signal, the ADD signal, the ADD1 signal, and the ADD2 signal change from the high level to the low level, and the combined operation of the potential fixing drive and the accumulation start drive ends. At time (t28), the ADD signal, ADD1 signal, and ADD2 signal are controlled from the high level to the low level simultaneously with the EN signal and the PCL signal. In this case, the pixel addition circuit shown in FIG. 8B and the clamp capacitor (Ccl) and the floating diffusion capacitor (Cfd) are electrically disconnected unless the TS signal and the TN signal are set to the high level. There is no problem even if such driving is performed.

  After time (t28), the operation is performed with the same drive pattern as that after time (t13) in FIG. 1 in the first embodiment.

  By operating the pixel circuit by combining the fixed potential drive and the accumulation start drive, the accumulation start drive can be performed at the same time as the potential fixed drive is completed. For this reason, it is possible to reduce the time required for acquiring the first image after the photoelectric conversion element starts the potential fixing drive.

  According to the present embodiment, the indefinite potential of the floating part in the pixel circuit is fixed at a predetermined voltage of the power supply at the timing before imaging by the imaging unit, the noise component is reduced, and the fixed pattern noise is accurately corrected. It becomes possible.

(Third embodiment)
FIG. 3 shows a schematic configuration of a radiation imaging apparatus according to the third embodiment of the present invention. All CMOS image sensors 202 (pixel circuits) in the radiation imaging apparatus 204 are connected to the imaging control unit 201, and each CMOS image sensor 202 (pixel circuit) is controlled by a control signal from the imaging control unit 201. Is done. The radiation imaging apparatus 204 has a timer 205 (timer unit) that measures time. The imaging control unit 201 stores the time at which the control signal is transmitted to the CMOS type imaging device 202 (pixel circuit) in order to perform fixed potential driving in the memory 203 connected to the imaging control unit 201.

  It is assumed that after the power is turned on to the radiation imaging apparatus 204, the moving image is acquired by driving according to the first setting, and then the moving image is acquired by changing to the second setting immediately. When a moving image is acquired for the first time after the radiation imaging apparatus 204 is turned on, the potential difference between the floating portions in the CMOS image sensor 202 (pixel circuit) becomes indefinite, and the time until the potential of the floating portion becomes stable is obtained. Will inevitably be longer. However, when recapturing a moving image after capturing a moving image, since the potential is fixed once, the time until the potential of the floating portion is fixed is shortened. May not be necessary. Whether to perform the fixed potential drive or not, or for how long it should be performed depends on how much time has elapsed since the previous fixed potential drive.

  When the moving image is captured by the second imaging after the first image is captured, the imaging control unit 201 compares the current time with the time stored in the memory 203, and The elapsed time from the previous time when the fixed potential drive was performed is calculated. A threshold time serving as a reference for controlling the potential fixing drive can be stored in the memory 203 in advance, for example. Alternatively, the threshold time can be set via an operation input unit (not shown). The imaging control unit 201 can compare the threshold time (TH) with the calculated elapsed time (TE) and control the potential fixing drive according to the comparison result.

  For example, when the elapsed time is within the threshold time (TE ≦ TH), the imaging control unit 201 can perform control so as not to perform the fixed potential drive. On the other hand, when the elapsed time (TE) exceeds the threshold time (TH) (TE> TH), the imaging control unit 201 can perform control such that the potential is fixed. The imaging control unit 201 operates the switch unit 910, the storage unit 920, the removal unit 930, and the holding unit 940 that configure the pixel circuit, and sets a potential corresponding to a predetermined voltage of a power source connected via the switch unit 910. The storage unit 920, the removal unit 930, and the holding unit 940 are set.

  As the threshold time, one or two or more (TH1, TH2: TH1 <TH2) can be used according to the imaging environment of the moving image and the imaging conditions. In this case, the imaging control unit 201 compares the elapsed time (TE) with the first threshold time (TH1) and the second threshold time (TH2), and can control the potential fixing drive according to the comparison result. It is. For example, when the elapsed time (TE) is within the first threshold time (TH1) (TE ≦ TH1), the imaging control unit 201 can perform control so as not to perform the fixed potential drive. On the other hand, when the elapsed time (TE) exceeds the first threshold time (TH1) and is within the second threshold time (TH2) (TH1 <TE ≦ TH2), the imaging control unit 201 performs the first potential fixing time. In (TC1), it is possible to perform control so as to perform fixed potential driving. Further, when the elapsed time (TE) exceeds the second threshold time (TH2), the imaging control unit 201 fixes the potential in the second potential fixing time (TC2) longer than the first potential fixing time (TC1). It is possible to control to drive. In the above-described example, an example in which the first threshold time (TH1) and the second threshold time (TH2) are used as an example of a plurality of threshold times is shown. However, the gist of the present invention is not limited to this example. Absent. For example, the imaging control unit 201 can control the potential fixing drive in multiple stages using the elapsed time (TE) and N (natural number) threshold times.

  In accordance with the comparison result between the elapsed time and the threshold time, the time of the fixed potential driving is changed. As a result, it is possible to reduce the time loss due to the potential fixing drive until the radiation exposure is possible when the moving image is captured once and then the re-imaging is performed.

  Alternatively, a method of preparing a counter that is reset when the imaging control unit 201 performs a fixed potential drive without using the memory 203 that stores the time at which the control signal is transmitted may be used. The imaging control unit 201 can also control the potential fixing drive with reference to the counter value.

(Fourth embodiment)
FIG. 4 shows a schematic configuration of a radiation imaging apparatus according to the fourth embodiment of the present invention. The radiation imaging apparatus 204 includes a system control unit 206 that controls the operation of the apparatus, a radiation image display unit 207, and an X-ray generation device 208 that is connected to the X-ray tube 209. All CMOS image sensors 202 (pixel circuits) in the radiation imaging apparatus 204 are connected to the imaging control unit 201, and each CMOS image sensor 202 (pixel circuit) is controlled by a control signal from the imaging control unit 201. Is done.

  The system control unit 206 has an image processing function, processes an image captured by the CMOS image sensor 202 (pixel circuit), and outputs the processed image to the radiation image display unit 207. At the time of imaging, the system controller 206 controls the radiation imaging apparatus 204 and the X-ray generation apparatus 208 synchronously. The radiation that has passed through the subject is converted into visible light by a scintillator (not shown). Thereafter, photoelectric conversion corresponding to the amount of light is performed by the CMOS image sensor 202 of the radiation imaging apparatus 204. After photoelectric conversion, A / D conversion is performed, and frame image data corresponding to X-ray irradiation is transferred from the radiation imaging apparatus 204 to the system control unit 206. After the image processing is performed by the image processing function of the system control unit 206, the radiation image is displayed on the radiation image display unit 207 in real time. Here, the system control unit 206 communicates with the imaging control unit 201 of the radiation imaging apparatus 204 by a command. The imaging control unit 201 controls the power supply of the CMOS type image sensor 202 and sets the drive according to the command transmitted from the system control unit 206. The drive setting is a setting of sensitivity, pixel addition, frame rate, and radiation accumulation time.

  FIG. 5 is a diagram illustrating a flow of a driving procedure of the imaging control unit 201 in the radiation imaging apparatus 204 according to the fourth embodiment. The processing flow will be described with reference to FIG. The imaging control unit 201 has a communication function for performing wired or wireless communication with the external system control unit 206. First, the system control unit 206 transmits a command for initial setting of the radiation imaging apparatus 204 to the imaging control unit 201 (c1). Next, the system control unit 206 transmits a setting command for driving the CMOS image sensor 202 (pixel circuit) to the imaging control unit 201 (c2). Here, the imaging control unit 201 that has received the setting command sets sensitivity, pixel addition, frame rate, and radiation accumulation time. Subsequently, the system control unit 206 transmits a command for turning on the power of the CMOS image sensor 202 to the imaging control unit 201 (c3). When the imaging control unit 201 receives the command transmitted from the system control unit 206 in step (c3), the imaging control unit 201 turns on the power of the CMOS type image sensor 202 and further starts the potential fixing drive. Here, the order of step (c2) and step (c3) may be reversed. Subsequently, the system control unit 206 transmits a command to start imaging to the imaging control unit 201 (c4). When the imaging control unit 201 receives the command transmitted in step (c4), the imaging control unit 201 ends the potential fixing drive and starts the imaging drive for the CMOS image sensor 202. The imaging drive indicates a drive that starts from time (t13) in FIG. Thereafter, the system control unit 206 transmits an imaging end command to the imaging control unit 201 at the imaging end timing (c5). When the imaging control unit 201 receives the command transmitted in step (c5), the imaging control unit 201 causes the CMOS image sensor 202 to finish imaging driving.

  When there is next imaging, the system control unit 206 transmits a command for setting driving again to the imaging control unit 201 (c6), and the sensitivity, pixel addition, frame rate, and radiation accumulation time in the imaging control unit 201 are transmitted. Perform resetting. When the imaging control unit 201 receives the command transmitted in step (c6), the imaging control unit 201 causes the CMOS image sensor to start a fixed potential drive. Then, the system control unit 206 transmits an imaging start command to the imaging control unit 201 (c7), and starts imaging driving of the CMOS image sensor. When ending imaging, the system control unit 206 transmits an imaging end command to the imaging control unit 201 at the imaging end timing, as in the previous step (c5). When the imaging control unit 201 receives the transmitted imaging end command, the imaging control unit 201 causes the CMOS image sensor 202 to finish imaging driving.

  As described above, the fixed potential driving is started when the imaging control unit 201 receives a command from the system control unit 206 (steps (c2) and (c6)). When the imaging control unit 201 receives a command to start imaging (steps (c4) and (c7)) and performs the fixed potential drive, the radiation imaging apparatus 204 permits exposure during the time during which the fixed potential drive is operated. It will not be in a state. For this reason, radiation exposure cannot be started immediately at the timing at which the operator wants to start imaging, and the operator must operate while taking into account the delay in imaging start in anticipation of potential fixed drive. However, according to the present embodiment, it is possible to start the potential fixing drive in advance before receiving the imaging start command. Therefore, a sufficient time can be provided for the potential fixing drive, and the operator can operate the radiation imaging apparatus without considering the delay of the imaging start timing due to the potential fixing driving.

(Other examples)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (10)

A pixel amplifier for outputting a voltage corresponding to the charge generated in the photodiode; a signal sample-and-hold switch for causing the signal hold capacitor to sample and hold the charge corresponding to the voltage; and the pixel amplifier and the photodiode an imaging unit in which a plurality of pixel circuits are arranged, each having a switching means for supplying a predetermined voltage, the between,
Imaging control means for controlling the operations of the plurality of pixel circuits so that the plurality of pixel circuits perform imaging a plurality of times to output a signal corresponding to the charge held in the signal hold capacitor ;
A time measuring means for measuring time;
A storage unit that stores a time at which a control signal is transmitted from the imaging control unit to operate the switch unit when performing the first imaging among the plurality of imagings;
With
A voltage is supplied to the pixel circuit, and before the imaging , the imaging control unit operates the pixel amplifier, the signal sample hold switch, and the switching unit to respond to the predetermined voltage. Sampled and held in the signal hold capacitor,
When the second imaging is performed after the first imaging, the imaging control unit causes the elapsed time from the time stored in the storage unit to the current time obtained by the timing unit to exceed a threshold time In this case, before the second imaging, the pixel amplifier, the signal sample hold switch, and the switch means are operated,
If the elapsed time from the time stored in the storage means to the current time obtained by the time measuring means is within a threshold time, before the second imaging, the pixel amplifier, the signal sample hold switch, The radiation imaging apparatus is characterized in that the switch means is not operated . Each of the plurality of pixel circuits further includes a noise sample and hold switch for causing the noise hold capacitor to sample and hold a charge corresponding to noise of the pixel amplifier,
The image pickup control means operates the pixel amplifier, the noise sample hold switch, the signal sample hold switch, and the switch means before the image pickup, and charges corresponding to the predetermined voltage are operated. The radiation imaging apparatus according to claim 1, wherein the noise hold capacitor and the signal hold capacitor are sampled and held. The plurality of pixel circuits are respectively for the signal hold capacitor of the predetermined pixel circuit of the plurality of pixel circuits and for the signal of another pixel circuit different from the predetermined pixel circuit of the plurality of pixel circuits. A signal adder circuit for connecting a hold capacitor; and a noise adder circuit for connecting the noise hold capacitor of the predetermined pixel circuit and the noise hold capacitor of the other pixel circuit; Including
  The signal adding circuit of the predetermined pixel circuit and the signal adding circuit of the other pixel circuit are connected;
  The noise adding circuit of the predetermined pixel circuit and the noise adding circuit of the other pixel circuit are connected;
  The imaging control means operates the pixel amplifier, the noise sample hold switch, the signal sample hold switch, the signal addition circuit, the noise addition circuit, and the switch means before the imaging. The radiation imaging apparatus according to claim 2. Each of the plurality of pixel circuits includes a charge accumulation unit for accumulating charges generated in the photodiode, and another pixel amplifier for outputting a voltage corresponding to the charges accumulated in the charge accumulation unit. A reset switch for supplying a reset voltage to the charge storage section, and a clamp capacitor provided between the other pixel amplifier and the switch means and between the pixel amplifier and the switch means, Including
The imaging control means includes the pixel amplifier, the noise sample hold switch, the signal sample hold switch, the signal addition circuit, the noise addition circuit, the other pixel amplifier, the reset, before the imaging. The radiation imaging apparatus according to claim 3 , wherein the switch and the switch unit are operated . Each of the plurality of pixel circuits further includes a sensitivity changeover switch for connecting the charge storage unit and a dynamic range expansion capacitor,
The imaging control means includes the pixel amplifier, the noise sample hold switch, the signal sample hold switch, the signal addition circuit, the noise addition circuit, the other pixel amplifier, the reset, before the imaging. The radiation imaging apparatus according to claim 4 , wherein the switch, the sensitivity changeover switch, and the switch unit are operated . Each of the plurality of pixel circuits further includes a selection switch for operating the pixel amplifier, and another selection switch for operating the other pixel amplifier,
The imaging control means includes the selection switch, the noise sample hold switch, the signal sample hold switch, the signal addition circuit, the noise addition circuit, the other selection switch, and the reset before the imaging. The radiation imaging apparatus according to claim 5 , wherein the switch, the sensitivity changeover switch, and the switch unit are operated . The storage means, when performing the first imaging, the selection switch, the noise sample hold switch, the signal sample hold switch, the signal addition circuit, the noise addition circuit, the other selection switch Storing the time when the control signal is transmitted from the imaging control means to operate the reset switch, the sensitivity changeover switch, and the switch means;
When performing the second imaging, the imaging control means
When the elapsed time from the time stored in the storage means to the current time obtained by the time measuring means exceeds a threshold time, the selection switch, the noise sample hold switch, the signal sample hold switch, Operating the signal addition circuit, the noise addition circuit, the other selection switch, the reset switch, the sensitivity changeover switch, and the switch means,
When the elapsed time from the time stored in the storage means to the current time is within a threshold time, the selection switch, the noise sample hold switch, the signal sample hold switch, the signal addition circuit, the noise The radiation imaging apparatus according to claim 6 , wherein the adder circuit, the other selection switch, the reset switch, the sensitivity changeover switch, and the switch unit are not operated . The imaging control unit includes a communication unit that communicates with a system control unit that controls the operation of the radiation imaging apparatus,
The imaging control means receives the command for turning on the power of the pixel circuit transmitted from the system control unit, and receives the selection switch, the noise sample hold switch, the signal sample hold switch, and the signal addition circuit. The radiation imaging apparatus according to claim 7 , wherein the noise addition circuit, the other selection switch, the reset switch, the sensitivity changeover switch, and the switch unit are operated . The imaging control means receives the setting command transmitted from the system control unit for driving the pixel circuit, and selects the selection switch, the noise sample hold switch, the signal sample hold switch, and the signal summing circuit, the noise addition circuit, the other selection switch, the reset switch, the sensitivity changeover switch, and a radiation imaging equipment according to claim 8, characterized in that for operating the switch means. Each of the plurality of pixel circuits outputs a voltage corresponding to the charge sampled and held in the noise hold capacitor, and a third pixel amplifier that outputs a voltage corresponding to the charge sampled and held in the signal hold capacitor. The radiation imaging apparatus according to claim 9, further comprising a fourth pixel amplifier.

Images