JP2011142434A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of acquiring a high definition image in which breakdown does not occur. <P>SOLUTION: A vertical scanning circuit 300 reads an optical signal in each divided area obtained by dividing a pixel 100 of a pixel 200 into a plurality of areas during a unit period being a period from an exposure start to the next exposure start, resets a charge holding part only in a portion of divided areas among the divided areas, reads a reset signal from the reset charge holding part, and performs control so as to change divided areas for reading a reset signal in each unit period. A subtractor 620 generates an imaging signal from a signal obtained by taking a difference between the optical signal and an optical signal read in the preceding unit period or the reset signal. A level control part 700 controls the accumulable capacity of a photodiode so as to be a level corresponding to the number of frames from which the optical signal is read by the time the next reset signal is read after reading the reset signal about the same divided area. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device in which a plurality of pixels are arranged, and more particularly to a solid-state imaging device having a global shutter function.

  Conventionally, as a MOS type solid-state imaging device, a global shutter system is known in which the exposure start time and exposure end time of all pixels are the same, that is, the exposure period of all pixels is the same (see, for example, Patent Document 1). FIG. 6 shows a pixel configuration of a global shutter type MOS solid-state imaging device. In FIG. 6, a single pixel 100 includes a photodiode 101, a transfer transistor 102, a charge holding unit (FD) 103, an FD reset transistor 104, an amplification transistor 105, a selection transistor 106, and a PD reset transistor 107.

  The photodiode 101 is a photoelectric conversion element that converts incident light into signal charges and accumulates them. The transfer transistor 102 is a transistor for transferring the signal charge accumulated in the photodiode 101 to the charge holding unit 103 (FD). The charge holding unit 103 holds the signal charge transferred from the photodiode 101 by the transfer transistor 102. The FD reset transistor 104 is a transistor for resetting signal charges in the charge holding unit 103. The amplification transistor 105 is a transistor for amplifying the voltage level of the charge holding unit 103 and outputting it as a pixel signal. The selection transistor 106 is a transistor for outputting a pixel signal to the vertical signal line 114 when the pixel 100 is selected as a pixel from which signal charges are read. The PD reset transistor 107 is a transistor for resetting the signal charge in the photodiode 101. Here, light is shielded except for the photodiode 101.

  In addition to the vertical signal line 114, a pixel power line 110, an FD reset line 111, a transfer line 112, a selection line 113, and a PD reset line 115 are arranged in the pixel 100. The pixel power supply line 110 is a signal line for applying the power supply voltage VDD, and is electrically connected to the drain side of the amplification transistor 105, the drain side of the PD reset transistor 107, and the drain side of the FD reset transistor 104. . The FD reset line 111 is a signal line for applying an FD reset pulse φRMi (i = 1 to m, m is the number of rows) for resetting the charge holding unit 103 for one row. The reset transistor 104 is connected to the gate.

  The transfer line 112 is a signal line for applying a row transfer pulse φTRi (i = 1 to m) for transferring the signal charges of pixels for one row to the charge holding unit 103 of each pixel. The pixel is electrically connected to the gate of the transfer transistor 102 of the pixel. The selection line 113 is a signal line for applying a row selection pulse φSEi (i = 1 to m) for selecting pixels for one row from which pixel signals are read out. It is electrically connected to the gate. Thus, a photoelectric conversion function, a reset function, an amplification read function, a temporary memory function, and a selection function are realized by a pixel configuration using five transistors.

  FIG. 7 shows a configuration of the MOS type solid-state imaging device. 7 includes a pixel unit 200, a vertical scanning circuit 300, a horizontal signal readout circuit 400, a current source 150, a column processing circuit 350, an ADC (AD (Analog to Digital) converter) 500, and a noise suppression circuit 600. It has.

  The pixel unit 200 has a structure in which the pixels 100 shown in FIG. 6 are arranged in a 3 × 3 two-dimensional shape. The vertical scanning circuit 300 performs drive control of the pixel unit 200 in units of rows. In order to perform this drive control, the vertical scanning circuit 300 includes unit circuits 301-1, 301-2, and 301-3 as many as the number of rows. Each unit circuit includes control units 302-i, 303-i, 304-i, and 305-i (i = 1, 2, 3).

  The control unit 302-i independently controls the FD reset pulse φRMi (i = 1, 2, 3) for resetting the charge holding unit 103 for one row for each row. The control unit 303-i independently generates a row transfer pulse φTRi (i = 1, 2, 3) for transferring the signal charges of the pixels 100 for one row to the charge holding unit 103 of each pixel 100 for each row. Control. The control unit 304-i controls the PD reset pulse φRPDi (i = 1, 2, 3) for resetting the photodiodes 101 for one row independently for each row. The control unit 305-i independently controls the row selection pulse φSEi (i = 1, 2, 3) for selecting the pixels 100 for one row from which signals are read out for each row. The signal of the pixel 100 in the row selected by the row selection pulse φSEi is output to the vertical signal line 114 provided for each column.

  The current source 150 is connected to the vertical signal line 114, and forms a source follower circuit with the amplification transistor 105 in the pixel 100. The column processing circuit 350 is a circuit that performs a clamp operation and an amplification operation on the pixel signal output to the vertical signal line 114. The horizontal signal readout circuit 400 outputs the pixel signals of the pixels 100 for one row, which are output to the vertical signal line 114 and processed by the column processing circuit 350, from the output terminal 410 in time series in the horizontal order. The ADC 500 performs A / D conversion on the signal output from the output terminal 410.

  The noise suppression circuit 600 suppresses noise of the signal output from the ADC 500. The noise suppression circuit 600 includes a frame memory 610 and a subtracter 620. The frame memory 610 stores the signal that has been A / D converted by the ADC 500. The subtracter 620 subtracts the signal stored in the frame memory 610 from the signal A / D converted by the ADC 500 to generate an imaging signal.

  In FIG. 7, the FD reset line 111, the transfer line 112, the selection line 113, the vertical signal line 114, and the PD reset line 115 are illustrated, but the pixel power supply line 110 that supplies the power supply voltage VDD is not illustrated.

  Next, a global shutter reading operation when the solid-state imaging device shown in FIG. 7 is applied to a digital camera or the like and a still image is taken will be described with reference to a timing chart shown in FIG. When the solid-state imaging device receives an imaging start signal, first, PD reset pulse φRPDi of all rows is “H” level, FD reset pulse φRMi is “L” level, row transfer pulse φTRi is “L” level, row selection pulse When φSEi becomes “L” level and the PD reset transistor 107 is turned on, the photodiodes 101 of all the pixels are reset. The PD reset pulse φRPDi, the FD reset pulse φRMi, the row transfer pulse φTRi, and the row selection pulse φSEi are output from the vertical scanning circuit 300.

  Subsequently, the FD reset pulse φRM1 in the first row becomes “H” level, and the FD reset transistor 104 in the first row is turned on, so that the charge holding unit 103 in the first row is reset. Then, after the FD reset pulse φRM1 in the first row becomes “L” level and the FD reset transistor 104 in the first row turns off, the row selection pulse φSE1 in the first row becomes “H” level. When the selection transistor 106 is turned on, the reset level of the charge holding unit 103 in the first row is output to the horizontal signal readout circuit 400 via the column processing circuit 350, and the reset signal corresponding to the reset level is output to the horizontal signal. The signals are output in time series from the output terminal 410 of the reading circuit 400 in the order of horizontal arrangement. The output reset signal in the first row is A / D converted by the ADC 500 and held in the frame memory 610. After the reset signal is read, the row selection pulse φSE1 in the first row becomes “L” level, and the selection transistor 106 in the first row is turned off.

  Subsequently, the same operation as the first row is performed for the second and third rows, and the reset signals of all the pixels are read out.

  Subsequently, the PD reset pulse φRPDi of all rows becomes “L” level and the PD reset transistor 107 is turned off, whereby the photodiode 101 starts accumulation. When the desired accumulation time has elapsed, the row transfer pulse φTRi for all rows becomes “H” level, and the transfer transistors 102 for all the pixels are turned on, so that the signal charges accumulated in the photodiodes 101 for all the pixels are retained. Transferred to the unit 103. The period from the start of accumulation of the photodiode 101 to the end of transfer of the signal charge to the charge holding unit 103 is an accumulation period (exposure period indicated by an arrow in FIG. 8). Immediately after the signal charge transfer operation is completed, the row transfer pulse φTRi of all rows becomes “L” level, the transfer transistors 102 of all pixels are turned off, and the PD reset pulse φRPDi of all rows is “H”. The photodiode 101 of all pixels is reset.

  Subsequently, the row selection pulse φSE1 of the first row becomes “H” level, and the optical signal level corresponding to the signal charge is output from the pixels of the first row to the horizontal signal readout circuit 400 via the column processing circuit 350, Optical signals are output in time series from the output terminal 410 of the horizontal signal readout circuit 400 in the order of horizontal arrangement. The output optical signal in the first row is A / D converted by the ADC 500 and input to the subtractor 620. The subtractor 620 calculates the difference between the optical signal of the first row and the reset signal of the charge holding unit 103 of the first row held in the frame memory 610, and is stored in the photodiode 101 during the exposure period. Only the optical signal component corresponding to the received signal charge is extracted. In this operation, the reset noise of the charge holding unit 103 can be removed, so that a high S / N signal can be obtained. After the optical signal is read, the row selection pulse φSE1 of the first row becomes “L” level.

  Subsequently, the same operation as the first row is performed for the second and third rows, the optical signals of all pixels are read out, and the difference from the reset signal is taken to obtain a high S / N optical signal component. Only is taken out. An imaging signal composed of an optical signal component is input to an image processing circuit (not shown) and processed, and a final still image can be obtained. As described above, according to the solid-state imaging device shown in FIG. 7, it is possible to realize a global shutter operation in which the start and end timings of signal accumulation in all rows are the same.

JP 2005-65184 A

  The operation for acquiring one still image is as shown in the timing chart of FIG. On the other hand, when continuous shooting (continuous shooting) is performed, the operation shown in FIG. 8 is repeatedly performed as shown in FIG. 9, and therefore the reset signal and the optical signal must be read for each shooting. In other words, the interval of continuous shooting is more than twice the time required to read out signals from all pixels. In FIG. 9, the first frame and the second frame, the third frame and the fourth frame,..., The seventh frame and the eighth frame signal reading each constitute a single shooting and increase the continuous shooting speed. Is difficult. In order to improve the continuous shooting speed, a method of shortening the readout period of the reset signal using nondestructive readout can be considered. Hereinafter, this method will be described with reference to the timing chart of FIG.

  In FIG. 10, the shooting operation for the first image is the same as that in FIG. 9, but the shooting operation for the second and subsequent images is different from the holding operation in the frame memory 610. The optical signal read in the second frame is input to the subtracter 620 and overwritten and held in the frame memory 610. The subtracter 620 calculates a difference between the optical signal read in the second frame and the reset signal read in the first frame, and outputs the difference as an imaging signal. Thereafter, the FD reset pulse φRM1 and the row selection pulse φSE1 are driven only in the first row, and the reset level reading of the charge holding unit 103 and the overwrite holding operation to the frame memory 610 are performed. Subsequently, the PD reset pulse φRPDi of all rows becomes “L” level, and the photodiode 101 starts accumulation. When a desired accumulation time elapses, the row transfer pulse φTRi for all rows becomes “H” level, and the signal charges accumulated in the photodiodes 101 of all pixels are transferred to the charge holding unit 103.

  Subsequently, in the third frame, an optical signal reading operation, an operation for obtaining a difference between the optical signal and the signal held in the frame memory 610, and an overwrite holding operation on the frame memory 610 are performed. Since the charge holding unit 103 in the first row is reset in the second frame, the optical signal read from the first row in the third frame corresponds to the signal charge accumulated in the photodiode 101 during the second exposure period. Signal. On the other hand, the charge holding units 103 in the second and third rows are not reset in the second frame, and a non-destructive read operation is performed, so the optical signals read from the second and third rows in the third frame are This is the sum of the optical signal read in the second frame and the optical signal corresponding to the signal charge accumulated in the photodiode 101 during the second exposure period.

  The frame memory 610 holds the reset signal of the first row read out in the second frame and the optical signals of the second row and the third row read out in the second frame. Therefore, by taking the difference between the optical signal read out in the third frame and the signal overwritten and held in the frame memory 610, it corresponds to the signal charge accumulated in the photodiode 101 in the second exposure period. An imaging signal can be obtained. In the third frame, the charge holding unit 103 is reset only in the second row, and a reset signal read operation and an overwrite holding operation to the frame memory 610 are performed.

  In the fourth frame, an optical signal read operation, an operation for obtaining the difference between the optical signal and the signal held in the frame memory 610, an optical signal overwrite holding operation in the frame memory 610, and only the third row of the charge holding unit 103 A reset operation, a reset signal read operation, and a reset signal overwrite holding operation to the frame memory 610 are performed.

  Similar operations are repeated after 5 frames. Therefore, in each pixel, the optical signal is read out three times using nondestructive reading after the charge holding unit 103 is reset. In addition, by performing the reset operation of the charge holding unit 103 in different frames for each row, the optical signal readout period and the reset signal readout period of each frame can be made the same, and the reset signal readout period can be reduced. It is possible to improve the copying speed. Here, the case where the number of rows is three is shown, but when the number of pixels is large, the pixel region is divided into a plurality of regions, and the pixels of the divided regions are changed for each frame. A similar effect can be obtained by performing the reset operation.

  However, in the operation shown in FIG. 10, the non-destructive readout is used and the difference between the optical signal read out in the current frame and the optical signal read out in the previous frame is taken. When the signal is saturated in the holding unit 103, the subsequent signals are not valid, and the signal after the difference processing is broken. For example, when a signal is read three times by nondestructive reading, as shown in FIG. 11A, when none of the first to third optical signal outputs is saturated, a signal corresponding to exposure is obtained by differential processing. Can be obtained correctly. On the other hand, as shown in FIG. 11 (b), when the second and third optical signal outputs are saturated, the first optical signal is correct, but the second optical signal output is not saturated. In addition, it is possible that the output will be larger and may not be correct. In addition, the third optical signal is not correct because the output is saturated at the second time.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a solid-state imaging device that can obtain a high-quality image that does not fail.

  The present invention has been made in order to solve the above-described problem. The photoelectric conversion element, the first reset unit that resets the signal charge accumulated in the photoelectric conversion element, and the photoelectric conversion element accumulated. A charge holding unit that holds a signal charge; a transfer unit that transfers the signal charge accumulated in the photoelectric conversion element to the charge holding unit; and a second reset unit that resets the signal charge held in the charge holding unit The pixel unit is arranged in a two-dimensional manner, and the photoelectric conversion elements of all the pixels in a predetermined region are collectively reset, and after the exposure period has elapsed from the reset, the photoelectric conversion element A solid-state imaging device that continuously reads out the optical signal corresponding to the signal charge transferred to the charge holding unit after transferring the accumulated signal charge to the charge holding unit collectively in all pixels In In the unit period that is a period from the start of exposure to the start of the next exposure, the optical signal is read out for each divided region obtained by dividing the pixel of the pixel unit into a plurality of regions, and only a part of the divided regions is included A signal reading control unit that resets the charge holding unit, reads a reset signal from the resetting charge holding unit, and changes a divided region for reading the reset signal for each unit period; and the light A difference processing unit that generates an imaging signal from a signal obtained by taking a difference between the signal and the optical signal or the reset signal read in the previous unit period, and after reading the reset signal for the same divided region, The photoelectric conversion element can be accumulated so that the level corresponds to the number of frames from which the optical signal is read before the reset signal is read. A storage capacitor control unit for controlling an amount, a solid state imaging device characterized in that it comprises a.

  In the solid-state imaging device of the present invention, the storage capacitance control unit causes the signal charge stored in the photoelectric conversion element to overflow through the first reset unit before being transferred to the charge holding unit. It is characterized by that.

  In addition, the solid-state imaging device of the present invention clips the pixel output when the reset signal is read and only the optical signal of the divided area from which the reset signal is read is continuously read in a plurality of the unit periods. In addition, a clip portion that can change the level of the clip for each unit period is further provided.

  According to the present invention, photoelectric conversion elements can be accumulated so that the level is in accordance with the number of frames from which optical signals are read out after the reset signal is read out for the same divided region. Control the capacity. As a result, the signal charge accumulated in the photoelectric conversion element during the exposure period can be prevented from exceeding a predetermined amount, and the signal can be prevented from being saturated even if the reading is performed a plurality of times by nondestructive reading. Become. For this reason, it is possible to obtain a high-quality image that does not fail.

1 is a block diagram illustrating a configuration of a solid-state imaging device according to a first embodiment of the present invention. 3 is a timing chart illustrating an operation of the solid-state imaging device according to the first embodiment of the present invention. FIG. 3 is a reference diagram for explaining a method of controlling the storable capacity of a photodiode in the first embodiment of the present invention. It is a block diagram which shows the structure of the solid-state imaging device by the 2nd Embodiment of this invention. It is a partial circuit diagram which shows the structure of the clip part with which the solid-state imaging device by the 1st Embodiment of this invention is provided. It is a circuit diagram which shows the structure of the pixel which a solid-state imaging device has. It is a block diagram which shows the structure of the conventional solid-state imaging device. It is a timing chart which shows operation | movement of the conventional solid-state imaging device. It is a timing chart which shows operation | movement of the conventional solid-state imaging device. It is a timing chart which shows operation | movement of the solid-state imaging device which shortened the read period of the reset signal. It is a reference figure which shows the level of the optical signal read from a pixel.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows the configuration of the solid-state imaging device according to the present embodiment. The solid-state imaging device shown in FIG. 1 includes a pixel unit 200, a vertical scanning circuit 300, a horizontal signal readout circuit 400, a current source 150, a column processing circuit 350, an ADC 500, a noise suppression circuit 600, and a level control unit 700. The configuration shown in FIG. 1 is obtained by adding a level control unit 700 to the configuration shown in FIG. Other configurations are as described above. The configuration of the pixel 100 is as shown in FIG. In the present embodiment, a divided region obtained by dividing a pixel region into a plurality corresponds to a row, but this is not restrictive.

  The level control unit 700 controls the capacity of signal charges that can be accumulated in the photodiode 101 by controlling the output level of the PD reset pulse ΦRPD. More specifically, the level control unit 700 reads the reset signal for the same row, and then reads the photodiode so that the level is in accordance with the number of frames from which the optical signal is read before the reset signal is read. The capacity of signal charges that can be stored in 101 is controlled. In the present embodiment, for each row, the optical signal is read out three times by nondestructive reading between the readout of the reset signal at the Nth frame and the readout of the reset signal at the N + 3th frame, so that it is stored in the photodiode 101. The number of signal charges to be generated is controlled to be 1/3 or less of the number of saturated charges.

  Next, the operation of the solid-state imaging device shown in FIG. 1 will be described using the timing chart of FIG. The timing chart of FIG. 2 is different from FIG. 10 only in the level of the PD reset pulse ΦRPDi during the exposure period, and a detailed description thereof will be omitted. As described above, in the pixel unit 200, each pulse output from the vertical scanning circuit 300 reads an optical signal for each row in one frame, which is a unit period from the start of exposure to the start of the next exposure, and then partially Control for resetting the charge holding unit 103 and reading the reset signal is performed only for the first row, and control for changing the row for reading the reset signal for each frame is performed. In FIG. 10, the level of the PD reset pulse ΦRPDi during the exposure period is a level at which the PD reset transistor 107 is turned off. The level of the PD reset pulse ΦRPDi during the exposure period in FIG. It is an intermediate level between the level at which 107 is turned on and the level at which it is turned off (hereinafter referred to as intermediate potential).

  As described above, when the level of the PD reset pulse ΦRPD during the exposure period is set to the intermediate potential, the potential under the gate electrode of the PD reset transistor 107 increases as shown in the potential diagram of FIG. For this reason, signal charges exceeding the amount determined by this potential are discharged to the power supply VDD side via the PD reset transistor 107, and the photodiode 101 performs an overflow operation. Therefore, the maximum number of charges accumulated in the photodiode 101 is less than the original number of saturated charges. This maximum number of accumulated charges can be controlled by controlling the level of the PD reset pulse ΦRPD. In the present embodiment, after resetting the charge holding unit 103, the optical signal is read out three times by nondestructive reading until the next time the charge holding unit 103 is reset, so that the maximum charge accumulated in the photodiode 101 is The number may be controlled to be 1/3 or less of the original saturated charge number.

  According to the above operation, the signal charge accumulated in the photodiode 101 during the exposure period of 1 to 3 times is 1/3 or less of the original saturated charge number. Therefore, the first optical signal output is less than 1/3 of the original saturation output, the second optical signal output is less than 2/3 of the original saturation output, and the third optical signal output is less than the original saturation output. It becomes. Therefore, it is possible to obtain a correct signal that does not fail even if the difference between the first optical signal and the reset signal, the second optical signal and the first optical signal, and the third optical signal and the second optical signal is taken. . Therefore, according to the present embodiment, it is possible to obtain a high-quality image that does not fail.

  In the present embodiment, the case where the pixels are arranged in 3 rows and 3 columns has been described in a simple manner. However, the present invention is not limited to this, and can be changed without departing from the purpose. For example, when the number of pixels is large, it is possible to divide the pixel region into a plurality of regions and change the pixels in the divided regions for each frame to perform the reset operation of the charge holding unit 103. In addition, the order of reading signals and the order of resetting the charge holding unit 103 are the first, second, and third lines, but the order is not limited to this. Furthermore, the storage capacity of the photodiode 101 is controlled by controlling the level of the PD reset pulse ΦRPD, but this is not a limitation. For example, the power source of the PD reset transistor 107 is made independent of the pixel power source, and the potential is set. It is also possible to control, and it is also possible to control via the transfer transistor 102 and the FD reset transistor 104.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 4 shows the configuration of the solid-state imaging device according to the present embodiment. The configuration shown in FIG. 4 is obtained by adding a clip unit 800 to the configuration shown in FIG. Other configurations are as described above. In the present embodiment, a divided region obtained by dividing a pixel region into a plurality corresponds to a row, but this is not restrictive.

  As shown in FIG. 5, the clip unit 800 is configured such that a MOS transistor is connected to the vertical signal line 114, and the clip power supply VCL and the control signal ΦCL are input to the MOS transistor so as to clip the signal level of the vertical signal line 114. It has become. The signal level of the vertical signal line 114 is output to the column processing circuit 350 until the signal level of the vertical signal line 114 reaches the level of the clip power supply VCL. When the signal level of the vertical signal line 114 exceeds the level of the clip power supply VCL, the signal level of the vertical signal line 114 is clipped to the level of the clip power supply VCL by the clip unit 800 and this level is output to the column processing circuit 350. The The clip level is controlled for each frame.

  Since the operation of the solid-state imaging device shown in FIG. 4 is the same as the operation shown in FIG. 2 in the first embodiment, detailed description thereof is omitted. In the present embodiment, after the charge holding unit 103 is reset, the optical signal is read out three times by nondestructive reading until the charge holding unit 103 is reset next. The level to be clipped at 800 (hereinafter referred to as clip level) is controlled as follows. That is, the clip level is 1/3 of the original saturation output in the first optical signal readout period, 2/3 of the original saturation output in the second optical signal readout period, and in the third optical signal readout period. Control is performed to achieve the original saturation output.

  According to the above operation, as described in the first embodiment, by setting the level of the PD reset pulse ΦRPD to the intermediate potential, the first optical signal output becomes 1/3 or less of the original saturation output, and the second time The optical signal output is less than 2/3 of the original saturation output, and the third optical signal output is less than the original saturation output. Even if noise is mixed in the charge holding unit 103 due to light leakage or the like and an output of a level higher than the expected level appears, the clip unit 800 causes the pixel output to be below the assumed level. Therefore, it is possible to obtain a correct signal that does not fail even if the difference between the first optical signal and the reset signal, the second optical signal and the first optical signal, and the difference between the third optical signal and the second optical signal is taken. . Therefore, according to the present embodiment, it is possible to obtain a high-quality image that does not fail.

  In the present embodiment, the case where the pixels are arranged in 3 rows and 3 columns has been described in a simple manner. However, the present invention is not limited to this, and can be changed without departing from the purpose. For example, when the number of pixels is large, it is possible to divide the pixel region into a plurality of regions and change the pixels in the divided regions for each frame to perform the reset operation of the charge holding unit 103. In addition, the order of reading signals and the order of resetting the charge holding unit 103 are the first, second, and third lines, but the order is not limited to this. Needless to say, the clip unit 800 is not limited to the configuration shown in FIG. 5 as long as the clip level can be controlled in accordance with the number of times the optical signal is read.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. .

  100 ... Pixel, 101 ... Photodiode (photoelectric conversion element), 102 ... Transfer transistor (transfer part), 103 ... Charge holding part, 104 ... FD reset transistor (second reset part) ), 105... Amplification transistor, 106... Selection transistor, 107... PD reset transistor (first reset unit), 150... Current source, 200. Scanning circuit (signal readout control unit), 350 ... column processing circuit, 400 ... horizontal signal readout circuit, 500 ... ADC, 600 ... noise suppression circuit, 610 ... frame memory, 620 ...・ Subtracter (difference processing unit), 700 ... level control unit (storage capacity control unit), 800 ... clip unit

Claims (3)

A photoelectric conversion element; a first reset unit that resets signal charges accumulated in the photoelectric conversion element; a charge holding unit that retains signal charges accumulated in the photoelectric conversion element; and A pixel unit in which pixels having a transfer unit that transfers the signal charge to the charge holding unit and a second reset unit that resets the signal charge held in the charge holding unit are arranged two-dimensionally ,
The photoelectric conversion elements of all pixels in a predetermined region are collectively reset, and after the exposure period has elapsed since the reset, the signal charges accumulated in the photoelectric conversion elements are collectively stored in the pixels in the charge holding unit. A solid-state imaging device that continuously reads out an optical signal corresponding to the signal charge transferred to the charge holding unit after being transferred to
In a unit period that is a period from the start of exposure to the start of the next exposure, the optical signal is read for each divided region obtained by dividing the pixel of the pixel portion into a plurality of regions, and the charge is applied to only a part of the divided regions. A signal readout control unit that resets a holding unit, reads a reset signal from the charge holding unit that has performed the reset, and performs control to change a divided region from which the reset signal is read for each unit period;
A difference processing unit for generating an imaging signal from a signal obtained by taking a difference between the optical signal and the optical signal or the reset signal read in the immediately preceding unit period;
Capacitance that can be stored in the photoelectric conversion element so that the level is in accordance with the number of frames from which the optical signal is read out after the reset signal is read out for the same divided region. A storage capacity control unit for controlling
A solid-state imaging device.   2. The storage capacitor control unit according to claim 1, wherein the signal charge stored in the photoelectric conversion element is caused to overflow through the first reset unit before being transferred to the charge holding unit. Solid-state imaging device.   After reading out the reset signal, when only the optical signal in the divided area from which the reset signal has been read out is read out continuously in a plurality of the unit periods, the output of the pixel is clipped and the level of the clip is The solid-state imaging device according to claim 1, further comprising a clip portion that is variable for each.

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