JP4973115B2 - Solid-state imaging device, driving method of solid-state imaging device, and imaging device - Google Patents

Solid-state imaging device, driving method of solid-state imaging device, and imaging device Download PDF

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JP4973115B2
JP4973115B2 JP2006280959A JP2006280959A JP4973115B2 JP 4973115 B2 JP4973115 B2 JP 4973115B2 JP 2006280959 A JP2006280959 A JP 2006280959A JP 2006280959 A JP2006280959 A JP 2006280959A JP 4973115 B2 JP4973115 B2 JP 4973115B2
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voltage
transfer gate
control
control voltage
solid
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JP2008099158A (en
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祐輔 大池
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ソニー株式会社
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
    • H04N5/351Control of the SSIS depending on the scene, e.g. brightness or motion in the scene
    • H04N5/355Control of the dynamic range
    • H04N5/35536Control of the dynamic range involving multiple exposures
    • H04N5/35545Control of the dynamic range involving multiple exposures being simultaneously taken
    • H04N5/35554Control of the dynamic range involving multiple exposures being simultaneously taken with different integration times

Description

  The present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an imaging device.

  In recent years, CCD (Charge Coupled Device) image sensors and amplification-type image sensors, known as solid-state imaging devices suitable for applications such as video cameras and digital still cameras, have a high sensitivity due to an increase in the number of pixels and a reduction in image size. The pixel size is becoming finer. On the other hand, in general, solid-state imaging devices such as CCD image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors tend to be used in various environments such as indoors, outdoors, daytime, and nighttime. Accordingly, it is often necessary to perform an electronic shutter operation or the like that adjusts the exposure time by controlling the charge accumulation period in the photoelectric conversion element and optimizes the sensitivity.

  By the way, in a CMOS image sensor, as a method of expanding the dynamic range, a method of adjusting an exposure time by turning an electronic shutter at a high speed, a method of photographing a plurality of frames at a high speed, and a photoelectric conversion of a light receiving unit A method of making the characteristic logarithmic response is known.

  However, for a high-contrast shooting scene in which a bright place and a dark place are mixed, the method of releasing the electronic shutter at high speed does not allow a sufficient exposure time particularly in a dark place, that is, a low-light scene. N deteriorates and the image quality deteriorates. The method of capturing and overlaying multiple frames at high speed can improve the S / N by superimposing images compared to the method of simply releasing the electronic shutter, but the readout noise accumulates as much as multiple readouts. As a result, the S / N deteriorates at low illumination.

  Although a method of expanding the dynamic range by using logarithmic response characteristics is effective, fixed pattern noise due to variations in threshold values of transistors operating in the subthreshold region is particularly noticeable in the low illuminance region. For example, when taking a picture of a person by the window from the room, if the sensitivity is matched to the person, the scenery of the window is saturated white and cannot be reproduced. When the sensitivity is adjusted to the scenery of the window, the person is photographed darkly and the signal level cannot be sufficiently secured. Therefore, the S / N is lowered, and high image quality cannot be obtained even after amplification after photographing.

  That is, in a certain photographing, it is necessary to achieve a high S / N with a long exposure time for a pixel with little incident light on the image sensor, and a wide dynamic range that avoids saturation for a pixel with much incident light.

  Conventionally, a technique described in Non-Patent Document 1 is known as a method of realizing a S / N substantially equivalent to a normal operation in a low-illuminance pixel and expanding a dynamic range in a high-illuminance pixel. Specifically, as shown in FIG. 32, in an amplification type image sensor in which pixels 100 having a photodiode 101, a transfer transistor 102, a reset transistor 103, an amplification transistor 104, and a selection transistor 105 are arranged in a matrix, transfer is performed. When the transistor 102 is turned off, the voltage applied to the control electrode is not at a level at which the voltage is completely turned off as usual, but a level Vtrg that causes excess to overflow to the FD unit 106 if electrons are accumulated more than a certain level. Set to.

  When electrons accumulate in the photodiode 101 and exceed the level Vtrg, leakage starts to the FD portion 106 in the subthreshold region. Since this leak operates in the subthreshold region, the number of electrons remaining in the photodiode 101 becomes a logarithmic response.

  As shown in FIG. 33, after the reset operation in the period T0, accumulation is executed while the voltage Vtrg is applied to the control electrode of the transfer transistor 102. In the state of the period T1 where the number of accumulated electrons is small, all the electrons are held in the photodiode 101. However, when the number of accumulated electrons exceeds the level of Vtrg, the electrons start to leak to the FD portion 106 as in the period T2.

  Since leakage occurs in the subthreshold region, electrons are accumulated with a logarithmic characteristic with respect to the incident light intensity even when accumulation is continued (T3). In the period T4, the electrons overflowing to the FD unit 106 are reset, and all the electrons held in the photodiode 101 are read out by complete transfer. The relationship between the incident light intensity and the number of output electrons at this time is shown in FIG. In the case of incident light having an intensity exceeding the upper limit Qlinear of the linear region set by the voltage Vtrg, the number of output electrons is determined by a logarithmic response.

IEEE International Solid-State Circuits Conference (ISSCC) 2005, pp.354, Feb.2005

  However, in the prior art described in Non-Patent Document 1, it has been reported that a dynamic range of 124 dB has been realized. However, in this report, the saturation level in the linear region where high S / N can be realized is the normal saturation level Qs. Less than half. Although the logarithmic response realizes a very wide dynamic range, it is a logarithmic response circuit that is susceptible to the threshold variation of the transfer transistor 102 and the like, and therefore the threshold variation with respect to the fixed pattern noise of 0.8 mV in the linear region. Even if the cancel operation is executed, a large fixed pattern noise of 5 mV in the logarithmic region remains in the wide dynamic range region.

  Therefore, the present invention enables linear and high signal-to-noise acquisition without reducing the normal saturation level at low illuminance, and is good in the linear region even for incident light above the normal saturation level. An object of the present invention is to provide a solid-state imaging device, a driving method of the solid-state imaging device, and an imaging device capable of expanding a dynamic range while realizing S / N.

In order to achieve the above object, according to the present invention, unit pixels including a light receiving unit that converts an optical signal into a signal charge and a transfer gate that transfers a signal charge photoelectrically converted by the light receiving unit are arranged in a two-dimensional matrix. In the solid-state imaging device having the pixel array unit, the signal charge accumulated in the unit pixel is read out by applying a first voltage to the transfer gate during the first exposure time, and the read signal charge is first read out. Output from the pixel array unit as a video signal, and prior to the output of the first video signal, during the first exposure time period, the first gate is supplied to the transfer gate of the unit pixel that outputs the first video signal . A configuration is adopted in which a plurality of second voltages lower than the first voltage are applied to perform a plurality of read operations .

  In the solid-state imaging device configured as described above, the unit pixel is a destructive readout pixel having a transfer gate. The first video signal is a high-sensitivity video signal based on the first exposure time, and the second video signal is a low-sensitivity video signal based on the second exposure time set within the first exposure time. These first and second video signals are read from the same unit pixel without spatially dividing the pixel array section (pixel array). Since the accumulation operation based on the second exposure time can be set at an arbitrary timing within the first exposure time, the read timing of the second video signal is arbitrary.

  As a result, a high frame rate depending on the shortest exposure time interval is not necessary, and a video signal with a shorter exposure time can be obtained at a frame rate determined by the number of times the video signal is read. Also, the frame period is not divided in time by setting the second exposure time within the first exposure time. Accordingly, since the maximum time as the first exposure time can be ensured as the same as the frame period, it is possible to increase the dynamic range with the second exposure time and to reduce the sensitivity of the first video signal without reducing the sensitivity of the first video signal. N (high image quality) video signals can be acquired.

  According to the present invention, it is possible to obtain a signal with a linear and high S / N without narrowing a normal saturation level at low illuminance, and good in a linear region even for incident light above a normal saturation level. Since the dynamic range can be expanded while realizing S / N, it is possible to acquire high-quality images with high S / N in low-light scenes against changes in external light under various environments. In addition, images with less saturation in high-illuminance scenes can be acquired with high image quality by linear response, and even in high-contrast scenes where low and high illuminance are mixed, high illuminance is maintained while maintaining high S / N in the low-illuminance part. Partial saturation can be avoided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a system configuration diagram showing a configuration example of a solid-state imaging device, for example, a CMOS image sensor according to the first embodiment of the present invention.

  As shown in FIG. 1, the CMOS image sensor 10 according to the present embodiment includes unit pixels (hereinafter, simply referred to as “pixels”) 20 including photoelectric conversion elements that are two-dimensionally arranged in a matrix (matrix). As a peripheral circuit of the pixel array unit 11, a row selection circuit 12, a preceding selection circuit 13, a logic circuit 14, a driver circuit 15, a controller unit 16, a voltage supply circuit 17, and a column circuit are provided. 18 and a horizontal scanning circuit 19.

  In the pixel array unit 11, a vertical signal line 111 is wired for each column with respect to the matrix-like arrangement of the unit pixels 20, and a drive control line such as a transfer control line 112, a reset control line 113, and a selection control are arranged for each row. Line 114 is wired.

(Pixel circuit)
FIG. 2 shows an example of the configuration of the unit pixel 20. The unit pixel 20 according to this circuit example has a pixel configuration having four transistors, for example, a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to a photoelectric conversion element, for example, a photodiode 21, that is, a claim. The destructive readout pixel configuration has a transfer transistor 22 corresponding to the transfer gate in the range of. Here, as these transistors 22 to 25, for example, NMOS transistors are used.

  The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and an FD (floating diffusion) unit 26 that is a charge-voltage converter, and is photoelectrically converted by the photodiode 21 and accumulated in the signal charge (here, , Electrons) is transferred to the FD section 26 by applying a transfer pulse TRG to the gate electrode (control electrode).

  The reset transistor 23 has a drain electrode connected to the pixel power supply VDD and a source electrode connected to the FD unit 26, and a reset pulse RST is applied to the gate electrode prior to transfer of signal charges from the photodiode 21 to the FD unit 26. As a result, the potential of the FD unit 26 is reset to a predetermined potential.

  The amplification transistor 24 has a gate electrode connected to the FD unit 26 and a drain electrode connected to the pixel power supply VDD, and outputs the potential of the FD unit 26 after being reset by the reset transistor 23 as a reset level. The potential of the FD portion 26 after the signal charge is transferred is output as a signal level.

  In the selection transistor 25, for example, the drain electrode is connected to the source electrode of the amplification transistor 24, the source electrode is connected to the vertical signal line 111, and the selection pulse SEL is applied to the gate electrode, so that the pixel 20 is selected. The signal output from the amplification transistor 24 is output to the vertical signal line 111.

  Note that the selection transistor 25 may be configured to be connected between the pixel power supply VDD and the drain electrode of the amplification transistor 24. Further, the pixel circuit is not limited to the four-transistor configuration described above, and the selection transistor 25 is omitted, and the three transistors that also use the amplification transistor 24 as the selection transistor 25 or the amplification transistor 24 between a plurality of unit pixels. It may be a configuration shared with each other.

(Row selection circuit)
The row selection circuit 12 corresponds to the first drive means in the claims, and is constituted by a shift register, an address decoder, or the like. Under the control of the controller unit 16, the transfer pulse TRG, the reset pulse RST, the selection pulse SEL, etc. By appropriately generating the pixel drive pulse, each pixel 20 of the pixel array unit 11 is selected while scanning in the vertical direction (vertical direction) in units of rows for each of the electronic shutter row and the readout row, and the electronic shutter row is selected. Performs an electronic shutter operation for sweeping out the signals of the pixels 20 in the row and performs a readout operation for reading out the signals of the pixels 20 in the row for the readout row.

  Although not shown here, the row selection circuit 12 performs a readout operation for performing a readout operation of reading out the signal of each pixel 20 in the readout row while sequentially scanning the pixels 20 in units of rows, and the readout. An electronic shutter scanning system for performing an electronic shutter operation on the same row (electronic shutter row) is preceded by a time corresponding to the shutter speed before the readout scanning by the scanning system.

  The period from the timing when the unnecessary charge of the photodiode 21 is reset by the electronic shutter operation by the electronic shutter scanning system to the timing when the signal of the pixel 20 is read by the reading operation by the readout scanning system is the signal charge in the pixel 20. Accumulation period (first exposure time). That is, the electronic shutter operation is an operation that resets (sweeps out) signal charges accumulated in the photodiode 21 and newly starts accumulation of signal charges after the reset.

(Pre-selection circuit)
The preceding selection circuit 13 corresponds to the second driving means in the claims, and is constituted by a plurality of row selection circuits, for example, two row selection circuits 13A and 13B, and precedes the readout row to be selectively scanned by the row selection circuit 12. Then, a plurality of rows (two rows in this example) are selectively scanned at equal intervals.

  The row selection circuits 13A and 13B are configured by a shift register, an address decoder, or the like, and appropriately generate a transfer pulse TRG in synchronization with the selection scanning of the row selection circuit 12 under the control of the controller unit 16. Two rows are selectively scanned at equal intervals prior to the readout row that is selectively scanned by the selection circuit 12. In this selective scanning, an operation of transferring the signal charge accumulated in the photodiode 21 to the FD unit 26 is performed based on the transfer pulse TRG. Details thereof will be described later.

(Logic circuit)
The logic circuit 14, under the control of the controller unit 16, receives a transfer pulse TRG, a reset pulse RST, and a reset pulse RST output from the two row selection circuits 13 A and 13 B of the row selection circuit 12 and the preceding selection circuit 13, respectively. The selection pulse SEL is supplied to the transfer control line 112, the reset control line 113, and the selection control line 114 of the pixel array unit 11 through the driver 15, and a signal for selecting the voltage value of the transfer pulse TRG as described later. This is given to the driver circuit 15.

(Driver circuit)
The driver circuit 15 outputs a voltage transfer pulse TRG, a reset pulse RST, and a selection pulse SEL for turning on / off the transistors 22, 23, and 25 of the pixel 20 in synchronization with the selection scanning by the row selection circuit 12. And an intermediate voltage (hereinafter referred to as “intermediate voltage”) for turning on / off the transistors 22, 23, 25 of the pixel 20 in synchronization with the selective scanning by the row selection circuits 13A, 13B. The transfer pulse TRG (described below) is supplied to the pixel 20. In other words, the driver circuit 15 has a function as first to third supply voltage control means in the claims.

  FIG. 3 is a circuit diagram showing an example of the configuration of the driver circuit 15. Here, the configuration of the unit circuit for the transfer pulse TRG of the driver circuit 15 corresponding to a certain row is shown. The driver circuit 15 is configured by arranging the unit circuits for the transfer pulse TRG as many as the number of rows of the pixel array unit 11 together with the unit circuits for the reset pulse RST and the selection pulse SEL.

  As shown in FIG. 3, the driver circuit (unit circuit) 15 according to this example includes three circuit blocks 131 to 133 corresponding to, for example, three voltages Vtrg1, Vtrg2, and Vtrg3 supplied from the voltage supply circuit 17, and 2 The circuit configuration includes an input NOR circuit 134.

  Of these three voltages Vtrg1, Vtrg2, and Vtrg3, the voltages Vtrg1 and Vtrg3 are voltages for turning on / off the transistors 22, 23, and 25 of the pixel 20, and the voltage Vtrg2 is the intermediate voltage described above.

  The driver circuit 15 receives an address signal ADR from the row selection circuit 12 and the row selection circuits 13A and 13B, and receives a timing signal PTRG1 from the logic circuit 14 at a row selection timing under the control of the controller unit 16. A timing signal PTRG2 is given at the timing of applying the voltage.

  The circuit block 131 includes a NAND circuit 1311 having two inputs of an address signal ADR and a timing signal PTRG1 and a P-channel drive transistor 1313, and selects the voltage Vtrg1 and supplies it to the gate electrode of the transfer transistor 22.

  The circuit block 132 includes an AND circuit 1321 that receives the address signal ADR and the timing signal PTRG2 as two inputs and an N-channel drive transistor 1322, and selects a voltage Vtrg2 that is an intermediate voltage and supplies it to the gate electrode of the transfer transistor 22. To do.

  The circuit block 133 includes an OR circuit 1331 having the address signal ADR as one (negative) input and the output signal of the NOR circuit 134 as the other input and an N-channel driving transistor 1332, and selects and transfers the voltage Vtrg3. This is supplied to the gate electrode of the transistor 22.

  That is, the circuit block 133 supplies another voltage, for example, a ground voltage or a voltage lower than the ground voltage (for example, −1.0 V) as a voltage for turning off the transfer transistor 22, by the action of the NOR circuit 134. The circuit blocks 131 and 132 have a circuit configuration that operates exclusively.

(Column circuit)
The column circuit 18 is composed of a set of unit circuits arranged for each pixel column of the pixel array unit 11, for example, with a one-to-one correspondence with the pixel column, and includes the row selection circuit 12 and the row selection circuits 13A and 13B. Predetermined signal processing is performed on signals output from the pixels 20 of the readout row selected by the above through the vertical signal line 111, and the pixel signals after the signal processing are temporarily held.

  The column circuit 18 includes a circuit configuration including a sample and hold circuit that samples and holds a signal output through the vertical signal line 111, and a sample and hold circuit, and performs CDS (Correlated Double Sampling) processing. A circuit having a noise removal circuit for removing fixed pattern noise unique to a pixel such as reset noise and threshold variation of the amplification transistor 24 is used.

  However, the configuration of the column circuit 18 is merely an example, and the present invention is not limited to this. For example, the column circuit 16 may have an A / D (analog / digital) conversion function, and a signal level may be output as a digital signal.

(Horizontal scanning circuit)
The horizontal scanning circuit 19 is configured by a shift register, an address decoder, or the like, and temporarily scans each unit circuit of the column circuit 18 for each pixel column of the pixel array unit 11 in order while temporarily scanning each unit circuit of the column circuit 18. The held pixel signals are sequentially output.

  Next, the operation of the CMOS image sensor 10 according to the present embodiment having the above configuration will be described with reference to the timing chart of FIG.

  In the CMOS image sensor 10 in which the unit pixels 20 having the pixel circuit configuration shown in FIG. 2 are arranged in a matrix, generally, as shown in FIG. 4A, the photodiode 21 and the FD unit 26 are arranged in a period T1. The light is reset to a predetermined potential, and the light received in the period T2 is photoelectrically converted into electrons and accumulated in the photodiode 21. Further, the FD unit 26 is reset in a period T4 in the latter half of the period T2, the potential of the FD unit 26 at this time is read as a reset level, and then electrons accumulated in the photodiode 21 in the period T3 are transferred to the FD unit 26. Then, the potential of the FD unit 26 at this time is read as a signal level in the period T5.

  In contrast to this normal read operation, in the present invention, the gate of the transfer transistor 22 is stored in the accumulation period (first exposure time) in which electrons are accumulated by photoelectric conversion in order to increase the S / N and wide dynamic range. A first control voltage is supplied to the electrode, and a second control voltage having a voltage value different from the first control voltage is supplied once or a plurality of times to supply any one or a plurality of second control voltages. In advance, a third control voltage having the same voltage value as any one or more of the individual second control voltages is supplied one or more times, and the transfer transistor 22 supplies the first control voltage when the first control voltage is supplied. The signal charge transferred to the FD section 26 is read out, and the drive for reading the signal charge transferred to the FD section 26 one or more times by the transfer transistor 22 when the second control voltage is sequentially supplied is performed. It is a sign.

  Here, the first control voltage is a voltage at which the charge accumulated in the photodiode 21 can be completely transferred to the FD unit 26 by the transfer transistor 22. Hereinafter, the first control voltage is described as a complete transfer voltage. The second and third control voltages are the intermediate voltages described above. Hereinafter, the second and third control voltages are described as intermediate voltages. In this example, since the transfer transistor 22 is an NMOS transistor, a voltage value different from the first control voltage means a voltage value lower than the first control voltage. As a matter of course, when the transfer transistor 22 is a PMOS transistor, the voltage value is lower than the first control voltage. Further, regarding the second and third control voltages, the “same voltage value” does not mean only the case where the voltage values are completely the same, but also includes a slight error of about several percent.

  Specifically, as illustrated in FIG. 4B, the photodiode 21 and the FD unit 26 are reset in a period T <b> 10, and light received in the period T <b> 11 is photoelectrically converted into electrons and accumulated in the photodiode 21. Next, the FD unit 26 is reset in a period T12. Here, the potential of the FD unit 26 in the period T12 may be read as the reset level.

  Next, in period T13, an intermediate voltage (third control voltage) Vtrg is supplied to the gate electrode of the transfer transistor 22, and is partially transferred to the FD unit 26 according to the amount of accumulated electrons in the photodiode 21 determined by the incident light intensity. To do. In the period T14, the potential of the FD unit 26 corresponding to the amount of transferred electrons is read as a signal level, and if necessary, noise canceling processing is performed in the column circuit 18, for example, using the reset level read in the period T12. .

  The accumulation operation is continuously executed in the period T15, and the FD unit 26 is reset again in the period T16. Here, the potential of the FD unit 26 in the period T16 may be read as the reset level. Further, an intermediate voltage (third control voltage) Vtrg is supplied to the gate electrode of the transfer transistor 22 in the period T17, and the sum of the electrons not transferred in the period T13 but remaining in the photodiode 21 and accumulated in the period T15. Of this, the portion exceeding the potential of the transfer transistor 22 due to the application of the intermediate voltage is transferred to the FD section 26. You may read as a signal level in period T18.

  In the period T19 to the period T22, an intermediate voltage (second control voltage) Vtrg having the same voltage value as the previous intermediate voltage is applied to the gate electrode of the transfer transistor 22, and the same operation is repeated. Further, the operation from the period T11 to the period T14 is executed once or a plurality of times while changing the supply voltage to the transfer transistor 22. After the exposure in the period T23, the reset operation is performed again in the period T24 to read out the reset level. Next, in the period T25, the transfer transistor 22 is completely turned on to perform the complete transfer to the FD unit 26. Read the signal level.

  Here, FIG. 5 shows an example of the potential in the pixel when the intermediate voltage Vtrg is supplied to the gate electrode of the transfer transistor 22. When the number of electrons accumulated in the photodiode 21 is large and exceeds the potential trg due to application of the intermediate voltage Vtrg, the electrons accumulated in the photodiode 21 are partially transferred to the FD unit 26.

  FIG. 6 is a potential diagram showing an example of potential change when the intermediate voltage Vtrg is supplied a plurality of times when the incident light is weak. When the number of electrons stored in the photodiode 21 is small, the potential trg of the transfer transistor 22 is not exceeded. Therefore, the electrons generated by the photoelectric conversion are held in the photodiode 21 and are transferred to the FD unit 26 at the last complete transfer. It is transferred and read as a signal level.

  On the other hand, as shown in FIG. 7, when the incident light is strong, electrons exceeding the potential trg are transferred to the FD unit 26 and sequentially read out as signal levels. As a result, it is possible to read with complete transfer after a sufficient exposure time without signal deterioration at low illuminance, and finally, by reading out the surplus beyond the potential trg step by step at high illuminance, finally wide dynamic A composite image of the range can be created.

  Note that the operation periods T10 to T26 in FIGS. 6 and 7 correspond to the operation periods T10 to T26 in the timing chart of FIG.

  Here, before describing the operation and effect of driving the supply of the intermediate voltage having the same voltage value to the gate electrode of the transfer transistor 22 a plurality of times, which is a feature of the present invention, different voltages are applied to the gate electrode of the transfer transistor 22. Consider the case of supplying an intermediate value voltage multiple times.

<Effects of applying intermediate voltage multiple times>
First, during the exposure period from when the electronic shutter is turned off to when the transfer transistor 22 of the pixel 20 is turned on and the accumulated charge is read, one or more intermediate voltages are applied to the transfer transistor 22 of the pixel 20 and read. In addition, information on the high illuminance region can be acquired while ensuring a high S / N in the low illuminance region.

  Further, a reset operation is performed in which the transfer is performed a plurality of times using a plurality of intermediate voltages, and the FD unit 26 is reset to a predetermined potential (for example, the power supply potential VDD) without being read once or a plurality of times. By executing the reset operation by the reset means including the row selection circuits 13A and 13B for applying the reset pulse RST to the reset transistor 23, the threshold variation of the transfer transistor 22 of the pixel 20 can be effectively canceled.

Specifically, as shown in FIG. 8, the potential of the transfer transistor 22 when the voltage Vtrg1 is applied to the gate electrode of the transfer transistor 22 in the first transfer is φ trg1 , and the potential of the photodiode 21 before the charge is accumulated. φ pd0 , the number of electrons held in the photodiode 21 is Q PD1 , the number of electrons overflowing the FD portion 26 is Q FD1 , and the potential of the photodiode 21 when the number of electrons Q PD1 is held is φ pd1 . Assuming that the photocurrent generated in the photodiode 21 in proportion to the incident light intensity is Ipd, the exposure time until the first transfer is ΔT, and the capacitance of the photodiode 21 is Cpd, Q PD1 and Q FD1 are expressed by the following equations. expressed.

Q PD1 = Cpd · φ pd1
Q FD1 = Ipd · ΔT-Q FD1
φ pd1 = φ pd0 −φ trg1
φ trg1 = Vtrg1-(Vth + ΔVth)
Here, Vth is a threshold value of the transfer transistor 22, and ΔVth is a threshold value variation of the transfer transistor 22.

Furthermore, in the second transfer in which a different voltage Vtrg2 is applied after exposure for ΔT time and accumulation of photocurrent , the potential of the transfer transistor 22 is similarly φ trg2 , and the number of electrons held in the photodiode 21 is Q PD2, FD unit 26 to the overflowing electron number Q FD2, when the potential of the photodiode 21 and phi pd2 when holding the number of electrons Q PD2, is expressed by the following equation.

Q PD2 = Cpd ・ φ pd2
φ pd2 = φ pd0 −φ trg2
φ trg2 = Vtrg2-(Vth + ΔVth)
Q FD2 = (Q PD1 + Ipd · ΔT)-Q PD2
= Cpd · φ pd1 + Ipd · ΔT-Cpd · φ pd2
= Cpd · (φ pd0trg1 ) + Ipd · ΔT
−Cpd ・ (φ pd0 −φ trg2 )
= Cpd · φ trg1 + Ipd · ΔT-Cpd · φ trg2
= Cpd · {Vtrg1-(Vth + ΔVth)} + Ipd · ΔT
−Cpd · {Vtrg2 − (Vth + ΔVth)}
= Ipd · ΔT-Cpd · (Vtrg2-Vtrg1)

  As described above, after the second transfer, the number of electrons transferred to the FD unit 26 is applied immediately before the incident light intensity, that is, the generated photoelectric flow rate, the voltage Vtrg2 applied to the control electrode of the transfer transistor 22. It is determined by the difference from the applied voltage Vtrg1, and it is possible to reduce the influence of the threshold variation ΔVth of the transfer transistor 22. Furthermore, since the number of electrons transferred through the transfer transistor 22 at each timing has a phase, the number of residual electrons that cannot be transferred within the transfer period due to the number of electrons exceeding the potential also has a phase. From the second time onward, variation due to residual electrons is also reduced.

As is apparent from the above, when a plurality of intermediate voltages Vtrg1 and Vtrg2 are applied to the transfer transistor 22 at different timings during the exposure period, the potentials Φtrg1 and Φtrg2 of the transfer transistor section at that time are the transfer transistor 22 respectively. Threshold variation. Then, the charge corresponding to the threshold variation is thrown away to the FD section 26 by the transfer operation at the potential Φtrg1, and therefore, in the transfer operation at the next potential Φtrg2, the charge accumulated during that time and the difference between the potentials Φtrg1 and Φtrg2 The charge amount Q FD2 determined by the difference in the amount of charge held in the photodiode 21 is transferred to the FD unit 26. Since the potentials Φtrg1 and Φtrg2 have the same threshold variation of the transfer transistor 22, the influence of the intermediate voltages Vtrg1 and Vtrg2 on the transfer charge amount can be canceled without affecting the difference in the retained charge amount.

  Here, when setting a plurality of intermediate voltages Vtrg1 and Vtrg2, the accumulated charge at each timing under the condition that the amount of light reaching the saturation level is incident during the exposure period from the electronic shutter to normal reading is applied to the photodiode. It is conceivable to set a voltage that can be held at 21. Specifically, as shown in FIG. 9, the amount of charge to be held in the photodiode 21 at the timing of applying the intermediate voltage is estimated from the straight line that reaches the saturation charge amount Qs in the exposure time, and the amount of charge is held. A possible applied voltage is determined from the relationship between the applied voltage and the number of electrons held in the light receiving unit as shown in FIG.

<When the voltage value of the intermediate voltage is different>
However, the voltage value of the intermediate voltage (second control voltage) applied during the intermediate read operation is different from the intermediate voltage (third control voltage) applied in advance for suppressing the threshold variation of the transfer transistor 22. There is a concern that the following characteristic variation cannot be sufficiently canceled.

(1) Offset value of the supplied intermediate voltage When two types of intermediate voltages Vtrg1 and Vtrg2 are applied to the transfer transistor 22 at different timings during the exposure period, the transfer amount by the second intermediate voltage is as described above. The charge accumulated during transfer due to the application of each intermediate voltage is determined by the voltage difference between the intermediate voltage Vtrg1 and the intermediate voltage Vtrg2. When the intermediate voltage supplied to the transfer transistor 22 has an offset with respect to the set voltage value, the voltage difference between the two intermediate voltages Vtrg1 and Vtrg2 occurs with the set value, and the image quality in the high illuminance region is generated as noise. May deteriorate.

(2) Offset value of the intermediate voltage in the pixel array When applying the intermediate voltage to the pixel array, the intermediate voltage may have an offset depending on the position in the pixel array due to the parasitic resistance of the wiring to be supplied. Since the voltage values of the plurality of intermediate voltages to be applied are different, this offset value is different for each transfer, and there is a possibility that the image quality in the high illuminance region is degraded as noise.

(3) Variation in the time during which the intermediate voltage is applied to the transfer transistors in the pixel array When supplying the intermediate voltage to the transfer transistor 22 via the drive circuit, the position in the pixel array due to the resistance and capacitance of the wiring and transistor The rise time and fall time are different depending on the type. Since the transfer due to the application of the intermediate voltage converges in the sub-threshold region, the amount of transferred charge may change if the time during which a desired voltage is applied to the transfer transistor 22 is different between pixels, resulting in a high illuminance region as noise. Degrading the image quality.

(4) Transfer residual charge amount in intermediate voltage transfer If the charge amount accumulated in the light receiving section (photodiode 21) immediately before application of the intermediate voltage is different, transfer by application of the intermediate voltage operates in the subthreshold region. When the application time of the intermediate voltage is shorter than the time required for the charge transfer to converge, different transfer residues occur depending on the amount of accumulated charge immediately before the transfer. Thereby, there is a possibility of degrading the image quality in the high illuminance region as noise.

<When the voltage value of the intermediate voltage is the same>
Therefore, in the present embodiment, as shown in FIG. 11, intermediate voltage transfer (intermediate voltage (intermediate voltage)) is performed during the first exposure time Tlow during which an image in a low illuminance region is acquired from the electronic shutter operation to the normal readout operation. Read scanning by the second control voltage (transfer by application) is executed. Furthermore, the row for dummy transfer with the intermediate voltage (third control voltage) having the same voltage value precedes the read operation by the intermediate voltage transfer by the second exposure time Thigh for acquiring the image in the high illuminance region. A selective scan is performed once or multiple times. The time intervals for the plurality of intermediate voltage transfers are all set to the second exposure time Thigh. That is, the intermediate voltage (third control voltage) is applied to the transfer transistor 22 a plurality of times at equal time intervals.

  FIG. 12 shows a driving timing chart of the pixel 20 by applying the intermediate voltage. FIG. 13 shows a potential diagram of a pixel driven by applying an intermediate voltage.

  Here, the pixel circuit has the four-transistor configuration shown in FIG. 2 as an example. However, the pixel circuit is not limited to this, and includes at least a transfer transistor 22 (transfer gate) in addition to the photodiode (light-receiving portion) 21. Any pixel circuit for destructive readout may be used.

  In FIG. 12, timings t1 and t6 before and after each transfer operation by applying an intermediate voltage to the gate electrode of the transfer transistor 22 are defined as t1 to t6. As in vertical scanning 1 (1a, 1b, 1c) to 3 in FIG. 12, row selection scanning is executed by the row selection circuits 12, 13A, and 13B. Then, the charges of the photodiodes 21 are swept out by the vertical scanning 1a by the row selection circuit 12, and accumulation of charges generated by exposure and photoelectric conversion is started.

  Next, as shown in FIG. 12, normal complete transfer to the gate electrode (transfer gate) of the transfer transistor 22 is performed in the vertical scan 2 by the row selection circuit 13A prior to the vertical scan 1b by the row selection circuit 12. Supply an intermediate voltage lower than the required voltage. As described above, a plurality of intermediate voltages to be supplied are supplied from the voltage supply circuit 17 of FIG. 1 to the driver circuit 15, and based on the timing signals PTRG1 and PTRG2 supplied from the logic circuit 14 in response to a signal from the controller unit. Is selected by the driver circuit 15.

  By applying an intermediate voltage to the gate electrode of the transfer transistor 22, the charge Qpd + ΔQ + ΔQr is held and transferred to the FD unit 26 as t = t1 to t2 in FIG. 13, and then the FD unit 26 is reset. Here, ΔQ is a variation in the held charge due to the potential difference ΔV due to a threshold variation of the transfer transistor 22, an offset of the voltage supplied from the voltage supply circuit 17, an offset of the supply voltage depending on the position of the two-dimensional pixel array, and the like. . ΔQr is a residual transfer difference caused by a difference in the initial state before the transfer.

  Further, by supplying the same intermediate voltage to the gate electrode of the transfer transistor 22 in the vertical scanning 3 by the row selection circuit 13A, Qpd + ΔQ is held as t = t3 to t4 in FIG. 13, and the FD unit 26 is reset. Is done. In the vertical scanning 1b by the row selection circuit 12, the signal charge transferred by the intermediate voltage having the same voltage value as that of the vertical scannings 2 and 3 is read by the column circuit 18 through the vertical signal line 11, and the horizontal scanning circuit 19 Output by scanning.

  In this transfer, as shown in t = t5 to t6, Qpd + ΔQ is held in the photodiode 21, and the charge Qi accumulated at the exposure time Thigh shown in FIG. 12 can be read as a signal charge. This result corresponds to the second video signal with a short exposure time (second exposure time Thigh), that is, photographing with low sensitivity, and becomes image information in a high illuminance region.

  Further, the exposure is continued, and a supply voltage different from the supply voltage (intermediate voltage) is applied to the gate electrode of the transfer transistor 22 in the vertical scanning 1c by the row selection circuit 12 as shown in FIG. The transferred charges are completely transferred to the FD unit 26 and read out. This result corresponds to the first video signal with a long exposure time (first exposure time Tlow), that is, photographing with high sensitivity, and image information in a low illuminance region.

  Subsequently, the reason why the above-mentioned points (1) to (4), which are problematic when the voltage value of the intermediate voltage Vtrg is different, can be solved by using the intermediate voltage Vtrg having the same voltage value will be specifically described below. To do.

  First, FIG. 14 shows the principle of canceling “threshold variation of transfer transistors” and “(1) offset value of supplied intermediate voltage” and “(2) offset value of intermediate voltage in pixel array” described above. It explains using.

  These cancellations are realized by intermediate voltage transfer t = t5 to t6 for executing reading and dummy transfer t = t3 to t4 at the same intermediate voltage immediately before that. Let Qo be the charge accumulated in the photodiode 21 at t = t3. In addition, the cancel operation is executed in two operations A and B.

  In the operation A, the held charge amount Qpd determined by the applied intermediate voltage remains in the photodiode (PD) 21 and Qo-Qpd is transferred to the FD unit 26. At t = t5, Qpd + Qi added to the charge Qi accumulated at the exposure time Thigh is accumulated in the photodiode 21, and at t = t6, the charge Qpd remains in the photodiode 21 by transferring at the same intermediate voltage. The charge Qi stored at time Thigh can be read out.

  On the other hand, in the operation B, a potential difference of ΔV is generated as compared with the operation A due to the threshold variation of the transistors and the offset value of the intermediate voltage. In this case, the charge held in the photodiode 21 changes by ΔQ due to the potential difference ΔV at t = t4, and the charge of Qpd + ΔQ remains. Therefore, the transfer charge at this time is Qo− (Qpd + ΔQ).

  Similarly to the operation A, when the accumulated charge increases by Qi at the exposure time Thigh, the accumulated charge at t = t5 is Qpd + ΔQ + Qi. When the transfer is executed at the same intermediate voltage as t = t4 at t = t6, the threshold difference of the transistors, the offset value of the supplied intermediate voltage, and the position in the pixel array are the same. = T4 is the same. Therefore, the retained charge is Qpd + ΔQ, and the transfer charge is Qi that is the charge accumulated during the exposure time Thigh. The charge Qi accumulated at the exposure time Thigh is obtained in both the operation A and the operation B, and the effect of canceling variation and offset can be obtained.

  Next, FIG. 15 shows an operation for canceling “(3) variation in time during which intermediate voltage is applied to transfer transistors in the pixel array” and “(4) variation in transfer residual charge amount in intermediate voltage transfer”. It explains using.

  In charge transfer by applying an intermediate voltage to the gate electrode of the transfer transistor 22, the transfer transistor 22 operates in the subthreshold region. FIG. 16 shows characteristics in which charges accumulated in the photodiode 21 before the start of transfer are transferred with time by applying an intermediate voltage. In the case of Qini0 to Qini3 in which the initial charge accumulated in the photodiode 21 is smaller than the maximum charge amount Qpd that can be held by the applied intermediate voltage, the initial charge is not transferred but continues to be held in the photodiode 21.

  On the other hand, in the case of the charge amounts Qini4 to Qini8 which are larger than the maximum charge amount Qpd, the charge remaining in the photodiode 21 is reduced by the charge transfer and converges with the maximum charge amount Qpd. However, if there is a large difference in the initial state and the transfer time is not sufficient, the intermediate voltage transfer is completed before the convergence to the maximum charge amount Qpd, and a residual difference is generated by ΔQr.

  In the operation A of FIG. 15, the charge Qini is accumulated at t = t1, the accumulation is continued with the retained charge Qpd remaining at t = t2, and the newly accumulated charge Qi is retained at the exposure time Thigh at t = t3. The charged charge Qpd is accumulated in the photodiode 21. In the intermediate voltage transfer at t = t4, Qi is transferred.

  On the other hand, in the operation B having a different initial state, the charge Qini ′ is accumulated at t = t2, and a residual difference is generated by ΔQr in addition to the held charge Qpd at t = t2. At t = t3, the charge Qi newly accumulated at the exposure time Thigh is added thereto, and Qpd + Qi + ΔQr is accumulated. In the transfer by the intermediate voltage at t = t4, not only the accumulation increment Qi but also the residual difference ΔQr is transferred. However, since the residual difference ΔQr is small, the states of the operation A and the operation B at t = t3 are almost equal. , The holding charges Qpd in the operation A and the operation B at t = t4 are also highly correlated and have substantially the same value.

  As a result, immediately before the transfer by the intermediate voltage for reading, both operation A and operation B are stored in the photodiode 21 with Qpd + Qi, which is the sum of the stored charge Qpd and the charge Qi stored at the exposure time Thigh, in the same state. Can be transferred by increment Qi. That is, as shown in FIG. 13, the correlation between the initial state of the intermediate voltage transfer for reading and the initial state of the dummy transfer due to the application of the intermediate voltage immediately before is further increased by the dummy transfer before that Sometimes only the increment Qi at the exposure time Thigh can be transferred.

  As a result, the transfer residual difference ΔQr depending on the initial state of the photodiode 21 in the intermediate voltage transfer can be further reduced, so that the S / N of an image in a particularly high illuminance region can be improved. Further, even if the time during which a desired intermediate voltage is applied in the pixel array varies and the transfer residual difference ΔQr is different, there is a canceling effect for each pixel, and the influence on transfer due to the intermediate voltage for reading is suppressed. be able to. In addition, since it is possible to acquire a plurality of images in the high illuminance region by the intermediate transfer operation, it can be used for blur correction of the moving object, and there is an effect of improving the S / N by adding the images.

<High S / N and wide dynamic range processing>
Here, as an example, the signal obtained by the intermediate transfer by supplying the intermediate voltage multiple times is clipped and added at a preset saturation level as shown in FIG. Get. For example, in FIG. 17, the result of the complete transfer in the normal exposure which is the i-th readout is output at a high S / N to the normal saturation level, and the exposure time is halved in the previous i-1 transfer. In the middle transfer, approximately twice the dynamic range is possible, and in the i-2th transfer, the exposure time is 1/8 and the intermediate transfer is approximately eight times the dynamic range. Clip and add together to get continuous characteristics.

  Such a process of increasing S / N and wide dynamic range by performing clipping and addition is read out a plurality of times, for example, in a signal processing circuit (not shown) provided at the subsequent stage of the CMOS image sensor 10. It is executed by using a frame memory for storing images.

  However, this processing example is only an example, and if an image read out a plurality of times is stored, it can be processed by a personal computer or the like, and a frame memory is mounted on the CMOS image sensor 10. Thus, it is also possible to adopt a configuration in which only the final image is processed by processing on the image sensor 10.

(Operational effects of the first embodiment)
As described above, in the CMOS image sensor 10 according to the first embodiment, since the unit pixel 20 is a destructive readout pixel having the transfer transistor 22 as a transfer gate, a low dark current and a voltage per electron can be obtained. There is an effect of high S / N due to the high conversion efficiency shown and the fact that the reset level can perform a noise canceling operation called interphase double sampling (CDS).

  In addition, in the CMOS image sensor 10 according to the present embodiment, during the first exposure time Tlow, the time interval for driving the transfer transistor 22 to the unit pixel that outputs the first video signal with high sensitivity according to the exposure time Tlow. The signal charges accumulated in proportion to the second exposure time Thigh determined by the above are read, and a sensitivity different from the first video signal, specifically a low-sensitivity second video signal, preferably a plurality of different from the first video signal. By adopting a configuration that outputs from the pixel array unit 11 as a sensitivity video signal, the following operational effects can be obtained.

  That is, as shown in FIG. 18, since the accumulation operation by the second exposure time Thigh (periods B and C in the figure) can be set at an arbitrary timing within the first exposure time Tlow (period D in the figure), The read timing of the second video signal (high luminance signals 1 and 2 in the figure) is arbitrary. As a result, a high frame rate depending on the shortest exposure time interval is not necessary, and a video signal with a shorter exposure time can be obtained at a frame rate determined by the number of times the video signal is read.

  In FIG. 18, Qsat represents the saturation level of the pixel, and Qmid represents the difference between the saturation level Qsat of the pixel and the intermediate voltage holding level. Also, the alternate long and short dash line represents the case of high luminance, the alternate long and two short dashes line represents the case of medium luminance, and the solid line represents the case of low luminance. Then, in the reading of the high luminance signal 1 by the second exposure time B, the signal charge Q (B) accumulated in proportion to the second exposure time B at the middle luminance is read as the second video signal. In reading out the high luminance signal 2 by the two exposure time C, the signal charge Q (C) accumulated in proportion to the second exposure time C at the high luminance and medium luminance is read out as the second video signal. Further, in the readout of the low luminance signal by the first exposure time D, the signal charge Q (D) accumulated in proportion to the first exposure time D when the luminance is low is read as the first video signal.

  Incidentally, when the unit pixel 20 is a non-destructive readout pixel, a video signal can be read from the pixel at an arbitrary timing during the accumulation time, but a video signal having a second exposure time Thigh with a short exposure time is acquired. Needs to read video signals at frame intervals determined by the second exposure time Thigh. That is, a high frame rate for reading out the video signal at the shortest exposure time interval is required.

  In particular, in the CMOS image sensor 10 according to the present embodiment, the FD unit 26 that accumulates the signal charges transferred by the transfer transistor 22 is set to a predetermined potential (the main voltage) before the first control voltage and the second control voltage are supplied. In the example, since the power supply potential VDD) is reset, a video signal having a sensitivity proportional to the exposure time (B, C, D) determined by the time interval for driving the transfer transistor 22 can be obtained. Further, the pixel variation in the video signal does not include the threshold variation of the transfer transistor 22, the parasitic capacitance variation of the photodiode 21, that is, the saturation electron number variation, the intermediate voltage variation, and the like.

  Incidentally, in the case where the FD unit 26 is not reset before the first control voltage and the second control voltage are supplied, as shown in FIG. During the exposure time A, the charge Q (A ′) accumulated in the period A ′ from the timing when the holding amount at the time of supplying the intermediate voltage is exceeded to the transfer is not proportional to the exposure time A. The timing exceeding the holding amount varies depending on the intensity of incident light and the sensitivity of the light receiving element.

  Further, since the charge Q (B) accumulated in the exposure time B is transferred and added to the charge Q (A ′), the video signal becomes Q (A ′) + Q (B), and exposure is performed. Neither time A + B nor exposure time B is proportional. Further, when the light receiving unit is saturated at the previous exposure time (for example, exposure time A with respect to exposure time B, exposure time A and exposure time B with respect to exposure time C), the saturation level Qsat and intermediate Since Qmid, which is the difference from the holding level due to voltage, is included in the video signal, a video signal having a sensitivity proportional to the exposure time cannot be obtained.

  In addition, if the third control voltage (previous dummy intermediate transfer) referred to in the present embodiment is not provided, and the charges due to the individual transfers are individually read out as video signals, the video is displayed at the shortest exposure time interval. Since it is necessary to read out the signal from the pixel array unit 11, it is necessary to read out a video signal having a high frame rate determined by the shortest exposure time (C or the like).

  In the CMOS image sensor 10 according to the present embodiment, outputting a low-sensitivity second video signal from a unit pixel that outputs a high-sensitivity first video signal means that the first and second video signals are converted into a pixel array. This means that the pixel array of the unit 11 is read from the same pixel without being spatially divided. In this way, by adopting a configuration in which the first and second video signals are output from the same pixel without spatially dividing the pixel array, video signals having a plurality of sensitivities (a plurality of exposure times) are obtained from all the pixels. Therefore, the resolution is not deteriorated.

  For example, as shown in FIG. 20, a first exposure time (long exposure time) is set for unit pixels in odd rows, and a high-sensitivity image (first video signal) is output from the odd rows, and even rows are output. When the pixel array is spatially divided such that a second exposure time (short exposure time) is set for the unit pixel and a low-sensitivity image (second video signal) is output from the even-numbered rows. Because the amount of information of high-sensitivity and low-sensitivity images is half the number of pixels, the resolution decreases.

  Further, in the CMOS image sensor 10 according to the present embodiment, as shown in FIG. 21A, the frame period is divided in time by setting the second exposure time Thigh within the first exposure time Tlow. Nor. Therefore, since the maximum time within the first exposure time Tlow can be secured as long as the frame period, the dynamic range is expanded at the second exposure time Thigh without reducing the sensitivity of the first video signal. A high S / N (high image quality) video signal can be acquired.

  Incidentally, in the multiple exposure called so-called multi-sampling, as shown in FIG. 21B, the frame period is divided in time, and a long exposure time (first exposure time) and a short exposure time (second exposure time). ), The first exposure time is always shorter than the frame period, the sensitivity is lowered, and as a result, the image quality is deteriorated.

  Further, in the CMOS image sensor 10 according to the present embodiment, as a more specific drive, when the plurality of first intermediate voltages are sequentially supplied to the gate electrode of the transfer transistor 22 as the second control voltage, the transfer transistor 22 causes the FD section. The threshold value variation of the transfer transistor 22 can be canceled by executing the drive for reading the signal charge transferred to the signal 26 one or more times under the drive of the row selection circuit 12 and the preceding selection circuit 13. This enables linear and high S / N signal acquisition without reducing the normal saturation level at low illuminance, and good S / N in the linear region for incident light above the normal saturation level. The dynamic range can be expanded while realizing

  In particular, any one or more of the first intermediate voltages (second control voltages) or the second intermediate voltage (third control voltage) preceding each of the first intermediate voltages (second control voltages) may be replaced with any one or more individual second voltages. When the first intermediate voltage is set to the same voltage value as one intermediate voltage, specifically, the plurality of first intermediate voltages are set to V1, V2,... (These first intermediate voltages may be the same voltage value or different voltage values). The second intermediate voltage preceding V1 is set to the same voltage value as V1, the second intermediate voltage preceding V2 is set to the same voltage value as V2, and when the voltage values of V1 and V2 are different, the second intermediate voltage is also By using different voltage values, in addition to the threshold variation of the transfer transistor 22, the offset value of the supplied intermediate voltage Vtrg, the offset value of the intermediate voltage Vtrg in the pixel array, and the transfer transistor in the pixel array 22 to intermediate voltage Vt Since it is possible to cancel the variation in the time during which g is applied and the variation in the residual charge amount in the intermediate transfer due to the application of the intermediate voltage Vtrg, the effect of improving the S / N of the image particularly in the high illuminance region There is.

  Note that the time interval for supplying the intermediate voltage of the same voltage value a plurality of times, specifically, the time interval between the vertical scan 2 and the vertical scan 3 and the time interval between the vertical scan 3 and the vertical scan 1b in FIG. However, even if they are not necessarily equal, a corresponding canceling effect can be obtained. However, when the time interval is equal, the offset value of the supplied intermediate voltage Vtrg, the offset value of the intermediate voltage Vtrg in the pixel array, or the intermediate voltage Vtrg is applied to the transfer transistor 22 in the pixel array. There is an effect that the variation in time and the variation in the residual transfer charge amount in the intermediate transfer due to the application of the intermediate voltage Vtrg can be canceled more reliably.

  As described above, it is possible to obtain a high-quality image with a high S / N in a low-light scene in response to changes in external light in various environments such as indoors, outdoors, daytime, and nighttime. Images with less saturation in the scene can be acquired with high image quality by linear response, and even in high-contrast scenes with a mixture of low and high illuminance, saturation of the high illuminance part is maintained while maintaining high S / N in the low illuminance part. It can be avoided.

  In addition, even when high-sensitivity pixels are arranged in a normal pixel array for the purpose of increasing sensitivity, it is not necessary to match the exposure time with the high-sensitivity pixels and degrade the S / N of the normal pixels. A high S / N image of a high sensitivity pixel can be obtained in accordance with the appropriate exposure of the pixel, which is advantageous for the subsequent high image quality processing.

  In addition, since the conventional pixel circuit can be used as it is without increasing the number of constituent elements as the unit circuit 20, the circuit scale of the unit circuit 20 does not increase. The intended purpose can be achieved without causing a decrease in the number of pixels due to an increase in the resolution, and hence a decrease in resolution.

(First modification)
In the above embodiment, the vertical scan preceding the read operation (vertical scan 1b in FIG. 12) is executed twice (vertical scans 2 and 3 in FIG. 12). However, the present invention is not limited to two. As shown in FIG. 22, it is possible to execute three or more times, in this example, four times (vertical scanning 2 to 5). In this case, a row selection circuit may be added, a row selection circuit that has been scanned is used again, or a row selection circuit that can select two or more rows may be used.

  Further, as shown in FIG. 23, in the vertical scanning 2 and the vertical scanning 3 preceding the reading operation (vertical scanning 1b in FIG. 12), the FD unit 26 is reset after reading any or all of the transfer charges. It may be.

(Second modification)
Further, in the above embodiment, the vertical scanning 1b for supplying the first intermediate voltage in FIG. 12 is different from the supply voltage (intermediate voltage) for completely transferring the charges accumulated in the photodiode 21 to the FD unit 26. The vertical scan 1c for supplying the voltage may be shared as in the vertical scan 1b in FIG. The drive timing in this case is shown in FIG.

  In the case of the second modified example, in the same vertical scanning, the reading of the charges transferred by the first intermediate voltage and the reading of all the charges remaining in the photodiode 21 are continuously executed in the same row. . In addition, since the image in the high illuminance area and the image in the low illuminance area are alternately output for each row, a frame memory for one image is not required in the subsequent signal processing.

(Third Modification)
As shown in FIG. 26, when a read operation (vertical scan 1b, 1b ') by applying a plurality of intermediate voltages is executed before a normal read operation (vertical scan 1c) by complete transfer, Prior to the vertical scan of FIG. 26, the same voltage as each supply voltage is supplied by a plurality of vertical scans, and for example, the vertical scans 2, 3, 2 ′, 3 ′ of FIG. 26 may be executed. Is possible.

  At this time, the time interval T0 between the vertical scan 2 and the vertical scan 3 is equal to the time interval T0 between the vertical scan 3 and the vertical scan 1b, and the time interval T1 between the vertical scan 2 'and the vertical scan 3' is equal to the time interval T1. The time interval T1 between the vertical scan 3 'and the vertical scan 1b' is preferably the same time, but the time interval T0 and the time interval T1 may be different times.

  As described above, when the combination of the intermediate voltage transfer + reading and the dummy transfer at the intermediate voltage is executed a plurality of times, the time interval (T0 / T1) is set to be different to acquire an image of the high illuminance region. Since a plurality of exposure times Thigh can be set, a plurality of images in a high illuminance region with different sensitivities can be acquired. As a result, the S / N in the medium illuminance region can be improved.

  That is, changing the time interval when executing the combination of the intermediate voltage transfer + reading and the dummy transfer at the intermediate voltage a plurality of times is equivalent to changing the sensitivity of the obtained image. For example, when the exposure time Thigh for low illuminance acquisition is 1, and the time intervals Thigh_1, Thigh_2, and Thigh_3 of the second control voltage preceding the plurality of first control voltages are 1/10, 1/100, 1/1000, An image having a sensitivity of 1/10, an image having a sensitivity of 1/100, and an image having a sensitivity of 1/1000 are obtained in stages. In general, images with higher sensitivity have a limited dynamic range, but have lower noise and better image quality. can get.

  The voltages supplied to the gate electrode of the transfer transistor 22 in the vertical scans 2, 3, 1b and the vertical scans 2 ′, 3 ′, 1b ′ may be equal or different. May be. However, by supplying intermediate voltages having different voltage values, it is possible to acquire an image in the low illuminance region without impairing the accumulated charge in the low illuminance region. That is, the effect of maintaining the saturation charge amount in the low illuminance region can be obtained.

[Second Embodiment]
FIG. 27 is a system configuration diagram showing a configuration example of a solid-state imaging device according to the second embodiment of the present invention, for example, a CMOS image sensor. In FIG. 27, the same components as those in FIG. Yes.

  The CMOS image sensor 10 according to the first embodiment is compatible with rolling shutter (focal plane shutter) imaging in which each pixel 20 of the pixel array unit 11 is sequentially scanned for each pixel row to reset a signal. The CMOS image sensor 50 according to the present embodiment is compatible with global shutter (electronic shutter for all pixels) imaging that exposes all the pixels 20 of the pixel array unit 11 at the same timing.

  Specifically, the CMOS image sensor 50 according to the present embodiment includes a multiple-row simultaneous selection circuit 51 that simultaneously selects a plurality of rows in place of the preceding selection circuit 13 of FIG. 1 in order to realize global shutter imaging. ing. Further, although not shown, a mechanical shutter (hereinafter abbreviated as “mechanical shutter”) is provided upstream of the CMOS image sensor 50 in order to cope with the global shutter. Other configurations are basically the same as those of the CMOS image sensor 10 according to the first embodiment.

  Next, the operation of the CMOS image sensor 50 according to this embodiment having the above-described configuration will be described with reference to the timing chart of FIG.

  During a period in which the mechanical shutter is open, a plurality of rows are simultaneously selected by the plurality of rows simultaneous selection circuit 51 and the charge accumulated in the photodiode 21 is swept out. Prior to the timing of closing the mechanical shutter, an intermediate voltage having the same voltage value is applied to the gate electrodes of the transfer transistors 22 of the plurality of rows simultaneously selected by the multi-row simultaneous selection circuit 51 once or a plurality of times (at the same time interval T0). In the example, it is supplied twice).

  After the mechanical shutter is closed, an intermediate voltage having the same voltage value as the previous intermediate voltage is supplied to the gate electrode of the transfer transistor 22 in the vertical scanning 1b by the vertical scanning circuit 12, and the transfer transistor 22 causes the photodiode 21 to the FD section 20 to be supplied. Read the charge transferred to. Further, in the vertical scanning 1c by the vertical scanning circuit 12, the accumulated charge in the photodiode 21 is completely transferred to the FD unit 26, and the transferred charge is read out.

  With the above-described driving, in the CMOS image sensor 50 corresponding to the global shutter, as in the case of the CMOS image sensor 10 corresponding to the rolling shutter, an intermediate voltage is supplied to the gate electrode of the transfer transistor 22 as a control voltage a plurality of times. The threshold value variation of the transfer transistor 22 can be canceled by executing the drive for reading the signal charge transferred by the transfer transistor 22 twice or more under the drive of the row selection circuit 12 and the preceding selection circuit 13. Incidentally, in the global shutter, an artifact caused by a rolling shutter (charge sweeping out by vertical scanning) does not occur.

  In particular, by setting the intermediate voltage supplied to the gate electrode of the transfer transistor 22 a plurality of times to the same voltage value, the offset value of the supplied intermediate voltage, the offset value of the intermediate voltage in the pixel array, The variation in time during which the intermediate voltage is applied to the transfer transistors and the variation in the residual transfer charge amount in the intermediate transfer due to the intermediate voltage application can also be canceled. This enables linear and high S / N signal acquisition without reducing the normal saturation level at low illuminance, and good S / N in the linear region for incident light above the normal saturation level. The dynamic range can be expanded while realizing

[Third Embodiment]
FIG. 29 is a system configuration diagram showing a configuration example of a solid-state imaging device according to the third embodiment of the present invention, for example, a CMOS image sensor. In FIG. 29, the same parts as those in FIG. 1 and FIG. It shows.

  As shown in FIG. 29, the CMOS image sensor 60 according to the present embodiment includes the preceding selection circuit 13 shown in FIG. 1 and the multiple row simultaneous selection shown in FIG. 27 in addition to the row selection circuit 12 that performs normal row selection. The circuit 51 is provided. Other configurations are basically the same as those of the CMOS image sensor 10 according to the first embodiment.

  In this way, by adopting a configuration having both the preceding selection circuit 13 and the multiple-row simultaneous selection circuit 51, it becomes possible to switch between the driving corresponding to the focal plane shutter and the driving corresponding to the global shutter, and to execute them. Even in this case, it is possible to obtain a signal with linear and high S / N without reducing the normal saturation level at low illuminance, and good S / N in the linear region for incident light above the normal saturation level. The dynamic range can be expanded while realizing N.

[Application to CCD image sensor]
In the first to third embodiments (including modifications) described above, the case where the present invention is applied to a CMOS image sensor has been described as an example. However, the present invention is not limited to a CMOS image sensor, but an amplification type solid-state imaging device. In general, since the invention relates to a portion for reading signal charges from a photoelectric conversion element, the invention can be similarly applied to a charge transfer type solid-state imaging device represented by a CCD image sensor.

  FIG. 30 shows an example when applied to a CCD image sensor. In the CCD image sensor, photoelectric conversion is performed by a photodiode (light receiving unit) 71 which is a photoelectric conversion element, and signal charges accumulated therein are transferred to a vertical CCD (vertical transfer unit) 73 by a transfer gate (read gate) 72. The data is read out by the vertical transfer by the vertical CCD 73. In this CCD image sensor, the amount of electrons transferred to the vertical CCD 73 can be controlled by applying the above-described intermediate voltage Vtrg to the transfer gate 72 as a control voltage.

  When the incident light is weak (A), since the amount of photoelectrically converted electrons is small, even if the intermediate voltage Vtrg is applied to the transfer gate 72, the accumulated electrons of the photodiode 71 have a potential below the transfer gate 72. It is not exceeded and is held in the photodiode 71. On the other hand, when the incident light is strong (B), since the amount of photoelectrically converted electrons is large, the intermediate voltage Vtrg is applied to the transfer gate 72, so that the accumulated electrons of the photodiode 71 are below the transfer gate 72. It is partially transferred to the vertical CCD 73 beyond the potential.

  Then, by applying the intermediate voltage Vtrg at the same control timing as in the case of the CMOS image sensor, as in the case of the CMOS image sensor, the signal charge at the low illuminance is maintained and the transfer gate 72 is supplied to the transfer gate 72 at the high illuminance. Signal acquisition can be performed by intermediate transfer by application of the intermediate voltage Vtrg.

[Imaging device]
The CMOS image sensors 10, 50, 60 according to the first to third embodiments (including modifications) described above are used as an imaging device (image input device) in an imaging apparatus such as a digital still camera or a video camera. Is preferred.

  Here, the imaging device includes a solid-state imaging device as an imaging device, an optical system that forms image light of a subject on an imaging surface (light-receiving surface) of the solid-state imaging device, and a signal processing circuit of the solid-state imaging device. A camera module (for example, used by being mounted on an electronic device such as a mobile phone) and a camera system such as a digital still camera or a video camera equipped with the camera module.

  FIG. 31 is a block diagram showing an example of the configuration of the imaging apparatus according to the present invention. As shown in FIG. 31, the imaging apparatus according to the present invention includes an optical system including a lens 81, an imaging device (imaging unit) 82, a camera signal processing circuit 83, and the like.

  The lens 81 forms image light from the subject on the imaging surface of the imaging device 82. The imaging device 82 outputs an image signal obtained by converting the image light imaged on the imaging surface by the lens 81 into an electrical signal for each pixel. As the imaging device 82, the CMOS image sensors 10, 50, 60 according to the first to third embodiments (including modifications) described above are used. The camera signal processing unit 83 performs various signal processes on the image signal output from the imaging device 82.

  As described above, in an imaging apparatus such as a video camera, an electronic still camera, and a camera module for a mobile device such as a mobile phone, the CMOS image sensor 10 according to the first to third embodiments described above as the imaging device 82, By using 50, 60, the CMOS image sensor 10, 50, 60 can acquire a linear and high S / N signal without narrowing the normal saturation level at low illuminance, and more than the normal saturation level. Since the dynamic range can be expanded while realizing good S / N in the linear region even with respect to the incident light, an advantage that the image quality of the captured image can be further improved can be obtained.

1 is a system configuration diagram illustrating a configuration example of a CMOS image sensor according to a first embodiment of the present invention. It is a circuit diagram which shows an example of a structure of a unit pixel. It is a circuit diagram which shows an example of a structure of a driver circuit. It is a timing diagram for explaining each operation in the case of normal reading (A) and the case of achieving a high S / N and wide dynamic range (B). It is a potential diagram showing an example of a potential in a pixel when a plurality of voltages are selectively supplied to a control electrode of a transfer transistor. It is a potential diagram showing an example of potential change when incident light is weak. It is a potential diagram showing an example of potential change when incident light is weak. It is explanatory drawing of the reason for which threshold variation is canceled by the transfer after the 2nd time. It is a figure which shows the relationship between exposure time Ts and the light-receiving part holding | maintenance electron count Qs. It is a figure which shows the relationship between some intermediate voltage (supply voltage) and the light-receiving part holding | maintenance electron count Qs. It is a timing diagram which shows the concept of the drive which concerns on 1st Embodiment. It is a drive timing diagram of a pixel by application of intermediate voltage. It is a potential diagram of a pixel driven by applying an intermediate voltage. It is operation | movement explanatory drawing (the 1) of dispersion | variation cancellation operation | movement. It is operation | movement explanatory drawing (the 2) of dispersion | variation cancellation operation | movement. It is a figure which shows the characteristic by which the electric charge accumulate | stored in the light-receiving part before the transfer start is transferred with time by application of an intermediate voltage. It is explanatory drawing of high S / N and wide dynamic range. It is a figure where it uses for description of the effect which concerns on 1st Embodiment. It is a figure where it uses for description of operation | movement when not taking the structure which resets an FD part before supply of a 1st control voltage and supply of a 2nd control voltage. It is a figure where it uses for description which divides | segments a pixel array spatially. It is a figure with which it uses for description of operation | movement of the case where the exposure period is not divided | segmented (A) and the case where it divides | segments (B). FIG. 6 is a timing diagram (part 1) illustrating a concept of driving according to a first modification of the first embodiment. FIG. 9 is a timing diagram (part 2) illustrating the concept of driving according to a first modification of the first embodiment. FIG. 10 is a timing diagram (part 1) illustrating a concept of driving according to a second modification of the first embodiment. FIG. 10 is a timing diagram (part 2) illustrating a concept of driving according to a second modification of the first embodiment. FIG. 10 is a timing diagram illustrating a concept of driving according to a third modification of the first embodiment. It is a system block diagram which shows the structural example of the CMOS image sensor which concerns on 2nd Embodiment of this invention. It is a timing diagram which shows the concept of the drive which concerns on 2nd Embodiment. It is a system block diagram which shows the structural example of the CMOS image sensor which concerns on 3rd Embodiment of this invention. It is a potential diagram which shows the example at the time of applying to a CCD image sensor. It is a block diagram which shows an example of a structure of the imaging device which concerns on this invention. It is a circuit diagram which shows an example of the circuit structure of a pixel. FIG. 10 is a potential diagram in the prior art described in Non-Patent Document 1. It is a figure which shows the relationship between the incident light intensity in the prior art of a nonpatent literature 1, and the number of output electrons.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,50,60 * CMOS image sensor, 11 ... Pixel array part, 12, 13A, 13B ... Row selection circuit, 13 ... Predecessor selection circuit, 14 ... Logic circuit, 15 ... Driver circuit, 16 ... Controller unit, 17 ... Voltage Supply circuit, 18 ... column circuit, 19 ... horizontal scanning circuit, 20 ... unit pixel, 21 ... photodiode, 22 ... transfer transistor, 23 ... reset transistor, 24 ... amplification transistor, 25 ... selection transistor, 26 ... FD (floating diffusion) ) Part, 51... Multiple row simultaneous selection circuit, 81... Photodiode, 82... Transfer gate, 83.

Claims (20)

  1. A pixel array unit in which unit pixels including a light receiving unit that converts an optical signal into a signal charge and a transfer gate that transfers a signal charge photoelectrically converted by the light receiving unit are two-dimensionally arranged in a matrix;
    The signal charge accumulated in the unit pixel during the first exposure time is read by applying a first voltage to the transfer gate, and the read signal charge is output from the pixel array unit as a first video signal . Prior to outputting one video signal, a plurality of second voltages lower than the first voltage are applied to the transfer gates of the unit pixels that output the first video signal during the first exposure time period. Driving means for performing a plurality of read operations ;
    A solid-state imaging device.
  2. A solid-state imaging device having a pixel array unit in which unit pixels including a light receiving unit that converts an optical signal into a signal charge and a transfer gate that transfers a signal charge photoelectrically converted by the light receiving unit are two-dimensionally arranged in a matrix A driving method comprising:
    The signal charge accumulated in the unit pixel during the first exposure time is read by applying a first voltage to the transfer gate, and the read signal charge is output from the pixel array unit as a first video signal . Prior to outputting one video signal, a plurality of second voltages lower than the first voltage are applied to the transfer gates of the unit pixels that output the first video signal during the first exposure time period. Perform multiple read operations ,
    A driving method of a solid-state imaging device.
  3. During the period of the first exposure time, signal charges accumulated in proportion to a plurality of exposure times determined by a time interval for driving the transfer gate to the unit pixel that outputs the first video signal are read out and the first pixel is output. The readout operation is performed a plurality of times so that a plurality of video signals having different sensitivities from the video signal can be sequentially output from the pixel array unit.
    The method for driving a solid-state imaging device according to claim 2.
  4. A solid-state imaging device in which unit pixels including a light receiving unit that converts an optical signal into a signal charge and a transfer gate that transfers a signal charge photoelectrically converted by the light receiving unit are two-dimensionally arranged in a matrix;
    An optical system for guiding light from a subject onto the imaging surface of the solid-state imaging device ;
    Comprising
    The solid-state imaging device
    A pixel array unit in which the unit pixels are two-dimensionally arranged in a matrix;
    The signal charge accumulated in the unit pixel during the first exposure time is read by applying a first voltage to the transfer gate, and the read signal charge is output from the pixel array unit as a first video signal . Prior to outputting one video signal, a plurality of second voltages lower than the first voltage are applied to the transfer gates of the unit pixels that output the first video signal during the first exposure time period. Driving means for performing a plurality of read operations ;
    An imaging apparatus comprising:
  5. A pixel array unit in which unit pixels including a photoelectric conversion element that converts an optical signal into a signal charge and a transfer gate that transfers a signal charge photoelectrically converted by the photoelectric conversion element are two-dimensionally arranged in a matrix;
    First supply voltage control means for supplying a first control voltage to the control electrode of the transfer gate;
    Second supply voltage control means for sequentially supplying one or a plurality of second control voltages having a voltage value different from the first control voltage to the control electrode of the transfer gate;
    Prior to the supply of the second control voltage, third supply voltage control means for supplying a third control voltage having the same voltage value as the one or more individual second control voltages a plurality of times,
    First driving means for reading a signal charge transferred by the transfer gate when the first control voltage is supplied;
    Second driving means for reading out signal charges transferred by the transfer gate when the second control voltage is sequentially supplied;
    A solid-state imaging device.
  6. The second control voltage is a voltage capable of transferring the accumulated charge exceeding the retained amount by the transfer gate while retaining a part of the charge accumulated in the photoelectric conversion element.
    The solid-state imaging device according to claim 5.
  7. Reset means for resetting a floating diffusion for accumulating the charges transferred by the transfer gate to a predetermined potential before the supply of the first control voltage and the supply of the second control voltage;
    The solid-state imaging device according to claim 5.
  8. The third supply voltage control means supplies the third control voltage a plurality of times at equal time intervals in each of the plurality of supplies when the third control voltage precedes the plurality of supplies of the second control voltage. ,
    The solid-state imaging device according to claim 5.
  9. The third supply voltage control means supplies the third control voltage at different time intervals between the plurality of supplies.
    The solid-state imaging device according to claim 8.
  10. The second supply voltage control means supplies the second control voltage having a voltage value different between the plurality of supplies.
    The solid-state imaging device according to claim 5.
  11. The unit pixel includes an amplification transistor that amplifies and outputs a signal charge transferred from the photoelectric conversion element by the transfer gate as a signal voltage,
    Each of the first driving means and the second driving means reads the signal charge transferred to the amplification transistor by the transfer gate through the amplification transistor.
    The solid-state imaging device according to claim 5.
  12. A charge transfer unit that transfers signal charges transferred from the photoelectric conversion element by the transfer gate;
    Each of the first driving unit and the second driving unit reads out the signal charge transferred to the charge transfer unit by the transfer gate via the charge transfer unit.
    The solid-state imaging device according to claim 5.
  13. Each of the first driving means and the second driving means is
    Means for reading out signal charges transferred by the transfer gate, sequentially selecting one or more rows in the two-dimensional array of unit pixels, and supplying the first to third control voltages to the transfer gate;
    6. The means for selecting one or a plurality of rows and supplying the first to third control voltages to the transfer gate a plurality of times prior to the selected row by the sequential scanning. Solid-state imaging device.
  14. A solid-state imaging device driving method in which unit pixels including a photoelectric conversion element that converts an optical signal into a signal charge and a transfer gate that transfers a signal charge photoelectrically converted by the photoelectric conversion element are two-dimensionally arranged in a matrix. There,
    Supplying a first control voltage to the control electrode of the transfer gate and supplying a second control voltage having a voltage value different from the first control voltage once or a plurality of times;
    Prior to the supply of the second control voltage, a third control voltage having the same voltage value as the one or more individual second control voltages is supplied a plurality of times,
    Read the signal charge transferred by the transfer gate when the first control voltage is supplied;
    Reading out signal charges transferred by the transfer gate when the second control voltage is sequentially supplied;
    A driving method of a solid-state imaging device.
  15. The second control voltage is a voltage capable of transferring the accumulated charge exceeding the retained amount by the transfer gate while retaining a part of the charge accumulated in the photoelectric conversion element.
    The method for driving a solid-state imaging device according to claim 14.
  16. Before the supply of the first control voltage and the supply of the second control voltage, the floating diffusion for accumulating the charges transferred by the transfer gate is reset to a predetermined potential;
    The method for driving a solid-state imaging device according to claim 14.
  17. Supplying the third control voltage a plurality of times at equal time intervals in each of the plurality of supplies when the third control voltage precedes the plurality of supplies of the second control voltage;
    The method for driving a solid-state imaging device according to claim 14.
  18. Supplying the second control voltage with a different voltage value between the plurality of supplies;
    The method for driving a solid-state imaging device according to claim 14.
  19. A solid-state imaging device in which unit pixels including a photoelectric conversion element that converts an optical signal into a signal charge and a transfer gate that transfers a signal charge photoelectrically converted by the photoelectric conversion element are two-dimensionally arranged in a matrix;
    An optical system for guiding light from a subject onto the imaging surface of the solid-state imaging device,
    The solid-state imaging device
    First supply voltage control means for supplying a first control voltage to the control electrode of the transfer gate;
    Second supply voltage control means for sequentially supplying one or a plurality of second control voltages having a voltage value different from the first control voltage to the control electrode of the transfer gate;
    Prior to the supply of the second control voltage, third supply voltage control means for supplying a third control voltage having the same voltage value as the one or more individual second control voltages a plurality of times,
    First driving means for reading a signal charge transferred by the transfer gate when the first control voltage is supplied;
    Second driving means for reading out signal charges transferred by the transfer gate when the second control voltage is sequentially supplied;
    An imaging apparatus comprising:
  20. A pixel array unit in which unit pixels including a photoelectric conversion element that converts an optical signal into a signal charge and a transfer gate that transfers a signal charge photoelectrically converted by the photoelectric conversion element are two-dimensionally arranged in a matrix;
    First supply voltage control means for supplying a first control voltage to the control electrode of the transfer gate;
    Second supply voltage control means for sequentially supplying a plurality of second control voltages having voltage values different from the first control voltage to the control electrode of the transfer gate;
    Prior to the supply of the second control voltage, third supply voltage control means for supplying a third control voltage having the same voltage value as the second control voltage one or more times;
    First driving means for reading a signal charge transferred by the transfer gate when the first control voltage is supplied;
    Second driving means for reading out signal charges transferred by the transfer gate when the second control voltage is sequentially supplied;
    A solid-state imaging device.
JP2006280959A 2006-10-16 2006-10-16 Solid-state imaging device, driving method of solid-state imaging device, and imaging device Expired - Fee Related JP4973115B2 (en)

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Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7057256B2 (en) 2001-05-25 2006-06-06 President & Fellows Of Harvard College Silicon-based visible and near-infrared optoelectric devices
US7442629B2 (en) 2004-09-24 2008-10-28 President & Fellows Of Harvard College Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate
JP4905187B2 (en) * 2007-03-09 2012-03-28 ソニー株式会社 Image processing apparatus, imaging apparatus, image processing method, and computer program
JP4325703B2 (en) * 2007-05-24 2009-09-02 ソニー株式会社 Solid-state imaging device, signal processing device and signal processing method for solid-state imaging device, and imaging device
JP5213632B2 (en) 2008-10-09 2013-06-19 キヤノン株式会社 Imaging device
JP5219724B2 (en) 2008-10-09 2013-06-26 キヤノン株式会社 Solid-state imaging device
JP5212022B2 (en) * 2008-10-30 2013-06-19 ソニー株式会社 Solid-state imaging device, imaging device, pixel driving voltage optimization device, and pixel driving voltage optimization method
US8772727B2 (en) * 2008-11-24 2014-07-08 Trixell X-ray detector
JP2010279016A (en) 2009-04-30 2010-12-09 Sony Corp Solid-state imaging device, driving method thereof, and imaging apparatus
JP5661260B2 (en) 2009-07-16 2015-01-28 キヤノン株式会社 Solid-state imaging device and driving method thereof
US9673243B2 (en) 2009-09-17 2017-06-06 Sionyx, Llc Photosensitive imaging devices and associated methods
JP5458865B2 (en) 2009-09-18 2014-04-02 ソニー株式会社 Image processing apparatus, imaging apparatus, image processing method, and program
JP5589446B2 (en) 2009-09-18 2014-09-17 ソニー株式会社 Image processing apparatus, imaging apparatus, image processing method, and program
DE102009053281A1 (en) 2009-11-13 2011-06-16 Arnold & Richter Cine Technik Gmbh & Co. Betriebs Kg Image sensor
JP5428792B2 (en) * 2009-11-17 2014-02-26 ソニー株式会社 Solid-state imaging device, driving method thereof, camera system, and program
US8692198B2 (en) 2010-04-21 2014-04-08 Sionyx, Inc. Photosensitive imaging devices and associated methods
EP2583312A2 (en) 2010-06-18 2013-04-24 Sionyx, Inc. High speed photosensitive devices and associated methods
JP5617445B2 (en) 2010-08-31 2014-11-05 ソニー株式会社 Imaging apparatus, signal processing method, and program
JP5569298B2 (en) * 2010-09-28 2014-08-13 ソニー株式会社 Image processing apparatus, image processing method, and program
JP2012105225A (en) 2010-11-12 2012-05-31 Sony Corp Image processing system, imaging apparatus, image processing method and program
JP2012195734A (en) 2011-03-16 2012-10-11 Sony Corp Solid state imaging apparatus, imaging apparatus, electronic apparatus, and solid state imaging apparatus driving method
JP2012235332A (en) 2011-05-02 2012-11-29 Sony Corp Imaging apparatus, imaging apparatus control method and program
JP2012234393A (en) 2011-05-02 2012-11-29 Sony Corp Image processing device, image processing method, and program
JP5333522B2 (en) 2011-06-06 2013-11-06 カシオ計算機株式会社 Movie generation device, movie generation method, and program
US9496308B2 (en) 2011-06-09 2016-11-15 Sionyx, Llc Process module for increasing the response of backside illuminated photosensitive imagers and associated methods
WO2013010127A2 (en) 2011-07-13 2013-01-17 Sionyx, Inc. Biometric imaging devices and associated methods
JP5967915B2 (en) * 2011-12-09 2016-08-10 キヤノン株式会社 Driving method of solid-state imaging device
WO2014127376A2 (en) * 2013-02-15 2014-08-21 Sionyx, Inc. High dynamic range cmos image sensor having anti-blooming properties and associated methods
JP5570628B2 (en) * 2013-02-28 2014-08-13 キヤノン株式会社 Solid-state imaging device
KR20140126144A (en) 2013-04-22 2014-10-30 삼성전자주식회사 Image sensor and computing system having the same
WO2014209421A1 (en) 2013-06-29 2014-12-31 Sionyx, Inc. Shallow trench textured regions and associated methods
TWI464526B (en) * 2013-08-08 2014-12-11 Quanta Comp Inc Method of controlling exposure time of high dynamic range image
CN104811634B (en) * 2013-12-29 2018-07-31 芯视达系统公司 Support the compact row decoder of multiple voltage
US9843750B2 (en) 2014-03-25 2017-12-12 Samsung Electronics Co., Ltd. Methods of calibrating linear-logarithmic image sensors
KR101867345B1 (en) 2017-02-20 2018-06-18 (주)픽셀플러스 Driving method of pixel and CMOS image sensor using the same
JP2018148359A (en) 2017-03-03 2018-09-20 株式会社リコー Solid state image sensor and imaging apparatus

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2568231B2 (en) * 1987-12-04 1996-12-25 株式会社日立製作所 Charge transfer type solid-state image sensor
JPH0250584A (en) * 1988-08-11 1990-02-20 Olympus Optical Co Ltd Dynamic range enlarging system
JPH05260391A (en) * 1992-03-11 1993-10-08 Sony Corp Solid-state image pickup element
JP3657780B2 (en) * 1998-06-30 2005-06-08 株式会社東芝 Imaging device
JP3667220B2 (en) * 1999-10-05 2005-07-06 キヤノン株式会社 Solid-state imaging device, imaging system, and driving method of solid-state imaging device
JP2001244451A (en) * 2000-02-29 2001-09-07 Fuji Film Microdevices Co Ltd Solid-state image pick-up device
JP4135360B2 (en) * 2001-12-25 2008-08-20 ソニー株式会社 Solid-state imaging device
JP4392492B2 (en) * 2003-06-02 2010-01-06 国立大学法人静岡大学 Wide dynamic range image sensor
JP2006086845A (en) * 2004-09-16 2006-03-30 Sony Corp Camera system and method for driving solid-state image sensor
JP4855704B2 (en) * 2005-03-31 2012-01-18 株式会社東芝 Solid-state imaging device
JP4014620B2 (en) * 2006-04-21 2007-11-28 オリンパス株式会社 Imaging device

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