JP3827146B2 - Solid-state imaging device and driving method of solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a driving method of the solid-state imaging device, and more particularly to a solid-state imaging device and a driving method of the solid-state imaging device that aim to expand a dynamic range in light detection.
[0002]
[Prior art]
FIG. 12 is a block diagram showing a conventional solid-state imaging device, FIG. 13 is a circuit diagram showing the periphery of one pixel constituting the solid-state imaging device of FIG. 12, and FIG. 14 is a timing chart showing the operation of the circuit shown in FIG. is there.
The solid-state imaging device 102 shown in FIG. 12 is specifically a CMOS photosensor, and includes a pixel unit 104, a V selection unit 106, an H selection unit 108, a timing generator 110 (TG), and an S formed on a semiconductor substrate. / H · CDS section 112, constant current section 114A, and the like. In the pixel portion 104, a large number of pixels are arranged in a matrix, and an electric signal generated by detecting light from each pixel is sequentially generated by the V selection unit 106 and the H selection unit 108 based on the timing pulse from the timing generator 110. The selected signal is output from the horizontal signal line 116 through the output unit 118.
[0003]
As shown in FIG. 13, the pixel 120 is supplied with a photodiode 122, a floating diffusion unit 124 (FD unit 124) that is a charge-voltage conversion unit that generates a voltage having a magnitude corresponding to the amount of charge, and a transfer pulse. And a transfer gate 126 for connecting the photodiode 122 to the FD unit 124, a reset gate 128 for connecting the FD unit 124 to the power source Vdd when a reset pulse is supplied, and an amplification transistor 130 for outputting the voltage of the FD unit 124. Has been.
[0004]
The photodiode 122 has an anode connected to the ground and a cathode connected to the source of an N-type MOSFET (MOS field effect transistor) constituting the transfer gate 126. The drain of the MOSFET is connected to the FD unit 124, and the transfer pulse 132 is supplied to the gate from the V selection means 106. The reset gate 128 is also composed of an N-type MOSFET, its source is connected to the FD unit 124, its drain is connected to the power supply Vdd, and the gate is supplied with a reset pulse 134 from the V selection means 106.
[0005]
The gate of the N-type MOSFET constituting the amplification transistor 130 is connected to the FD unit 124, and the drain is connected to the power supply Vdd. An address gate 138 made of an N-type MOSFET is interposed between the amplification transistor 130 and the vertical signal line 136, and an address pulse 140 is supplied from the V selection means 106 to the gate. The source of the amplification transistor 130 is connected to the drain of the address gate 138, and the source of the address gate 138 is connected to the vertical signal line 136.
[0006]
The vertical signal line 136 is provided for each column of the pixels 120 arranged in a matrix, and the sources of the address gates 138 of the pixels 120 belonging to the same column are all connected to the corresponding vertical signal line 136. One end of the vertical signal line 136 is connected to a constant current source 114 in a constant current portion 114A arranged outside the pixel portion 104, and a constant current is passed through the vertical signal line 136 by the constant current source 114. The other end of the vertical signal line 136 is connected to the S / H • CDS unit 112 arranged outside the pixel unit 104.
[0007]
The S / H • CDS section 112 is provided with an S / H • CDS circuit 146 for each vertical signal line 136. The first and second sampling pulses 148 and 150 are supplied from the timing generator 110 to each S / H • CDS circuit, and the signal charge generated by the photodiode 122 output from the amplification transistor 130 to the vertical signal line 136 is added. The voltage (photodetection voltage) originally generated by the FD unit 124 and the voltage (offset voltage) of the FD unit 124 at the time of reset are held, and a voltage corresponding to the difference between the two voltages is output. When the offset voltage is held in the S / H • CDS circuit 146, the first and second sampling pulses 148 and 150 are supplied simultaneously, and when the photodetection voltage is held, only the second sampling pulse 150 is supplied. Is done.
[0008]
The output signal of the S / H / CDS circuit 146 for each vertical signal line 136 is sequentially selected by the H selection means 108 that operates based on the timing signal from the timing generator 110, and is output to the horizontal signal line 116, and is output. 118 is output. Specifically, the output unit 118 includes an amplifier circuit, an AGC circuit, an A / D converter, and the like.
[0009]
Next, the operation of the solid-state imaging device 102 configured as described above will be described focusing on the operation of the pixel 120 with reference to FIG.
The V selection unit 106 operates based on the timing pulse from the timing generator 110, selects a row of the pixel unit 104, and outputs an address pulse 140 (high level) at a timing T1 to the pixels 120 belonging to the selected row. . The address pulse 140 is supplied to the address gate 138 in each pixel 120. As a result, the address gate 138 is turned on, and the amplification transistor 130 is connected to the vertical signal line 136.
[0010]
Next, the V selection means 106 outputs a reset pulse 134 at timing T2, whereby the reset gate 128 is turned on, the FD portion 124 is connected to the power supply Vdd, and the charges (electrons) accumulated in the FD portion 124 are stored. Eliminated. Then, the voltage of the reset FD unit 124 is output to the vertical signal line 136 by the amplification transistor 130. Since the amplification transistor 130 forms a source follower circuit together with the constant current source 114 when the address gate 138 is on, the gate voltage, that is, the voltage following the voltage of the FD unit 124 is perpendicular to the amplification transistor 130. The signal is output to the signal line 136 with low impedance.
[0011]
Subsequently, at timing T 3, the timing generator 110 outputs first and second sampling pulses 148 and 150 to each S / H • CDS circuit 146 provided for each vertical signal line 136, and the amplification transistor 130 outputs the vertical signal. The offset voltage output to the line 136 is held.
[0012]
Thereafter, at timing T 4, the V selection unit 106 outputs a transfer pulse 132, turns on the transfer gate 126, and transfers charges (electrons) received and accumulated by the photodiode 122 until timing T 4 to the FD unit 124. The FD unit 124 generates a voltage according to the transferred charge amount, and the amplification transistor 130 outputs the voltage to the vertical signal line 136 with low impedance.
[0013]
The timing generator 110 outputs the second sampling pulse 150 to each S / H • CDS circuit 146 provided for each vertical signal line 136 at the timing T5. At this time, each S / H • CDS circuit 146 holds the voltage output from the amplification transistor 130 to the vertical signal line 136, the previously held offset voltage, and the newly held photodetection voltage. And a voltage having a magnitude corresponding to the amount of light incident on the photodiode 122, from which the offset is removed, is output.
Since the size of the offset is different for each pixel 120, noise due to variations in offset can be removed by removing the offset by the S / H / CDS circuit 146 in this way.
[0014]
The output signal of the S / H / CDS circuit 146 for each vertical signal line 136 is sequentially selected by the H selection means 108 based on the timing pulse from the timing generator 110 and output to the horizontal signal line 116, and the image is output through the output unit 118. Output as a signal.
V selection means 106 At timing T6, the address pulse 140 is returned to the low level. As a result, the address gate 138 is turned off, the amplification transistor 130 is disconnected from the vertical signal line 136, and the operation for the pixels 120 for one row is completed.
[0015]
Thereafter, the V selection unit 106 operates based on the timing pulse from the timing generator 110 and sequentially selects each row of the pixels 120. Then, the operation as described above is performed for each row, and when the V selection unit 106 selects all rows, an image signal for one image generated by all the pixels 120 is output.
[0016]
[Problems to be solved by the invention]
However, in such a solid-state imaging device 102, only the amount of light in the range until the charge generated by the photodiode 122 overflows, that is, the range up to the saturation level of the photodiode 122, can be detected. Therefore, for example, when the aperture or shutter speed is adjusted to the dark part of the subject, the photodiode 122 is saturated in the bright part of the subject, so that the entire image is taken, for example, white, and an image is obtained. I couldn't.
[0017]
In order to solve this problem, Japanese Patent Application Laid-Open No. 11-313257 discloses a solid-state imaging device whose dynamic range is expanded by outputting a signal corresponding to the logarithm of the incident light quantity. However, since this solid-state imaging device uses a capacitor, it takes time to charge and discharge, and there is a drawback that an afterimage is generated. Also, since the embedded photodiode (for example, a P + layer is formed between the insulating film on the surface of the photodiode and the photodiode) having a merit that noise is structurally low cannot be used, the image quality is inferior. There is a problem. And since there are many components of a pixel circuit, size reduction is difficult.
[0018]
Also, the dynamic range is expanded by changing the shutter speed, and hence the charge accumulation time in the photodiode 122, and taking a short time when the photodiode 122 does not saturate and a sufficiently long time, and combining the captured images. Although the method of doing is also known, since this method requires a line memory and a frame memory, the apparatus becomes large and the cost becomes high. Since two signals with different exposure periods are combined, it is difficult to apply to a moving subject. Furthermore, there is a known technology that eliminates the need for memory by changing the charge accumulation time between adjacent rows of the pixel portion. However, this technology requires arithmetic processing between adjacent rows of pixels, which increases the size of the device. In addition, the configuration becomes complicated. Furthermore, since one signal is generated by two pixels, the resolution is degraded.
[0019]
The present invention has been made to solve such problems, and an object thereof is to provide a solid-state imaging device having a wide dynamic range, a small size, a low cost, and a high performance.
[0020]
[Means for Solving the Problems]
Up To achieve the purpose, A solid-state imaging device according to the present invention includes: A plurality of pixels arranged in a matrix on a semiconductor substrate, a signal line provided for each column of the pixels, and a first timing control means; A second timing control means, a third timing control means, a first calculation means provided for each of the signal lines, and a second calculation means provided for each of the signal lines; The pixel receives light and generates a signal charge; and Accumulated Charge voltage conversion means for generating a voltage corresponding to the amount of signal charge, and the photodiode generates Faith A transfer means for transferring a signal charge to the charge voltage conversion means, and a charge voltage conversion means Power A buffer means for outputting a pressure to the corresponding signal line; and a reset means for eliminating the charge accumulated in the charge-voltage conversion means and resetting the charge-voltage conversion means, and the excess generated by the photodiode Faith The signal charge moves to the charge voltage conversion means through the transfer means regardless of the transfer operation of the transfer means. Like The first timing control means includes: By supplying control pulses, (a) Sequentially selecting rows of the pixels; (B) Selected row of For each pixel Leave Causing the reset means to reset the charge voltage conversion means. The , After the third voltage generated by the charge-voltage converter immediately after the reset is taken into the first arithmetic means via the buffer means and the signal line, The photodiode is generated in the transfer means. Faith The charge is transferred to the charge voltage conversion means. The , The first voltage generated by the charge voltage conversion means by the signal charge is used as the buffer means. as well as Signal line The first calculation means takes the third voltage of one pixel previously acquired and the first voltage of the same pixel subsequently acquired from the first calculation means. Outputting a signal corresponding to the difference, the second timing control means, The first timing control means Selected In each pixel in the selected row, the reset means resets the charge voltage conversion means. straight before , Select Supply a control pulse to each pixel in the selected row ,then The buffer means generates the second voltage generated by the charge voltage conversion means. as well as The signal line The third timing control means supplies the control pulse to the second calculation means, and (a) a pixel row that follows the currently selected row and is the next selected row. (B) in each pixel of the newly selected selected row, the charge voltage conversion unit is reset by the reset unit, and the charge voltage conversion unit generates the fourth immediately after the reset. The voltage is taken into the second computing means via the buffer means and the signal line, and the second computing means captures the fourth voltage of one pixel previously captured and the same captured subsequently. A signal corresponding to the difference from the second voltage of the pixel is output. It is characterized by that.
[0021]
In the solid-state imaging device of the present invention, before the charge voltage conversion unit is reset by the control of the first timing control unit in the pixels in the selected row, the charge voltage conversion unit is generated by the control of the second timing control unit. The second voltage is output to the signal line through the buffer means. Further, before the pixel row is selected by the first timing control means, the charge voltage conversion means of each pixel in the pixel row is reset in advance under the control of the third timing control means. Therefore, when the incident light quantity is excessive, the second voltage is the charge voltage conversion because the excessive signal charge generated by the photodiode overflows after the charge voltage conversion means is reset by the control of the third timing control means. The voltage generated by the charge voltage conversion means as a result of moving to the means and accumulating.
[0022]
That is, in the solid-state imaging device of the present invention, even when the amount of incident light is excessive and the signal charge generated by the photodiode overflows from the photodiode to the charge-voltage conversion means, the voltage varies linearly with the amount of overflowing signal charge. Is generated by the charge-voltage conversion means and output to the signal line as the second voltage. Therefore, the first voltage is used when the incident light amount is normal, and the image signal is generated using the second voltage when the incident light amount is excessive. An image signal whose size changes linearly with respect to the amount of light can be obtained, and wide dynamic range photography is possible.
[0023]
The present invention also provides: A plurality of pixels arranged in a matrix on a semiconductor substrate, a signal line provided for each column of the pixels, a first arithmetic means provided for each signal line, and a signal line provided for each signal line The pixel includes a photodiode that receives light and generates a signal charge, and a charge-voltage conversion unit that generates a voltage corresponding to the amount of the accumulated signal charge. Is a solid-state imaging device driving method in which excess signal charge generated from the photodiode overflows from the photodiode and moves to the charge-voltage conversion means. The charge voltage conversion means is reset, and immediately after the reset, the third voltage generated by the charge voltage conversion means is taken into the first calculation means via the signal line, The signal charge generated by the photodiode is transferred to the charge voltage conversion means, and the first voltage generated by the charge voltage conversion means by the signal charge is taken into the first calculation means via the signal line. And a signal corresponding to a difference between the third voltage of one pixel previously captured and the first voltage of the same pixel captured subsequently in the first calculation means. And a control pulse is supplied to each pixel in the selected row immediately before resetting the charge voltage conversion unit in each pixel in the selected row in the first timing control step, and then the charge voltage conversion unit A second timing control step of taking in the second voltage generated by the second calculation means via the signal line, and a pixel row following the currently selected row, The selected pixel row is selected, the charge voltage conversion unit is reset in each pixel of the newly selected selection row, and the fourth voltage generated by the charge voltage conversion unit is immediately after the reset. A third timing control step for fetching into the second computing means via the signal line; and the fourth voltage of one pixel previously fetched in the second computing means and the same fetched subsequently. A signal corresponding to the difference from the second voltage of the pixel is output. And a step.
[0024]
In the solid-state imaging device driving method of the present invention, the charge voltage conversion means is generated in the second timing control step before the charge voltage conversion means is reset in the pixels in the selected row in the first timing control step. The second voltage is output to the signal line through the buffer means. Further, prior to selecting a pixel row in the first timing control step, the charge voltage conversion means of each pixel in the pixel row is reset in advance in the third timing control step. Therefore, when the incident light quantity is excessive, the second voltage is transferred to the charge voltage conversion means because the excessive signal charge generated by the photodiode overflows after resetting the charge voltage conversion means in the third timing control step. As a result, the voltage is generated by the charge-voltage conversion means.
[0025]
That is, in the solid-state imaging device driving method of the present invention, even when the amount of incident light is excessive and the signal charge generated by the photodiode overflows from the photodiode to the charge-voltage conversion means, the amount of signal charge overflowed linearly. The changing voltage is generated by the charge voltage conversion means and output to the signal line as the second voltage. Therefore, the first voltage is used when the incident light amount is normal, and the image signal is generated using the second voltage when the incident light amount is excessive. An image signal whose size changes linearly with respect to the amount of light can be obtained, and wide dynamic range photography is possible.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing the periphery of a pixel constituting an example of a solid-state imaging device according to the present invention, FIG. 2 is a configuration diagram showing the entire solid-state imaging device of an embodiment, and FIG. It is a timing chart which shows. 1 and 2, the same elements as those in FIGS. 12 and 13 are denoted by the same reference numerals, and detailed description thereof will be omitted here. Hereinafter, an example of a solid-state imaging device according to the present invention will be described with reference to these drawings, and at the same time, embodiments of a driving method of the solid-state imaging device according to the present invention will be described.
[0027]
As shown in FIGS. 1 and 2, in the solid-state imaging device 2 according to the embodiment, the S / H / CDS circuit 4 (for each pixel column of the pixel unit 104 in which the pixels 120 are arranged in a matrix form. A second computing means) is newly provided. The S / H • CDS section circuit 4 holds the voltage output to the vertical signal line 136 based on the sampling pulse 8 and the first sampling pulse 148 from the timing generator 6 (FIG. 2), and at different timings. The difference between the two held voltages is calculated, the offset is removed, and the signal component is output. The S / H / CDS unit 4 is arranged in the S / H / CDS unit 10 shown in FIG.
[0028]
In the present embodiment, as shown in FIG. 2, an H selection means 12 is newly provided together with the S / H • CDS unit 10, and the output of the S / H • CDS circuit 4 of the S / H • CDS unit 10. The signals are sequentially selected by the H selection means 12 and output from the output unit 16 through the horizontal signal line 14. Specifically, the output unit 16 includes an amplifier circuit, an AGC circuit, an A / D converter, and the like.
[0029]
The timing generator 6 supplies timing pulses to the V selection means 7, the H selection means 108, and the S / H • CDS section 112 as well as the conventional technique, and also applies timing pulses to the S / H • CDS section 10 and the H selection means 12. Supply. In the present embodiment, the timing generator 6 and the V selection means 7 constitute first to third timing control means according to the present invention.
[0030]
Specifically, the constant current source 114 (FIG. 1) is configured by, for example, a MOS transistor 114B having a threshold voltage Vth of 0.45V, its gate is connected to a power line 114C of 0.8V, and its source is connected to the ground. When the vertical signal line 136 is 0.4 V or higher, a constant current of about 10 μA is passed through the vertical signal line 136. Since capacitors are inserted in series at the input portions of the S / H • CDS circuits 4, 146, no direct current flows through the S / H • CDS circuits 4, 146.
[0031]
Next, the operation of the solid-state imaging device 2 of the present embodiment will be described with reference to FIG. In FIG. 3, the same reference numerals are given to the timings corresponding to the timings shown in FIG.
The V selection means 7 selects a pixel row of the pixel unit 104 based on the timing pulse from the timing generator 6, and outputs an address pulse 140 (high level) at the timing T1 to the pixels 120 belonging to the selected row. The address pulse 140 (control pulse according to the present invention) is supplied to the address gate 138 in each pixel 120. As a result, the address gate 138 is turned on and the amplification transistor 130 (buffer means according to the present invention) is turned on to the vertical signal line. 136. At this time, since the amplification transistor 130 forms a source follower circuit together with the constant current source 114, a gate voltage, that is, a voltage following the voltage of the FD unit 124 is output from the amplification transistor 130 to the vertical signal line 136 with low impedance.
[0032]
After that, the timing generator 6 operates as the second timing control according to the present invention, and outputs the second sampling pulse 8 (control pulse according to the present invention) to the S / H • CDS unit 4 at the timing T1a. Then, the voltage of the FD unit 124 output to the vertical signal line 136 through the amplification transistor 130, that is, the second voltage according to the present invention (hereinafter also referred to as a wide D voltage) is held (the second voltage according to the present invention). Timing control step). The type of voltage will be described in detail later.
[0033]
Next, the V selection means 7 outputs a reset pulse 134 at the timing T2, whereby the reset gate 128 is turned on, the FD section 124 is connected to the power supply Vdd, and the signal charge accumulated in the FD section 124 is eliminated. The Then, the voltage of the reset FD unit 124, that is, the offset voltage (the third voltage according to the present invention) is output to the vertical signal line 136 by the amplification transistor 130.
[0034]
Subsequently, at timing T 3, the timing generator 6 sends first and second sampling pulses 148, 150 to the S / H • CDS circuit 146 (first arithmetic means according to the present invention) provided for each vertical signal line 136. The first sampling pulse 148 and the second sampling 8 are output to the S / H • CDS circuit 4 to hold the offset voltage output to the vertical signal line 136 by the amplification transistor 130.
[0035]
Thereafter, at timing T4, the V selection means 7 outputs a transfer pulse 132, turns on the transfer gate 126, and the photodiode 122 receives the signal charge received and accumulated by the timing T4 after the previous transfer pulse 132. The data is transferred to the FD unit 124. The FD unit 124 generates a voltage corresponding to the amount of signal charge transferred, that is, a normal light detection voltage (first voltage according to the present invention), and the amplification transistor 130 supplies the voltage to the vertical signal line 136 with low impedance. Output.
[0036]
The timing generator 6 outputs the second sampling pulse 150 to each S / H • CDS circuit 146 provided for each vertical signal line 136 at the timing T5, and at this time, the amplification transistor 130 outputs to the vertical signal line 136. The normal light detection voltage is maintained. Thus, each S / H • CDS circuit 146 calculates the difference between the normal light detection voltage and the offset voltage held as described above, removes the offset, and has a magnitude corresponding to the incident light amount of the photodiode 122. Is output. The output signal of the S / H / CDS circuit 146 for each vertical signal line 136 is sequentially selected by the H selection means 108 based on the timing pulse from the timing generator 6 and output to the horizontal signal line 116, and the image is output through the output unit 118. Output as a signal.
[0037]
On the other hand, in the S / H • CDS unit 10, the S / H • CDS circuit 4 provided for each vertical signal line 136 calculates the difference between the wide D voltage and the offset voltage held as described above, and the offset A voltage having a magnitude corresponding to the amount of light incident on the photodiode 122 is output. The output signal of the S / H / CDS circuit 4 for each vertical signal line 136 is sequentially selected by the H selection means 12 based on the timing pulse from the timing generator 6 and output to the horizontal signal line 14, and the image is transmitted through the output unit 16. Output as a signal.
[0038]
The V selection means 7 The reset pulse 134 is output again at the timing T5a to prepare for the next cycle. As a result, the reset gate 128 is turned on, the FD portion 124 is connected to the power supply Vdd, and the signal charge accumulated in the FD portion 124 is eliminated.
V selection means 7 At timing T6, the address pulse 140 is returned to the low level. As a result, the address gate 138 is turned off, the amplification transistor 130 is disconnected from the vertical signal line 136, and the operation for the pixels 120 for one row is completed.
[0039]
In the above operation, the V selection means 7 and the timing generator 6 operate as the first timing control means according to the present invention, supply the address pulse 140 to the pixels in the selected row at the timing T1, and the FD unit 124 at the timing T2. , The signal charge generated by the photodiode 122 at the timing T4 is transferred to the FD unit 124, and the normal photodetection voltage is output to the vertical signal line. At this time, the first timing according to the present invention is output. A control step is being executed.
[0040]
Subsequently, the V selection means 7 operates as the third timing control means according to the present invention together with the timing generator 6, and by way of example, the pixel row (FD) advanced by 5 rows from the selected row selected from the timings T1 to T6. For each pixel in the electronic shutter row), at timing T7, a reset pulse 134 is output to reset the FD unit 124 (third timing control step according to the present invention).
[0041]
FIG. 4 is an explanatory diagram showing the relationship between the FD electronic shutter row and the selected row. The pixel portion 104 is schematically shown, and each square 20 represents an individual pixel. For example, the selected row 22 is a row selected from the timings T1 to T6, and the reset pulse 134 is supplied to the FD unit 124 of each pixel as described above in the FD electronic shutter row 24 at the timing T7. Line.
[0042]
Here, the FD electronic shutter row 24 is selected and becomes a selected row after the four rows following the selected row 22 are selected, and the selected row (FD electronic shutter row 24) is performed at the timings T1 to T6 described above. The same operation as that related to the selected row 22 is performed. Therefore, resetting the FD unit 124 constituting the pixels of the FD electronic shutter row 24 at the timing T7 is performed before the pixel row (FD electronic shutter row 24) is selected by the V selection unit 7 later. That is, the FD portion 124 of each pixel is reset.
[0043]
The operations relating to the selected row 22 and the FD electronic shutter row 24 as described above are performed while sequentially shifting the selected row 22 and the FD electronic shutter row 24 one by one in the direction of the arrow A, and the V selection means 7 performs all the rows. When is selected, one image signal generated by all the pixels 120 is output.
[0044]
Next, the wide D voltage sampled at the timing T1a and the reset of the FD unit 124 in the FD electronic shutter row 24 will be described in detail.
When the amount of light incident on the photodiode 122 is large, excess signal charge generated by receiving light from the photodiode 122 overflows the transfer gate 126 to the FD section 124 and further overflows to the FD section 124, and the signal charge is reset gate. It flows into the power supply Vdd over 128.
[0045]
At this time, the voltage of the FD unit 124 is determined by the magnitude of current due to the signal charge flowing out to the power supply Vdd, but the amount of signal charge generated by the photodiode 122 is small, and the current flowing through the channel of the reset gate 128 by the MOSFET is nano. Since the current is weak in the order of amperes and the reset gate 128 operates in the subthreshold region, the voltage of the FD portion 124 becomes a value corresponding to the logarithm of the current value. Since the voltage of the FD unit 124 is output through the amplification transistor 130 and supplied to the S / H • CDS circuit 4, when the amount of incident light is excessive, the S / H • CDS circuit 4 holds at timing T <b> 1 a. The D voltage is a value corresponding to the logarithm of the incident light amount.
[0046]
However, in this embodiment, as described above, the FD portion 124 of each pixel of the FD electronic shutter row 24 is reset in advance at the stage five rows before being selected. Therefore, after the reset of the FD unit 124, the signal charge overflowing from the photodiode 122 is gradually accumulated in the FD unit 124, but when the selected row is shifted by 5 rows, the amount of signal charge accumulated in the FD unit 124 during this time A wide D voltage having a magnitude proportional to is taken into the S / H • CDS circuit 4. As described above, in the present embodiment, the charge accumulation time in the FD unit 124 is shortened. Therefore, even when the amount of incident light is excessive and the signal charge overflows from the photodiode 122, it is linear with respect to the amount of overflowing signal charge. Voltage (wide D voltage) can be obtained.
[0047]
Therefore, when the incident light quantity is normal, a signal generated by the S / H • CDS circuit 146 using the normal light detection voltage and output through the output unit 118 is used. When the incident light quantity is excessive, a wide D voltage is used. By generating an image signal using a signal generated by the S / H / CDS circuit 4 and output from the output unit 16, an image signal whose magnitude linearly changes with respect to the incident light amount even when the incident light amount is excessive. And wide dynamic range shooting is possible.
[0048]
When the amount of incident light is larger, the signal charge overflowing from the photodiode 122 overflows in the stage before the timing T1a in the FD unit 124 after reset and flows through the reset gate 128 as described above, so that the wide D voltage is The value corresponds to the logarithm of the incident light quantity. Therefore, although an image signal whose magnitude varies in proportion to the incident light quantity cannot be obtained, an image signal having a magnitude corresponding to the incident light quantity can be obtained. In this case as well, wide dynamic range shooting is possible.
[0049]
Further, in the present embodiment, since the signals can be simultaneously output from the output units 16 and 118 as described above, it is possible to select whether to use both outputs or only one as necessary, and the subsequent signal High degree of freedom in processing.
In addition, since it is not necessary to use a line memory or a frame memory, or to perform arithmetic processing between the rows of the pixel portion 104, the configuration and processing contents are simple, which is advantageous for downsizing of the apparatus and the manufacturing cost. There is no particular rise. Furthermore, since the configuration of the pixel 120 is the same as the conventional one, the size of the pixel 120 does not increase, and this is also advantageous for downsizing the solid-state imaging device.
In addition, when the incident light quantity is extremely large and the output of the output unit 16 has a magnitude corresponding to the logarithm of the incident light quantity, a capacitor is not used for logarithmic conversion, so there is no problem of afterimages and the embedded photodiode has little noise. Since 122 can be used, performance does not deteriorate in terms of image quality.
[0050]
In the present embodiment, as shown in FIG. 4, the FD electronic shutter row 22 precedes the selected row 22 by five rows, but by changing the interval between these rows variously, The charge accumulation time in the FD unit 124 can be changed, and when the incident light amount is excessive, the light amount range in which a wide D voltage that changes linearly with respect to the incident light amount can be obtained can be adjusted. The narrower the row interval, the wider the range of light quantity that can obtain a wide D voltage that changes linearly with respect to the incident light quantity. For example, when one frame is composed of 500 pixel rows, FD electrons Assuming that the shutter row 24 is the next row after the selected row 22, the enlargement is 500 times larger than when the FD unit 124 is not reset in the FD electronic shutter row 24.
[0051]
In this embodiment, electrons are carriers. However, even when a P-type MOSFET is used as a MOSFET constituting each gate and holes are carriers, the basic operation remains the same. The same effect can be obtained.
In this embodiment, the timing generator is incorporated. However, the timing generator can be externally provided.
[0052]
Next, a second embodiment of the present invention will be described.
FIG. 5 is a circuit diagram showing the periphery of the pixels constituting the solid-state imaging device of the second embodiment, and FIG. 6 is an explanation showing the relationship between the FD electronic shutter row 24 and the selected row 22 in the second embodiment. FIG. 7 is a circuit diagram showing in detail the S / H • CDS circuit, and FIG. 8 is a timing chart showing the operation of the second embodiment. In the drawing, the same elements as those in FIGS. 1 and 4 are denoted by the same reference numerals. The overall configuration of the second embodiment is the same as the configuration of the solid-state imaging device 2 shown in FIG. 2, and therefore FIG. 2 is also referred to as appropriate. Hereinafter, a solid-state imaging device as a second embodiment of the present invention will be described with reference to these drawings, and at the same time, another example of the driving method of the solid-state imaging device of the present invention will be described.
[0053]
As shown in FIG. 6, the solid-state imaging device of the second embodiment has the FD electronic shutter row 24 as a row next to the selected row 22, and the above-described embodiment is configured as shown in FIG. The S / H • CDS circuit 4 to be replaced is replaced with an S / H • CDS circuit 146A. Further, as described below, the embodiment described above is used in terms of the timing of taking the offset voltage into the S / H • CDS circuit 146A. This is different from the solid-state imaging device 2 of FIG.
[0054]
First, the S / H • CDS circuit 146 will be described in detail with reference to FIG.
As shown in FIG. 7, the S / H • CDS circuit 146 includes transistors 56 and 58, capacitors 60 and 62, and a horizontal selection transistor 64. The drain of the transistor 56 is connected to the vertical signal line 136 and the source is connected to one end of the capacitor 60, and the second sampling pulse 150 is supplied from the timing generator 6 to the gate of the transistor 56. The drain of the transistor 58 is connected to the bias voltage source Vb, the source is connected to the other end of the capacitor 60, and the first sampling pulse 148 is supplied to the gate from the timing generator 6. The first and second sampling pulses 148 and 150 are supplied in common to the gates of the transistors 56 and 58 of all the S / H / CDS units 146 arranged in the S / H / CDS unit 112.
[0055]
A capacitor 62 is connected between the other end of the capacitor 60 and the ground, and a drain of a horizontal selection transistor 64 is further connected to the other end of the capacitor 60. The source of the horizontal selection transistor 64 is connected to the horizontal signal line 116, and a selection pulse is individually supplied to the gate from the H selection means 108 for each S / H • CDS circuit 146.
[0056]
In such a configuration, when the first and second sampling pulses 148 and 150 are supplied, the transistors 56 and 58 are both turned on, whereby the offset voltage of the FD unit 124 output to the vertical signal line 136 is set. Is stored in the capacitor 60.
On the other hand, when only the second sampling pulse 150 is supplied, the transistor 56 is turned on, and the photodetection voltage output to the vertical signal line 136 is applied to the capacitor 62 through the transistor 56 and the capacitor 60. Here, since the capacitor 60 holds a voltage corresponding to the offset voltage, the capacitor 62 holds a voltage corresponding to a voltage obtained by subtracting this voltage.
[0057]
Then, the H selection means 108 sequentially outputs a selection pulse to the horizontal selection transistor 64 of the S / H • CDS circuit 146 for each vertical signal line 136, sequentially turns on the horizontal selection transistor 64, and the capacitor 62 holds it. Are sequentially output to the horizontal signal line 116.
The S / H • CDS circuit 146A has the same configuration as the S / H • CDS circuit 146 in this embodiment.
[0058]
Next, the operation will be described with reference to FIG. 8, focusing on the incorporation of the wide D voltage, the offset voltage, and the normal light detection voltage into the S / H • CDS circuits 146 and 146A.
The timing chart shown in FIG. 8 differs from the timing chart shown in FIG. 3 in that the first and second sampling pulses 148A and 150A are not supplied to the S / H • CDS circuit 146A at the timing T3, and the timing T8 The address pulse 140 is supplied at timing T6a. The points other than these are the same as those in FIG. 3 and the related operations are also the same. Therefore, here, the operations at these timings will be mainly described.
[0059]
As described above, at the timing T3, the first and second sampling pulses 148A and 150A are not supplied to the S / H • CDS circuit 146A, and the timing generator 6 is only the first to the S / H • CDS circuit 146. The second sampling pulses 148 and 150 are supplied to hold the offset voltage of the FD unit 124 output to the vertical signal line 136. Specifically, as shown in FIG. 7, at this time, both the transistors 56 and 58 are turned on, and a voltage corresponding to the offset voltage is held in the capacitor 60.
[0060]
After that, the second sampling pulse 150 is supplied to the S / H • CDS circuit 146 at the timing T5 as in the case of the solid-state imaging device 2, and the S / H • CDS circuit 146 holds the normal light detection voltage. Specifically, as shown in FIG. 7, at this time, the transistor 56 is turned on, and the capacitor 62 holds a voltage corresponding to the voltage obtained by subtracting the offset voltage from the normal photodetection voltage. To the horizontal signal line 116.
[0061]
The V selection means 7 operates together with the timing generator 6 as the third timing control means according to the present invention. First, the timing T6a with respect to the address gate 138 constituting the pixels of the FD electronic shutter row 24 shown in FIG. Then, the address pulse 140 is supplied to turn on the address gate 138. Next, at the timing T7, the reset pulse 134 is supplied to the reset gate 128 to reset the FD unit 124, as in the case of the solid-state imaging device 2.
[0062]
At timing T8, the timing generator 6 outputs the first and second sampling pulses 148A and 150A to the respective S / H / CDS circuits 146A and outputs to the vertical signal line 136 the offset voltage of the FD unit 124 ( The fourth voltage according to the present invention is maintained. Specifically, as shown in FIG. 7, at this time, both the transistors 56 and 58 are turned on, and a voltage corresponding to the offset voltage is held in the capacitor 60. The V selection means 7 then returns the address pulse to the original low level at timing T9.
[0063]
After that, when the current FD electronic shutter row 24 becomes the selected row in the next cycle, the timing generator 6 applies the second sampling pulse 150A to each S / H · at timing T1a as in the case of the solid-state imaging device 2. The wide D voltage supplied to the CDS circuit 146A and outputted to the vertical signal line 136 is held. Specifically, as shown in FIG. 7, the transistor 56 is turned on at this time, and the capacitor 62 holds a voltage corresponding to the voltage obtained by subtracting the offset voltage from the wide D voltage. This voltage is later transmitted through the transistor 64. It is output to the horizontal signal line 116.
Thereafter, the above operation is repeated while the selected row 22 and the FD electronic shutter row 24 are sequentially shifted one by one in the direction of the arrow A.
[0064]
As described above, in the solid-state imaging device according to the second embodiment, the offset voltage is first supplied to both the S / H • CDS circuits 146 and 146A, and then the normal light detection voltage and the wide voltage are widened. Each of the D voltages is supplied. Therefore, as shown in FIG. 7, the S / H • CDS circuits 146 and 146A can obtain the same polarity voltage obtained by subtracting the offset voltage from the normal light detection voltage and the wide D voltage, respectively, with the same configuration. .
[0065]
In the case of the S / H • CDS circuit 4 shown in FIG. 1, the wide D voltage is first supplied at the timing T1a as described above, and then the offset voltage of the FD unit 124 is supplied at the timing T3. When the / H · CDS circuit 4 has the same configuration as that of the S / H · CDS circuit 146, the voltage corresponding to the wide D voltage is held in the capacitor 60. The opposite signal is output. Therefore, the S / H • CDS circuit 4 must have a configuration different from that of the S / H • CDS circuit 146 in order to make the polarity of the output signal the same as that of the S / H • CDS circuit 146.
In the second embodiment, as described above, the S / H • CDS circuit 146A may have the same configuration as the S / H • CDS circuit 146, and signals of the same polarity are output from both circuits. Therefore, it is easy to design an S / H • CDS circuit, which is advantageous in manufacturing.
[0066]
In the second embodiment, as described above, the FD unit 124 of the pixel in the FD electronic shutter row is reset at the timing T7, and the offset voltage is held in the S / H • CDS circuit 146A at the timing T8. Immediately after that, the wide D voltage is taken into the S / H • CDS circuit 146A at the timing T1a from the pixel of the next selected row (that is, the FD electronic shutter row) to obtain a signal corresponding to the wide D voltage from which the offset is removed. . Therefore, noise such as KTC noise included in the wide D voltage can be effectively removed.
That is, when the FD unit 124 of the pixel in the FD electronic shutter row is reset at the timing T7, the voltage (offset voltage) of the FD unit 124 is superimposed with noise such as KTC noise. Thereafter, the signal charge overflowing from the photodiode 122 is accumulated in the FD unit 124, and the FD unit 124 generates a corresponding voltage, and the noise after the reset is superimposed on this voltage. Therefore, at the timing T1a of the next cycle, the wide D voltage superimposed with the same noise as the noise superimposed on the offset voltage is taken into the S / H / CDS circuit 146A, and the offset immediately after the reset is taken in at the timing T8 first. When the voltage is reduced, the noise component can be surely removed.
[0067]
In the second embodiment, since the selected row and the FD electronic shutter row are adjacent to each other and the positional relationship between the two rows is fixed, adjustment of the accumulation time of the signal charge overflowing from the photodiode 122 in the FD portion is adjusted. It is not possible to adjust the sensitivity when the amount of incident light is excessive. However, since the dynamic range is maximized by setting the FD electronic shutter row as the row next to the selected row, fixing the FD electronic shutter row in this way is not necessarily disadvantageous. In addition, fixing the sensitivity when the amount of incident light is excessive works advantageously in that signal processing at a later stage becomes easy.
[0068]
Next, a third embodiment of the present invention will be described.
FIG. 9 is a timing chart showing the operation of the third embodiment, and FIG. 10 is an explanatory diagram showing the relationship between the photodiode electronic shutter row, the FD electronic shutter row, and the selected row in the third embodiment. . 10, the same elements as those in FIG. 4 are denoted by the same reference numerals. Hereinafter, with reference to these drawings, a solid-state imaging device as a third exemplary embodiment of the present invention will be described, and at the same time, another example of the driving method of the solid-state imaging device of the present invention will be described.
The overall configuration and pixel configuration of the solid-state imaging device according to the third embodiment are the same as those of the solid-state imaging device 2 according to the first embodiment, and therefore FIG. 1 and FIG.
[0069]
In the third embodiment, as shown in FIG. 10, the photodiode electronic shutter row 26 is set together with the FD electronic shutter row 24, and the timing control by the timing generator 6 and the V selection means 7 is changed. Thus, the solid-state imaging device 2 is different. In this embodiment, the FD electronic shutter row 24 is at a position that precedes the selected row 22 by four rows, and the photodiode electronic shutter row 26 is at a position that precedes the selected row 22 by seven rows.
[0070]
The operation of this embodiment will be described. The V selection means 7 (FIG. 2) outputs an address pulse 140 (high level) to each pixel in the selected row 22 at timing T1. As a result, the address gate 138 (FIG. 1) is turned on, and the amplification transistor 130 is connected to the vertical signal line 136.
After that, the timing generator 6 outputs the sampling pulse 8 to the S / H • CDS circuit 4 at the timing T1a, and holds the wide D voltage output to the vertical signal line 136 through the amplification transistor 130.
Next, the V selection unit 7 outputs a reset pulse 134 to each of the selected row 22, the FD electronic shutter row 24, and the photodiode electronic shutter row 26 at the timing T2. As a result, the reset gate 128 is turned on and the FD unit 124 is reset in each pixel of the three rows. In the selected row 22, the voltage of the reset FD unit 124, that is, the offset voltage is output to the vertical signal line 136 by the amplification transistor 130.
[0071]
Subsequently, at timing T 3, the timing generator 6 supplies the first and second sampling pulses 148 and 150 to the S / H • CDS circuit 146 provided for each vertical signal line 136 and the S / H • CDS circuit 4 to the first. One sampling pulse 148 and the second sampling 8 are output, and the offset voltage output to the vertical signal line 136 by the amplification transistor 130 in the selected row 22 is held.
[0072]
After that, at timing T4, the V selection means 7 supplies the transfer pulse 132 to the transfer gates constituting the pixels of the selected row 22 and the photodiode electronic shutter row 26 to turn on, and the photodiode 122 receives light by this timing. The accumulated signal charge is transferred to the FD unit 124. The FD unit 124 of each pixel in the selected row 22 generates a normal light detection voltage, and the amplification transistor 130 outputs the voltage to the vertical signal line 136 with a low impedance.
[0073]
Then, the timing generator 6 outputs the second sampling pulse 150 to each S / H • CDS circuit 146 at the timing T5, and at this time, the normal photodetection voltage output from the amplification transistor 130 to the vertical signal line 136 is output. Hold. Accordingly, each S / H • CDS circuit 146 subtracts the offset voltage from the normal light detection voltage held as described above, and outputs a voltage having a magnitude corresponding to the amount of light incident on the photodiode 122. The output signal of the S / H / CDS circuit 146 for each vertical signal line 136 is sequentially selected by the H selection means 108 based on the timing pulse from the timing generator 6 and output to the horizontal signal line 116, and the image is output through the output unit 118. Output as a signal.
[0074]
On the other hand, in the S / H • CDS unit 10, each S / H • CDS circuit 4 subtracts the offset voltage from the wide D voltage held as described above and outputs a voltage having a magnitude corresponding to the incident light amount of the photodiode 122. To do. The output signals of the respective S / H / CDS circuits 4 are sequentially selected by the H selection means 12 based on the timing pulse from the timing generator 6, output to the horizontal signal line 14, and output as an image signal through the output unit 16.
[0075]
The V selection means 7 In preparation for the next cycle, the reset pulse 134 is output again to the selected row 22, the FD electronic shutter row 24, and the photodiode electronic shutter row 26 at the timing T5a. As a result, the reset gate 128 constituting the pixel of each row is turned on, and the FD unit 124 is reset. Since the transfer pulse 132 is supplied to the pixels of the photodiode electronic shutter row 26 at the timing T4, both the photodiode 122 and the FD unit 124 constituting the pixels of the photodiode electronic shutter row 26 are reset at this stage. It becomes a state.
[0076]
V selection means 7 The address pulse 140 supplied to the pixel of the selected row 22 is returned to the low level at the timing T6. As a result, the address gate 138 constituting the pixel of the selected row 22 is turned off, and the amplification transistor 130 is disconnected from the vertical signal line 136. It is. Thereafter, the V selection means 7 performs such an operation while sequentially shifting the selection row 22, the FD electronic shutter row 24, and the photodiode electronic shutter row 26 one by one in the direction of the arrow A (FIG. 10). .
[0077]
In the above operation, the photodiode electronic shutter row 26 shown in FIG. 10 is selected and becomes the selected row after the selection of the six rows following the selected row 22, and is performed at the above-described timings T1 to T6. The same operation as that for the selected row 22 shown in FIG. 10 is performed in the photodiode electronic shutter row 26 (new selected row 22). Therefore, at timing T4, a transfer pulse 134 is supplied to the pixels of the photodiode electronic shutter row 26 to transfer the signal charge of the photodiode 122 to the FD unit 124, and further, a reset pulse is supplied at timing T5a to set the FD unit 124. Resetting means resetting the photodiode 122 and the FD portion 124 of the pixel before the pixel row (photodiode electronic shutter row 26) is selected by the V selection means 7 later (the present invention). 4th timing control step). Here, the V selection means 7 for supplying the transfer pulse and the reset pulse to the photodiode electronic shutter row 26 operates together with the timing generator 6 as the fourth timing control means according to the present invention.
[0078]
Thus, in the third embodiment, the photodiode electronic shutter row 26 is set and the photodiode 122 is reset in advance, so that the charge accumulation time in the photodiode 122 is changed from the selected row 22 to the photodiode electrons. The time corresponds to the number of lines up to the shutter line 26. Therefore, by adjusting the number of rows in various ways, the charge accumulation time in the photodiode 122 can be changed, and the same effect as that of the first embodiment can be obtained. It becomes possible to adjust the sensitivity with respect to the amount of light.
[0079]
In the third embodiment, the reset pulse 134 is supplied to the pixels of the FD electronic shutter row 24 at the timing T2. However, the reset pulse is not supplied at this timing, and the reset pulse is only supplied at the timing T5a. In such a case, the FD unit 124 can be reset in advance in preparation for the FD electronic shutter row 24 being selected later. Of course, as in the case of the first embodiment, it is possible to reset the FD unit 124 at a timing after timing 6.
However, the selection row 22, the FD electronic shutter row 24, and the photodiode electronic shutter row 26 have common timing control for the pixels in the respective rows, thereby facilitating the design, and the selection row 22 with respect to the FD electronic shutter row 24. It is more advantageous to supply a reset pulse at the same timing as the above.
[0080]
Furthermore, in the third embodiment, the reset pulse 134 and the transfer pulse 132 are supplied to the pixels in the photodiode electronic shutter row 26 at the same timing as the pixels in the selected row 22, but the photodiode electronic shutter Since such timing control for the row 26 is intended to reset the photodiode 122 and the FD unit 124 of the photodiode electronic shutter row 26 in advance, the photodiode 122 and the FD are different in timing from the selected row 22. Of course, it is possible to configure the unit 124 to be reset.
[0081]
Next, a fourth embodiment of the present invention will be described.
FIG. 11 is a block diagram showing the entirety of a solid-state imaging device as a fourth embodiment of the present invention. In the figure, the same elements as those in FIG. 2 are denoted by the same reference numerals.
In the solid-state imaging device 34 of the present embodiment, CDS / AGC units 10A and 114A are provided instead of the S / H / CDS units 10 and 112 shown in FIG. 1, and a signal synthesis / A / D conversion unit 28 is provided. The communication unit 30 is newly provided, and the horizontal signal line 116 is replaced with a bus line 116A.
[0082]
The CDS / AGC units 10A and 114A are obtained by adding an AGC (automatic gain control) function to the S / H / CDS units 10 and 112 of FIG. These voltages are output after adjusting the level.
Then, the signal synthesis / A / D conversion unit 28 synthesizes the wide D voltage and the normal light detection voltage from the CDS / AGC units 10A and 114A into a light detection voltage having a wide dynamic range, and further converts it into a digital signal. And output. The digital signals are sequentially read out to the bus line by the H selection means 108 and output through the digital output terminal 32.
The communication unit 30 controls the operation of the timing generator 6 and the drive mode of the solid-state imaging device 34 based on a mode control signal input through the mode control terminal 36.
[0083]
Therefore, in the solid-state imaging device 34 of the fourth embodiment, the light detection result when the amount of light incident on the photodiode is a normal level and the light detection result when it is excessive are output in a combined state. Therefore, it is not necessary to provide a circuit for signal synthesis outside. In addition, the operation of the solid-state imaging device 34 can be variously controlled through the communication unit 30, and the flexibility in the operation is increased.
[0084]
【The invention's effect】
As described above, in the solid-state imaging device of the present invention, the charge voltage is controlled by the second timing control unit before the charge voltage conversion unit is reset by the control of the first timing control unit in the pixels of the selected row. The second voltage generated by the conversion means is output to the signal line through the buffer means. Further, before the pixel row is selected by the first timing control means, the charge voltage conversion means of each pixel in the pixel row is reset in advance under the control of the third timing control means. Therefore, when the incident light quantity is excessive, the second voltage is the charge voltage conversion because the excessive signal charge generated by the photodiode overflows after the charge voltage conversion means is reset by the control of the third timing control means. The voltage generated by the charge voltage conversion means as a result of moving to the means and accumulating.
[0085]
That is, in the solid-state imaging device of the present invention, even when the amount of incident light is excessive and the signal charge generated by the photodiode overflows from the photodiode to the charge-voltage conversion means, the voltage varies linearly with the amount of overflowing signal charge. Is generated by the charge-voltage conversion means and output to the signal line as the second voltage. Therefore, the first voltage is used when the incident light amount is normal, and the image signal is generated using the second voltage when the incident light amount is excessive. An image signal whose size changes linearly with respect to the amount of light can be obtained, and wide dynamic range photography is possible.
[0086]
Since there is no need to use a line memory or a frame memory, or to perform arithmetic processing between pixel rows, the configuration and processing contents are simple, which is advantageous for downsizing of the apparatus and the manufacturing cost is low. There is no particular rise.
Furthermore, since the pixel configuration is the same as the conventional one, the pixel size does not increase, and this is also advantageous for downsizing the solid-state imaging device.
In addition, when the incident light quantity is extremely large and the second voltage has a magnitude corresponding to the logarithm of the incident light quantity, a capacitor or the like is not used for logarithmic conversion, so there is no problem of afterimages and there is little noise in the embedded photodiode. Therefore, the performance is not deteriorated in terms of image quality.
[0087]
In the solid-state imaging device driving method of the present invention, the charge voltage conversion unit generates the charge voltage conversion unit in the second timing control step before resetting the charge voltage conversion unit in the pixel in the selected row in the first timing control step. The second voltage is output to the signal line through the buffer means. Further, prior to selecting a pixel row in the first timing control step, the charge voltage conversion means of each pixel in the pixel row is reset in advance in the third timing control step. Therefore, when the incident light quantity is excessive, the second voltage is transferred to the charge voltage conversion means because the excessive signal charge generated by the photodiode overflows after resetting the charge voltage conversion means in the third timing control step. As a result, the voltage is generated by the charge-voltage conversion means.
[0088]
That is, in the solid-state imaging device driving method of the present invention, even when the amount of incident light is excessive and the signal charge generated by the photodiode overflows from the photodiode to the charge-voltage conversion means, the amount of signal charge overflowed linearly. The changing voltage is generated by the charge voltage conversion means and output to the signal line as the second voltage. Therefore, the first voltage is used when the incident light amount is normal, and the image signal is generated using the second voltage when the incident light amount is excessive. An image signal whose size changes linearly with respect to the amount of light can be obtained, and wide dynamic range photography is possible.
[0089]
Since there is no need to use a line memory or a frame memory, or to perform arithmetic processing between pixel rows, the configuration and processing contents of the solid-state imaging device are simple, which is advantageous for downsizing the device. The manufacturing cost is not particularly increased.
Furthermore, since the pixel configuration may be the same as the conventional one, the pixel size does not increase, which is advantageous for downsizing of the solid-state imaging device.
In addition, when the incident light quantity is extremely large and the second voltage has a magnitude corresponding to the logarithm of the incident light quantity, a capacitor or the like is not used for logarithmic conversion, so there is no problem of afterimages and there is little noise in the embedded photodiode. Therefore, the performance is not deteriorated in terms of image quality.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a periphery of a pixel constituting an example of a solid-state imaging device according to the present invention.
FIG. 2 is a configuration diagram illustrating an entire solid-state imaging device according to an embodiment.
FIG. 3 is a timing chart showing an operation related to the pixel of FIG. 1;
FIG. 4 is an explanatory diagram showing a relationship between an FD electronic shutter row and a selected row.
FIG. 5 is a circuit diagram showing the periphery of a pixel constituting the solid-state imaging device according to the second embodiment.
FIG. 6 is an explanatory diagram showing a relationship between an FD electronic shutter row and a selected row in the second embodiment.
FIG. 7 is a circuit diagram showing in detail an S / H • CDS circuit.
FIG. 8 is a timing chart showing the operation of the second exemplary embodiment.
FIG. 9 is a timing chart showing the operation of the third exemplary embodiment.
FIG. 10 is an explanatory diagram showing a relationship between a photodiode preceding reset row, an FD electronic shutter row, and a selected row in the third embodiment.
FIG. 11 is a block diagram showing the entirety of a solid-state imaging device as a fourth embodiment of the present invention.
FIG. 12 is a configuration diagram illustrating a conventional solid-state imaging device.
13 is a circuit diagram showing the periphery of one pixel constituting the solid-state imaging device of FIG. 12. FIG.
14 is a timing chart showing the operation of the circuit shown in FIG.
[Explanation of symbols]
2, 34... Solid imaging device, 4, 146... S / H / CDS circuit, 6... Timing generator, 7. H selection means, 14, 116 ... horizontal signal line, 16, 118 ... output unit, 22 ... selected row, 24 ... FD electronic shutter row, 26 ... photodiode electronic shutter row, 104 ... pixel portion, 120... Pixel, 136... Vertical signal line.

Claims (2)

A plurality of pixels arranged in a matrix on a semiconductor substrate, a signal line provided for each column of the pixels, a first timing control means, a second timing control means, and a third timing control means And a first computing means provided for each signal line, and a second computing means provided for each signal line ,
The pixel includes a light receiving to a photodiode for generating a signal charge, accumulated signal and charge-voltage converting means for generating a voltage corresponding to the amount of charge, the charge-voltage converting the signal charges the photodiode was produced transfer means for transferring the unit, the charge voltage and buffer means for outputting to the signal line converting means corresponding to the generated voltage, the charge-voltage converting means and the charge-voltage converting means to eliminate the accumulated charges in Resetting means for resetting,
The excessive signal charge by the photodiode-generated Yes so as to move in the charge-voltage converting means through said transfer means regardless of transfer operation of the transfer means,
Said first timing control means, by supplying a control pulse, (b) said sequentially selects a row of pixels, (b) Oite to each pixel of the selected row, the charge-voltage converting means to the reset means was allowed to reset, the third voltage the charge-voltage converting means immediately after a reset is generated after incorporated into the first arithmetic means through said buffer means and said signal lines, said transfer means said the signal charges by the photodiode-generated by transferred to the charge-voltage converting means, wherein the first voltage generated by the charge-voltage converting means by the signal charges via the buffer means and said signal line a 1 to the calculation means,
The first calculation means outputs a signal corresponding to a difference between the third voltage of one pixel previously captured and the first voltage of the same pixel captured subsequently,
It said second timing control means, wherein immediately prior to reset the charge-voltage converting means to the reset means in each pixel of the first timing control means is selected 択行, a control pulse to each pixel of the selected択行supplying to, then allowed to ingest the second voltage is the charge-voltage converting means is generating said second calculation means via said buffer means and said signal line,
The third timing control means supplies a control pulse to select (a) a pixel row subsequent to the currently selected row and the pixel row to be selected next, and (b) newly selected. In each pixel of the selected row, the charge voltage conversion unit is reset by the reset unit, and a fourth voltage generated by the charge voltage conversion unit immediately after the reset is generated via the buffer unit and the signal line. Let the second computing means capture,
The second calculation means outputs a signal corresponding to a difference between the fourth voltage of one pixel previously captured and the second voltage of the same pixel captured subsequently.
A solid-state imaging device. A plurality of pixels arranged in a matrix on a semiconductor substrate, a signal line provided for each column of the pixels, a first arithmetic means provided for each signal line, and a signal line provided for each signal line The pixel includes a photodiode that receives light and generates a signal charge, and a charge-voltage conversion unit that generates a voltage corresponding to the amount of the accumulated signal charge. The excessive signal charge generated by the liquid crystal overflows from the photodiode and moves to the charge voltage conversion means, and is a driving method of a solid-state imaging device,
The row of pixels is sequentially selected, the charge voltage conversion unit is reset in each pixel of the selected row, and the third voltage generated by the charge voltage conversion unit immediately after the reset is supplied via the signal line. The signal charge generated by the photodiode is transferred to the charge voltage conversion means after being taken into the first calculation means, and the first voltage generated by the charge voltage conversion means by the signal charge is transferred to the signal. A first timing control step for taking in the first calculation means via a line;
Generating a signal corresponding to a difference between the third voltage of one pixel previously captured and the first voltage of the same pixel captured subsequently in the first arithmetic means;
Immediately before resetting the charge-voltage converter in each pixel in the selected row in the first timing control step, a control pulse is supplied to each pixel in the selected row, and the charge-voltage converter is generated at that time. The second voltage is taken into the second calculation means via the signal line. Two timing control steps;
The pixel row that is the pixel row that follows the currently selected row and that is the next selected row is selected, the charge-voltage conversion unit is reset in each pixel of the newly selected selected row, and the charge voltage immediately after the reset A third timing control step of taking the fourth voltage generated by the conversion means into the second calculation means via the signal line;
A step of outputting a signal corresponding to a difference between the fourth voltage of one pixel captured in advance and the second voltage of the same pixel captured subsequently in the second arithmetic means;
The solid-state imaging device drive method characterized by including.

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