JP2021168450A - Radiation imaging apparatus, radiation imaging system, method for driving radiation imaging apparatus, and program - Google Patents

Abstract

To provide a technique that is advantageous for preventing the generation of artifact.SOLUTION: A radiation imaging apparatus includes a conversion unit and a sample hold unit. The conversion unit includes a conversion element, a first source follower circuit that is arranged on a path connecting an output node of the conversion element with the sample hold unit, an additional capacitance for changing the sensitivity of the conversion unit from a first sensitivity to a second sensitivity lower than the first sensitivity, a switch that is arranged on a path connecting the output node with the additional capacitance, and a second source follower circuit that is arranged on a path connecting the additional capacitance with the sample hold unit. The first source follower circuit includes an amplification transistor and a selection transistor for causing the amplification transistor to perform a source follower operation. In imaging with the second sensitivity, after the switch starts the accumulation of electric charges in an on state and before the sample hold unit samples a signal, for a predetermined period, a first operation is executed in which the switch becomes an off state and the selection transistor becomes an on state.SELECTED DRAWING: Figure 3

Description

The present invention relates to a radiation imaging device, a radiation imaging system, a method for driving the radiation imaging device, and a program.

Radiation imaging devices including a flat pixel panel in which pixels combining a conversion element such as a photodiode and a switch element such as a thin film transistor (TFT) are arranged in an array are widely used. Patent Document 1 discloses that the sensitivity is switched by connecting the capacitance for sensitivity switching to the output node of the photodiode via a switch and switching the switch on / off.

Japanese Unexamined Patent Publication No. 2012-019359

In the circuit configuration shown in Patent Document 1, two sources follower circuits for outputting a signal from a charge-voltage conversion unit including a photodiode are arranged. One is a source follower circuit that outputs a signal when shooting with high sensitivity, and the other passes through a switch for switching sensitivity when shooting with low sensitivity (high dynamic range). It is a source follower circuit that outputs a signal via a current path. When shooting with low sensitivity, the voltage of the source follower circuit may change due to the influence of the leakage current of the transistor included in the source follower circuit for high sensitivity in the non-operating state. If the change in the voltage of the source follower circuit for high sensitivity propagates to the charge-voltage converter via parasitic capacitance or the like, an artifact may occur.

An object of the present invention is to provide an advantageous technique for suppressing the occurrence of artifacts in a radiation imaging device.

In view of the above problems, the radiation imaging device according to the embodiment of the present invention is a radiation imaging device including a plurality of pixels including a conversion unit and a sample holding unit, and the conversion unit responds to radiation. The sensitivity of the first source follower circuit, which is arranged in the path connecting the conversion element that generates the charge, the output node of the conversion element, and the sample hold unit, and outputs the signal according to the charge, and the sensitivity of the conversion unit are changed from the first sensitivity. The additional capacitance for changing to the second sensitivity, which is lower than the first sensitivity, the switch arranged on the path connecting the output node and the additional capacitance, and the path connecting the additional capacitance and the sample hold unit. The first source follower circuit includes a second source follower circuit that outputs a signal according to the charge, and the first source follower circuit is arranged in a path connecting the amplification transistor, the amplification transistor, and the current source, and the amplification transistor is used as the source follower. A predetermined transistor including a selection transistor for operation is included, and in imaging at the second sensitivity, after the conversion unit starts accumulating charge with the switch on and before the sample hold unit samples the signal, a predetermined value is provided. Over a period of time, the switch is turned on after the first operation in which the switch is in the off state and the selection transistor is in the on state, and the sample hold unit samples the signal via the second source follower circuit. The second operation is performed.

By the above means, the radiographic imaging apparatus provides an advantageous technique for suppressing the occurrence of artifacts.

The figure which shows the configuration example of the radiation imaging system including the radiation imaging apparatus which concerns on this embodiment. The figure which shows the structural example of the pixel of the radiation imaging apparatus of FIG. The timing diagram explaining the control example of the drive of the radiation imaging apparatus of FIG. The figure which shows the structural example of the sensor unit of the radiation imaging apparatus of FIG. The figure which shows the structural example of the reading part of the radiation imaging apparatus of FIG. The timing diagram explaining the control example of the drive of the radiation imaging apparatus of FIG. The timing diagram explaining the control example of the drive of the radiation imaging apparatus of FIG.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiment, not all of the plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the attached drawings, the same or similar configurations are given the same reference numbers, and duplicate explanations are omitted.

Further, the radiation in the present invention includes beams having the same or higher energy, for example, X, in addition to α-rays, β-rays, γ-rays, etc., which are beams produced by particles (including photons) emitted by radiation decay. It can also include lines, particle beams, cosmic rays, etc.

The configuration and driving method of the radiation imaging apparatus according to the present embodiment will be described with reference to FIGS. 1 to 7. FIG. 1 is a system block diagram showing an overall configuration example of a radiation imaging system SYS including the radiation imaging device 100 according to the present embodiment. The radiation imaging system SYS includes a radiation imaging device 100, a system control unit 101, a display unit 102, an irradiation control unit 103, and a radiation source 104.

The radiation imaging device 100 acquires image data indicating internal information of the subject by imaging using radiation, and outputs the image data to the system control unit 101. The system control unit 101 also functions as a control unit that exchanges control signals between the units and performs system control and synchronous control of the entire radiation imaging system SYS including the radiation imaging device 100 and the irradiation control unit 103. The display unit 102 includes, for example, a display, and displays a radiation image based on image data output from the radiation imaging device 100 via the system control unit 101. For example, frame image data corresponding to radiation irradiation is transferred from the radiation imaging device 100 to the system control unit 101, image processing is performed by the system control unit 101, and then the radiation image is displayed on the display unit 102 in real time. ..

The irradiation control unit 103 is controlled by the system control unit 101 so as to be synchronized with the radiation imaging device 100 when capturing a radiation image. The irradiation control unit 103 outputs a signal for irradiating radiation to the radiation source 104, which is a radiation generator, in response to the control signal output from the system control unit 101. The radiation source 104 generates radiation for performing radiation imaging in response to a signal output from the irradiation control unit 103. In other words, the system control unit 101 outputs a signal for controlling the irradiation of radiation to the radiation source 104 for irradiating the radiation imaging device 100 with radiation via the irradiation control unit 103.

The radiation imaging device 100 includes a sensor panel 105, a reading unit 106, and a control unit 109. The reading unit 106 reads out an image signal output from the sensor panel 105. The control unit 109 controls each unit in the radiation imaging device 100 while exchanging signals such as control signals with the system control unit 101.

A plurality of sensor units 120 are arranged on the sensor panel 105. Each sensor unit 120 can be, for example, a sensor chip manufactured by a known semiconductor manufacturing process using a semiconductor substrate such as a silicon wafer, and pixels that are CMOS type image pickup elements are arranged in a two-dimensional array. .. Each sensor unit 120 has an imaging region for acquiring an image signal indicating internal information of the subject. Further, each sensor unit 120 may have a light-shielded optical black region in addition to the imaging region. Each sensor unit 120 may be physically separated by dicing or the like. In other words, the plurality of sensor units 120 arranged on the sensor panel 105 may have a separable configuration for each sensor unit 120. By tiling a plurality of sensor units 120 on a plate-shaped base (not shown), the sensor panel 105 can be enlarged. Each sensor unit 120 can be tiled so that the pixel conversion elements formed in the sensor unit 120 are arranged at the same pitch as the inside of the sensor unit 120 across the boundary of the sensor units 120 adjacent to each other. .. The configuration shown in FIG. 1 shows a configuration in which the sensor unit 120 is tiling over 2 rows × 7 columns for the sake of simplicity, but the configuration of the sensor panel 105 is not limited to this configuration.

For example, a scintillator (not shown) that converts radiation into light is arranged on the side of the incident surface of the sensor panel 105 that is irradiated with radiation, and a pixel conversion element arranged in each sensor unit 120 of the sensor panel 105. Provides an electrical signal corresponding to the light converted from the radiation. In the present embodiment, a configuration example of an image pickup apparatus using a pixel including an indirect type conversion element that converts radiation into light by a scintillator and photoelectrically converts the converted light is shown, but radiation is directly converted into an electric signal. An image pickup apparatus using a direct type conversion element may be used.

The reading unit 106 includes, for example, a differential amplifier 107 and an A / D converter 108 that performs analog-to-digital (A / D) conversion. The configuration and operation of the differential amplifier 107 and the A / D converter 108 will be described later.

Electrodes for sending and receiving signals or supplying power are arranged on the upper and lower sides of the sensor panel 105. The electrodes are connected to an external circuit by a flying lead type printed wiring board (not shown) or the like. For example, the image signal from the sensor panel 105 is read by the reading unit 106 via the electrode, and the control signal from the control unit 109 is supplied to the sensor panel 105 via the electrode.

The control unit 109 controls the operation of the sensor panel 105, the differential amplifier 107, and the A / D converter 108. For example, the setting of the reference voltage supplied to each sensor unit 120, the drive control of each pixel, and the operation mode. Take control. Further, the control unit 109 uses one image signal (digital data) output from each sensor of the sensor panel 105 that has been A / D converted by the A / D converter 108 of the reading unit for each unit period. Generate frame data. The generated frame data is output to the system control unit 101 as image data.

The radiation imaging device 100 may further include a memory 115. The memory 115 may store a program or the like for operating the radiation imaging device 100. Further, various correction data and parameters may be stored in the memory 115.

Control signals such as control commands and image data are exchanged between the control unit 109 and the system control unit 101 via various interfaces. The control interface 110 is an interface for exchanging image pickup information and setting information such as a drive mode and various parameters. Further, the control interface 110 may exchange device information such as the operating state of the radiation imaging device 100. The image data interface 111 is an interface for outputting an image signal (image data) output from the radiation imaging device 100 to the system control unit 101. Further, the control unit 109 notifies the system control unit 101 by the READY signal 112 that the radiation imaging device 100 is ready for imaging. The system control unit 101 notifies the control unit 109 of the timing of radiation irradiation start (exposure) by the synchronization signal 113 in response to the READY signal 112 output from the control unit 109. The system control unit 101 outputs a control signal to the irradiation control unit 103 while the exposure permission signal 114 output from the control unit 109 is in the enabled state, and starts irradiation of radiation.

With the above configuration, control of each unit in the radiation imaging system SYS, for example, drive control, synchronous control, drive mode control, and the like is performed. For example, an information input unit for the user to input imaging information such as an operation mode and various parameters and an input unit (not shown) such as an information input terminal may be connected to the system control unit 101, and each unit may be connected. Is controlled based on the imaging information input by the user. For example, the system control unit 101 functions as a drive mode setting unit, selects a drive mode based on the imaging information input by the user, and controls the entire radiation imaging system SYS so that the radiation imaging system SYS operates. Then, the radiation imaging apparatus 100 generates frame data for each unit period of the image signal from the pixels read from the sensor panel 105, and outputs the image data to the system control unit 101. The system control unit 101 performs predetermined image processing and data processing on the image data, and causes the display unit 102 to display a radiation image based on the image data.

Each unit in the radiation imaging system SYS is not limited to the above configuration, and the configuration of each unit may be appropriately changed depending on the purpose and the like. For example, each function of two or more units such as the system control unit 101 and the irradiation control unit 103 may be achieved by one unit. Further, for example, in the present embodiment, the radiation imaging apparatus 100 and the system control unit 101 are shown as separate units, but the present invention is not limited thereto. The radiation imaging device 100 may include some or all of the functions of the system control unit 101, the display unit 102, and the irradiation control unit 103, in addition to the functions provided by the radiation imaging device 100.

FIG. 2 shows a circuit configuration example of one pixel PIX out of a plurality of pixel PIXs arranged in each sensor unit 120 of the sensor panel 105. In the present embodiment, each pixel PIX includes a conversion unit 201, a sample hold unit 203, and a clamp circuit 202 arranged in a path connecting the conversion unit 201 and the sample hold unit 203. In FIG. 2, the photodiode PD is a photoelectric conversion element, and converts the light generated by the scintillator according to the incident radiation into an electric signal. Therefore, the conversion unit 201 that generates a signal corresponding to the incident radiation includes a scintillator and a photodiode PD that is a conversion element. Specifically, the photodiode PD generates an electric charge in an amount corresponding to the amount of light generated by the scintillator. In the present embodiment, the sensor panel 105 using the indirect type conversion element is considered as described above, and the configuration in which the photodiode PD is used as the conversion unit 201 for converting radiation into an electric signal (charge) is shown. However, it is not limited to this. As the conversion unit 201 for converting radiation into an electric signal, for example, a direct type conversion element that directly converts radiation into an electric signal may be used.

Capacities Cfd, C1, C2, transistors M2, M3, M4, M17, M18, M19, and M20 are further arranged in the conversion unit 201. The capacitance Cfd is the capacitance of the floating diffusion (floating diffusion region) for accumulating the electric charge generated by the photodiode PD. In addition, the capacitance Cfd may also include a parasitic capacitance parasitic on the photodiode PD. The capacitance C1 is an additional capacitance for changing the sensitivity of the conversion unit 201 to radiation from a high-sensitivity mode using only the capacitance Cfd to a medium-sensitivity mode having a lower sensitivity than the high-sensitivity mode. It can be said that the medium-sensitivity mode has a wider dynamic range than the high-sensitivity mode. The transistor M17 is a switch arranged in a path connecting the output node of the photodiode PD and the capacitance C1 which is an additional capacitance. More specifically, the transistor M17 is a switch element for switching the sensitivity of the pixel PIX to radiation from high sensitivity to medium sensitivity. The capacitance C2 is an additional capacitance for changing the sensitivity of the conversion unit 201 to radiation from a medium-sensitivity mode using the capacitances Cfd and C1 to a low-sensitivity mode having a lower sensitivity than the medium-sensitivity mode. It can be said that the low-sensitivity mode has a wider dynamic range than the medium-sensitivity mode. The transistor M18 is an additional switch arranged in a path connecting the output node of the photodiode PD and the additional capacitance C2. More specifically, the transistor M18 is a switch element for switching the sensitivity of the pixel PIX to radiation from medium sensitivity to low sensitivity by turning on the transistor M18 together with the transistor M17.

The transistor M2 is a reset switch for discharging the electric charge accumulated in the photodiode PD, the capacitances Cfd, C1 and C2. When the transistors M3, M4 and the current source IS1 are arranged in a path connecting the output node of the photodiode PD, which is a conversion element, and the sample hold portion 203 (hereinafter, referred to as a source follower circuit including the transistor M4). There is.). The source follower circuit including the transistor M4 outputs a signal corresponding to the electric charge generated in the photodiode PD in the high sensitivity mode. The transistor M4 is an amplification transistor (pixel amplifier) for operating as a source follower by connecting the gate to the output node of the photodiode PD. The transistor M3 is arranged in a path connecting the source of the transistor M4 and the current source IS1, and is a selection switch for operating the transistor M4, which is an amplification transistor, as a source follower. When the transistor M3, which is a selection switch, is turned on, the source follower circuit including the transistor M4 is put into an operating state. When the transistors M19, M20 and the current source IS1 are arranged in a path connecting the output node of the photodiode PD, which is a conversion element, and the sample hold unit 203 (hereinafter, referred to as a source follower circuit including the transistor M20). There is.). The source follower circuit including the transistor M20 outputs a signal corresponding to the charge generated in the photodiode PD in the medium-sensitivity and low-sensitivity modes. The transistor M20 is an amplification transistor (pixel amplifier) for operating as a source follower by connecting the gate to the output node of the photodiode PD. The transistor M19 is arranged in a path connecting the source of the transistor M20 and the current source IS, and is a selection switch for operating the transistor M20, which is an amplification transistor, as a source follower. When the transistor M19, which is a selection switch, is turned on, the source follower circuit including the transistor M20 is put into an operating state.

The output of the source follower circuit including the transistor M4 and the output of the source follower circuit including the transistor M20 are connected to a common node. A clamp circuit 202 for removing kTC noise generated in the conversion unit 201 including the photodiode PD is provided in the subsequent stage of the transistors M3 and M19 connected to the common node. The capacitance Ccl is the clamp capacitance, and the transistor M5 is a clamp switch for clamping. The transistors M6 and M7 and the current source IS2 are source follower circuits for outputting a signal to the sample hold unit 203. The transistor M7 is an amplification transistor (pixel amplifier) for operating as a source follower by connecting a gate to an output node having a clamp capacitance of Ccl. The transistor M6 is arranged in a path connecting the source of the transistor M7 and the current source IS2, and is a selection switch for operating the transistor M7, which is an amplification transistor, as a source follower. When the transistor M6, which is a selection switch, is turned on, the source follower circuit including the transistors M6, M7 and the current source IS2 (hereinafter, may be referred to as a source follower circuit including the transistor M7) is put into an operating state.

A sample hold portion 203 provided with two sample hold circuits is arranged after the transistor M6. The sample hold unit 203 includes sampling switches M8 and M14 arranged on a path connecting the hold capacitances CS and CN and the outputs of the source follower circuit including the hold capacitances CS and CN and the transistor M4 and the output of the source follower circuit including the transistor M20. And, including. The transistor M8 is a sampling switch that constitutes a sample hold circuit for accumulating an optical signal that is a pixel signal for an image generated by a photodiode PD by light converted from radiation. The hold capacitance CS is a hold capacitance for holding the sampled optical signal. The transistor M14 is a sampling switch that constitutes a sample hold circuit for accumulating a reference voltage signal generated by the photodiode PD without irradiating it with radiation. The hold capacitance CN is a hold capacitance for holding the sampled reference signal. The transistor M10 is an optical signal amplification transistor (pixel amplifier) that operates as a source follower. The analog switch M9 is a transfer switch for outputting the optical signal amplified by the transistor M10 to the optical signal output unit S, respectively. The transistor M16 is a reference signal amplification transistor (pixel amplifier) that operates as a source follower. The analog switch M15 is a transfer switch for outputting the reference signal amplified by the transistor M16 to the reference signal output unit N.

The signals EN1 and EN2 are control signals connected to the gates of the transistors M3 and M19, respectively, to control the operating state of the source follower circuit including the transistors M4 and M20. When the signal EN1 is at a high level, the source follower circuit including the transistor M4 is in the operating state. Similarly, when the signal EN2 is at a high level, the source follower circuit including the transistor M20 is in the operating state. The signal EN3 is a control signal connected to the gate of the transistor M6 and for controlling the operating state of the source follower circuit including the transistor M7. When the signal EN3 is at a high level, the source follower circuit including the transistor M4 is in the operating state, and a signal is output from the clamp circuit 202 to the sample hold unit 203.

The signal PRESS is a control signal (reset signal) connected to the gate of the transistor M2 and for controlling the operating state of the transistor M2. When the signal PRESS is at a high level, the transistor M2 is turned on and discharges the charges stored in the photodiode PD, the capacitances Cfd, C1 and C2.

The signal PCL is a control signal connected to the gate of the transistor M5 to control the transistor M5. When the signal PCL is at a high level, the transistor M5 is turned on and the capacitance Ccl is set to the reference voltage VCL.

The signal TS is a control signal connected to the gate of the transistor M8 and controlling sampling of an optical signal. By setting the signal TS to a high level for all the pixels PIX at once and turning on the transistor M8, the optical signal is collectively transferred to the hold capacitance CS via the transistor M7. Next, the signal TS is set to the low level for all the pixels PIX at once, and the transistor M8 is turned off, so that the sampling of the optical signal to the hold capacitance CS of the sample hold circuit is completed. As described above, the sample hold unit 203 can sample the pixel signals (optical signals) generated by the photodiode PD at the same time in each of the plurality of pixel PIXs with different sensitivities. The signal TN is a control signal connected to the gate of the transistor M14 and controlling the sampling of the reference signal. By setting the signal TN to a high level and turning on the transistor M14 for all the pixels PIX at once, the reference signal is collectively transferred to the hold capacitance CN via the transistor M7. Next, by setting the signal TN to a low level for all the pixels and turning off the transistor M14, sampling of the reference signal to the hold capacitance CN of the sample hold circuit is completed. As for the reference signal, the sample hold unit 203 can simultaneously sample each of the plurality of pixels PIX. After sampling to the hold capacitances CS and CN, the transistors M8 and M14 are turned off, and the hold capacitances CS and CN are separated from the conversion unit 201 and the clamp circuit 202 in the previous stage. Therefore, the optical signal and the reference signal sampled in the hold capacitance CS and CN can be read out non-destructively by making the analog switches M9 and M15 conductive, respectively, until sampling is performed again. That is, the optical signal and the reference signal held while the transistors M8 and M14 are in the non-conducting state can be read out at an arbitrary timing.

In the present embodiment, the sample hold unit 203 includes two hold capacitances CS and CN and transistors M8 and M14 which are two sampling switches corresponding to the two hold capacitances CS and CN, respectively. However, it is not limited to this. For example, the hold capacitance and the transistor functioning as a sampling switch may be one by one. Further, three or more hold capacities and sampling switches corresponding to the respective hold capacities may be arranged.

In this embodiment, each of the transistors M2, M3, M4, M5, M6, M7, M8, M14, M17, M18, M19, and M20 shown in FIG. 2 is a p-type transistor. However, the present invention is not limited to this, and each pixel PIX may be configured by appropriately using an n-type transistor. The arrangement and configuration of each component may be appropriately changed according to the conductive type of the transistor.

FIG. 3 is a timing diagram showing an example of drive control in the pixel PIX shown in FIG. 2 when the transistor M17 is turned on and a moving image is captured in a medium sensitivity mode. Hereinafter, the timing of the control signal until the electric charge is sampled in the hold capacitances CS and CN when the moving image is captured will be described.

First, at time t1, the user sets the imaging mode such as the medium sensitivity mode such as the sensitivity and the accumulation time at the time of imaging, and then the imaging start setting is made. Then, at time t2, when the control unit 109 detects that the external synchronization signal has reached a high level, the drive for imaging is started.

Here, the reset drive R starting from the time t3 will be described. The reset drive R is a drive for resetting and clamping. First, at time t3, the control unit 109 raises the signal EN2 and the signal EN3 to a high level, and puts the source follower circuit including the transistor M20 and the source follower circuit including the transistor M7 into an operating state. Here, when each signal such as the signal EN2 becomes a high level, it means that the transistor controlled by each signal (for example, the transistor M19 controlled by the signal EN2) is turned on. Further, when each signal becomes low level, it means that the transistor controlled by each signal is turned off.

At time t3, the control unit 109 further sets the signal WIDE1 and the signal PRESS to a high level, sets the signal WIDE2 to a low level, turns the transistor M17 on, and connects the photodiode PD to the reference voltage VRES. Further, the control unit 109 turns on the transistor M5 by raising the signal PCL to a high level, and the reference voltage VCL is connected to the side of the transistor M7 having the capacitance Ccl. At the same time, the control unit 109 sets the signals TS and TN to high levels and turns on the transistors M8 and M14.

Next, at time t4, the control unit 109 sets the signal PRESS to a low level, ends the reset, and sets the reset voltage on the side of the transistor M4 having the capacitance Ccl. Further, the capacitance C1 is also held on the side of the transistor M17 by the reset voltage VRES to prevent an indefinite voltage from being generated. Further, the control unit 109 turns off the transistor M5, charges corresponding to the voltage difference between the reference voltage VCL and the reference voltage VRES are accumulated in the capacitance Ccl, and the clamping is completed. Further, the control unit 109 also turns off the transistors M8 and M14, and samples the reference signal when the reference voltage VCL is set in the hold capacitance CS for the optical signal and the hold capacitance CN for the reference signal. The influence of the afterimage is reduced by making the charges of the hold capacitance CS and the hold capacitance CN constant before sampling the signal for the image.

The reset drive R ends at time t4, and from time t4, charge accumulation in imaging in the medium-sensitivity mode in which the transistor M17 is on in the pixel PIX is started. Since the pixel PIX is in the accumulated state, the control unit 109 enables the exposure permission signal 114 and requests radiation exposure. Further, the control unit 109 sets the signal EN2 and the signal EN3 to a low level, and puts the source follower circuit including the transistor M4 and the source follower circuit including the transistor M7 into a non-operating state.

The reset drive R is collectively performed for all the pixels PIX arranged in the radiation imaging apparatus 100. The subsequent reset drive R is also controlled at the same timing. At the same timing and the same period in all the pixel PIXs arranged in the radiation imaging apparatus 100, in order to prevent the image shift caused by the time switching shift between the pixels and the scanning lines when capturing a moving image or a still image. Reset drive R can be performed at. After that, the charge is accumulated by irradiation with radiation, and the signal charge generated in the photodiode PD of each pixel PIX is accumulated in the parasitic capacitances of the capacitances Cfd, C1 and the photodiode PD.

Next, the sampling drive S starting from time t11 will be described. At time t11, the control unit 109 turns on the transistor M19 by setting the signal EN2 to a high level, and puts the source follower circuit including the transistor M20 into an operating state. Further, the control unit 109 turns on the transistor M6 by setting the signal EN3 to a high level, and puts the source follower circuit including the transistor M7 into an operating state. As a result, the charges stored in the capacitances Cfd and C1 are charged / voltage converted and output to the capacitance Ccl as a voltage from the transistor M20 operating as a source follower. The output of the transistor M20 includes reset noise, but since the side of the transistor M7 having a capacitance Ccl is set to the reference voltage VCL when the reset drive R is performed by the clamp circuit 202, the optical signal from which the reset noise has been removed is set. Is output to the transistor M7. At this time, the signal EN1 is still at the low level, and the transistor M3 is in the off state. Therefore, the source follower circuit including the transistor M4 is in a non-operating state.

Next, at time t12, the control unit 109 sets the signal EN2 and the signal WIDE1 to the low level, and sets the signal EN1 to the high level. As a result, the pixel PIX switches to a high-sensitivity mode in which the transistor M17 is in the off state, the source follower circuit including the transistor M20 is in the non-operating state, and the source follower circuit including the transistor M4 is in the operating state. Next, at time t13, the control unit 109 sets the signal EN1 to the low level and the signal EN2 and the signal WIDE1 to the high level. As a result, the pixel PIX is placed in a medium-sensitivity mode in which the transistor M17 is in the on state, the source follower circuit including the transistor M20 is in the operating state, and the transistor M3 is in the off state, so that the source follower circuit including the transistor M4 is in the non-operating state. return. Next, at time t14, the control unit 109 sets the signal TS to a high level and turns on the transistor M8, so that the optical signal is collectively transferred to the hold capacitance CS for the optical signal through the source follower circuit including the transistor M7. NS. The optical signal at this time is a signal captured in the medium sensitivity mode during irradiation of radiation because the signal WIDE1 has a high level and the signal WIDE2 has a low level. At the following time t15, the control unit 109 disables the exposure permission signal 114 and stops the radiation exposure. At this time, the control unit 109 sets the signal TS to the low level and turns off the transistor M8, so that the signal acquired in the medium sensitivity mode is sampled in the hold capacitance CS.

Next, at time t16, the control unit 109 sets the reset signal PRESS to a high level, turns on the transistor M2, and resets the capacitances Cfd and C1 to the reference voltage VRES. Subsequently, at time t17, the control unit 109 switches the pixel PIX to the high-sensitivity mode with the signal EN2 and the signal WIDE1 at the low level and the signal EN1 at the high level, similarly to the time t12. Further, at the time t18, the control unit 109 sets the signal EN1 to the low level, sets the signal EN2 and the signal WIDE1 to the high level, and returns the pixel PIX to the medium sensitivity mode, similarly to the time t13. Next, at time t19, the control unit 109 sets the signal PCL to a high level. A charge in which reset noise is superimposed on the voltage difference between the voltage VCL and the voltage VRES is accumulated in the capacitance Ccl. Next, at time t20, the control unit 109 sets the signal TN to a high level and turns on the transistor M14 to transfer the reference signal when set to the reference voltage VCL to the hold capacitance CN for the reference signal. .. By this operation, a reference signal which is a signal imaged without irradiating radiation is acquired. At time t21, the control unit 109 sets the signal TN to a low level and turns off the transistor M14, so that the reference signal is sampled in the hold capacitance CN. At time t22, the control unit 109 sets the reset signal PRESS to a low level and completes the reset. At time t23, the control unit 109 sets the signal PCL to a low level, then sets the signals EN2 and EN3 to a low level at time t24, and ends the sampling drive S.

Sampling drive S is performed collectively for all pixel PIX. Subsequent sampling drive is also controlled at the same timing. When it is detected that the external synchronization signal becomes a high level after the sampling drive S, the reset drive R is performed again from the time t51, and the accumulation in the photodiode PD of the next frame is started.

When imaging is performed in the medium sensitivity mode, the source voltage of the transistor M4 may increase due to the leakage current of the transistor M3 in the source follower circuit including the transistor M4 for high sensitivity. When the source voltage of the transistor M4 rises, the voltage of the output node of the photodiode PD rises through the parasitic capacitance between the gate and the source of the transistor M4, which may cause an artifact. This effect can be significant when the amount of radiation is large and the accumulation time is long.

On the other hand, in the imaging in the medium sensitivity mode, after the conversion unit 201 starts accumulating charges while the transistor M17 is on and before the sample hold unit 203 samples the signal, for a predetermined period of time. The first operation is executed in which the transistor M17 is in the off state, the transistor M3 which is the selection transistor is in the on state, and the source follower circuit including the transistor M4 is in the operating state (time t12 to time t13). Following this first operation, the transistor M17 is turned on, and the second operation of sampling the signal by the sample hold unit 203 via the source follower circuit including the transistor M20 is executed (time t13 to time t15). Before sampling the optical signal, the first operation (time t12 to time t13) of setting the pixel PIX to the high-sensitivity mode is performed, so that the source voltages of the transistor M4 and the transistor M20 become equal. This makes it possible to suppress the influence of the leakage current of the transistor M3 of the source follower circuit including the transistor M4 which is not used in the medium sensitivity mode. As a result, it becomes possible to suppress the occurrence of artifacts.

Further, not only in the imaging in which the optical signal generated by the conversion unit 201 by irradiation with radiation is sampled, but also in the imaging in which the reference signal generated by the conversion unit 201 is sampled without irradiation with radiation, the second operation (time t18). -Before the time t21), the first operation (time t17 to time t18) for setting the pixel PIX to the high-sensitivity mode is executed. This makes it possible to further suppress the occurrence of artifacts and improve the image quality of the obtained radiation image.

The reading scan of the optical signal and the reference signal is performed for each pixel PIX. By turning on the analog switches M9 and M15, respectively, the voltage of the hold capacitance CS for the optical signal and the voltage of the hold capacitance CN for the reference signal are transferred to the optical signal output unit S, respectively, via the transistors M10 and M16. It is output to the corresponding column signal line via the reference signal output unit N.

In the pixel PIX shown in FIG. 2, the timing of starting the accumulation of the photodiode PD is the time t4 when the signal PCL becomes low level and the clamping is completed after the end of the reset drive R shown in FIG. Further, the timing of the end of charge accumulation of the conversion unit 201 is the time t15 when the signal TS becomes low level, the exposure permission signal 114 is disabled, and the optical signal is sampled. After the end of the sampling drive S, a read process for reading an optical signal and a reference signal from the pixel PIX is performed from time t25.

FIG. 4 is a diagram schematically showing a configuration example of the internal structure of the sensor unit 120. Each sensor unit 120 has a chip select terminal CS, an optical signal output terminal TS, a reference signal output terminal TN, a vertical scanning circuit start signal terminal VST, a vertical scanning circuit clock terminal CLKV, a horizontal scanning circuit start signal terminal HST, and a horizontal scanning circuit. Includes each terminal of the clock terminal CLKH. Further, in the sensor unit 120, m pixels in the column direction and n pixels in the row direction are arranged in a two-dimensional array. The vertical scanning circuit 403 selects pixel PIXs arranged in the row direction for each row, and sequentially scans the pixel group in the vertical direction, which is the sub-scanning direction, in synchronization with the vertical scanning clock CLKV. The vertical scanning circuit 403 may be composed of, for example, a shift register. The horizontal scanning circuit 404 sequentially selects one pixel at a time in synchronization with the horizontal scanning clock CLKH, for the column signal lines of the pixels PIX in the column direction, which is the main inspection direction selected by the vertical scanning circuit 403. Each pixel PIX outputs a sampled optical signal and a reference signal to the column signal lines 406 and 407, respectively, by enabling the row signal line 405 connected to the vertical scanning circuit 403. When the horizontal scanning circuit 404 sequentially selects the signals output to the column signal lines 406 and 407, the signals of the pixel PIX are sequentially output to the analog output lines 408 and 409, respectively. As described above, in the sensor unit 120, the pixel PIX is selected by the switching operation by the XY address method using the vertical scanning circuit 403 and the horizontal scanning circuit 404. The optical signal and the reference signal of each pixel PIX are output from the optical signal output terminal TS and the reference signal output terminal TN through the column signal lines 406 and 407 and the analog output lines 408 and 409.

FIG. 5 is a diagram showing a configuration example of a reading unit 106 including a differential amplifier 107 for A / D conversion of an optical signal and a reference signal output from each pixel PIX and an A / D converter 108. The output of the optical signal output terminal TS is input to the negative side of the differential amplifier 107, and the output of the reference signal output terminal TN is input to the positive input side. By subtracting the optical signal from the reference signal with the differential amplifier 107, fixed pattern noise (FPN) and the like due to process variation in each pixel amplifier in the pixel PIX can be removed. The output of the differential amplifier 107 is input to the A / D converter 108. The A / D converter 108 receives the clock signal from the signal ADCLK, and outputs the A / D converted digital optical signal ADOUT to the control unit 109 for each sensor unit 120 at the timing when the signal ADCLK is switched to the high level.

Next, with reference to FIG. 6, an example of drive control for continuously acquiring a plurality of images having different sensitivities when capturing a moving image will be described. FIG. 6 is a timing diagram when images of medium sensitivity and low sensitivity are continuously acquired. In the timing diagram shown in FIG. 3, only the imaging in the medium sensitivity mode is executed in response to the one-time external synchronization signal, whereas the imaging shown in FIG. 6 is performed in response to the one-time external synchronization signal. The signal accumulated in the conversion unit 201 is acquired in two different sensitivity modes, medium sensitivity and low sensitivity. Since the operation from the setting by the user at time 1 to the time t4 at which the reset drive R ends may be the same as the operation described with reference to FIG. 3, the description thereof is omitted here and is referred to as the operation of FIG. Will focus on the different parts.

From time t11, the sampling drive SM of the optical signal in the medium sensitivity mode is started. First, at time t11, the control unit 109 turns on the transistor M19 by setting the signal EN2 to a high level, and puts the source follower circuit including the transistor M20 into an operating state. Further, the control unit 109 turns on the transistor M6 by setting the signal EN3 to a high level, and puts the source follower circuit including the transistor M7 into an operating state. As a result, the charges stored in the capacitances Cfd and C1 are charged / voltage converted and output to the capacitance Ccl as a voltage from the transistor M20 operating as a source follower. The output of the transistor M20 includes reset noise, but since the side of the transistor M7 having a capacitance Ccl is set to the reference voltage VCL when the reset drive R is performed by the clamp circuit 202, the optical signal from which the reset noise has been removed is set. Is output to the transistor M7. At this time, the signal EN1 is at a low level, and the transistor M3 is in the off state. Therefore, the source follower circuit including the transistor M4 is in a non-operating state.

Next, at time t12, the control unit 109 sets the signal EN2 and the signal WIDE1 to the low level, and sets the signal EN1 to the high level. As a result, the pixel PIX switches to a high-sensitivity mode in which the transistor M17 is in the off state, the source follower circuit including the transistor M20 is in the non-operating state, and the source follower circuit including the transistor M4 is in the operating state. Next, at time t13, the control unit 109 sets the signal EN1 to the low level and the signal EN2 and the signal WIDE1 to the high level. As a result, the pixel PIX returns to the medium-sensitivity mode in which the transistor M17 is on, the source follower circuit including the transistor M20 is in the operating state, and the source follower circuit including the transistor M4 is in the non-operating state. Next, at time t14, the control unit 109 sets the signal TS to a high level and turns on the transistor M8, so that the optical signal is collectively transferred to the hold capacitance CS for the optical signal through the source follower circuit including the transistor M7. NS. The optical signal at this time is a signal acquired in the medium sensitivity mode because the signal WIDE1 has a high level and the signal WIDE2 has a low level. At the following time t15, the control unit 109 disables the exposure permission signal 114 and stops the radiation exposure. At this time, the control unit 109 sets the signal TS to the low level and turns off the transistor M8, so that the signal acquired in the medium sensitivity mode is sampled in the hold capacitance CS.

Next, at time t16, the control unit 109 sets the signals WIDE1 and WIDE2 to high levels and turns on the transistors M17 and M18. When the transistors M17 and M18 are turned on, the capacitance connected to the output node of the photodiode PD increases, and the sensitivity of the pixel PIX changes from medium sensitivity to low sensitivity. At time t17, the control unit 109 sets the signals EN2 and EN3 to low levels and ends the sampling drive SM in the medium sensitivity mode. After the end of the sampling drive SM at the medium sensitivity, the optical signal obtained in the medium sensitivity mode is read from time t18 (the period of “ROM” in FIG. 6).

After all the optical signals acquired in the medium sensitivity mode are read out, the sampling drive SL with low sensitivity is started from time t31. First, at time t31, the control unit 109 turns on the transistor M19 by setting the signal EN2 to a high level, and puts the source follower circuit including the transistor M20 into an operating state. Further, the control unit 109 turns on the transistor M6 by setting the signal EN3 to a high level, and puts the source follower circuit including the transistor M7 into an operating state. As a result, the charges stored in the capacitances Cfd, C1 and C2 are charge / voltage converted and output to the capacitance Ccl as a voltage from the transistor M20 operating as a source follower. The output of the transistor M20 includes reset noise, but since the side of the transistor M7 having a capacitance Ccl is set to the reference voltage VCL when the reset drive R is performed by the clamp circuit 202, the optical signal from which the reset noise has been removed is set. Is output to the transistor M7. At this time, the signal EN1 is at a low level, and the transistor M3 is in the off state. Therefore, the source follower circuit including the transistor M4 is in a non-operating state.

Next, at time t32, the control unit 109 sets the signal EN2 and the signals WIDE1 and WIDE2 to the low level, and sets the signal EN1 to the high level. As a result, the pixel PIX switches to a high-sensitivity mode in which the transistors M17 and M18 are in the off state, the source follower circuit including the transistor M20 is in the non-operating state, and the source follower circuit including the transistor M4 is in the operating state. At this time, the high level of the signal WIDE2 is maintained, and the transistor M18 may be in the ON state. Next, at time t33, the control unit 109 sets the signal EN1 to the low level and sets the signal EN2 and the signals WIDE1 and WIDE2 to the high level. As a result, the pixel PIX has low sensitivity in which the transistors M17 and M18 are in the on state, the source follower circuit including the transistor M20 is in the operating state, the transistor M3 which is the selection transistor is in the off state, and the source follower circuit including the transistor M4 is in the non-operating state. Return to the mode of. Next, at time t34, the control unit 109 sets the signal TS to a high level and turns on the transistor M8, so that the optical signal is collectively transferred to the hold capacitance CS for the optical signal through the source follower circuit including the transistor M7. NS. The optical signal at this time is a signal acquired in the low sensitivity mode because the signals WIDE1 and WIDE2 are set to high levels. At the subsequent time t35, the control unit 109 sets the signal TS to the low level and turns off the transistor M8, so that the signal acquired in the low-sensitivity mode is sampled in the hold capacitance CS.

Next, at time t36, the control unit 109 sets the reset signal PRESS to a high level, turns on the transistor M2, and resets the capacitances Cfd, C1, and C2 to the reference voltage VRES. Subsequently, at the time t37, the control unit 109 switches the pixel PIX to the high-sensitivity mode with the signal EN2 and the signals WIDE1 and WIDE2 at the low level and the signal EN1 at the high level, similarly to the time t32. Further, at the time t38, the control unit 109 sets the signal EN1 to the low level, sets the signal EN2 and the signals WIDE1 and WIDE2 to the high level, and returns the pixel PIX to the low sensitivity mode, similarly to the time t33. Next, at time t39, the control unit 109 sets the signal PCL to a high level. A charge in which reset noise is superimposed on the voltage difference between the voltage VCL and the voltage VRES is accumulated in the capacitance Ccl. Next, at time t40, the control unit 109 sets the signal TN to a high level and turns on the transistor M14 to transfer the reference signal when set to the reference voltage VCL to the hold capacitance CN for the reference signal. .. At time t41, the control unit 109 sets the signal TN to a low level and turns off the transistor M14, so that the reference signal is sampled in the hold capacitance CN. At time t42, the control unit 109 sets the reset signal PRESS to a low level and completes the reset. At time t43, the control unit 109 sets the signal PCL to a low level, and then at time t44, the control unit 109 sets the signals EN2 and EN3 to a low level and ends the sampling drive S. After the end of the sampling drive SL with low sensitivity, the reading process of the optical signal obtained in the low sensitivity mode is performed from time t45 (the period of "ROL" in FIG. 6).

Sampling drive SM in the medium sensitivity mode and sampling drive SL in the low sensitivity mode perform all pixels at once. It is performed collectively for all pixel PIX. Subsequent sampling drive is also controlled at the same timing. When it is detected that the external synchronization signal becomes a high level after the sampling drive S, the reset drive R is performed again from the time t51, and the accumulation in the photodiode PD of the next frame is started.

Also in the operation shown in FIG. 6, the first operation (time t12 to time t13, time t32 to time t33) of setting the pixel PIX to the high sensitivity mode before sampling the optical signal in the medium sensitivity and low sensitivity modes. By doing so, the source voltages of the transistor M4 and the transistor M20 are made equal. This makes it possible to suppress the influence of the leakage current of the transistor M3 of the source follower circuit including the transistor M4 which is not used in the medium sensitivity and low sensitivity modes. As a result, it becomes possible to suppress the occurrence of artifacts.

Further, not only in the imaging in which the optical signal generated by the conversion unit 201 by irradiation with radiation is sampled, but also in the imaging in which the reference signal generated by the conversion unit 201 is sampled without irradiation with radiation, the second operation (time t38). The first operation (time t37 to time t38) for setting the pixel PIX to the high-sensitivity mode is executed before the time t41). This makes it possible to further suppress the occurrence of artifacts and improve the image quality of the obtained radiation image.

In the pixel PIX shown in FIG. 2, the timing of starting the accumulation of the photodiode PD is the time t4 when the signal PCL becomes low level and the clamping is completed after the end of the reset drive R shown in FIG. Further, the timing of the end of charge accumulation of the conversion unit 201 is the time t15 when the signal TS becomes low level, the exposure permission signal 114 is disabled, and the optical signal in the medium sensitivity mode is sampled.

Next, with reference to FIG. 7, an example of drive control for continuously acquiring a plurality of images having different sensitivities when capturing a moving image will be described. FIG. 7 is a timing diagram when images of high sensitivity and low sensitivity are continuously acquired. In the operation of FIG. 7, as compared with the operation of FIG. 6, the image is acquired in the high-sensitivity mode instead of the medium-sensitivity mode, and only the optical signal is sampled in the sampling drive SL in the low-sensitivity mode. It is different in that it is. Since the operations other than this may be the same as the operations described with reference to FIG. 6, the differences will be mainly described.

The operation up to time t4 is the same as the operation of FIGS. 3 and 6 described above. On the other hand, in order to perform imaging in the high-sensitivity mode, at time t4, the control unit 109 controls the signals WIDE1 and WIDE2 at a low level, and the capacitance connected to the output node of the photodiode PD is limited to the capacitance Cfd. ..

Next, the sampling drive SH with high sensitivity starting from time t11 will be described. At time t11, the control unit 109 turns on the transistor M3 by setting the signal EN1 to a high level, and puts the source follower circuit including the transistor M4 into an operating state. Further, the control unit 109 turns on the transistor M6 by setting the signal EN3 to a high level, and puts the source follower circuit including the transistor M7 into an operating state. As a result, the charge stored in the capacitance Cfd is converted into charge / voltage and output to the capacitance Ccl as a voltage from the transistor M4 that operates as a source follower. The output of the transistor M4 includes reset noise, but since the side of the transistor M7 having a capacitance Ccl is set to the reference voltage VCL when the reset drive R is performed by the clamp circuit 202, the optical signal from which the reset noise has been removed is set. Is output to the transistor M7. At this time, the signal EN2 is at a low level, and the transistor M19 is in the off state. Therefore, the source follower circuit including the transistor M20 is in a non-operating state.

Next, at time t14, the control unit 109 sets the signal TS to a high level and turns on the transistor M8, so that the optical signal is collectively transferred to the hold capacitance CS for the optical signal through the source follower circuit including the transistor M7. NS. Since the optical signals at this time have the signals WIDE1 and WIDE2 at low levels, they are signals acquired in the high-sensitivity mode. At the following time t15, the control unit 109 disables the exposure permission signal 114 and stops the radiation exposure. At this time, the control unit 109 sets the signal TS to the low level and turns off the transistor M8, so that the signal acquired in the high-sensitivity mode is sampled in the hold capacitance CS.

Next, at time t16, the control unit 109 sets the signals WIDE1 and WIDE2 to high levels and turns on the transistors M17 and M18. When the transistors M17 and M18 are turned on, the capacitance connected to the output node of the photodiode PD increases, and the sensitivity of the pixel PIX changes from high sensitivity to low sensitivity. At time t17, the control unit 109 sets the signals EN1 and EN3 to low levels, and ends the sampling drive SH in the high-sensitivity mode. After the end of the sampling drive SH with high sensitivity, the reading process of the optical signal obtained in the high sensitivity mode is performed from time t18 (the period of “ROH” in FIG. 7).

After all the optical signals acquired in the high-sensitivity mode are read out, the sampling drive SL with low sensitivity is started from time t31. First, at time t31, the control unit 109 turns on the transistor M19 by setting the signal EN2 to a high level, and puts the source follower circuit including the transistor M20 into an operating state. Further, the control unit 109 turns on the transistor M6 by setting the signal EN3 to a high level, and puts the source follower circuit including the transistor M7 into an operating state. As a result, the charges stored in the capacitances Cfd, C1 and C2 are charge / voltage converted and output to the capacitance Ccl as a voltage from the transistor M20 operating as a source follower. The output of the transistor M20 includes reset noise, but since the side of the transistor M7 having a capacitance Ccl is set to the reference voltage VCL when the reset drive R is performed by the clamp circuit 202, the optical signal from which the reset noise has been removed is set. Is output to the transistor M7. At this time, the signal EN1 is at a low level, and the transistor M3 is in the off state. Therefore, the source follower circuit including the transistor M4 is in a non-operating state.

Next, at time t32, the control unit 109 sets the signal EN2 and the signals WIDE1 and WIDE2 to the low level, and sets the signal EN1 to the high level. As a result, the pixel PIX switches to a high-sensitivity mode in which the transistors M17 and M18 are in the off state, the source follower circuit including the transistor M20 is in the non-operating state, and the source follower circuit including the transistor M4 is in the operating state. Next, at time t33, the control unit 109 sets the signal EN1 to the low level and sets the signal EN2 and the signals WIDE1 and WIDE2 to the high level. As a result, the pixel PIX returns to the low-sensitivity mode in which the transistors M17 and M18 are on, the source follower circuit including the transistor M20 is in the operating state, and the source follower circuit including the transistor M4 is in the non-operating state. Next, at time t34, the control unit 109 sets the signal TS to a high level and turns on the transistor M8, so that the optical signal is collectively transferred to the hold capacitance CS for the optical signal through the source follower circuit including the transistor M7. NS. The optical signal at this time is a signal acquired in the low sensitivity mode because the signals WIDE1 and WIDE2 are set to high levels. At the subsequent time t35, the control unit 109 sets the signal TS to the low level and turns off the transistor M8, so that the signal acquired in the low-sensitivity mode is sampled in the hold capacitance CS.

Next, at time t36, the control unit 109 sets the signals EN2 and EN3 to low levels, and ends the sampling drive SL in the low-sensitivity mode. After the end of the sampling drive SL in the low-sensitivity mode, the optical signal obtained in the low-sensitivity mode is read out from time t38 (the period of “ROL” in FIG. 7).

Also in the operation shown in FIG. 7, the first operation (time t32 to time t33) for setting the pixel PIX to the high sensitivity mode is performed before sampling the optical signal in the low sensitivity mode, so that the transistor M4 and the transistor M4 are used. Make the source voltage of the transistor M20 equal. This makes it possible to suppress the influence of the leakage current of the transistor M3 of the source follower circuit including the transistor M4 which is not used in the low sensitivity mode. As a result, it becomes possible to suppress the occurrence of artifacts.

Although the three types of operations have been described above with reference to FIGS. 3, 6 and 7, these operations may be used in combination as appropriate. For example, in the operation shown in FIG. 3, it is not necessary to sample the reference signal. Further, for example, in the operation shown in FIG. 6, optical signals having high sensitivity and medium sensitivity may be sampled. Further, in the operations shown in FIGS. 6 and 7, the sensitivity is changed and the optical signal is sampled, but the optical signal may be sampled a plurality of times with the same sensitivity. The first operation of putting the pixel PIX into the high sensitivity mode may be performed before sampling the optical signal in the medium and low sensitivity modes.

Further, in the present embodiment, a configuration capable of acquiring an optical signal with three types of sensitivities is shown, but the present invention is not limited to this. The sensitivity that can be selected by the conversion unit 201 may be two types or four or more types. Before sampling the optical signal in a mode other than the most sensitive mode, the first operation of setting the pixel PIX to the most sensitive mode may be executed.

The present invention supplies software (program) that realizes the functions of the above embodiments to a system or device via a network or various storage media, and a computer (CPU, MPU, etc.) of the system or device reads the program. It may be executed. The present invention can also be realized by a process in which one or more processors in a computer of a system or an apparatus reads and executes a program, and can also be realized by a circuit (for example, an ASIC) that realizes one or more functions.

The invention is not limited to the above embodiments, and various modifications and modifications can be made without departing from the spirit and scope of the invention. Therefore, a claim is attached to make the scope of the invention public.

201: Conversion unit, 203: Sample hold unit

Claims (16)

A radiation imaging apparatus including a plurality of pixels including a conversion unit and a sample hold unit.
The conversion unit is arranged in a path connecting a conversion element that generates an electric charge according to radiation, an output node of the conversion element, and the sample hold unit, and is a first source follower that outputs a signal corresponding to the electric charge. The circuit, the additional capacity for changing the sensitivity of the conversion unit from the first sensitivity to the second sensitivity lower than the first sensitivity, and the path connecting the output node and the additional capacity are arranged. It includes a switch, a second source follower circuit arranged in a path connecting the additional capacitance and the sample hold unit, and outputting a signal corresponding to the electric charge.
The first source follower circuit includes an amplification transistor and a selection transistor arranged in a path connecting the amplification transistor and a current source to operate the amplification transistor as a source follower.
In the imaging with the second sensitivity,
The switch is off and the selection transistor is on for a predetermined period of time after the converter has started accumulating charges while the switch is on and before the sample hold has sampled the signal. The first action to be in the state and
Following the first operation, the switch is turned on, and the sample hold unit samples a signal via the second source follower circuit.
A radiation imaging device characterized in that The radiation imaging apparatus according to claim 1, wherein in the second operation, the selection transistor is in an off state. The radiation imaging apparatus according to claim 1 or 2, wherein in the first operation, the second source follower circuit is in a non-operating state. While the converter accumulates charge, the second source follower circuit is in a non-operating state.
In the imaging with the second sensitivity, the third operation that puts the second source follower circuit into the operating state is executed before the first operation, and the first operation is executed after the third operation. The radiation imaging apparatus according to any one of claims 1 to 3, wherein the radiation imaging apparatus is characterized. In the second-sensitivity imaging, the sample holding unit samples the signal generated by the conversion unit by irradiation with radiation, and the sample holds the signal generated by the conversion unit without irradiating radiation. The second imaging, which is sampled by the hold unit, is executed, and
The radiation imaging apparatus according to any one of claims 1 to 4, wherein in the first imaging and the second imaging, the first operation and the second operation are executed. The conversion unit is arranged in a path connecting an additional capacitance for changing the sensitivity of the conversion unit to a third sensitivity lower than the second sensitivity, and the switch and the additional capacitance. Including additional switches,
1. The first operation and the second operation following the first operation are executed in the imaging with the third sensitivity in the state where the switch and the additional switch are on. The radiation imaging apparatus according to any one of 5 to 5. 6. The image according to claim 6, wherein in the imaging with the third sensitivity, the additional switch is in the off state during the first operation, and the additional switch is in the on state during the second operation. The radiation imaging apparatus according to. In the third-sensitivity imaging, a third imaging that samples a signal generated by the conversion unit by irradiation with radiation, and a fourth imaging that samples a signal generated by the conversion unit without irradiating radiation. Is executed,
The radiation imaging apparatus according to claim 6 or 7, wherein in the third imaging and the fourth imaging, the first operation and the second operation are executed. The amplification transistor is used as the first amplification transistor, and the selection transistor is used as the first selection transistor.
The second source follower circuit is arranged in a path connecting the second amplification transistor, the second amplification transistor, and the current source, and a second selection transistor for operating the second amplification transistor as a source follower. The radiation imaging apparatus according to any one of claims 1 to 8, wherein the radiation imaging apparatus comprises. The radiation imaging apparatus according to any one of claims 1 to 9, wherein the output of the first source follower circuit and the output of the second source follower circuit are connected to a common node. The sample hold unit includes a hold capacitance and a sampling switch arranged in a path connecting the hold capacitance and the output of the first source follower circuit and the output of the second source follower circuit.
The radiation imaging apparatus according to any one of claims 1 to 10, wherein when the sampling switch is turned on, the sample hold unit samples a signal in the hold capacitance. The radiation imaging apparatus according to claim 11, wherein the sample holding unit includes a plurality of the holding capacities and a plurality of the sampling switches corresponding to the plurality of the holding capacities. The radiation imaging device according to any one of claims 1 to 12, wherein the radiation imaging device includes a clamp circuit in a path connecting a conversion unit and a sample hold unit. The radiation imaging apparatus according to any one of claims 1 to 13.
A radiation generator that irradiates the radiation imaging device with radiation,
A radiation imaging system characterized by being equipped with. It is a driving method of a radiation imaging apparatus including a plurality of pixels including a conversion unit and a sample hold unit.
The conversion unit is arranged in a path connecting a conversion element that generates an electric charge according to radiation, an output node of the conversion element, and the sample hold unit, and is a first source follower that outputs a signal corresponding to the electric charge. The circuit, the additional capacity for changing the sensitivity of the conversion unit from the first sensitivity to the second sensitivity lower than the first sensitivity, and the path connecting the output node and the additional capacity are arranged. It includes a switch, a second source follower circuit arranged in a path connecting the additional capacitance and the sample hold unit, and outputting a signal corresponding to the electric charge.
The first source follower circuit includes an amplification transistor and a selection transistor arranged in a path connecting the amplification transistor and a current source to operate the amplification transistor as a source follower.
Imaging with the second sensitivity
The switch is off and the selection transistor is on for a predetermined period of time after the converter has started accumulating charges while the switch is on and before the sample hold has sampled the signal. The first step to be in a state and
Following the first step, the switch is turned on, and the sample hold unit samples a signal via the second source follower circuit.
A driving method characterized by including. A program for causing a computer to execute each step of the driving method according to claim 15.

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