JP5567118B2 - ディスプレイ回路及びその動作方法 - Google Patents
ディスプレイ回路及びその動作方法 Download PDFInfo
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
Description
AC 交流
CMOS 相補型MOS(P型及びN型の双方のFETを利用可能)
COM LCD装置のコモン電極
DC 直流
ECB 電気的に制御される複屈折
ESD 静電放電
ESL 電子棚ラベル
FET 電界効果トランジスタ
IC 集積回路
IDS ドレイン−ソース電流
LCD 液晶ディスプレイ
MOS 金属酸化物半導体
MTN ミックスモードねじれネマチック
NMOS NチャネルMOS
OCB 光学的に補償される屈曲
PDLC 高分子分散液晶
RGB 赤、緑、青
RGBW 赤、緑、青、白
RMS 二乗平均平方根
RTN 反射型ねじれネマチック
TFT 薄膜トランジスタ
VGS ゲート−ソース電圧
は、相対的に独立に振る舞う。ここで、ΔVTは閾値シフトであり、VGはデバイスの閾値電圧より低いゲートバイアスであり、tSTは総ストレス時間であり、Aは実験に基づく定数であり、Dは駆動信号の正の部分のデューティサイクルであり、FPWは負ストレス蓄積の周波数依存性を指し示す0と1との間の係数である。一般的に、ストレス誘起閾値シフトは、ゲート駆動振幅(VGS−VT)のおよそ1.5乗から2.0乗に比例するとともに、デューティサイクルを考慮に入れた総ストレス時間の平方根にほぼ比例する(例えば、α+/−〜=1.7且つβ+/−〜=0.4)。およそ二乗則の電圧依存性により、短期間の高振幅ゲート駆動信号は、より長い時間期間にわたって印加される一層低いゲート電圧より有意に大きいストレスを生成し得る。好適な一形態において、ゲート駆動振幅は最小化され、充電時間及びTFTサイズは、必要なVGS駆動を低下させてTFTストレスを最小化するために最大化される。
バックライトと比較して無視できる電力のみを消費する。しかしながら、非常に低いフレームレート(例えば、1Hz)で駆動される反射型フラットパネルディスプレイでは、ESD保護デバイスによって消費される電力は、総電力消費のうちの有意な部分となり得る。低フレームレートのフラットパネルディスプレイの静的電力消散を低減するためには、ESD回路の電力消散を低減することが望ましい。ESDデバイスのサイズを縮小する普通の方法は、そのようなESDデバイスによって提供される静電放電に対する保護を低下させるという望ましくない副作用を有する。この教示により、非常に低いフレームレートのディスプレイで標準的なESD保護デバイスにおける電力消費を最小化する回路及び駆動方法が説明される。
Claims (9)
- ディスプレイ回路を動作させる方法であって、前記ディスプレイ回路は、コモン電極に接続され且つ複数の行信号を介して行ドライバ回路に接続される複数のアクティブマトリクスセルを有し、当該方法は:
前記コモン電極を変調すること;
前記複数のアクティブマトリクスセルに複数の電荷を書き込むこと;及び
前記アクティブマトリクスセルの電荷を維持し且つ前記行ドライバ回路における電力損失を低減するよう、フレーム書込処理の開始時に前記コモン電極の負側への変調と同時に、前記コモン電極の前記負側への変調と同じ極性及び振幅で、前記行信号の全てを変調すること;
を有し、
前記ディスプレイ回路は、行及び列のドライバと、前記行及び列のドライバに結合された複数の画素回路とを有し、各画素回路が、液晶ディスプレイ(LCD)の1つの画素に接続された少なくとも2つの直列のトランジスタを有し、
当該方法は:
前記行及び列のドライバが、前記画素回路の前記トランジスタに第1の負のゲート電圧及び第1の正のゲート電圧を印加して前記LCDの画素への導通経路を形成し、前記導通経路を介して画素に電荷を送ることによって、前記LCDに新たなフレームを書き込むフレーム書込処理と、
フレーム書込処理同士の間に、各画素回路に対して、前記第1の負のゲート電圧より高い第2の負のゲート電圧を印加することと
を有する、
方法。 - 前記第2の負のゲート電圧は、前記画素回路の前記トランジスタのドレーン−ソース電流を最小化する、請求項1に記載の方法。
- フレーム書込処理同士の間に、前記行ドライバは、前記フレーム書込処理のレートより高いレートで、前記画素回路の前記トランジスタの全てより少ないトランジスタに、前記第1の正のゲート電圧より低い第2の正のゲート電圧を印加する、請求項1又は2に記載の方法。
- 前記第2の正のゲート電圧は、画素の前記2つの直列のトランジスタの一方ずつに交互に印加される、請求項3に記載の方法。
- 前記第2の正のゲート電圧は、全ての行に同時に印加される、請求項4に記載の方法。
- 前記行及び列のドライバは、10Hz以下のレートで前記LCDのフレームを更新する、請求項1乃至5の何れか一項に記載の方法。
- 前記行及び列のドライバは、1Hz以下のレートで前記LCDのフレームを更新する、請求項1乃至6の何れか一項に記載の方法。
- 画素アレイ用のディスプレイ回路であって:
行及び列のドライバ;
コモン電極に接続され且つ複数の行信号を介して前記行ドライバに接続される複数のアクティブマトリクス画素;及び
前記行及び列のドライバに結合された複数の画素回路であり、各画素回路が、液晶ディスプレイ(LCD)の1つの画素に接続された少なくとも2つの直列のトランジスタを有する、複数の画素回路;
を有し、
当該ディスプレイ回路は、請求項1乃至7の何れか一項に記載の方法によって動作されるように構成されている、
ディスプレイ回路。 - 前記トランジスタは、水素化アモルファスシリコン薄膜トランジスタ(a−Si:H TFT)を有する、請求項8に記載のディスプレイ回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/424,319 US8248341B2 (en) | 2009-04-15 | 2009-04-15 | Low power active matrix display |
US12/424,319 | 2009-04-15 | ||
PCT/EP2010/054994 WO2010119113A1 (en) | 2009-04-15 | 2010-04-15 | Low power active matrix display |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012524289A JP2012524289A (ja) | 2012-10-11 |
JP5567118B2 true JP5567118B2 (ja) | 2014-08-06 |
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US8248341B2 (en) | 2012-08-21 |
JP2012524289A (ja) | 2012-10-11 |
MX2011010906A (es) | 2012-01-27 |
AU2010238466A1 (en) | 2011-11-03 |
CA2758803C (en) | 2015-12-01 |
EP2419894A1 (en) | 2012-02-22 |
US20100265168A1 (en) | 2010-10-21 |
EP2419894B1 (en) | 2018-11-28 |
AU2010238466B2 (en) | 2015-01-22 |
CA2758803A1 (en) | 2010-10-21 |
DK2419894T3 (en) | 2019-03-04 |
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WO2010119113A1 (en) | 2010-10-21 |
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