JP5531427B2 - Switch, information processing apparatus, arbitration method, and image forming system - Google Patents

Description

The present invention relates to the fields of switches , information processing apparatuses, arbitration methods, and image forming systems.

  In recent years, high-speed serial transmission lines have been put into practical use that have transmission speeds exceeding several Gbps and can transfer data much faster than Ethernet (registered trademark). I / O (In / Out) standards are spreading. For this reason, data communication networks within LSI (Large Scale Integration) chips, between chips, and between boards are also used for embedded electronic devices by packet data communication using serial transmission lines and switches, similar to computer networks. It came to be.

  Specifically, PCI Express (registered trademark: hereinafter sometimes referred to as PCIe) is used for embedded data such as a PC (Personal Computer) system and an MFP (Multi Function Printer) to transfer a large amount of data in the device. It has become like this. As a merit of PCIe, which is a high-speed serial communication standard, it is only necessary to increase the number of lanes in order to expand the bandwidth, and the increase / decrease in bandwidth is more flexible than PCI based on the conventional parallel communication standard. In addition, there are advantages such as reducing the number of terminals of the mounting LSI and reducing the number of wirings on the mounting board. Since it is mass-produced for PCs, one of the merits is that the price of mounted components is relatively low.

  In order to connect multiple PCIe devices to one PCIe system, it is necessary to mount multiple PCIe ports in the system. Usually, since PCIe ports are mounted as LSIs, to increase the number of PCI Express ports after LSI development is completed. In this case, LSI redevelopment or PCI Express Switch (hereinafter sometimes referred to as PCIe SW or simply switch) is used. The adoption of PCIe SW is advantageous in that it eliminates the need for redevelopment of LSIs and can reduce costs (development costs and development time) required for redevelopment. Even in the above-described MFP, if PCIe SW is used for connection between the controller and the scanner and between the controller and the plotter, a plurality of devices can be connected by one controller without changing the controller LSI. Further, for example, it is easy to further expand a plurality of plotter outputs.

  By the way, in a data communication system in which a plurality of devices (data communication devices) are connected via a common communication path and perform data communication with each other, when different types of traffic perform data transfer using the same communication path. There is a problem that contention occurs and communication quality (data transfer rate and continuity) required for each traffic cannot be obtained. Therefore, when there are a plurality of devices on a communication path (such as a bus), the usage right must be assigned to each device in some way. Although the right to use can be assigned in the order of communication that arrives earliest (early win method), depending on the device and application, there is a case where it is desired to give priority to some communication over quality.

  In the current PCIe standard, PCIe SW arbitration function (arbitration function) such as RR (Round Robin), WRR (Weighted Round Robin), and TBWRR (Time Base Weighted Round Robin) Is provided. If these functions are used, an arbitration function (port arbitration function) is provided for each port as long as the transfer is relatively large (for example, a bandwidth utilization rate of about 30% to 70%) with respect to the PCIe bandwidth. Works effectively and gives proper service to the port. FIG. 1 is an example of a diagram schematically showing communication path contention. An example is shown in which when the communication with the device 0 competes, the right of use is assigned to the data communication from the device 2 in the PCIe SW. Furthermore, I will touch on the details of the arbitration function of PCIe SW.

(1) RR (Round Robin) / WRR (Weighted Round Robin)
In the arbitration of the RR method, the communication priority reaches each port in order, and when a communication conflict occurs, the port with the highest priority can perform communication. The port that communicated has the lowest priority. If the other port is not communicating, communication is possible. However, while the other port is communicating, communication is performed until the priority of the own port is increased. It is not possible. When the RR method is used, priority is assigned to each port in order, and if the normal communication state (for example, bandwidth utilization rate of about 30% to 70%), almost equal communication opportunities are assigned to each port. It can be performed.

  The arbitration of the WRR (Weighted Round Robin) method is basically the same as the RR method, but is characterized in that it can be weighted for each port. For example, when a weight of 2: 1 is set for port 1: port 2 and the priority of port 1 becomes high, port 1 can preferentially perform two communications, and the two communications are completed. At this stage, the priority of port 1 decreases and the priority of port 2 increases. As a result, a large number of communication opportunities can be assigned to devices that are to be preferentially communicated.

(2) TBWRR (Time Base Weighted Round Robin) method
In the TBWRR system arbitration, the communication allocation time of each port is determined in advance with respect to the communication time, and even if there is data from a plurality of ports, the allocated bandwidth is ensured. That is, in one communication allocation time (time slot: PCI Express standard value 100 ns), a port capable of communication for each time slot is determined. For example, when port 1 (P1) and port 2 (P2) communicate at a ratio of 1: 2, the arbitration table is set as follows.
P1 / P2 / P2 / P1 / P2 / P2 / P1 / P2 / P2
In the above table, the communicable port is switched for each time slot, and communication other than that port is not allowed. For this reason, if each port issues a request, communication can be performed without fail in the time slot in which the order has come.

  However, even if an arbitration function such as the RR, WRR, and TBWRR methods is used in PCIe SW, a problem may occur. For example, RR or WRR arbitration described above performs arbitration when contention occurs, so if there is a difference in request issue capability between devices, devices with high request issue capability communicate one after another. Therefore, there is a problem that the intended bandwidth cannot be allocated. A specific description will be given below.

  FIG. 2 is an example of a diagram for explaining RR / WRR arbitration. As shown in the figure, when communication is performed from port 1 to port 0 (read access: Memory Read Request) and no communication has occurred from port 2 to port 0, there is no communication contention at port 0. (And arbitration) do not occur, and communication can be performed with the full bandwidth including the response.

  FIG. 3 is an example of a diagram illustrating arbitration of the RR / WRR method. As a precondition, the bandwidth setting of port 1 and port 2 is 2: 1. As shown in the figure, communication (read access) is performed from port 1 to port 0, and communication (read access) is performed from port 2 to port 0. Note that the request issue capability of the devices connected to port 1 and port 2 is equal to 1: 1 (4: 4). When read request 1 and read request 2 are issued at the same time, the arbitration function operates at port 0 and is stored in the output buffer at a ratio of read request 1: read request 2 = 2: 1. Up stream). Responses to these read requests are returned in the order in which the requests are issued. Note that the read access (request) is a request for reading data to the memory connected to the port 0, for example, so that the response (data) has a relatively large data capacity. Each port issues the next read request when response data for the read request is returned. In such a case, arbitration (arbitration) is performed at 2: 1 as set for both the read request and the response, and the operation according to the previous band setting is realized.

  FIG. 4 is an example of a diagram for explaining the problems of the RR / WRR arbitration. As a precondition, the bandwidth setting of port 1 and port 2 is 2: 1. As shown in the figure, communication (read access) is performed from port 1 to port 0, and communication (read access) is performed from port 2 to port 0. Note that the request issue capability of devices connected to port 1 and port 2 is different from 1: 2 (4: 8), and the request issue capability of devices connected to port 2 is high. Each port issues the next read request when response data for the read request is returned. Here, in the standard implementation of the PCIe target device, when the NPH (Non-Posted-Header) buffer is used up, the next request cannot be issued until the response data returns. Can be issued. When read request 1 and read request 2 are issued simultaneously, the arbitration function operates at port 0 and is stored in the output buffer at a ratio of read request 1: read request 2 = 1: 2, and then port 0 ( Up stream). Responses to these read requests are returned in the order in which the requests are issued. Note that the RR / WRR arbitration function operates when communication reaches (conflicts) at the same time. When there is no conflict, the arbitration function is transferred from the reached communication. As shown in the figure, when there is a difference in request issue capability between devices, communication from the device connected to the port 2 issues the read request 2 one after another. The read request itself has a small amount of data, but the response data amount is large, and the response 2 clogs the downstream in port 0. Therefore, there is a delay before response 1 from port 1 to be prioritized returns. It will occur. Of course, this delay is not limited to the case of a read request, and a delay can occur in the case of a write access (Memory Write Request) that is a write request to a memory. Note that PCIe SW port arbitration mediates communication (request) contention from the inside of the port to the outside, and does not mediate communication (request or response) from the outside of the port to the inside.

  Also, in the TBWRR arbitration described above, ports that can communicate for each time slot are determined, so if each port issues a request, it can always communicate in the time slot in which the turn has come. . Therefore, in the arbitration table, it is only necessary to set the allocation time for the communication (port) to be given priority. However, if the port does not communicate in the time slot of its own port, no communication will occur in that order. If another port is waiting for communication at that time, the time slot will be There is a problem of being wasted. Specifically, when there is no data to be communicated in port 1 in the order of port 1, and there is data to communicate in port 2, port 2 cannot communicate in the time slot of port 1. Since the port 2 is kept waiting for communication until the time slot of the port 2 arrives, a waste of bandwidth occurs during this time. This is because there is no communication (idle) during that time. In the above example, since the arbitration table is set at a time slot ratio of 2: 1 for port 1 and port 2, even if there is no communication at port 1, the maximum communication bandwidth of port 2 is Only one third of this can be secured.

  As described above, when the arbitration function of the RR / WRR method is used, unlike the TBWRR method, the port can communicate whenever the communication is relatively free. There is a case where a delay in response occurs even in a device to be performed. In other words, depending on the device's ability to issue requests and the type of traffic data, the port arbitration settings may not match well with the actual traffic priority. In addition, when the TBWRR arbitration function is used, many time slots are assigned to the priority devices, so communication can be performed without delay in the time slots that have been turned in order, but communication is not available. Even when the time slot is present, the other ports cannot communicate until the time slot is assigned, and the time slot is wasted as described above. That is, any arbitration method has advantages and disadvantages and is not universal.

  By the way, the delay when using the RR and WRR arbitration functions may be a serious problem depending on the system. In other words, in the situation described below, the arbitration function does not work as intended, and in systems where data isochronism is particularly problematic, data transfer must be completed within the expected time. The system may fail.

For example, in a system such as an MFP (multi-function printer) or LP (laser printer), the line data to be drawn is transferred from the main memory to the line buffer of the plotter within one line drawing time (for example, 100 usec). The transfer needs to be completed. If a data transfer delay occurs, printing becomes an abnormal image, which becomes a serious problem for the system. As an example, the trial calculation of one line drawing time is as follows.
<Conditions>
60 A4 presses per minute
The A4 paper longitudinal direction is about 7300 lines (at 600 dpi)
Assuming paper spacing for printing paper transport is about 20% of A4 paper <Calculation>
Drawing time per line = 60 [sec] ÷ (7300 [line] x 120 [%] x 60 [sheets]) = 114 [usec]
If the print data CMYK is 2 bits each,
2 [bit] x 5200 [dot] / 1 [line] x4 [color] = 41600 [bit] / 1 [line]
Average transfer rate within one line = 41.6k [bit] / 1 [line] / 114 [usec] = 364.90M [bit] / [sec]
In other words, an average transfer rate of 364.90 Mbps or more is required for one line, and an abnormal image is generated if one line falls below this rate during a printing operation. Since an image is finally printed on a paper medium, there is a very severe restriction that data deterioration and quality deterioration due to compression are not allowed at all as in the case of streaming video and audio in computer network communication. This is because the data transfer synchronization constraint is determined by the mechanical drive conditions. In particular, in the plotter using the electrophotographic process, the heavy photoconductor drum and the paper transport mechanism are driven at high speed. The speed cannot be changed. For this reason, it is necessary to control the data transfer amount at a timing synchronized with the driving speed of the mechanism.

  Conventionally, in an image processing apparatus using PCI Express SW, when a communication conflict occurs, bandwidth allocation for each port cannot be performed well. For example, x4 or x16 is sufficient where the number of mounted lanes is sufficient. It was necessary to mount PCI Express SW with ports with excessive bandwidth. Alternatively, it was necessary to divide the PCI Express SW into a printer system, a scanner system, an arithmetic processing system, etc. in order to avoid bandwidth conflict. However, these solutions have a problem in that the mounting component cost increases and the mounting area also increases.

  The invention described in Patent Document 1 provides a system in which a user selects an arbitration table in accordance with an application in order to solve such a problem. In this system, an arbitration method is selected by a user or software (BIOS). However, the arbitration method cannot be switched within a short time by a user's manual operation or software operation.

  For example, in the internal bus of the image forming apparatus (MFP), data is output from the printer unit while reading data from the scanner unit during a copying operation, but 100usec or less is used for one-line data transfer of the printer unit during the copying operation. Time is required. However, if line data transfer to the printer unit and data transfer from the scanner unit occur at the same time, a large amount of data transfer occurs from a plurality of devices in a short time, and contention occurs in the PCIe SW. This is because, in order to complete the transfer of line data within a specified time, it is necessary to switch the arbitration in a short time of about 1 us or less in order to effectively use the PCIe bandwidth within a time of about 100 us or less.

  In view of the above problems, the present invention provides a data transfer device, an information processing device, an arbitration method, and an image forming system that realize efficient data transfer by switching to appropriate arbitration at appropriate timing. With the goal.

  Therefore, in order to solve the above-described problem, the data transfer apparatus according to the present invention includes a detection unit that detects a trigger for switching the arbitration table, and the switching of the arbitration table based on the trigger detected by the detection unit. And a arbiter that arbitrates in accordance with the arbitration table after switching and transfers a plurality of data when the arbitration table is switched.

  In addition, what applied the arbitrary combination of the component of this invention, expression, or a component to a method, an apparatus, a system, a computer program, a recording medium, etc. is effective as an aspect of this invention.

  According to the present invention, it is possible to provide a data transfer apparatus, an information processing apparatus, an arbitration method, and an image forming system that realize efficient data transfer by switching to appropriate arbitration at appropriate timing.

It is a figure which shows an example of competition of a communication path typically. It is a figure explaining an example of arbitration of a RR / WRR system. It is a figure explaining an example of arbitration of a RR / WRR system. It is a figure explaining an example of the problem of arbitration of a RR / WRR system. It is a figure which shows the general structural example of a PCI Express system. It is a figure which shows the structural example of the PCI Express system in this embodiment. 2 is a diagram illustrating a configuration example of a switch 110. FIG. It is a figure which shows an example of the functional block diagram which shows the main function structures of the switch 110 which concerns on this embodiment. It is a figure which shows an example of the mode of the data transfer in the port 0 when there exists data to give priority. It is a figure explaining an example of port arbitration of a TBWRR system. 4 is a flowchart illustrating an example of the operation of a switch 110. It is a figure explaining an example of table switching by detecting a memory request. It is a figure explaining an example of the vendor definition area | region in a header. It is a figure explaining an example of table switching by detecting a message packet. It is a figure explaining an example of the table switching based on the detection of a configuration request.

  DESCRIPTION OF EMBODIMENTS Embodiments for carrying out the present invention will be described in each embodiment with reference to the drawings. Hereinafter, the present invention will be described using a data transfer system based on PCIe as an example.

[Embodiment]
(System configuration)
FIG. 5 is an example of a diagram illustrating a general configuration of the PCI Express system. A PCIe graphic 113 is connected to the root complex 112 to which the CPU 110 and the memory 111 are connected by a PCIe 114a, and a switch (PCI Express Switch) 117a in which an endpoint 115a and a legacy endpoint 116a are connected by a PCIe 114b is a PCIe 114c. In addition, the switch 117b in which the endpoint 115b and the legacy endpoint 116b are connected by the PCIe 114d, and the PCI bridge 119 to which the PCI bus slot 118 is connected are connected to the switch 117c in which the PCIe 114e is connected to the tree. Structure (tree structure).

  FIG. 6 is an example of a diagram illustrating a configuration of the PCI Express system according to the present embodiment. The illustrated example shows an application example of PCI Express to an image forming apparatus (MFP) as an example applied to an embedded system. The image forming apparatus 1 according to the present embodiment includes a main memory 101, a controller 102, a network interface 103, a plotter engine 104, a plotter 105, and a switch (corresponding to the switch 117 in FIG. 5) 110 in the drawing.

  The main memory 101 is an image memory that is mounted on an application specific integrated circuit (ASIC) and stores print data (bitmap image). The controller 102 is a controller that controls the entire image forming apparatus, and includes a ROM (Read Only Memory), a RAM (Random Access Memory), and a CPU. The ROM stores programs executed when the image forming apparatus 1 is started up and various data. The RAM temporarily holds various programs and data read from the ROM and HDD (not shown). Further, the CPU executes a program temporarily stored in the RAM. For example, when the print data is received via the network interface 103, the controller executes a program (PDL parser) capable of interpreting PDL (Page Description Language) by the CPU, interprets the print data, and generates a bitmap image. Generate.

  The network interface 103 is an interface that connects the image forming apparatus 1 to a data transmission path such as a network. The plotter engine 104 and the plotter 105 print the bitmap image of the main memory 101 on a paper medium (printing paper) by an electrophotographic process method, for example.

  The switch 110 is a PCI Express Switch (data transfer device) that interconnects PCI Express devices as described above. The switch 110 shown in the figure includes ports 0 to 3, and the controller 102, the network interface 103, and the plotter engine 104 are connected to each other by PCI Express, which is a high-speed serial bus, in order to increase the speed of data transfer. A port on the upstream side (the side closer to the root complex (not shown)) is called an upstream port, and a port on the downstream side (a side far from the root complex (not shown)) is called a downstream port.

  In addition, although not shown, the image forming apparatus 1 includes an input panel composed of hardware keys, a touch panel, etc., an operation panel including a display device composed of a display and the like, and a document placed on the reading surface. Are provided with a scanner (scanner engine), a facsimile, and the like that optically read image data and realize a plurality of functions such as a copy, a printer, a facsimile, and a scanner.

  FIG. 7 shows an example of a configuration diagram of the switch 110. FIG. 7A is a diagram illustrating the overall configuration of the switch 110, and FIG. 7B is a diagram illustrating details of each port of the switch 110. The switch 110 includes a plurality of ports, has a transfer unit (including a reception unit and a transmission unit) that connects devices by PCI Express and transfers packets (data) transferred from the device.

  The switch 110 includes a PCIe core 111, a routing circuit 112, an arbiter circuit 113, a table switching circuit 114, and a table memory 115 as shown in the figure. The PCIe core 111 has a three-layer structure of Transaction Layer, Datalink Layer, and Physical Layer, which is the core of the PCI Express architecture, and is responsible for data communication by PCI Express. It is a communication part. The routing circuit 112 transfers the packet (data) received at the port to another appropriate transmission port. The arbiter circuit 113 receives the packet from the routing circuit 112, and arbitrates (determines) from which port the packet is transmitted by referring to the port arbitration table in the table memory 115 when there is data conflict. Although details will be described later, the arbiter circuit 113 according to the present invention corresponds to a plurality of port arbitration methods. The table switching circuit 114 acquires packet information from the Transaction Layer of the PCIe core 111, and changes the port arbitration method and the port arbitration table. The table memory 115 has a plurality of port arbitration tables for each port, and the currently valid port arbitration table is determined by the table switching circuit 114. In the figure, the port arbitration table 115a is a currently valid table, and the arbiter circuit 113 refers to the port arbitration table 115a to perform packet arbitration.

(function)
FIG. 8 is a functional block diagram showing the main functional configuration of the switch 110 according to the present embodiment. The switch 110 includes a transfer unit 801, an arbitration unit 802, a trigger detection unit 803, a table switching unit 804, and a table memory 115. Details will be described later, and will be briefly described here.

  The transfer unit 801 has a function of transferring a packet (data) transferred from the PCIe device. The transfer unit 801 corresponds to, for example, the above-described plurality of ports, the PCIe core 111, and the routing circuit 112.

  The arbitration unit 802 refers to a valid port arbitration table in the table memory 115 and performs packet arbitration. It also supports multiple arbitration methods such as the RR method, WRR method, and TBWRR method, and switches the port arbitration method according to the valid port arbitration table. The arbitrated packet is transferred by the transfer unit 801. The arbitration unit 802 corresponds to, for example, the arbiter circuit 113 described above.

  The trigger detection unit 803 has a function of detecting a trigger for switching an effective port arbitration table. When the trigger is detected, the trigger is transmitted to the table switching unit 804. The trigger detection unit 803 corresponds to, for example, the table switching circuit 114 described above.

  Upon receiving a trigger from the trigger detection unit 803, the table switching unit 804 switches a valid port arbitration table in the table memory. For example, the table is switched from the port arbitration table 115a to the port arbitration table 115b. The table switching unit 804 corresponds to, for example, the table switching circuit 114 described above.

  The table memory 115 has a plurality of port arbitration tables for each port. For example, it has a port arbitration table 115 corresponding to a plurality of arbitration methods such as the RR method, the WRR method, and the TBWRR method. Further, even if the same arbitration method is used, the port arbitration table 115 having different setting (definition) contents can be provided.

(Operation)
Next, the operation of the switch 110 according to the present embodiment will be described. A description will be given using a PCI Express system in which the network interface 103 and the plotter engine 104 are connected to the PCIe port of the controller 102 via the switch 110 as shown in FIG. Here, plotter data (print data) to the plotter engine 104 is traffic that requires a high data transfer rate and isochronism, and the print data from the network interface 103 is relatively weak in isochronous constraints. Shall.

  In this PCI Express system, when the image forming apparatus 1 receives a print request from another PC connected to the network, print data from the PC is temporarily stored in the main memory (image memory) 101. Since there is no data transfer to the plotter at this point, there is no problem even if the transfer from the network interface 103 to the main memory 101 uses up the data transfer band of the switch 110, and the RR or WRR method is suitable as the arbitration method. In the normal state, the switch 110 operates in a standard WRR method (or RR method) defined by the standard, and can transfer transfer data from the network interface 103 freely.

  At this time, the weight information of the WRR algorithm is stored (defined) in the port arbitration table 115a. In the WRR method, when data input from a plurality of input ports (ports 1 to x) is output to a smaller number of output ports (port 0) than the number of input ports, it competes for data transfer from each input port. When this occurs, arbitration of the data transfer amount is performed based on the weight information set for each port.

For example, as shown below:
Port 1: 1 (Weight)
Port 2: 1 (Weight)
Port x: 1 (Weight)
When the port arbitration table 115a is set in port 0, if a plurality of channels (ports 1 to x) of port 0 are issuing continuous requests, port 1, port 2, port x, port 1, Requests are arbitrated by the arbitration unit 802 in the order of port 2, port x,.

For example, as shown below:
Port 1: 1 (Weight)
Port 2: 2 (Weight)
Port x: 1 (Weight)
When the port arbitration table 115a is set for port 0, if a plurality of channels (port 1 and port 2) of port 0 issue continuous requests, port 1, port 2, port 2, port x , Port 1, port 2, port 2, port x... Are weighted at a ratio of 1: 2: 1 and arbitrated by the arbitration unit 802.

  In this way, when the print data from the PC is once stored in the main memory 101, there is no data transfer to a plotter (connected to port 2) that requires high data transfer rate and isochronism. Arbitration at port 1 and other ports x is operated by the WRR method (or RR method).

  Next, print data for one page is sent from the PC, and after the rendering process, it is necessary to prioritize the data transfer to the plotter over the transfer from the network interface 103 at the stage of transferring the data to the plotter. is there. This is because data transfer to the plotter requires high data transfer rate and isochronism. In this case, the TBWRR method is suitable as an arbitration method. This is because, as described above, a delay may be caused in data transfer to the plotter due to a write access (Memory Write Request) from the network interface 103.

  FIG. 9 is an example of a diagram showing a state of data transfer at port 0 when there is data to be prioritized. Preferably, as shown in FIG. 9B, the memory read request and the read print data from the plotter engine 104 are sent so that the print (plotter) data from the main memory 101 to the plotter engine 104 can be read without interruption. The included memory read request response may be processed with priority. Therefore, the trigger detection unit 803 detects data transfer to the plotter to be prioritized as a trigger, and the table switching unit 804 switches the valid port arbitration table in the table memory 115 in response to the trigger. For example, the table is switched from the port arbitration table 115a to the port arbitration table 115b. The port arbitration table 115b in this case stores (defines) the time slot information of the TBWRR algorithm.

  FIG. 10 is an example of a diagram illustrating TBWRR port arbitration. 10A shows a setting example of the port arbitration table for port 0, and FIG. 10B shows a state of data transfer at port 0. FIG. In the case of the TBWRR method, a time of, for example, 100 ns (nanosecond) is allocated per entry of the table. As shown in the figure, many time slots are assigned to port 2 in the port arbitration table, and data from port 2 (plotter engine 104) is prioritized over data from port 1 (network interface 103). You can see that it has been transferred.

  FIG. 11 is a flowchart for explaining the operation of the switch 110. The operation of the above-described switch 110 will be described for confirmation. First, it is initialized when the PCIe system is started or when an application program that uses a plotter is started, and starts its operation (S1101). Recognizing that the plotter is connected to port 2 of the switch 110 and that a device other than the plotter is connected to port 1 of the switch 110, the above table switching function is applied to port 0 of the switch 110. To enable. In addition, a valid port arbitration table 115 is set at the initial stage.

  When the trigger detection unit 803 detects a trigger (details will be described later) (S1102), the trigger is analyzed (S1103), and it is determined whether the trigger is suitable for table change (S1104). Details of the trigger will be described later.

  When the trigger is to change the table, the table switching unit 804 switches the valid port arbitration table 115. Thereafter, the arbitration unit 802 performs data arbitration according to the changed port arbitration table (and arbitration method). If a trigger is detected again (again, S1102), there may be another table change. For example, when returning to the original WRR port arbitration. The flowchart can be ended (END) by system shutdown or the like.

<Example 1>
As described above, in the switch 110 according to the present invention, when the trigger detection unit 803 detects data transfer to the plotter to be prioritized as a trigger, the table switching unit 804 switches the port arbitration table 115 and the arbitration unit 802. Data arbitration is performed according to the arbitration method changed. Next, an example of trigger detection by the trigger detection unit 803 will be described.

  Specifically, the trigger detection unit 803 according to the present embodiment detects a “memory request” from a specific port of the switch 110 as a trigger. The memory request includes a memory read request and a memory write request. That is, the specific port is a port to which a device (plotter engine 104) that performs data transfer that should be prioritized is connected, and when a memory request packet passes from port 2, which is the specific port, the trigger detection unit 803 This is detected as a trigger.

  When starting the PCIe system or when starting an application program that uses the plotter, the plotter is connected to the port 2 of the switch 110 based on the register group having the specific information of the PCIe of the switch 110, and the switch 110 It recognizes that a device other than the plotter is connected to port 1. In addition, the above-described table switching function is enabled for port 0 of the switch 110, and a port arbitration table that is enabled (referenced) at the time of initialization is set (initialization operation). It should be noted that the register group of the switch 110 for performing various settings such as whether to use this table switching function, the port arbitration table that is enabled at the time of initialization, and which port's packet operates is included in each register group. It can be accessed from the CPU of the controller 102 via the port configuration register and the IO space assigned to the switch, and can be read and written by a configuration request.

  When the plotter data is prepared and the plotter starts data transfer after the PCIe system starts operating, the trigger detection unit 803 detects the passage of the memory read request from the plotter, and the table switching unit 804 detects the port arbitration table 115. The arbitration method is changed from the WRR method (or RR method) to the TBWRR method. While the plotter data is transferred more preferentially, the data transfer from the network interface 103 is also performed with the surplus bandwidth.

  When the plotter data transfer is completed, the table switching unit 804 changes the arbitration method from the TBWRR method to the original WRR method (or RR method) by changing the port arbitration table 115. As a method, when the trigger detection unit 803 does not detect the passage of the read request from the plotter for a certain period of time, a trigger for returning the arbitration method is retransmitted to the table switching unit 804.

  FIG. 12 is an example of a diagram for explaining table switching by detecting a memory request. As shown in the figure, when a memory read request from the port 2 is detected, the port arbitration table 115 is changed, whereby the arbitration method is changed from the WRR method to the TBWRR method. As a result, arbitration is performed according to the port arbitration table shown in FIG. 10A, and the plotter data is transferred more preferentially.

<Example 2>
When the trigger detection unit 803 of this embodiment receives a “message request” from a specific port of the switch 110, the trigger detection unit 803 detects this as a trigger. In the PCI Express standard, a vendor-specific message request packet (vendor message) can be defined. Therefore, a vendor message (Message Code and payload data) for changing the port arbitration table 115 is defined. FIG. 13 is an example of a diagram for explaining a vendor definition area in a header. As shown in the figure, Message Code and payload data can be freely defined. The plotter engine 104 is provided with a function for transmitting the above-described message request to the switch 110 when performing data transfer. In addition, a function for transmitting the above-described message request to the switch 110 even when data transfer is completed is provided.

  When the plotter data is ready and the plotter starts data transfer after the PCIe system starts operation, the plotter engine 104 transmits the above-described message request (packet) to the switch 110. The trigger detection unit 803 detects a message request from the plotter engine 104, and the table switching unit 804 changes the arbitration method from the WRR method (or RR method) to the TBWRR method by changing the port arbitration table 115. While the plotter data is transferred more preferentially, the data transfer from the network interface 103 is also performed with the surplus bandwidth. For example, if the payload data in the detected message request packet is “1”, it is switched to the first port arbitration table (TBWRR method), and if it is “0”, the port arbitration table (WRR at initialization) is switched. System).

  When the transfer of the plotter data is completed, the plotter engine 104 transmits the above-described message request whose payload data in the message request packet is “0” to the switch 110, for example. The trigger detection unit 803 can detect a message request from the plotter engine 104, and the table switching unit 804 can switch to the port arbitration table at the time of initialization by changing the port arbitration table 115. Specifically, the arbitration method is changed from the TBWRR method to the original WRR method (or RR method).

  FIG. 14 is an example for explaining table switching by detecting a message packet. As shown in the figure, when a message request from port 2 is detected, the port arbitration table 115 is changed, whereby the arbitration method is changed from the WRR method to the TBWRR method. As a result, arbitration is performed according to the port arbitration table shown in FIG. 10A, and the plotter data is transferred more preferentially.

<Example 3>
When receiving a “configuration request” from the CPU of the controller 102, the trigger detection unit 803 of the present embodiment detects this as a trigger. More specifically, after the plotter data is prepared, the CPU of the controller 102 issues a configuration request before starting (instructing) the data transfer of the plotter, and changes the port arbitration of port 0 of the switch 110. Rewrite the register. Similarly, when the transfer of plotter data is completed, a configuration request is issued to rewrite the port arbitration change register of port 0 of the switch 110.

  As described above, the port arbitration table that is enabled (referenced) at the time of initialization is set based on the register group having the PCIe specific information of the switch 110 when the PCIe system is started up (initialization operation) ). Therefore, the CPU of the controller 102 changes (sets) the port arbitration table that is enabled (referenced) by issuing a configuration request and rewriting the register before starting (instructing) the data transfer of the plotter. ) When the trigger detection unit 803 detects a configuration request as a trigger, the table switching unit 804 changes the port arbitration table 115, thereby changing the arbitration method from the WRR method (or RR method) to the TBWRR method. In this case, the table switching unit 804 switches the table by rewriting the register.

  Of course, since the register is actually rewritten, the arbitration unit 802 has the port arbitration table after rewriting (and the arbitration method) as if the port arbitration table after rewriting is a port arbitration table that is valid at the time of initialization. To perform data arbitration.

  FIG. 15 is an example of a diagram for explaining table switching by detecting a configuration request. As shown in the figure, when a configuration request from the CPU of the controller 102 is detected, the port arbitration table 115 is changed, whereby the arbitration method is changed from the WRR method to the TBWRR method. As a result, arbitration is performed according to the port arbitration table shown in FIG. 10A, and the plotter data is transferred more preferentially.

[Summary]
As described above, the PCI Express Switch according to the present invention has a specific port to which a device (for example, a plotter) for performing priority data transfer is connected when data from a plurality of downstream ports can occur in one upstream port. When the data transfer to be prioritized is performed, the port arbitration method in the upstream port is changed, and the data transfer to be prioritized is preferentially arbitrated and transferred. More specifically, by changing the port arbitration method (and the referenced port arbitration table) at the upstream port to the TBWRR method, the bandwidth should be allocated to the data that should be prioritized and the data that should be prioritized will be preferentially transferred. To do. On the other hand, when the data transfer that should be prioritized is not performed, the port arbitration method at the upstream port is changed to the RR / WRR method so that other ports can use the bandwidth effectively. Further, since the port arbitration method is changed by a predetermined trigger, it can be changed (switched) in a short time. Therefore, it is effective for transferring traffic requiring high data transfer rate and isochronism.

  That is, according to the present invention, it is possible to provide a data transfer apparatus, an information processing apparatus, an arbitration method, and an image forming system that realize efficient data transfer by switching to appropriate arbitration at appropriate timing.

  Note that the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

  For example, the present invention can be applied to an image forming system. In the above-described embodiment, as an example of applying the PCI Express system according to the present invention to an embedded system, an image forming apparatus (MFP) is taken as an example, but this can be applied to an image forming system. Specifically, the PCI Express Switch can connect (expand) a plurality of PCI Express devices more easily than PCI Express. Therefore, instead of the conventional connection using Ethernet (registered trademark) or the like, a plurality of image forming apparatuses are connected to each other via the PCI Express Switch. As a result, while enjoying the advantages of the high-speed serial bus, the PCI Express Switch performs the operation as described above, so that priority data can be transferred between the image forming apparatuses. This is particularly effective for transferring traffic requiring high data transfer rate and isochronism, such as data transfer between a main memory (image memory) and a scanner or plotter. The image forming apparatus includes a scanner, a printer, and the like, and a system can be constructed with any combination or configuration.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 101 Main memory 102 Controller 103 Network interface 104 Plotter engine 105 Plotter 110 Switch 111 PCIe core 112 Routing circuit 113 Arbiter circuit 114 Table switching circuit 114
115 Table memory 115
801 Transfer unit 802 Arbitration unit 803 Trigger detection unit 804 Table switching unit

JP 2006-155183 A

Claims (13)

The first downstream from the upstream port while performing a first data transfer between an upstream port of the ports and a first downstream port through a port to which a predetermined device can be connected Detecting means for detecting a trigger indicating a second data transfer to a second downstream port different from the port ;
When the trigger is detected, the arbitration table is changed from the first arbitration table used at the time of the first data transfer to the second arbitration table used at the time of the first data transfer and the second data transfer. Switching means for switching;
When the arbitration table is switched, a plurality of data consisting of the first data and the second data transferred with priority over the first data are arbitrated according to the second arbitration table after switching. Arbiter to transfer the
A switch comprising: The first arbitration table stores setting information according to an RR (Round Robin) method or a WRR (Weighted Round Robin) method, and the second arbitration table stores a TBWRR (Time Base Weighted Round Robin) method.
The switching means detects the TBWRR method from the first arbitration table of the RR method or the WRR method when the trigger indicating the second data transfer to be prioritized over the first data transfer is detected. Switch to the second arbitration table of
2. The switch according to claim 1, wherein the arbiter preferentially transfers the second data transfer to be arbitrated and prioritized according to the second arbitration table of the TBWRR method after switching . The detecting means detects a trigger indicating completion of the second data transfer;
The switching means executes switching from the second arbitration table to the first arbitration table when a trigger indicating completion is detected;
The arbiter switch as claimed in claim 2, wherein the transfer of said plurality of data arbitration according to the first arbitration table after switching. The second data transfer is a transfer of a memory request packet transmitted from a predetermined device that generates data to be prioritized;
The switch according to claim 2 or 3, wherein A plurality of data communication devices;
A switch connected to the plurality of data communication devices,
The switch
The plurality of data during execution of a first data transfer between an upstream port and a first downstream port of the ports from the plurality of data communication devices via a port to which a predetermined device can be connected Detection means for detecting a trigger indicating a second data transfer from a communication device to the second downstream port different from the first downstream port from the upstream port ;
When the trigger is detected, the arbitration table is changed from the first arbitration table used at the time of the first data transfer to the second arbitration table used at the time of the first data transfer and the second data transfer. Switching means for switching;
When the arbitration table is switched, a plurality of data consisting of the first data and the second data transferred with priority over the first data are arbitrated according to the second arbitration table after switching. Arbiter to transfer the
An information processing apparatus characterized by the above. The first arbitration table stores setting information according to an RR (Round Robin) method or a WRR (Weighted Round Robin) method, and the second arbitration table stores a TBWRR (Time Base Weighted Round Robin) method.
When the trigger indicating the second data transfer to be prioritized over the first data transfer is detected, the switching means switches from the arbitration table of the RR method or the WRR method to the arbitration table of the TBWRR method. Switch
6. The information processing apparatus according to claim 5, wherein the arbiter arbitrates in accordance with the second arbitration table of the TBWRR method after switching and transfers the second data transfer to be prioritized and transferred. . The detecting means detects a trigger indicating completion of the second data transfer;
The switching means performs switching from the second arbitration table to the first arbitration table when a trigger indicating the completion is detected;
The information processing apparatus according to claim 6, wherein the arbiter arbitrates according to the first arbitration table after switching and transfers the plurality of data. The second data transfer is a transfer of a memory request packet transmitted from a predetermined device that generates the data to be prioritized;
The information processing apparatus according to claim 6, wherein: The first downstream from the upstream port while performing a first data transfer between an upstream port of the ports and a first downstream port through a port to which a predetermined device can be connected A detection procedure indicating a second data transfer to a second downstream port different from the port ;
When the trigger is detected, the arbitration table is changed from the first arbitration table used at the time of the first data transfer to the second arbitration table used at the time of the first data transfer and the second data transfer. A switching procedure for switching,
When the arbitration table is switched, a plurality of data consisting of the first data and the second data transferred with priority over the first data are arbitrated according to the second arbitration table after switching. Transfer procedure to transfer
An arbitration method characterized by comprising: The first arbitration table stores setting information according to an RR (Round Robin) method or a WRR (Weighted Round Robin) method, and the second arbitration table stores a TBWRR (Time Base Weighted Round Robin) method.
In the switching procedure, when the trigger indicating the second data transfer to be prioritized over the first data transfer is detected, the TBWRR method is used from the first arbitration table of the RR method or the WRR method. To the second arbitration table,
In the transfer procedure, arbitration is performed according to the second arbitration table of the TBWRR method after switching, and the second data transfer to be prioritized is transferred with priority.
The arbitration method according to claim 9. A plurality of image forming apparatuses;
A switch connected to the plurality of image forming apparatuses,
The switch
The plurality of data during execution of a first data transfer between the upstream port and the first downstream port among the plurality of image forming apparatuses via a port to which a predetermined device can be connected. Detection means for detecting a trigger indicating a second data transfer from a communication device to the second downstream port different from the first downstream port from the upstream port ;
When the trigger is detected, the arbitration table is changed from the first arbitration table used at the time of the first data transfer to the second arbitration table used at the time of the first data transfer and the second data transfer. Means for switching;
When the arbitration table is switched, a plurality of data consisting of the first data and the second data transferred with priority over the first data are arbitrated according to the second arbitration table after switching. Arbiter to transfer the
An image forming system. The first arbitration table stores setting information according to an RR (Round Robin) method or a WRR (Weighted Round Robin) method, and the second arbitration table stores a TBWRR (Time Base Weighted Round Robin) method.
When the trigger indicating the second data transfer to be prioritized over the first data transfer is detected, the switching means switches from the arbitration table of the RR method or the WRR method to the arbitration table of the TBWRR method. Switch
12. The image forming system according to claim 11, wherein the arbiter arbitrates according to the second arbitration table of the TBWRR system after switching, and transfers the second data transfer to be prioritized and transferred. . The second data transfer is data transfer to a scanner or plotter provided in the image forming apparatus;
The image forming system according to claim 12.

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