JP2007067634A - Information processing system, program, and packet communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-speed data transfer wherein both the effects of a route delay and the overhead of a protocol are taken into consideration while the effects are well balanced. <P>SOLUTION: A curve 1 is detected, which indicates the ratio of a completion packet to a payload size (T1/T2) that is obtained, on the basis of a time difference T1 between a transmission start time of a request packet and a receiving time of the head of a completion packet corresponding to the request packet, and a time difference T2 between a transmission start time of the request packet and a reception completion time of the final completion packet of all the target data; a curve 2 is detected which indicates the ratio of a completion packet to a payload size (A/(A+B)) that is obtained on the basis of the header size A of the completion packet and the payload size B of the completion packet; and the payload size of a packet transfer that gives a less loss for the theoretical value of a transfer rate is determined on the basis of the curves 1 and 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing system such as a multifunction peripheral (MFP) that handles various images and performs various processes, a program, and a packet communication method.

  In general, in an image forming system such as a digital copying machine or a multifunction peripheral (MFP) that handles image data and other data, a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image forming apparatuses. The use of a high-speed serial interface such as IEEE1394 or USB is being considered in place of the parallel interface. For example, according to Patent Document 1, it is proposed to use a high-speed serial interface such as IEEE1394 or USB as an internal interface.

  As another high-speed serial interface, an interface called PCI Express (registered trademark), which is a successor to the PCI bus system, has been proposed and has been put to practical use (for example, see Non-Patent Document 1). This PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) such as a root complex-switch (arbitrary hierarchy) -device as shown in FIG. Has been.

JP 2001-016382 A “Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, in the case of Patent Document 1, there is no mention of a problem when simultaneously transferring a plurality of image data.

  In addition, since a serial and highly flexible system can be constructed, a plurality of traffics are generated, but there is no mention of influences such as variations in path delay.

  The present invention has been made in view of the above, and by effectively utilizing a PCI Express standard high-speed serial bus having features such as high scalability, the effects of path delay and protocol overhead can be reduced. The purpose is to realize high-speed data transfer in a balanced manner.

  In order to solve the above-described problems and achieve the object, the invention according to claim 1 is directed to a communication channel independent of transmission and reception via a communication network in which a point-to-point connection or a plurality of point-to-point connections are configured in a tree structure. In an information processing system that performs communication on a packet-by-packet basis using an established high-speed serial bus, the time difference T1 from the request packet transmission start time to the arrival time of the completion packet corresponding to the request packet, and the request packet Detects curve 1 in which the ratio (T1 / T2) to the payload size of the compression packet is obtained based on the time difference T2 from the transmission start time of the packet to the reception completion time of the last compression packet of all the target data And header size of compression packet Based on the curve 1 and the curve 2, and means for detecting the curve 2 for determining the ratio (A / (A + B)) to the payload size of the compression packet based on the payload size B of the compression packet; And means for determining a payload size of packet transfer with a small loss with respect to a theoretical value of the transfer rate.

  According to a second aspect of the present invention, in the information processing system according to the first aspect, the determined payload size is equal to or less than an intersection of the curve 1 and the curve 2.

  According to a third aspect of the present invention, in the information processing system according to the first aspect, the determined payload size is 1/4 to 4 times the payload size at the intersection of the curve 1 and the curve 2. Payload size.

  According to a fourth aspect of the present invention, in the information processing system according to any one of the first to third aspects, the payload size can be changed according to a delay amount of a path.

  According to a fifth aspect of the present invention, in the information processing system according to any one of the first to third aspects, the payload size can be changed according to the number of switch stages of the route.

  According to a sixth aspect of the present invention, in the information processing system according to the fourth or fifth aspect, the payload size is changed when the high-speed serial bus is reconfigured.

  According to a seventh aspect of the present invention, in the information processing system according to any one of the first to sixth aspects, from the transmission start time of the request packet to the time at which the head of the compression packet corresponding to the request packet arrives And a time difference measuring means for measuring the time difference T2 from the transmission start time of the request packet to the reception completion time of the last completion packet of all the target data, and the time difference measured by the time difference measuring means Curve 1 is detected based on T1 and time difference T2.

  According to an eighth aspect of the present invention, in the information processing system according to the seventh aspect, the time difference measuring means includes a measurement packet generator that generates a measurement packet, and a measurement packet generated by the measurement packet generator. A delay amount detection unit that detects a delay amount based on a packet output time and a reception time of a return packet from the end point; and a delay amount storage unit that stores a delay amount detected by the delay amount detection unit. ing.

  According to a ninth aspect of the present invention, in the information processing system according to the eighth aspect, as the measurement packet, a plurality of packets having different payload sizes are used.

  According to a tenth aspect of the present invention, in the information processing system according to any one of the first to ninth aspects, the high-speed serial bus is a PCI Express standard high-speed serial bus.

  According to the eleventh aspect of the present invention, communication in packet units by a high-speed serial bus is established in which a communication channel independent of transmission and reception is established through a communication network in which point-to-point connection or a plurality of point-to-point connections are configured in a tree structure. A program for causing a computer to execute processing, which is based on a time difference T1 from a request packet transmission start time to a arrival time of a completion packet corresponding to the request packet, and a request packet transmission start time. A function for detecting a curve 1 in which a ratio (T1 / T2) to the payload size of the completion packet is obtained based on the time difference T2 until the reception completion time of the last compression packet of all data, and the compression packet Header size A and completeness A function for detecting a curve 2 obtained from a ratio (A / (A + B)) to a payload size of a completion packet based on the payload size B of the packet, and a transfer rate based on the curve 1 and the curve 2 And causing the computer to execute a function of determining a payload size for packet transfer with a small loss with respect to the theoretical value.

  According to a twelfth aspect of the present invention, in the program according to the eleventh aspect, the determined payload size is equal to or less than an intersection of the curve 1 and the curve 2.

  According to a thirteenth aspect of the present invention, in the program according to the eleventh aspect, the payload size to be determined is 1/4 to 4 times the payload size centered on the payload size at the intersection of the curve 1 and the curve 2 It is.

  According to the fourteenth aspect of the present invention, communication is performed in units of packets by a high-speed serial bus in which a communication channel independent of transmission and reception is established through a communication network in which point-to-point connections or a plurality of point-to-point connections are configured in a tree structure. In the packet communication method in the information processing system, the time difference T1 from the transmission start time of the request packet to the arrival time of the beginning of the completion packet corresponding to the request packet, and the purpose from the transmission start time of the request packet The curve 1 obtained by calculating the ratio (T1 / T2) to the payload size of the completion packet based on the time difference T2 until the reception completion time of the last completion packet of all the data to be received is detected. Header size A and compression A curve 2 obtained by calculating the ratio (A / (A + B)) to the payload size of the compression packet based on the payload size B of the packet is detected, and the theoretical value of the transfer rate is calculated based on the curve 1 and the curve 2 The payload size of packet transfer with a small loss is determined.

  According to a fifteenth aspect of the present invention, in the packet communication method according to the fourteenth aspect, the determined payload size is equal to or less than an intersection of the curve 1 and the curve 2.

  The invention according to claim 16 is the packet communication method according to claim 14, wherein the determined payload size is 1/4 to 4 times the payload size at the intersection of the curve 1 and the curve 2 Payload size.

  According to the first aspect of the present invention, the curve 1 for determining the ratio of T1 / T2 to the payload size of the compression packet and the curve 2 for determining the ratio of A / (A + B) to the payload size of the compression packet Based on the above, it is possible to realize high-speed data transfer that balances the effects of path delay and protocol overhead by determining the payload size of packet transfer with little loss to the theoretical transfer rate There is an effect.

  Further, according to the invention of claim 2, since the determined payload size is equal to or less than the intersection of the curve 1 and the curve 2, it is possible to construct a system that is not affected by variations in path delay, and expandability is improved. There is an effect that it becomes much better.

  According to the invention of claim 3, the payload size to be determined is 1/4 to 4 times the payload size centering on the payload size at the intersection of the curves 1 and 2. Outside of 4 times, it is more than 20% lower, and the payload size to be used is not very practical. Therefore, high-speed data transfer that balances the effects of path delay variation and protocol overhead is realized. There is an effect that can be.

  According to the invention of claim 4, by making the payload size changeable according to the delay amount of the route, the fastest high-speed data transfer can always be realized even when the delay amount is dynamically changed. There is an effect.

  Further, according to the invention of claim 5, by enabling the payload size to be changed according to the number of switch stages of the route, the fastest high-speed data transfer can always be realized even when there is a dynamic change in the number of switch stages. There is an effect.

  According to the invention of claim 6, there is an effect that the payload size can be changed according to the delay amount of the route and the number of switch stages of the route.

  According to the invention of claim 7, by detecting the curve 1 according to the measured time difference T1 and time difference T2, even when there is a dynamic variation in the delay amount of the route and the number of switch stages of the route, the curve 1 is always detected. There is an effect that the curve 1 can be detected based on the actually measured value.

  Moreover, according to the invention concerning Claim 8, there exists an effect that the time difference T1 and the time difference T2 can be measured reliably.

  Moreover, according to the invention concerning Claim 9, there exists an effect that the intersection of 2 curves can be automatically estimated by using the several packet which changed the payload size as a packet for a measurement.

  Further, according to the invention of claim 10, by effectively utilizing a PCI Express standard high-speed serial bus having features such as high scalability, high-speed image data can be obtained even if there is an influence of variation in path delay. There is an effect that output and simultaneous transfer can be performed.

  According to the invention of claim 11, the curve 1 for determining the ratio of T1 / T2 to the payload size of the compression packet and the ratio of A / (A + B) to the payload size of the compression packet are obtained. Realizing high-speed data transfer considering the influence of path delay and protocol overhead in a well-balanced manner by determining the payload size of packet transfer with little loss to the theoretical transfer rate based on curve 2 There is an effect that can be.

  According to the invention of claim 12, since the determined payload size is equal to or less than the intersection of the curve 1 and the curve 2, it is possible to construct a system that is not affected by variations in path delay, and expandability is improved. There is an effect that it becomes much better.

  According to the invention of claim 13, the payload size to be determined is 1/4 to 4 times the payload size centered on the payload size at the intersection of the curves 1 and 2. Outside of 4 times, it is more than 20% lower, and the payload size to be used is not very practical. Therefore, high-speed data transfer that balances the effects of path delay variation and protocol overhead is realized. There is an effect that can be.

  According to the fourteenth aspect of the present invention, the curve 1 for determining the ratio of T1 / T2 to the payload size of the compression packet and the ratio of A / (A + B) to the payload size of the compression packet are determined. Realizing high-speed data transfer considering the influence of path delay and protocol overhead in a well-balanced manner by determining the payload size of packet transfer with little loss to the theoretical transfer rate based on curve 2 There is an effect that can be.

  According to the invention of claim 15, since the determined payload size is equal to or less than the intersection of the curve 1 and the curve 2, it is possible to construct a system that is not affected by variations in path delay, and expandability is improved. There is an effect that it becomes much better.

  According to the invention of claim 16, the payload size to be determined is 1/4 to 4 times the payload size centered on the payload size at the intersection of curve 1 and curve 2, and from 1/4 Outside of 4 times, it is more than 20% lower, and the payload size to be used is not very practical. Therefore, high-speed data transfer that balances the effects of path delay variation and protocol overhead is realized. There is an effect that can be.

  Exemplary embodiments of an information processing system, a program, and a packet communication method according to the present invention are explained in detail below with reference to the accompanying drawings.

  The best mode for carrying out the present invention will be described with reference to the drawings. In the following, details of PCI Express will be described in the columns [Outline of PCI Express Standard] to [Details of Architecture of PCI Express], and then the information processing system according to the present embodiment will be described in the [Information Processing System] column. I will explain it.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In an existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect a PCI-X bridge 105a to a host bridge 103 to which a CPU 100, AGP graphics 101, and memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Further, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects component links in a one-to-one relationship (point-to-point). . The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint does not request I / O resources in the BAR (Base Address Register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double arrows indicate the PCI Express link 114 (or 126), and 142a to 142d indicate ports. Among these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and there is no concept of hierarchy. In PCI Express, as shown in FIG. Like the standard communication protocol and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration employs a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the cross-point of the data signal. The system extracts the clock.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting the conventional access to the access by PCI Express is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions extended by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
The transaction layer packet (TLP) is automatically divided into data link layer packets (DLLP) as shown in FIG. 12 and transmitted to each lane when transmitted from the physical layer. A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Information processing system]
An information processing system such as a digital copying machine or MFP according to the present embodiment uses a PCI Express standard high-speed serial bus as described above for its internal interface.

  FIG. 16 is a schematic block diagram illustrating a configuration example of the information processing system according to the present embodiment. The information processing system 1 according to the present embodiment is applied to a device such as an MFP, and includes, as its components, a control unit 2, an input unit 3 that is an image input unit, and an output unit 4 that is an image output unit. A processing unit 5 which is an image processing unit and a storage unit 6 are provided. Here, the control unit 2 includes a CPU that controls the entire system according to an installed program (software), and means a device portion (printer controller) that performs processing such as path control and path determination. The input unit 3 is a device or unit for capturing image data based on a document image or the like into the system, and is configured by, for example, a scanner engine that photoelectrically reads a document image and acquires image data. Yes. The output unit 4 is a device or unit that prints out image data on paper or the like, and includes, for example, an electrophotographic plotter (printer) engine. The processing unit 5 is a device or unit portion that performs some kind of image processing such as enlargement / reduction, rotation, etc. on image data, and includes, for example, a magnification changer, a rotator, and a compression / decompression unit. Yes. The storage unit 6 is a device or unit including a memory, HDD, or the like that stores image data. In the present embodiment, the storage unit 6 is configured by, for example, a printer controller.

  With respect to the components of such an information processing system (MFP), in the present embodiment, for example, the processing unit 5 is configured to integrally include the input unit 3 and the output unit 4, and the storage unit 6 (printer controller). Is configured to include the control unit 2 and the devices of the processing unit 5 and the storage unit 6 are connected by the high-speed serial bus 7 according to the PCI Express standard as described above (therefore, the processing unit 5 and the storage unit). 6 has a port).

  In such a configuration, the image data captured from the input unit 3 under the control of the control unit 2 is subjected to image processing by the processing unit 5 as necessary, and then transferred to the storage unit 6 via the high-speed serial bus 7. And temporarily stored in the memory in the storage unit 6. Thereafter, the image data stored in the memory of the storage unit 6 is taken into the processing unit 5 via the high-speed serial bus 7 and is subjected to image processing as necessary, and then transferred to the output unit 4 for printout and the like. .

  In the case of the present embodiment, the processing unit 5 and the storage unit 6 are connected to each other in the information processing system 1 such as an MFP by the high-speed serial bus 7 based on the PCI Express standard. And can be configured by mounting the electrical system of each device on a separate board, greatly expanding design flexibility without sacrificing high-speed performance, and reducing costs by reducing board area Can also be planned.

  Note that the present embodiment shown in FIG. 16 is merely an example, and can be configured in various aspects as shown below, for example.

  In the configuration example shown in FIG. 17, the control unit 2 is provided in the processing unit 5.

  The configuration example shown in FIG. 18 makes the control unit 2 independent by individually connecting the input unit 3, the processing unit 5, the output unit 4, and the storage unit 6 to the control unit 2 through the high-speed serial buses 7a to 7d. The input unit 3, the processing unit 5, the output unit 4, and the storage unit 6 can be handled equivalently. Therefore, the control unit 2 in this case can be easily realized by using, for example, a root complex located at the root in the tree structure of the PCI Express system.

  Thus, for example, the image data captured by the input unit 3 is transferred into the control unit 2 through the high-speed serial bus 7a, transferred to the processing unit 5 through the high-speed serial bus 7b, and necessary image processing is performed. The data can be transferred to the storage unit 6 via the serial paths 7b and 7d and temporarily stored in the memory. In parallel with this, the image data stored in the memory of the storage unit 6 is transferred to the processing unit 5 through the high-speed serial buses 7d and 7b, and necessary image processing is performed, and further output through the high-speed serial paths 7b and 7c. The data can be transferred to the unit 4 and used for printout or the like.

  In the configuration example shown in FIG. 19, the input unit 3, the processing unit 5, and the output unit 4 are individually connected to the storage unit 6 having the control unit 2 by high-speed serial buses 7 a to 7 c, respectively. The unit 3, the processing unit 5, and the output unit 4 can be handled equivalently. As in the case of FIG. 18, the control unit 2 in this case can also use a root complex located at the root in the tree structure of the PCI Express system, for example.

  As a result, for example, image data captured by the input unit 3 is transferred to the storage unit 6 via the high-speed serial bus 7a, transferred to the processing unit 5 via the high-speed serial bus 7b, and necessary image processing is performed. The data can be transferred to the storage unit 6 via the serial path 7b and temporarily stored in the memory. In parallel with this, the image data stored in the memory of the storage unit 6 can be transferred to the output unit 4 via the high-speed serial bus 7c and used for printout or the like.

  In the configuration example shown in FIG. 20, the input unit 3 and the storage unit 6 are interchanged in comparison with FIG. 19. In the configuration example shown in FIG. 21, the processing unit 5 and the storage unit 6 are interchanged in comparison with FIG. 19. The configuration example shown in FIG. 22 is obtained by replacing the output unit 4 and the storage unit 6 with respect to FIG.

  In the configuration example shown in FIG. 23, in the configuration shown in FIG. 18, the switch 8 in the tree structure of the PCI Express system is interposed downstream of the control unit 2 via the high-speed serial bus 7e, and the input unit 3, processing unit 5, the output unit 4 and the storage unit 6 are respectively connected to the downstream ports of the switch 8 by high-speed serial buses 7a to 7d.

  FIGS. 24 to 27 are the same as the configurations shown in FIGS. 19 to 22, respectively, with the switch 8 in the tree structure of the PCI Express system interposed.

  By the way, an example of the optimum configuration of an information processing system in the case where a switch in a tree structure of a PCI Express system is interposed on a PCI Express standard high-speed serial bus path to achieve both expandability and high speed will be described with reference to FIG. To do. The configuration example of the information processing system shown in FIG. 28 is an example of an information processing system constructed by connecting a plurality of devices, not an example of an information processing system having a single configuration like the MFP described above. Basically, first, a plotter (or printer) 11 corresponding to an output unit and image memories 12 and 13 corresponding to a storage unit include a PCI Express standard high-speed serial bus 14a, 14b, 14c and a single-stage PCI. It is connected in the vicinity via an Express standard switch 15. Here, as the image memories 12 and 13, for example, dedicated memories for storing final dot data for printing out by the plotter 11 are used. However, it is not always necessary to use the final dot data, and if there is a real-time compression / decompression unit or the like on the way, a memory for storing the compressed data may be used. As described above, in addition to the basic configuration in which the plotter 11 and the image memories 12 and 13 are connected in the vicinity by the one-stage switch 15, the CPU 16 and the system memory 17 are connected to connect the route complex 18 corresponding to the control unit. May be connected to the upstream side of the switch 15 via a PCI Express standard high-speed serial bus 14d. Furthermore, when there is no timing restriction or it may be delayed, for example, when connecting a scanner 19 as an input unit or an image processing arithmetic unit 20 as a processing unit, an expansion unit is provided downstream of the switch 15. What is necessary is just to connect by the PCI Express standard high-speed serial buses 14e, 14f, and 14g through the PCI Express standard switch 21. That is, by interposing the switch 15, the system can be arbitrarily configured based on the expandability of the switch 15, and it is necessary to transfer image data in synchronization with the line synchronization signal. Since the plotter 11 with strict timing control and the image memories 12 and 13 are connected in the vicinity, a delay in data transfer can be suppressed and high-speed data transfer from the image memory 12 or 13 to the plotter 11 can be handled.

  In the system configuration example shown in FIG. 28, since the interface is common, the MFP 22 having both the scanner as the input unit and the plotter as the output unit is also compatible with the switch 15 according to the PCI Express standard. An example of connection via a high-speed serial bus 14h is shown. Also in this case, the plotter in the MFP 22 and the image memories 12 and 13 are connected in the vicinity via the one-stage switch 15 and are synchronized with the line synchronization signal from the image memory 12 or 13 to the plotter. The transferred image data can be transferred without delay.

  Data transfer in these configuration examples will be further described. For example, FIG. 16, FIG. 17, FIG. 19 and FIG. 23 to FIG. 27 can transfer data directly from the input unit 3 to the storage unit 6 and transfer data directly from the storage unit 6 to the output unit 4. As an example of data transfer applicable to the configuration example, image data is transferred from the input unit 3 to the storage unit 6 in synchronization with the line synchronization signal by the high-speed serial bus 7, and the image data is synchronized with the line synchronization signal. Basically, the data is transferred from the storage unit 6 to the output unit 4.

  FIG. 29 is a schematic timing chart showing the order of command issuance. In FIG. 29, the image data read request command MemReadReq. And the write request command MemWriteReq. Are transmitted using the high-speed serial bus 7 without setting the priority in synchronization with the line synchronization signal XLDSYNC and in accordance with the read request command MemReadReq. It is an operation example when receiving read data MemReadComp.

  However, when a command is issued as shown in FIG. 29, image data transfer cannot be performed normally due to variations in the influence of path delay (variations due to changes in connection configuration, timing variations due to competing data transfer, etc.). There is a case. That is, there may be a case where the read data MemReadComp. Cannot be received within the line valid period XLGATE as shown in FIG.

  FIG. 31 is an explanatory diagram showing a relationship between a request packet and a corresponding completion packet when a command is issued. FIG. 31 shows a state where a completion packet corresponding to the transmitted read request packet is returned. The completion packet is composed of a header part and a payload part. As shown in FIG. 31, the influence of the path delay between the read request packet (read request command MemReadReq.) And the completion packet (read data MemReadComp.) Varies, so that the read data MemReadComp. There will be cases where it cannot be received.

  Here, FIG. 32 is a characteristic diagram exemplarily showing the influence of delay in the case of passing through a switch and in the case of not passing through a switch. As shown in FIG. 32, when passing through a switch which is one of the delay elements in the path, the delay differs depending on the difference in the mounting method (for example, memory mounting method) inside the switch (structure 1-3). It can be seen that the characteristics change due to the variation. Here, the difference in the memory mounting method is whether it is a dual port memory or a single port memory.

  FIG. 33 is a characteristic diagram exemplarily showing the influence of delay due to the change in the number of stages when passing through a switch. As shown in FIG. 33, it can be seen that the variation in characteristics is further increased by changing the number of switch stages, which is one of the delay elements in the path.

  That is, in the prior art, since the optimum payload size (payload length) fluctuates by system expansion, there was no expandability. Also, due to the influence of path delay, the transfer rate as a system cannot be secured even if the payload size is increased. Therefore, in this embodiment, the payload size is determined by the following method.

  First, as shown in FIG. 31, the time difference (path delay) from the start time of transmission of the read request packet to the time of arrival of the head of the corresponding completion packet is set as T1, and the target from the start time of transmission of the read request packet. The time difference (transfer time) until the reception completion time of the last compression of all data is T2. Further, the header size of the compression packet is A [Byte], and the payload size of the compression packet is B [Byte].

  Next, a curve obtained by calculating a ratio of T1 / T2 to the payload size of the compression packet is defined as a curve 1 indicating a path delay overhead. On the other hand, a curve obtained by calculating a ratio of A / (A + B) to the payload size of the compression packet is a curve 2 indicating header overhead. Here, FIG. 34 is a characteristic diagram showing loss characteristics by factor. As shown in FIG. 34, the intersection of the curve 1 and the curve 2 is between 128 bytes and 256 bytes. Then, as shown in FIG. 34, it can be seen that there is little loss with respect to the theoretical value of the transfer rate when the payload size is equal to or less than the intersection of the curve 1 and the curve 2. Therefore, in the present embodiment, the transfer is performed with a payload size equal to or smaller than the intersection of the curve 1 and the curve 2. Thus, the curve obtained by calculating the ratio of T1 / T2 to the payload size of the compression packet is equal to or less than the intersection of the curve 1 and the curve 2 of calculating the ratio of A / (A + B) to the payload size of the compression packet. By performing the transfer with the payload size of 1, it is possible to realize high-speed data transfer in consideration of the influence of the path delay and the influence of the protocol overhead in a well-balanced manner.

  Here, as shown in FIG. 32, it can be seen that the larger the delay amount, the smaller the peak payload size, and the smaller the delay amount, the larger the peak payload size. The payload size of such a peak corresponds to the intersection of the two curves in FIG. That is, the larger the delay amount, the smaller the payload size at the intersection point, and the smaller the delay amount, the larger the payload size at the intersection point. That is, it is desirable to change the payload size according to the delay amount of the route. In this way, by making the payload size changeable according to the delay amount of the path, the fastest high-speed data transfer can always be realized even when the delay amount dynamically fluctuates.

  Further, as shown in FIG. 33, it can be seen that the peak payload size decreases as the number of switch stages increases, and the peak payload size increases as the number of switch stages decreases. That is, it is desirable to change the payload size according to the number of switch stages in the route. In this way, by making the payload size changeable according to the number of switch stages in the path, the fastest high-speed data transfer can always be realized even when there is a dynamic change in the number of switch stages.

  The payload size can be changed according to the delay amount of the path and the number of switch stages of the path by setting the configuration space register with software (see FIG. 10). In this way, the delay amount of the path and the number of switch stages of the path change usually when the connection is changed. In other words, the payload size may be changed according to the path delay amount and the path switch stage number at the time of PCI Express reconfiguration.

  The transfer may be performed using a payload size that is 1/4 to 4 times the center of the payload size at the intersection of the curves 1 and 2. As shown in FIG. 34, it is a decrease of 20% or more outside 1/4 to 4 times, and the payload size to be used is not very practical. In this case, the influence of the path delay and the header overhead are considered in a balanced manner, and high-speed data transfer can be realized.

  By the way, the time difference T1 from the adjacent start time of the read request packet to the time when the head of the corresponding compression packet arrives and the reception of the last completion packet of all the target data from the read start time of the read request packet. The time difference T2 until the completion time can be measured by a route complex (time difference measuring means) 31 corresponding to the control unit to which the CPU 30 is connected as shown in FIG. As shown in FIG. 35, a route complex (time difference measuring means) 31 corresponding to the control unit to which the CPU 30 is connected includes a measurement packet generation circuit 31a that is a measurement packet generation unit and a delay amount that is a delay amount detection unit. A detection circuit 31b and a delay amount storage circuit 31c as a delay amount storage unit are provided. The delay amount detection circuit 31b detects the time difference T1 and the time difference T2 based on the output time of the measurement packet generated by the measurement packet generation circuit 31a and the reception time of the return packet from the end point 32. The detected time difference T1 and time difference T2 are stored in the delay amount storage circuit 31c. Note that a plurality of packets with different payload sizes may be used as measurement packets. As a result, the intersection of the two curves can be automatically predicted based on the actual measurement value.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. It is a block diagram which shows the architecture of the existing PCI. It is a block diagram which shows the architecture of PCI Express. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. It is a schematic block diagram which shows the structural example of the information processing system of one Embodiment of this invention. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a schematic block diagram which shows the example of an optimal structure of an information processing system. It is a typical timing chart which shows command issue order. It is a typical timing chart which shows command issue order. It is explanatory drawing which shows the relationship between the request packet at the time of command issuing, and the corresponding completion packet. It is a characteristic view which shows the influence of the delay in the case where it does not pass through the case where it passes via a switch. It is a characteristic view which shows the influence of the delay by the change of the stage number at the time of passing through a switch exemplarily. It is a characteristic view which shows the loss characteristic according to factor. 1 is a configuration diagram exemplarily showing a PCI Express system including a delay amount detection unit. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing system 7 High-speed serial bus 31 Time difference measurement means 31a Measurement packet generation part 31b Delay amount detection part 31c Delay amount storage part

Claims (16)

In an information processing system that performs communication in units of packets by a high-speed serial bus in which a communication channel independent of transmission and reception is established through a communication network configured by a tree structure of point-to-point connections or multiple point-to-point connections
The time difference T1 from the request packet transmission start time to the arrival time of the beginning of the compression packet corresponding to the request packet, and the reception of the last compression packet of all target data from the request packet transmission start time Means for detecting a curve 1 in which a ratio (T1 / T2) to a payload size of a completion packet is obtained based on a time difference T2 until completion time;
Means for detecting a curve 2 in which a ratio (A / (A + B)) to the payload size of the completion packet is obtained based on the header size A of the completion packet and the payload size B of the completion packet;
Means for determining a payload size of packet transfer based on the curve 1 and the curve 2 with less loss with respect to a theoretical transfer rate;
An information processing system comprising: The determined payload size is less than or equal to the intersection of the curve 1 and the curve 2;
The information processing system according to claim 1. The payload size to be determined is a payload size that is 1/4 to 4 times the payload size at the intersection of the curve 1 and the curve 2;
The information processing system according to claim 1. The payload size can be changed according to the delay amount of the route.
The information processing system according to any one of claims 1 to 3, wherein The payload size can be changed according to the number of switch stages in the route.
The information processing system according to any one of claims 1 to 3, wherein The payload size change is performed during reconfiguration of the high-speed serial bus.
6. The information processing system according to claim 4 or 5, wherein Time difference T1 from the start time of transmission of the request packet to the time of arrival of the head of the compression packet corresponding to the request packet, and reception of the last compression packet of all the target data from the start time of transmission of the request packet It further comprises time difference measuring means for measuring the time difference T2 until the time,
The curve 1 is detected based on the time difference T1 and the time difference T2 measured by the time difference measuring means.
The information processing system according to claim 1, wherein the information processing system is an information processing system. The time difference measuring means calculates a delay amount based on a measurement packet generation unit that generates a measurement packet, an output time of the measurement packet generated by the measurement packet generation unit, and a reception time of a return packet from the end point. A delay amount detection unit to detect, and a delay amount storage unit to store the delay amount detected by the delay amount detection unit,
The information processing system according to claim 7. As the measurement packet, a plurality of packets having a payload size are used.
The information processing system according to claim 8. The high-speed serial bus is a PCI Express standard high-speed serial bus.
An information processing system according to any one of claims 1 to 9, wherein A program for causing a computer to execute communication processing in units of packets by a high-speed serial bus in which a communication channel independent of transmission and reception is established through a communication network in which point-to-point connection or a plurality of point-to-point connections are configured in a tree structure. ,
The time difference T1 from the request packet transmission start time to the arrival time of the beginning of the compression packet corresponding to the request packet, and the reception of the last compression packet of all target data from the request packet transmission start time A function of detecting a curve 1 in which a ratio (T1 / T2) to a payload size of a completion packet is obtained based on a time difference T2 until a completion time;
A function of detecting a curve 2 in which a ratio (A / (A + B)) to the payload size of the completion packet is obtained based on the header size A of the completion packet and the payload size B of the completion packet;
A function for determining a payload size for packet transfer based on the curve 1 and the curve 2 and having a small loss with respect to a theoretical transfer rate;
That causes the computer to execute the program. The determined payload size is less than or equal to the intersection of the curve 1 and the curve 2;
12. The program according to claim 11, wherein: The payload size to be determined is a payload size that is 1/4 to 4 times the payload size at the intersection of the curve 1 and the curve 2;
12. The program according to claim 11, wherein: A packet communication method in an information processing system that performs communication in units of packets by a high-speed serial bus in which a communication channel independent of transmission and reception is established through a communication network in which point-to-point connections or a plurality of point-to-point connections are configured in a tree structure And
The time difference T1 from the request packet transmission start time to the arrival time of the beginning of the compression packet corresponding to the request packet, and the reception of the last compression packet of all target data from the request packet transmission start time Detecting a curve 1 in which the ratio (T1 / T2) to the payload size of the completion packet is calculated based on the time difference T2 until the completion time,
A curve 2 is obtained that is obtained by calculating a ratio (A / (A + B)) to the payload size of the compression packet based on the header size A of the compression packet and the payload size B of the compression packet.
Based on the curve 1 and the curve 2, the payload size of the packet transfer with a small loss with respect to the theoretical value of the transfer rate is determined.
And a packet communication method. The determined payload size is less than or equal to the intersection of the curve 1 and the curve 2;
The packet communication method according to claim 14. The payload size to be determined is a payload size that is 1/4 to 4 times the payload size at the intersection of the curve 1 and the curve 2;
The packet communication method according to claim 14.

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