JP5510146B2 - Power converter control circuit - Google Patents

Description

  The present invention relates to a control circuit for a power converter that performs power conversion between a DC voltage and an AC voltage.

FIG. 8 is a main circuit configuration diagram of an inverter described in Non-Patent Document 1 described later. This circuit is composed of eight self-extinguishing semiconductor switches S _{1 to} S ₈ such as IGBTs and diodes D _{1 to} D _6, which are DC voltages of series circuits of capacitors C _{1 to} C ₄ having the same capacity. The U-phase unit 40U, the V-phase unit 40V, and the W-phase unit 40W are converted into a three-phase AC voltage and supplied to the load 50. This type of inverter is generally called a five-level inverter because it can output five voltage levels when viewed from the midpoint M of the DC circuit.
In FIG. 8, 10 is a three-phase AC power source, 20 is a rectifier circuit, 30 is a voltage equalizing circuit, P ₁ , P ₂ , N ₁ and N ₂ are nodes, and U, V and W are AC output terminals. .

In this 5-level inverter, the voltages of the _four capacitors C _{1 to} C ₄ may become non-uniform (hereinafter also referred to as unbalance) due to variations in the characteristics of the component parts. If the voltages of the capacitors C _{1 to} C ₄ are unbalanced, not only the desired output voltage cannot be obtained, but also the voltage applied to each component exceeds the maximum rated voltage, and the device may be destroyed. .
Therefore, in the circuit of FIG. 8, a voltage equalizing circuit 30 is provided to keep the voltages of the capacitors C _{1 to} C ₄ uniform (hereinafter also referred to as equilibrium). Here, the voltage equalization circuit 30 includes, between the output terminals of the rectifier circuit 20, semiconductor switches S _{11 to} S ₁₄ and a series resonance circuit (inductor L _r and capacitor C _r ), and similarly semiconductor switches S _{15 to} S ₁₈ and series. A circuit composed of a resonance circuit is connected in series, and the semiconductor switches S _{11 to} S ₁₈ are switched at a frequency lower than the resonance frequency of the series resonance circuit, so that the output phase voltage of the inverter is zero-phase voltage. Is superimposed to suppress the nodal current that causes voltage imbalance. Note that the specific operation of the voltage equalizing circuit 30 is not directly related to the present invention, and thus detailed description thereof is omitted here.

Kenichiro Sano, Hideaki Fujita, “Examination of current rating reduction of RSCC DC voltage equalization circuit for diode clamp type 5 level converter”, 2008 IEEJ Industrial Application Division Conference, 1st volume, I-549-552 (Fig. 1)

As described above, the voltage equalizing circuit 30 are those provided on the assumption that the voltage of the capacitor C ₁ -C ₄ are unbalanced, the voltage of the capacitor C ₁ -C ₄ by other means In the case where the balance can be achieved, the voltage equalizing circuit 30 itself hinders the reduction of the number of components, the miniaturization of the entire apparatus, and the cost reduction.
Accordingly, the problem to be solved by the present invention is to simplify the circuit configuration, reduce the overall size of the apparatus, and reduce the cost without adding a special circuit to balance the voltages of a plurality of capacitors to which a DC power supply voltage is applied. An object of the present invention is to provide a control circuit for a power conversion device that can be realized.

In order to solve the above-mentioned problem, the invention according to claim 1 is directed to a capacitor series circuit in which first and second capacitors are connected in series, a DC power supply connected in parallel to the capacitor series circuit, and a plurality of semiconductor switches. At least a semiconductor switch series circuit connected in series and a third capacitor connected to the semiconductor switch series circuit, and the voltage of the third capacitor is constant using the voltage of the first and second capacitors as a power source. In the control circuit of the power conversion device that turns on and off the semiconductor switch to be a value and outputs an alternating voltage according to a voltage command value from an internal connection point of the semiconductor switch series circuit,
Means for detecting a deviation in voltage of the first and second capacitors and means for adding a correction amount corresponding to the deviation to the voltage command value are provided.

  According to a second aspect of the present invention, in the control circuit of the power conversion device according to the first aspect, means for determining the load power factor, and means for inverting the polarity of the correction amount according to the determination result of the load power factor; , With.

  According to the present invention, the voltage of a plurality of capacitors can be balanced only by adding a few components to the conventional control circuit, and the circuit configuration can be simplified, the entire device can be reduced in size, and the cost can be reduced. is there.

It is a block diagram of the control circuit which shows 1st Embodiment of this invention. It is a block diagram of the control circuit which shows 2nd Embodiment of this invention. It is a main circuit block diagram for the output one phase of the power converter device which concerns on a prior application. FIG. 4 is a waveform diagram of an output voltage in FIG. 3. It is a block diagram of the control circuit of the power converter device which concerns on a prior application. It is a block diagram of the power converter device provided with the circuit of FIG. 3 for three phases. It is a main circuit block diagram for one output of another power converter to which the present invention is applied. 2 is a main circuit configuration diagram of an inverter described in Non-Patent Document 1. FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, as an example of a power conversion apparatus to which the present embodiment is applied, a power conversion apparatus according to an inventor's prior application (Japanese Patent Application No. 2009-89231) will be described. The main purpose of this power conversion device is to reduce the generation loss by reducing the number of semiconductor switches compared to the prior art of FIG.

FIG. 3 is a main circuit configuration diagram for one output phase (U phase) of the power conversion device according to the prior application.
In FIG. 3, a DC power source E is connected in parallel with a series circuit of semiconductor switches S _{1 to} S _{4 made} of an IGBT having anti-reflective diodes connected in antiparallel, and a series circuit of capacitors C ₁ and C ₂ . . In addition, a series circuit of bidirectional switches S ₅ and S ₆ , which can cut off bidirectional current by connecting IGBTs in anti-parallel, and has bidirectional breakdown voltage, is in parallel with a series circuit of semiconductor switches S ₂ and S _3. It is connected to, and is further connected in parallel also the capacitor C _3.
The series connection point of the bidirectional switches S ₅ and S ₆ is connected to the midpoint of the DC circuit (series connection point of the capacitors C ₁ and C ₂ ) M, and the series connection point of the semiconductor switches S ₂ and S ₃ is It is connected to a U-phase output terminal U.

Here, when the voltage of the DC power source E is E _d , the voltage of the capacitor C ₁ is V _c1 , the voltage of the capacitor C ₂ is V _c2 , and the voltage of the capacitor C ₃ is V _c3 , the output voltage V observed from the middle point M Table 1 shows the relationship between the _UM and the on / off states of the switches S _{1 to} S ₆ .
In Table 1, the operation modes corresponding to the on / off states of the switches S _{1 to} S ₆ are referred to as modes 1 to 8, respectively.

When an appropriate switch in FIG. 3 is selected and turned on / off based on Table 1, the output voltage V _UM is changed to five voltage levels (E _d / 2, E _d / 4, 0, − E _d / 4, −E _d / 2), and the average voltage is a sinusoidal waveform.
The current polarity in Table 1, there arrow direction of the load current i _U in FIG. 3 as the positive direction (+), the symbol c, d, respectively, by the polarity of the on-off mode and load current switch selected capacitor C ₃ is shown that is charged or discharged.

According to Table 1, for example, in order to set the output voltage to E _d / 4, either mode 2 or mode 3 may be selected. That is, the load current polarity and according to the voltage value V _c3 of the capacitor C _3, by selecting one of the mode 2 or mode 3, it is possible to charge or discharge the capacitor C _3, the voltage value V of the capacitor C ₃ It is possible to supply the output voltage of the same value (E _d / 4) to the load while adjusting _c3 to E _d / 4.

Next, FIG. 5 is a configuration diagram of a control circuit of the power conversion device shown in FIG.
In FIG. 5, the triangular waves tri _{1 to} tri ₄ have an amplitude (peak-peak value) of 1/2, and the DC components (offsets) of the triangular waves are 3/4, 1/4, -1 / 4, -3/4.
The first comparator 61 compares the voltage command value V _U ^* with the triangular waves tri _{1 to} tri ₄ , respectively, and based on the logic shown in Table 2 below, the five-level output voltage E _{d of the} power converter. / 2, E _d / 4, 0, -E _d / 4, -E _d / 2 are determined.

The second comparator 62 in FIG. 5 is for detecting that the voltage V _c3 of the capacitor C ₃ is equal to the command value E _d / 4. The comparator 62 has a hysteresis characteristic. May be allowed.
The third comparator 63 is for detecting the polarity of the load current i _U.

The on / off switch selection unit 70 of FIG. 5 outputs a drive signal so as to turn on / off an appropriate switch among the switches S _{1 to} S ₆ according to Table 1 based on the outputs of the comparators 61, 62, and 63.
For example, when the output voltage V _UM is E _d / 4, when the voltage of the capacitor C ₃ is lower than the command value E _d / 4 and the polarity of the load current i _U is positive, Mode 2 is selected, and each switch is turned on / off to output E _d / 4 while charging the capacitor C ₃ .
Further, according to Table 1, when the output voltage V _{UM is set} to 0, either mode 4 or mode 5 can be selected, but if only one mode is selected, loss is biased to a specific switch. The on / off switch selection unit 70 can also prevent loss from being biased to a specific switch by a method of alternately selecting mode 4 and mode 5.

FIG. 6 is a power conversion device provided with the circuit shown in FIG. 3 for three phases. The U-phase unit 100U, the V-phase unit 100V, and the W-phase unit 100W share capacitors C ₁ and C ₂ respectively. It has become. In FIG. 6, S _{1U to} S _6U , S _{1V to} S _6V , S _{1W to} S _6W are U, V, and W phase switches, and C _3U , C _3V , and C _3W are capacitors.
According to the power converter of FIG. 6, the DC voltage E _d of the power supply E into a three-phase AC voltage, AC output terminal U, V, W output to load the five voltage levels as seen from the middle point M to the 50 and a function equivalent to that of the prior art in FIG. 8 can be realized by a smaller number of semiconductor switches than in FIG.

In the power converter shown in FIG. 6 as well, there may be an imbalance in the voltages of the capacitors C ₁ and C ₂ on the DC power supply E side due to component variations and the like. A means for suppressing the voltage imbalance of the capacitors C ₁ and C ₂ without using the voltage equalizing circuit 30 as shown in FIG. 8 will be described below.

FIG. 1 is a configuration diagram of a control circuit according to the first embodiment of the present invention, and is for controlling the power conversion apparatus shown in FIG.
In FIG. 1, 5U is a U-phase control unit that controls on / off of switches S _{1U to} S _6U in FIG. 6, 5V is a V-phase control unit that similarly controls on / off of switches S _{1V to} S _6V , and 5W is also a switch S _{1W to} S _This is a W-phase control unit that performs on / off control of _6W . The configurations of these control units 5U, 5V, and 5W are basically the same as those shown in FIG. 5, but in this embodiment, the deviations of the voltages V _c1 and V _c2 of the capacitors C ₁ and C ₂ are _calculated . The correction amount obtained by detecting and amplifying the voltage deviation is added to the output voltage command values V _U ^* , V _V ^* , and V _W ^* of each phase to suppress the voltage imbalance of the capacitors C ₁ and C _2. The point is a feature.

That is, in FIG. 1, the subtractor 91 obtains the deviation between the voltage detection values V _c1 and V _c2 of the capacitors C ₁ and C ₂ . This deviation is amplified by the deviation amplifier 6, and is added to the output voltage command values V _U ^* , V _V ^* , V _W ^* by the adders 9U, 9V, 9W of the respective phases as correction amounts.
The outputs of the adders 9U, 9V, and 9W are input to the first comparators 1U, 1V, and 1W of the respective phases together with the triangular waves tri _{1 to} tri ₄ . As described above, the triangular waves tri _{1 to} tri ₄ have an amplitude (peak-peak value) of 1/2, and the DC components (offsets) of the triangular waves are 3/4, 1/4, −1 / 4, -3/4.
The first comparators 1U, 1V, and 1W respectively compare the outputs of the adders 9U, 9V, and 9W with the triangular waves tri _{1 to} tri ₄ and, for example, the U phase based on the logic shown in Table 2 described above (V The same applies to the phase and the W phase), and determines five voltage levels (E _d / 2, E _d / 4, 0, -E _d / 4, -E _d / 2) of the output voltage.

Further, the second comparators 2U, 2V, and 2W of the respective phases in FIG. 1 have voltages V _c3U , V _c3V , and V _c3W of the capacitors C _3U , C _3V , and C _3W in FIG. 6 and their command values E _d / 4. detecting respectively, that is equal to the addition, the phases of the third comparator 3U, 3V, 3W is for detecting the load current _{i U,} i V, the polarity of _{i W} respectively. Note that the detection outputs of the comparators 2U, 2V, 2W, 3U, 3V, and 3W are input to the on / off switch selection units 4U, 4V, and 4W of the respective phases.

In the present embodiment, as a result of correcting the output voltage command values V _U ^* , V _V ^* , and V _W ^* with the above configuration, each phase output voltage has a voltage corresponding to the voltage deviation of the capacitors C ₁ and C _2. It will be superimposed. However, since the superimposed voltage is canceled out by the line voltage, there is no problem that a direct current component is superimposed on each phase output voltage.
Hereinafter, the reason why the voltage imbalance of the capacitors C ₁ and C ₂ is suppressed according to the present embodiment will be conceptually described. In order to simplify the description, in the first embodiment, a state where the phase voltage and the phase of the current coincide with each other (load power factor = 1) is assumed.

3, the current flowing out from the connection point (middle point) M of the capacitors C ₁ and C ₂ is i _M, and the direction of the arrow i _M in FIG. 3 is the positive direction. When defined in this way, if i _M is positive, the capacitor C ₁ is charged and the voltage V _c1 rises. On the other hand, the capacitor _{C 2} is the voltage _{V c2} decreases in discharge.

  Table 3 below shows the load current path for each mode of each switch when the load power factor is 1. Modes 1 to 5 (states (1) to (5) for convenience) in the upper part of Table 3 correspond to the state in which the output voltage is a positive voltage and the output current flows in the positive direction. Modes 4 to 8 (states (6) to (10) for convenience) correspond to a state in which the output voltage is a negative voltage and the output current is flowing in the negative direction. Note that these modes 1 to 8 coincide with the modes 1 to 8 in Table 1 described above.

As can be seen from Table 3, i _M flows in states (3), (4), (5), (6), (7), and (8). For example, if the period in which the states (3), (4), (5) occur within one cycle of the AC output voltage decreases and the period in which the states (6), (7), (8) occur increases, the average value of i _M in one cycle of the AC output voltage is a negative value.
Taking this into consideration, for example, when the voltages of the capacitors C ₁ and C ₂ are V _c1 > V _c2 and are unbalanced, in order to suppress this, i _M in one cycle of the AC output voltage can be suppressed. It is sufficient to make the average value of the negative.

As an example, when V _c1 > V _c2 , consider adding a positive DC component to the output voltage by adding a correction amount to the output voltage command value. Considering the period in which the positive voltage is generated (states (1) to (5)), since the positive voltage output by superimposing the DC component increases, the states (1), ( The period in which 2) and (3) occur increases, and the period in which states (4) and (5) occur decreases. Here, considering that the average value of i _M to a negative value, contrary to the above, the period of occurrence of state (3) is increased.

However, considering that the voltage of the capacitor C ₃ is controlled to be a constant value, the period in which the capacitor C ₃ is charged (2) and the period in which the capacitor C ₃ is discharged (3) are equivalent. because there, as a result, the state (3) generating the period of an increase in does not contribute to increase or decrease the i _M. (I _M increases as the period in which state (3) occurs increases, but i _M decreases as the period in which state (2) occurs increases, resulting in states (2), (3 ) increase in the period of occurrence of do not contribute to the increase or decrease of the i _M).
That is, as a result, when the period in which the states (2) and (3) occur is excluded, the period in which the state (1) occurs increases and the period in which the states (4) and (5) occur By decreasing, i _M decreases.

On the other hand, considering the period during which a negative voltage is generated (states (6) to (10)), the negative voltage that is output by superimposing the DC component decreases (absolute value decreases). Therefore, the period in which states (6) and (7) occur increases, and the period in which states (8), (9) and (10) occur decreases. In this case, in the same manner as described above, as a result, given by excluding the period of occurrence of state (9) that condition (8) and a capacitor C ₃ of the capacitor C ₃ is discharged is charged, the state (6) , (7) the increased time to occur, that the period of occurrence of state (10) is reduced, i _M increases in the negative direction.

In _summary , in the case of V _c1 > V _c2 , if a positive DC component is superimposed on the output voltage, the average value of i _M in one cycle of the AC output voltage decreases (increases in the negative direction). Thus, voltage imbalance of the capacitors C ₁ and C ₂ can be suppressed.
In the case of V _c1 <V _c2 , if a negative DC component is superimposed on the output voltage, the average value of i _M in one cycle of the AC output voltage increases, and similarly, capacitors C ₁ and C ₂ Can be suppressed.
The subtractor 91, the deviation amplifier 6 and the adders 9U, 9V, and 9W in FIG. 1 use correction amounts generated according to the voltages V _c1 and V _c2 of the capacitors C ₁ and C ₂ in order to realize the above-described operation. It is used to correct the output voltage command values V _U ^* , V _V ^* , and V _W ^* of each phase.

  Next, FIG. 2 is a block diagram of a control circuit according to the second embodiment of the present invention. In this second embodiment, a deviation amplification polarity switching unit 80 comprising a power factor calculator 81, a power factor positive / negative discriminator 82, a switch 83 and a multiplier 84 is added to FIG. 1 described as the first embodiment. Is different.

Hereinafter, the operation of the second embodiment will be described. The first embodiment has been described when the load power factor is 1. On the other hand, when the load power factor is -1, the operation is reversed.
For example, when V _c1 > V _c2 , the first value in terms of suppressing the voltage imbalance of the capacitors C ₁ and C ₂ by making the average value of i _M in one cycle of the AC output voltage negative is the first This is the same as the embodiment. However, when the load power factor is −1, the polarity of the current is different from that in the first embodiment. Therefore, when V _c1 > V _c2 , if a positive DC component is superimposed on the output voltage as described above, the voltage is This will promote an imbalance.

For this reason, the power factor calculation unit 81 in the deviation amplification polarity switching unit 80 of FIG. 2 is based on the output voltage command values V _U ^* , V _V ^* , V _W ^* and the output current detection values i _U , i _V , i _W. By calculating the load power factor and switching the switch 83 according to the positive / negative discrimination result by the positive / negative discriminator 82, the multiplier 84 switches the gain multiplied by the output of the deviation amplifier 6 to “1” or “−1”. As a result, when the load power factor is negative, the polarity of the direct current component as a correction amount to be added to the voltage command values V _U ^* , V _V ^* , and V _W ^* can be inverted, thereby the capacitor C ₁ , C ₂ voltage imbalance can be suppressed.

Here, the above-described first and second embodiments are exclusively intended for the power conversion device shown in FIG. 6, but the present invention is a circuit having a configuration as shown in FIG. The present invention can also be applied to a power converter provided with three phases). In this power conversion device, the switches S _{1 to} S ₈ are appropriately selected and turned on / off, whereby the output voltage V _UM has nine voltage levels (V _c1 + V _c3 , V _c1 , V _c1 −V _c3 , V _c3 , 0, −V _c3 , −V _c2 + V _c3 , −V _c2 , −V _c2 −V _c3 ), and an average voltage having a sinusoidal waveform can be obtained. The configuration and operation of the power conversion device itself are not the gist of the present invention, and thus detailed description thereof is omitted here.

  In the above-described embodiment, the case where the DC voltage is converted into the three-phase AC voltage has been described. However, the present invention is naturally applicable to the case where the output frequency is 0 [Hz], that is, when the DC voltage is converted. It is.

_{S 1 ~S 4, S 1U ~S} 4U, S 1V ~S 4V, S 1W ~S 4W: semiconductor switches _{S 5, S 6, S 5U} , S 6U, S 5V, S 6V, S 5W, S 6W: Bidirectional switches C ₁ , C ₂ , C ₃ , C _3U , C _3V , C _3W : Capacitor E: DC power supply M: Midpoint U, V, W: AC output terminals 1U-3U, 1V-3V, 1W-3W : Comparator 4U, 4V, 4W: On / off switch selector 5U: U-phase controller 5V: V-phase controller 5W: W-phase controller 6: Deviation amplifiers 9U, 9V, 9W: Adder 50: Load 80: Deviation amplification Polarity switching unit 81: power factor calculator 82: positive / negative discriminator 83: switch 84: multiplier 91: subtractor 100U: U-phase unit 100V: V-phase unit 100W: W-phase unit

Claims (2)

A capacitor series circuit in which first and second capacitors are connected in series, a DC power source connected in parallel to the capacitor series circuit, a semiconductor switch series circuit in which a plurality of semiconductor switches are connected in series, and the semiconductor switch series circuit At least a third capacitor connected to the semiconductor switch, and the semiconductor switch is turned on and off so that the voltage of the third capacitor becomes a constant value using the voltage of the first and second capacitors as a power source. In the control circuit of the power converter that outputs AC voltage according to the voltage command value from the internal connection point of the series circuit,
A control circuit for a power converter, comprising: means for detecting a voltage deviation of the first and second capacitors; and means for adding a correction amount corresponding to the deviation to the voltage command value. In the control circuit of the power conversion device according to claim 1,
A control circuit for a power converter, comprising: means for determining a load power factor; and means for inverting the polarity of the correction amount according to a determination result of the load power factor.

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