JP4641500B2 - Power converter - Google Patents

Description

  The present invention relates to a power converter capable of combining a plurality of inverters and obtaining a desired output waveform by gradation control.

  A conventional power conversion device is composed of a single-phase multiple converter in which three single-phase inverters are connected in series. Each single-phase inverter has a three-phase converter section that rectifies and converts three-phase AC power drawn from the system through a transformer into DC power, a capacitor that smoothes the DC power, and uses the capacitor as a DC power source to convert DC power to AC. A single-phase inverter unit for converting into electric power. Each single-phase inverter configured as described above outputs voltages using voltages Va, Vb and Vc charged in the capacitors as voltage sources, but the relationship between Va, Vb and Vc is different from each other (Va <Vb). <Vc) and any of 1: 2: 4, 1: 3: 4, 1: 3: 5, 1: 3: 6, 1: 3: 7, 1: 3: 8, 1: 3: 9 It becomes a relationship. A very smooth output gradation voltage can be obtained by combining the voltages generated by the three single-phase inverters (see, for example, Patent Document 1).

  In addition, the conventional power conversion device according to another example has a multi-level inverter using a flying capacitor, and has a flying capacitor configuration in which the voltage ratio of the three capacitors is 1: 2: 3 (for example, see Non-Patent Document 1). .

JP 2004-007941 A “Multicell Converters: Active Control and Observation of Flying-Capacitor Voltages”, IEEE Trans. Ind. Electron. Vol. 49, No.5, pp. 998-1008, 2002.

  In the power conversion device disclosed in Patent Document 1, for example, a power conversion device including three single-phase inverters in which the relationship of Va, Vb, and Vc is 1: 2: 4, 12 switching elements and 3 capacitors are used. Maximum 7-level output on one side (excluding zero output) is possible. However, in order to operate with a large number of output levels, a power source for supplying power to the capacitors of each single-phase inverter is required. Even if the number of output levels is suppressed to about 4 levels on one side, the number of switching elements is It could not be reduced.

  On the other hand, the power conversion device disclosed in Non-Patent Document 1 enables one-side three-level output (not including zero output) with a small number of switching elements, and eliminates the need for a power supply for supplying power to each capacitor. However, there is a problem that the number of capacitors is large with respect to the number of output levels.

  The present invention has been made to solve the above-described problems, and in a power conversion device that performs gradation control of a plurality of single-phase inverters, a multilevel output with a small number of switching elements and capacitors. It is possible to simplify the device configuration and increase the efficiency by making it possible to omit the power supply and the converter for supplying power to each capacitor.

Power converting apparatus according to the present invention, each AC side of a plurality of single-phase inverter that converts the DC power of the DC voltage source and a plurality of switching elements DC voltage source to AC power are connected in series, the The output voltage is controlled by the sum of the voltages generated by a plurality of single-phase inverters to supply power to the load. Among the plurality of single-phase inverter, at least one has a said DC voltage source of multiple, alternating side the respective DC voltage source by a combination of on-off of the plurality of switching elements in either a positive or negative polarity This is a multilevel inverter that is connected between output terminals to enable multilevel voltage output. And then. Multi-level inverter, the plurality of the DC voltage source, constituted by a supplied external power or et power first DC voltage source and the other second DC voltage source of the voltage is maximum, the When the voltage is output between the AC side output terminals from both the first DC voltage source and the second DC voltage source, the first and second DC voltage sources are controlled by a combination of ON and OFF of the plurality of switch elements. the first is connected in series with opposite polarity to each other, in which the difference between the voltage of the second DC voltage source is output.

In such a power converter, to allow multi-level output in the conventional several switch element and a DC voltage source of less than that of. Further, among the plurality of DC voltage sources, a power supply and a converter for supplying power to a DC voltage source other than the first DC voltage source where the voltage in the multi-level inverter is maximum can be omitted. Can be achieved.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below.
1 is a diagram showing a main circuit configuration of a power conversion device according to Embodiment 1 of the present invention. As shown in the figure, the power conversion device 3 is configured by connecting the AC sides of a plurality of (in this case, two) single-phase inverters 41 and 42 in series. Each single-phase inverter 41, 42 converts the DC power from the independent DC voltage source 5 (51-53) into AC power, and combines the voltages generated by the single-phase inverters 41, 42 to give a predetermined total sum. And is connected to the load from the output terminals 2a and 2b via the output filter 6. Note that the output filter 6 may be omitted in applications where the waveform distortion of the output voltage is not questioned.
Each single-phase inverter 4 (41, 42) is composed of a plurality of self-extinguishing semiconductor switching elements (hereinafter referred to as switching elements) 7a to 7j such as IGBTs (Insulated Gate Bipolar Transistors) connected with diodes in antiparallel. Composed. The switch elements 7a to 7j may be GCT, GTO, transistor, MOSFET or the like in addition to the IGBT. A thyristor or the like that does not have a self-extinguishing function only needs to be able to perform forced commutation.

  One single-phase inverter 41 is a full-bridge inverter including two sets of two series switch elements (7a, 7b) and (7c, 7d), and the DC voltage of the capacitor 51 as the third DC voltage source is V1. In this case, any voltage of {−V1, 0, V1} can be applied between the output terminals of the single-phase inverter 41 depending on the on / off combination of the switch elements 7a to 7d.

The other single-phase inverter 42 is a multi-level inverter 42 in which a capacitor 53 as a first DC voltage source and a capacitor 52 as a second DC voltage source that are insulated from each other are input to DC power. The multi-level inverter 42 includes four series switch elements 7e to 7h and two series switch elements 7i and 7j connected between the positive and negative terminals of the capacitor 53, and the center of the four series switch elements 7e to 7h. A capacitor 52 is connected between both terminals of the two series switch elements 7f and 7g, and the midpoint of the four series switch elements 7e to 7h and the midpoint of the two series switch elements 7i and 7j are connected to the AC side of the multilevel inverter 42. Output pin.
When the voltages of the capacitors 52 and 53 of the multilevel inverter 42 are V2 and V3, {−V3, −V3 + V2, −V2, 0, Any voltage of V2, V3-V2, and V3} can be applied between the output terminals. Here, when voltage is output from both of the capacitors 52 and 53, it is understood that the capacitors 52 and 53 are connected in series with opposite polarities to output a differential voltage (-V3 + V2, V3-V2). .

Among the voltages of the three capacitors 51 to 53, the voltage V3 of the capacitor 53 is the maximum, and the capacitor 53 is supplied with electric power from the external power source 1 and is voltage-controlled. Reference numerals 81 to 83 denote voltage sensors that detect the voltages of the capacitors 51 to 53. Moreover, what can store direct-current power besides the capacitors 51-53 can be used for the 1st-3rd direct-current voltage source.
Here, the ratio of the voltages initially charged in the capacitors 51, 52, 53 is set to V1: V2: V3 = 1: 2: 4. Assuming that V1 = V0, V2 = 2V0, V3 = 4V0, the power conversion device 3 outputs the sum of the voltages generated by the single-phase inverter 41 and the multi-level inverter 42. Therefore, the maximum one-side five-level output (including zero output) Not possible). The output (Vout) of the power conversion device 3 is determined by determining an output pattern based on a predetermined combination selected from the three capacitors 51 to 53, and controlling the output of the single-phase inverter 41 and the multilevel inverter 42. The obtained half-cycle output pattern is shown in FIG. FIG. 4 shows the gate logic table in each of the output patterns A to K in FIG. 3, that is, the on / off combinations of the switch elements 7a to 7j.

The power conversion device 3 includes a control device as shown in FIG. 5 to control the single-phase inverters 41 and 42, and the control operation will be described below.
Voltages V1 to V3 of the capacitors 51 to 53 are monitored by voltage sensors 81 to 83, and outputs of the voltage sensors 81 to 83 are input to the comparator group 10. The comparator group 10 sets DC voltage upper and lower limit values 91a, 91b to 93a, 93b, which are threshold values, for the outputs of the voltage sensors 81 to 83, respectively. Here, 91a to 93a indicate upper limit values, and 91b to 93b indicate lower limit values. When each of the voltages V1 to V3 exceeds the set upper limit values 91a to 93a or falls below the lower limit values 91b to 93b, the output of the comparator group 10 changes from L to H. The determination output from the comparator group 10 is input to the synchronization unit 11, and the output of the synchronization unit 11 is input to the output pattern selection unit 12.

The synchronization unit 11 transmits the input state to the output side at a predetermined interval. By appropriately setting the predetermined interval, for example, even when the output of the comparator group 10 changes frequently, it is possible to suppress the output pattern output from the output pattern selection unit 12 from changing frequently. This synchronization unit 11 can be realized by establishing a hardware sample-and-hold circuit, an interrupt frequency for software processing, or the like.
The output current of the power conversion device 3 is monitored, and the output command voltage 13 and the output current monitor value 14 are input to the polarity determination comparator 15 (15a, 15b). An XOR logic 16 is provided at the subsequent stage of the polarity determination comparator 15 to determine whether or not the polarities of the output voltage and the output current are the same, and the same is input to the output pattern selection unit 12.

For example, when the output voltage and the output current have the same polarity and the power conversion device 3 outputs the voltage V0, there are three patterns (patterns B, C, and D) as shown in FIG. In this case, when the voltage V1 of the capacitor 51 exceeds the upper limit value 91a and the upper limit value signal 171a is input to the output pattern selection unit 12, the output pattern selection unit 12 selects the pattern B for discharging the capacitor 51.
Here, when the output voltage and the output current have the same polarity, the polarity sign of the voltage output from each of the capacitors 51 to 53 shown in FIG. 3 indicates that the capacitor energy is discharged, and − indicates that the capacitor energy is charged.

When the lower limit signal 171b is input to the output pattern selection unit 12 at the voltage V1 of the capacitor 51, the output pattern selection unit 12 selects the pattern C or the pattern D that charges the capacitor 51. At this time, if the upper limit signal 172a is input at the voltage V2 of the capacitor 52, the pattern C is selected, and if the lower limit signal 172b is input, the pattern D is selected.
The power supply 1 is connected to the capacitor 53 of the voltage V3, and the upper / lower limit value signals 173a and 173b can be ignored when the voltage V3 is considered to be substantially fixed to the median value of the upper and lower limit values 93a and 93b. Further, when none of the upper limit value signals 171a to 173a and the lower limit value signals 171b to 173b are input to the output pattern selection unit 12, that is, the voltages V1 to V3 of the capacitors 51 to 53 are the upper and lower limit values 91a, 91b to Any pattern may be selected when it is within the threshold width of 93a and 93b.

In this way, the power transfer is controlled by charging / discharging by the outputs of the single-phase inverter 41 and the multi-level inverter 42. When the voltages V1 and V2 of the capacitors 51 and 52 exceed the upper limit values 91a and 92a, the capacitor energy is discharged to lower the voltage. Conversely, when the voltages V1 and V2 are lower than the lower limit values 91b and 92b, the capacitor voltage is reduced by charging. By increasing the voltage, the voltages V1 and V2 of the capacitors 51 and 52 can be kept within the threshold width without supplying power from the external power source.
The output pattern command 18 selected in this way is input to the inverter drive control unit 19, and the gate drive signal 20 for driving the switch elements 7 a to 7 j of the single-phase inverter 41 and the multilevel inverter 42 is output. , 42 operates.

In the above description, the output pattern is determined by giving priority to the upper and lower limit signals 171a and 171b related to the voltage V1 of the capacitor 51. However, the priority order when determining the output pattern is not limited to this, and the voltage V2 of the capacitor 52 is determined. Even if priority is given to the upper and lower limit value signals 172a and 172b relating to the voltage V3 of the capacitor 53 or the upper and lower limit value signals 173a and 173b relating to the voltage V3 of the capacitor 53, substantially the same effect is obtained.
Further, when the output voltage and the output current have different polarities, the meanings of + and − of the polarity sign of the voltage output from each of the capacitors 51 to 53 shown in FIG. 3 are reversed. That is, + means charging of capacitor energy, and-means discharging.

  As described above, the case where the power conversion device 3 outputs the voltage V0 has been described. Similarly, for the output voltage 2V0 or more, by selecting the output pattern according to the upper / lower limit determination of the voltages of the capacitors 51 to 53, Control is performed so that each capacitor voltage is within a set threshold width.

  In this embodiment, the power conversion device 3 includes ten switch elements 7 a to 7 j for the three capacitors 51 to 53. The capacitor 53 having the maximum voltage V3 is supplied with electric power from the external power source 1, while the other capacitors 51 and 52 balance power transfer by charging / discharging by the outputs of the single-phase inverter 41 and the multi-level inverter 42. Let the voltage control. As a result, multi-level output is possible with a smaller number of switch elements and capacitors than conventional ones, and the power supply and converter for supplying power to the capacitors 51 and 52 can be omitted, thereby simplifying the device configuration and increasing the efficiency. .

Moreover, since it is determined using a comparator whether the voltages V1 to V3 of the capacitors 51 to 53 are within the set threshold width, A / D conversion is not required, and the control system can be simplified. it can.
Furthermore, in the process of determining the output pattern of the power conversion device 3, the maximum operating frequency is limited by the hardware sample and hold circuit, the interrupt frequency during software processing, etc., so the output pattern output by the output pattern selection unit 12 Can be prevented from changing frequently, and an increase in switching frequency can be prevented.

  Although the maximum one-side five-level output (not including zero output) is possible, the peak value of the output voltage is approximately equal to the maximum capacitor voltage V3, that is, one-side four-level output (not including zero output). Thus, as shown in FIG. 3, the capacitors 51 and 52 of the voltages V1 and V2 can select either + or − for each output voltage Vout. This makes it possible to control each capacitor voltage within an appropriate threshold width with respect to an arbitrary load connection.

  In the above description, the output pattern is selected based on the polarities of the output command voltage 13 and the output current monitor value 14. However, when the load power factor can be assumed in advance, the polarity determination is omitted and the upper limit signal 171a is omitted. The output pattern may be selected only from ˜173a and the lower limit signal 171b˜173b, and the control can be simplified.

  In this embodiment, one single-phase inverter 41 and one multi-level inverter 42 are connected. However, a plurality of single-phase inverters 41 may be connected, and a plurality of multi-level inverters 42 are also connected. May be connected. The capacitor of the multi-level inverter 42 may be composed of one capacitor 53 having the maximum voltage connected to the external power source and a plurality of other capacitors 52. When the maximum voltage capacitor is a voltage source such as a battery The external power supply is omitted.

Embodiment 2. FIG.
FIG. 6 is a diagram showing a main circuit configuration of a power conversion device according to Embodiment 2 of the present invention, in which a switching circuit for initial charging is provided in power conversion device 3 shown in FIG. As shown in the figure, a switching circuit including a charging resistor 22 and an output changeover switch 21 is provided on the AC output side of the power conversion device 3.
Next, an initial charging method at startup will be described.
First, at the initial startup, the output changeover switch 21 is connected to the charging resistor 22 side. The power from the power source 1 is supplied to the capacitor 53. At this time, the capacitors 51 and 52 are not charged. Then, the output control of the single-phase inverter 41 and the multi-level inverter 42 is AC output, charges as follows capacitors 51 and 52 through the charging resistor 22.

The output patterns D, F, H, and I shown in FIG. 3 are combined and output with respect to the target value of the output voltage similar to that during normal output of the power conversion device 3. Thereby, the capacitor 51 and the capacitor 52 can be charged using the energy of the capacitor 53.
Since the voltages of the capacitors 51 and 52 are 0 at the start of the initial charging, the voltage waveform across the charging resistor 22 is as shown in FIG. Since the voltages of the capacitors 51 and 52 increase with charging, the voltage across the charging resistor 22 has a waveform as shown in FIG. In FIG. 8, the hatched portion represents a waveform cut by charging the capacitors 51 and 52.
Assuming that V1: V2: V3 = 1: 2: 4 is a steady state, full charge occurs when the voltage waveform across the charging resistor 22 reaches the state shown in FIG. After all the capacitors 51 and 52 are fully charged, the output changeover switch 21 is switched from the charging resistor 22 side to the output terminals 2a and 2b, and the routine shifts to the steady operation shown in the first embodiment.

  By performing initial charging using the switching circuit including the charging resistor 22 as described above, it is not necessary to separately prepare a power source for initial charging, and the apparatus can be configured simply. In addition, since no voltage is generated at the output terminals 2a and 2b during initial charging, the load device can be stably operated without outputting an abnormal voltage.

Embodiment 3 FIG.
In the power conversion device 3 shown in the first embodiment, the voltage ratio of the capacitors 51 to 53 is V1: V2: V3 = 1: 2: 4. However, in the third embodiment, V1: V2: V3 A case where = 1: 3: 6 will be described.
When V1 = V0, V2 = 3V0, and V3 = 6V0, the power conversion device 3 outputs the sum of the voltages generated by the single-phase inverter 41 and the multi-level inverter 42, so that the maximum one-side 7-level output (including zero output) The output pattern of the half cycle in this case is shown in FIG.

  In this embodiment, the three capacitors 51 to 53 and the ten switch elements 7a to 7j having the same configuration as that of the above-described first embodiment enable further multi-level output and high accuracy. Output control becomes possible.

  As shown in FIG. 10, the voltage V <b> 2 of the capacitor 52 can control charging / discharging according to the selected output pattern, but the voltage V <b> 1 of the capacitor 51 is the output voltage level of the power converter 3. Is uniquely determined. Accordingly, the charge / discharge amount of the capacitor 51 is not balanced, and the capacitor voltage may not be controlled within the set threshold width. Therefore, as shown in FIG. 11, the auxiliary power supply 23 is provided, and the voltage V <b> 1 of the capacitor 51 can be maintained by supplying power corresponding to the fluctuation voltage.

It is a block diagram which shows the power converter device by Embodiment 1 of this invention. It is a figure which shows the relationship between the output of the multilevel inverter by Embodiment 1 of this invention, and switching control. It is a figure which shows the output pattern of the power converter device by Embodiment 1 of this invention. It is a figure which shows the gate logic table of the power converter device by Embodiment 1 of this invention. It is a figure which shows the control apparatus of the power converter device by Embodiment 1 of this invention. It is a block diagram which shows the power converter device by Embodiment 2 of this invention. It is a figure explaining the initial charging operation of the power converter device by Embodiment 2 of this invention. It is a figure explaining the initial charging operation of the power converter device by Embodiment 2 of this invention. It is a figure explaining the initial charging operation of the power converter device by Embodiment 2 of this invention. It is a figure which shows the output pattern of the power converter device by Embodiment 3 of this invention. It is a block diagram which shows the power converter device by another example of Embodiment 3 of this invention.

Explanation of symbols

1 power supply, 2a, 2b output terminal, 3 power converter, 7a-7j switch element,
41 single-phase inverter, 42 multi-level inverter,
51 a capacitor as a third DC voltage source,
52 a capacitor as a second DC voltage source,
53 a capacitor as a first DC voltage source, 81-83 voltage sensor,
91a, 91b to 93a, 93b DC voltage upper and lower limit values, 10 comparator groups,
11 synchronization unit, 12 output pattern selector, 13 output command voltage,
14 Output current monitor value, 15a, 15b Polarity judgment comparator,
16 XOR logic, 18 output pattern command, 19 inverter drive control unit,
20 gate drive signal, 21 output selector switch, 22 charging resistor.

Claims (11)

Respectively connected in series AC side of a plurality of single-phase inverter that converts the DC power of the DC voltage source to AC power and a plurality of switching elements DC voltage source, the generation of the plurality of single-phase inverters In a power converter that supplies power to a load by controlling the output voltage by the sum of voltages,
Among the plurality of single-phase inverter, at least one has a said DC voltage source of multiple, alternating side the respective DC voltage source by a combination of on-off of the plurality of switching elements in either a positive or negative polarity A multi-level inverter connected between output terminals to enable multi-level voltage output.
Multi-level inverter, the plurality of the DC voltage source, constituted by a supplied external power or et power first DC voltage source and the other second DC voltage source of the voltage is maximum, the When the voltage is output between the AC side output terminals from both the first DC voltage source and the second DC voltage source, the first and second DC voltage sources are controlled by a combination of ON and OFF of the plurality of switch elements. the first is connected in series with opposite polarity to each other, the power converter, wherein a difference between the voltage of the second DC voltage source is output. The multi-level inverter is connected to the first and second DC voltage sources and a plurality of switch elements connected in series between the positive and negative terminals of the first DC voltage source. A switch element and a diode connected in antiparallel to each switch element, and the second DC voltage source is connected between both terminals of the central two series switch element in the four series switch elements. 2. The power converter according to claim 1, wherein a midpoint of the four series switch elements and a midpoint of the two series switch elements are used as the AC output terminal. Among the plurality of single-phase inverters, the single-phase inverters other than multilevel inverter, a third DC voltage source voltage smaller than the voltage of the first DC voltage source as the direct-current voltage source, the 3. The power conversion device according to claim 1, wherein the power conversion device is a full-bridge inverter including two sets of two series switch elements which are a plurality of switch elements . The multilevel inverter is a single-phase inverter having one each of the first and second DC voltage sources, and the voltage ratio of the first to third DC voltage sources is 4: 2: 1. The power converter according to claim 3, wherein The multilevel inverter is a single-phase inverter having one each of the first and second DC voltage sources, and the voltage ratio of the first to third DC voltage sources is 6: 3: 1. The power converter according to claim 3, wherein And determining an output pattern according to a predetermined combination selected from the plurality of DC voltage sources of said plurality of single-phase inverters having said plurality of switching elements included in the respective single-phase inverters according to the output pattern The output voltage and polarity of each single-phase inverter are changed by a combination of ON and OFF, and among the plurality of DC voltage sources, each DC voltage source other than the first DC voltage source is charged by the DC voltage source. 6. The power converter according to claim 1, wherein the voltage is controlled by balancing power exchange by a discharge operation . 7. The power converter according to claim 6, wherein the maximum output voltage is limited by the voltage of the first DC voltage source. The power converter according to claim 6 or 7, wherein the output pattern is determined based on a mutual polarity relationship between an output voltage and an output current. Each DC voltage source includes voltage detection means and a comparator for detecting whether or not each detection voltage is within a predetermined threshold width, and the output pattern is set so that each detection voltage is within the threshold width of the comparator. The power converter according to claim 6, wherein the power converter is determined. The power conversion apparatus according to claim 9, wherein an upper limit is provided for a maximum operating frequency of the process for determining the output pattern. A switching circuit having a charging resistor , switching a current path to the charging resistor prior to supplying power to the load, and each of the switching elements included in each of the single-phase inverters according to a combination of ON and OFF. by changing the output voltage and the polarity of the single-phase inverter, the power exchange between the plurality of DC voltage sources, among the plurality of the DC voltage source, the initial charge of each DC voltage source other than said first DC voltage source The power conversion device according to any one of claims 1 to 10, wherein:

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