JP5502312B2 - 3-level inverter - Google Patents

Description

The present invention relates to a three- level inverter device, and is an effective device for, for example, a railway vehicle auxiliary power source.

  Conventionally, a railway vehicle auxiliary power source for generating a 440V AC power source at three phases 60 Hz for air conditioning and lighting of a railway vehicle from a DC voltage supplied from an overhead line is configured with two levels each composed of two semiconductor switching elements. An inverter has been applied (Patent Document 1).

However, the DC power supply voltage supplied to a general commuter train is generally 1500 V. In order to cope with this voltage, it is necessary to realize a 3.3 kV withstand voltage class high withstand voltage device. In this case, it is necessary to reduce an increase in heat generation temperature due to high switching loss, and the switching frequency is controlled to about 1000 Hz. For this reason, the AC power filter composed of an AC reactor and a capacitor installed to remove harmonics of the switching frequency component from the output waveform has a very large weight profile, and a railway vehicle power supply that is particularly required to be lightweight and compact. There was a need for improvement.
JP 2008-278577 A

  On the other hand, when a neutral point clamp type three-level inverter composed of four semiconductor switching elements for each of three phases and two diodes for clamping a DC neutral point is used as an auxiliary power supply for a railway vehicle, Even when the number of switching times of the element is 1000 Hz as in the case of the two-level inverter, the output waveform is multi-staged into three levels of positive, negative, and zero due to the deviation of the switching timing of the four switching elements, and more sine Get closer. For this reason, the weight outer shape of the AC filter for removing harmonics of the switching frequency component can be significantly reduced in size and weight as compared with the weight outer shape required for the two-level inverter.

  However, since the three-level inverter includes four semiconductor switching elements, two diodes, and a large number of semiconductor elements in each phase, the configuration of the conductor connecting the DC capacitor and the semiconductor switching element becomes complicated. As a result, in the three-level inverter, the wiring inductance becomes large, and the voltage jump due to the wiring inductance generated when the switch-off current of the semiconductor switching element is interrupted becomes very large. In order to suppress this, the snubber circuit, which could be omitted in the two-level inverter, became indispensable in the three-level inverter, resulting in an increase in the size and cost of the inverter circuit.

  In particular, the voltage jump at the time of the second and third current interruption of the four semiconductor switching elements indicates that the wiring inductance of the current path is the first and fourth semiconductor switching elements in the configuration of the three-level circuit. Is much larger than the wiring inductance of the current path when the current is cut off, which has been a hindrance to snubberlessness.

  As another method of suppressing the voltage jump at the time of current interruption, there is a method of increasing the gate drive resistance value for turning off the gate and slowing down the current interruption speed, but there is a transient large switching loss inside the semiconductor switching element. It will be necessary to increase the size of the inverter cooler.

Accordingly, an object of the present invention is to provide a three- level inverter device capable of obtaining a snubberless state by preventing a voltage jump while suppressing loss as much as possible in order to solve the above problems.

The present invention provides an inverter that converts a DC voltage into a three-phase AC having a constant frequency and a constant voltage, wherein four semiconductor switching elements are connected in series to both positive and negative terminals of the DC voltage, and the first of the semiconductor switching elements A neutral point clamp in which the second connection point and the DC intermediate potential portion are connected by a diode, and the third and fourth connection points of the semiconductor switching element and the DC intermediate potential portion are connected by a diode. In type 3 level inverter,
The gate drive resistance value for gate-off of the second and third semiconductor switching elements is larger than the gate drive resistance value for gate-off of the first and fourth semiconductor switching elements It is characterized by setting.
Specifically, in the neutral point clamp type three-level inverter device,
The first to fourth semiconductor switching elements are connected to first to fourth gate drive circuits for gate-on or gate-off, respectively.
Each of the first to fourth gate drive circuits is configured on one substrate,
First and second elements are connected in series, a gate drive output is taken out from a common connection point of the first and second elements, a gate-on resistance is connected in series to the first element, and the second element Is connected in series with a gate-off resistor,
A resistance value of a gate-off resistor for turning off the second and third semiconductor switching elements is larger than a resistance value of a gate-off resistor for turning off the first and fourth semiconductor switching elements. The resistance value of the gate-on resistance is a common value for all switching elements.

  By the above means, for example, in the neutral point clamp type three-level inverter when the railway vehicle auxiliary power supply is operated at a normal output power factor of 0.8 or more and the output power factor is high, the second of the four semiconductor switching elements is used. Focusing on the fact that the current and the third switching element cut off the current only during the slight switching in which the voltage and current have opposite polarities, the gate-off resistance of the second and third semiconductor switching elements is By providing a larger value than the gate-off resistance of the 4th and 4th semiconductor switching elements, a three-level inverter device for small and light rail vehicle auxiliary power supply is achieved without increasing the heat generated by inverter loss while achieving snubberlessness. To do.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration example of the first embodiment of the present invention. This embodiment is an auxiliary power circuit for railway vehicles, and includes a DC reactor 10, a positive DC capacitor 21 and a negative DC capacitor 22 connected in series between terminals 11 and 12.

  Further, three phase U, V, W neutral point clamp type three level inverters 31, 32, 33 are connected between the terminals 11, 12.

  This three-phase inverter has four semiconductor switching elements (IGBT: insulated gate bipolar transistors) Q1, Q2, Q3, and Q4 connected in series per phase. These will be referred to as first to fourth. A first clamp diode D1 is connected between the connection point of the capacitors 21 and 22 and the connection point of the first and second semiconductor switching elements Q1 and Q2. A second clamp diode D2 is connected between the connection point of the third and fourth semiconductor switching elements Q3 and Q4 and the connection point of the capacitors 21 and 22.

  The AC output terminals of the neutral point clamp type three-level inverters 31, 32, 33 of each phase are respectively connected to the windings of the three-phase insulating transformer 40 via AC reactors L1, L2, L3. Further, AC capacitors C1, C2, C3 are connected between the three-phase lines on the output side of the AC reactors L1, L2, L3. Lighting and an air conditioner (not shown) inside the railway vehicle are connected to the output stage of the three-phase insulating transformer 40 as a load.

  The switching operation of the semiconductor switching element (IGBT) is driven by a gate drive circuit connected between the gate and emitter of each element. FIG. 2 shows a circuit configuration example of the gate drive circuits A1, A2, A3, A4 of each element. Since each gate drive circuit A1, A2, A3, A4 has the same circuit configuration, one gate drive circuit A2 will be described as a representative.

  In FIG. 2, the transistors TR1 and TR2 are connected to a totem pole. The emitter of the transistor TR1 is connected to the emitter of the transistor TR2 and to the control terminal 53. The collector of the transistor RT1 is connected to a positive power supply 51 of DC 15V through a gate-on resistance RgON as a gate drive resistance. The collector of the transistor TR2 is connected to a negative power supply 52 of DC 15V through a gate-off resistor RgOFF as a gate drive resistor.

  The bases of the transistors TR1 and TR2 are connected to the control terminal 55. Further, the connection portion between the DC power sources 51 and 52 is connected to the control terminal 54. The control terminal 53 is connected to the gate electrode of the semiconductor switching element (IGBT), and the control terminal 54 is connected to the emitter electrode.

  The power supplies 51 and 52 are positive and negative DC 15V voltages obtained by rectifying a high-frequency voltage insulated and supplied from an external high-frequency switching power supply (not shown). A gate pulse sent from a control device (not shown) is supplied to the control terminal 55, and a semiconductor switching element (IGBT) is turned on or off between the control terminals 53 and 54 in response to the gate pulse. A voltage appears.

  Here, the gate-on resistance RgON is common to all elements, and 1.8Ω is used. On the other hand, the gate-off resistance RgOFF uses a different value according to the position of the element of the three-level inverter.

  The gate drive circuit for driving the semiconductor switching element is composed of two elements on one substrate, and one gate output stage has a low resistance gate drive resistance and the other output stage has a high resistance gate drive resistance. The gate drive circuit is made common.

  As shown in FIG. 3, the gate-off resistance RgOFF of the gate drive circuits A2 and A3 for the second and third semiconductor switching elements Q2 and Q3 is, for example, 40Ω, and the gate-off resistance RgOFF of the gate drive circuits A1 and A4 is For example, 10Ω is used.

  In order to change the semiconductor switching element (IGBT) from the on-state to the off-state, the charge inside the semiconductor switching element (IGBT) is absorbed (moved) from the gate portion to finally form the gate (G) emitter (E). Therefore, it is necessary to apply a voltage of minus 15V. By controlling the speed at the time of absorbing (moving) the charge, the switching speed can be controlled, and an increase in voltage jump due to a sharp current interruption can be suppressed. A gate-off resistor RgOFF is used to limit the charge absorption rate.

  If the value of the gate-off resistance RgOFF is increased, the switching speed is slowed down, so that the voltage jump can be suppressed. However, since the current interruption transient state continues for a long time, the switching loss increases.

  In a neutral-point clamped three-level inverter when the railcar auxiliary power supply is normally operated with an output power factor of 0.8 or higher and the output power factor is high, the second and third semiconductors of the four semiconductor switching elements Focusing on the fact that the switching elements Q2 and Q3 cut off the current only at the time of slight switching in which the voltage and current have opposite polarities, the gate-off resistances of the second and third semiconductor switching elements are changed to the first and A value larger than the gate-off resistance of the fourth semiconductor switching element is set.

  The figure explaining this is shown in FIGS. 4, 5, 6, and 7. FIG. Since the second and third semiconductor switching elements (IGBT) Q2 and Q3 have a smaller number of times of interrupting the current than the first and fourth semiconductor switching elements (IGBT), the switching loss is slightly increased. Ignore this and use a large gate-off resistance. As a result, it is possible to make the circuits around the second and third semiconductor switching elements Q2 and Q3 difficult to reduce the wiring inductance snubberless.

  FIG. 4 shows a current waveform and a voltage waveform appearing at the output portion of the neutral point clamp type three-level inverter. Regions A, B, C and D peculiar to the time direction are shown separately. In the auxiliary power supply, since the phase difference between the voltage and the current is small, there are almost no areas A and C. Here, attention is paid to the periods t1, t2, t3, and t4 in the region B where the current is positive.

During the periods t1, t2, t3, and t4, the semiconductor switching transistors Q1, Q2, Q3, and Q4 operate in a pattern as shown in FIG. 5 and FIG. That means
In the period t1, Q1 → on, Q2 → on, Q3 → off, Q4 → off,
In period t2, Q1 → off, Q2 → on, Q3 → on, Q4 → off,
In the period t3, Q1 → on, Q2 → on, Q3 → off, Q4 → off,
In the period t4, Q1 → off, Q2 → on, Q3 → on, Q4 → off, and such an operation pattern is repeated in the region B.

  As can be seen from the above operation, when the operation in the region D is also included, the second and third semiconductor switching elements (IGBT) Q2 and Q3 are compared with the first and fourth semiconductor switching elements (IGBT). The number of times to cut off the current is small.

  Here, attention is paid to the operation of the second switching element Q2. As shown in FIG. 7, it is assumed that a command for turning from on to off is given from the gate circuit A2. In the case of an on command, the transition speed of all the switching elements is the same. When the command is OFF, the transition speeds of the second and third semiconductor switching elements Q2 and Q3 are slower than the transition speeds of the first and fourth semiconductor switching elements.

  When the on command is changed to the off command, the current of the second switching element has abruptly changed as indicated by the current I1 because it responded immediately in the past. Along with this, the voltage resulting from the wiring inductance generated when the switch-off current of the semiconductor switching element is interrupted has a very large jump as shown by the voltage V1. This phenomenon becomes a factor causing unnecessary radiation in the vicinity.

  However, according to the circuit of this embodiment, since the gate-off resistance RgOFF is increased, the current of the second switching element changes with a delay as shown by the current I2 (the time constant increases). As a result, the jump due to the voltage caused by the wiring inductance generated when the switch-off current of the semiconductor switching element is interrupted is suppressed as indicated by the voltage V2.

  Here, when power consumption (loss W = I × V) is taken into consideration, the loss when the current I2 changes gently is larger than when the current I1 changes abruptly. However, in the present invention, the second and third semiconductor switching elements (IGBTs) Q2 and Q3 are less frequently interrupted than the first and fourth semiconductor switching elements (IGBTs). The importance of suppressing unwanted radiation is given priority over the importance of.

  As can be seen from the operation pattern shown in FIG. 6, in the region B, the semiconductor switching element Q3 is turned off when the voltage is positive and the current is positive, and is turned on when the voltage is zero and the current is positive. However, in this region B, since no current flows through the semiconductor switching element Q3, the loss due to turning on and off of the semiconductor switching element Q3 is zero.

  FIG. 8 shows a table summarizing whether or not the semiconductor switching elements Q1-Q4 have a current interruption when there is a relationship between the voltage waveform and the current waveform in FIG. In the region A, there is a current interruption by the semiconductor switching element Q3. In the region B, since the voltage shifts in the positive direction from the high level state to the midpoint potential side, there is a current interruption by the semiconductor switching element Q1. In the region C, since the voltage shifts from the medium potential to the lowest level state in the negative direction, there is a current interruption by the semiconductor switching element Q2. In the region D, since the voltage shifts from the lowest level state in the negative direction to the midpoint potential, the semiconductor switching element Q4 interrupts the current.

  Also from the above table, the second and third semiconductor switching elements (IGBTs) Q2 and Q3 have a smaller number of times of interrupting the current than the first and fourth semiconductor switching elements (IGBTs) Q1 and Q4. I understand that.

  As described above, according to the present invention, in the neutral-point clamped three-level inverter, the second and third switching elements of the four semiconductor switching elements are slightly switched so that voltages and currents have opposite polarities. Paying attention to the fact that current is cut off only at times, set the gate-off resistance of the second and third semiconductor switching elements to a value greater than the gate-off resistance of the first and fourth semiconductor switching elements Thus, it is possible to provide a small and light three-level inverter device for an auxiliary power supply for a railway vehicle without increasing the heat generation due to inverter loss while achieving snubberlessness.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.

1 is a circuit diagram showing an outline of an embodiment of an inverter device to which the present invention is applied. It is a figure which shows one of the gate drive circuits of FIG. 1 in detail. FIG. 3 is an explanatory diagram illustrating an example of a resistance value of a gate drive resistor of the gate drive circuit of FIG. 2. It is the voltage and current waveform figure shown in order to demonstrate the operation example of the inverter apparatus of this invention. It is the circuit diagram which showed the electric current path | route in order to demonstrate the operation example of the inverter apparatus of this invention. It is explanatory drawing which showed the state change of semiconductor switching element Q1-Q4 in order to demonstrate the operation example of the inverter apparatus of this invention. FIG. 3 is a timing diagram shown for explaining an operation principle of a main part of the inverter device of the present invention. It is explanatory drawing which tabulates and shows the presence or absence of the electric current interruption in the semiconductor switching element of the inverter apparatus of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... DC reactor, 11, 12 ... Terminal, 31, 32, 33 ... Neutral point clamp type 3 level inverter, Q1, Q2, Q3, Q4 ... Semiconductor switching element (IGBT: insulated gate) Type bipolar transistor), D1, D2 ... clamp diode, 21, 22 ... capacitor, L1, L2, L3 ... AC reactor, C1, C2, C3 ... AC capacitor, A1, A2, A3 , A4: Gate drive circuit, TR1, TR2: Transistor, RgON: Gate on resistance, RgOFF: Gate off resistance.

Claims (2)

An inverter for converting a DC voltage into a three-phase AC having a constant frequency and a constant voltage, wherein four semiconductor switching elements are connected in series to both positive and negative terminals of the DC voltage, and the first and second of the semiconductor switching elements A neutral point clamp type three- level inverter in which a connection point and a DC intermediate potential part are connected by a diode, and a third and fourth connection point of the semiconductor switching element and a DC intermediate potential part are connected by a diode. In the device
The first to fourth semiconductor switching elements are connected to first to fourth gate drive circuits for gate-on or gate-off, respectively.
Each of the first to fourth gate drive circuits is configured on one substrate,
First and second elements are connected in series, a gate drive output is taken out from a common connection point of the first and second elements, a gate-on resistance is connected in series to the first element, and the second element Is connected in series with a gate-off resistor,
A resistance value of a gate-off resistor for turning off the second and third semiconductor switching elements is larger than a resistance value of a gate-off resistor for turning off the first and fourth semiconductor switching elements. And the resistance value of the gate-on resistance is a common value for all switching elements . 2. The three- level inverter device according to claim 1, wherein a connection point between the second and third semiconductor switching elements is connected to a winding of a three-phase insulating transformer through an AC reactor .

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