JP7201045B2 - power converter - Google Patents

Description

The present technology relates to a power conversion device.

As a quadrature converter (DC (Direct Current)/AC (Alternate Current) converter), a multi-level inverter represented by a 3-level inverter can make the system smaller and more efficient than the conventional 2-level inverter. It is attracting attention as a power converter to be realized.

As a conventional technique for a three-level inverter, for example, the voltage drop characteristics of freewheeling diodes connected in anti-parallel to at least two switching elements connected in series between a positive terminal and a negative terminal are measured as a neutral point terminal and a neutral point terminal. A technology has been proposed in which the power loss is reduced by increasing the voltage drop characteristic of a freewheeling diode connected in anti-parallel to a switching element connected to an AC terminal (Patent Document 1).

JP 2013-116020 A

However, when an inductive load such as a motor is driven by the switching operation of the switching elements included in the 3-level inverter, if the load current flows back through the body diode in the switching element, the body diode deteriorates and power loss increases. There is a problem that

SUMMARY OF THE INVENTION It is an object of the present invention to provide a power converter that suppresses deterioration of body diodes and reduces power loss.

A power converter is provided to solve the above problems. This power converter includes a first switching element on the positive electrode side including a first body diode, a second switching element on the negative electrode side connected in series with the first switching element, and a parallel connection to the first switching element. and the switch circuit is turned on for a predetermined period during the period from the turn-off operation of the second switching element to the turn-on operation of the second switching element, thereby switching the first switching element and the second switching element. A control circuit that causes a load current directed from a load connected via an intermediate point where the switching element is connected in series to the first switching element to flow through the switch circuit, thereby making the load current non-conductive with respect to the first body diode. and
Also, in order to solve the above problems, a power converter is provided. This power converter includes a first switching element on the positive electrode side including a first body diode, a second switching element on the negative electrode side connected in series with the first switching element, and a parallel connection to the first switching element. and a control circuit for turning on the switch circuit for a predetermined period during the period from when the second switching element turns off until it turns on. Further, the orthogonal transform unit includes a first switching element including a first transistor and a first body diode, a second switching element including a second transistor and a second body diode, and third and fourth switching elements. A switch circuit including an element, first and second diodes, a positive power source, a negative power source, and a third transistor and a third diode. The positive terminal of the positive power supply is connected to the drain of the first transistor, the cathode of the first body diode and the source of the third transistor, and the negative terminal of the negative power supply is connected to the source of the second transistor. , the anode of the second body diode; the negative terminal of the positive power source is connected to the positive terminal of the negative power source, the emitter of the third switching element and the anode of the first diode; The collector of the switching element is connected to the cathode of the first diode, the cathode of the second diode and the collector of the fourth switching element, and the emitter of the fourth switching element is connected to the anode of the second diode and the first diode. connected to the source of the transistor, the anode of the first body diode, the anode of the third diode, the drain of the second transistor, the cathode of the second body diode and the intermediate point; connected to the drain of the transistor in

It is possible to suppress deterioration of the body diode and reduce power loss.

It is a figure which shows the structural example of the power converter device of this invention. It is a figure which shows the structural example of a 3 level inverter. It is a figure which shows an example of the switching pattern of a 3 level inverter. It is a figure which shows the output waveform of a 3 level inverter. FIG. 4 is a diagram showing a path through which load current flows; FIG. 4 is a diagram showing a path through which a load current flows when a voltage across a switching element on the negative electrode side exceeds a threshold level; FIG. 10 is a diagram for explaining a state when a body diode is conducting; It is a figure which shows the structural example of a power converter device. It is a figure for demonstrating operation|movement of a power converter device. It is a figure which shows the structural example of the power converter device of a modification. It is a figure for demonstrating operation|movement of the power converter device of a modification.

Embodiments will be described below with reference to the drawings.
FIG. 1 is a diagram showing a configuration example of a power converter according to the present invention. The power conversion device 1 includes an orthogonal converter 1a and a control circuit 1b. The orthogonal converter 1a includes switching elements T1 to T4, diodes D1 and D2 (first and second diodes), and a positive power source V1 and a negative power source V2 as DC power sources.

The switching element T1 (first switching element) on the positive electrode side includes an N-channel NMOS transistor M1 (first transistor) as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and further includes a body diode Dp1 (first switching element) which is a parasitic diode. 1 body diode). The switching element T2 (second switching element) on the negative electrode side is connected in series with the switching element T1.

The connection relationship in the orthogonal converter 1a is as follows. Connect to one end of T2.

The negative terminal of the positive power source V1 is connected to the positive terminal of the negative power source V2, one end of the switching element T3, and the anode of the diode D1. The other end of switching element T3 is connected to the cathode of diode D1, the cathode of diode D2 and one end of switching element T4.

The other end of the switching element T4 is connected to the anode of the diode D2, the source of the NMOS transistor M1, the anode of the body diode Dp1, the other end of the switching element T2 and the intermediate point U. A load 3 is connected to the intermediate point U via a filter (not shown).

The control circuit 1b performs switching drive control of the switching elements T1 to T4. In this case, the control circuit 1b turns on the switching element T1, which is in the off state during the switching operation of the switching element T2, for a predetermined period during the off period from when the switching element T2 is turned off to when it is turned on. do.

By performing such switching control, the control circuit 1b causes the load current (first load current) directed from the load 3 to the switching element T1 to flow to the side of the NMOS transistor M1 in the switching element T1, thereby switching the switching element T1. The load current is made non-conductive to the body diode Dp1 inside (suppresses the flow of the load current toward the body diode Dp1).

As a result, the return of the load current to the body diode Dp1 in the switching element T1 can be suppressed, so that the deterioration of the body diode Dp1 can be suppressed and the power loss can be reduced.

Next, before describing the details of the present invention, a three-level inverter, which is an application example of the present invention, will be described with reference to FIGS. 2 to 4. FIG. First, the configuration of the 3-level inverter will be described. FIG. 2 is a diagram showing a configuration example of a three-level inverter. The three-level inverter 100 includes switching elements T1 to T4, diodes D1 and D2, a positive power supply V1 and a negative power supply V2.

NMOS transistors M1 and M2, for example, are used for the switching elements T1 and T2. In this case, for example, a SiC (silicon carbide) MOSFET is used. A SiC-MOSFET has a smaller switching loss than a Si (silicon) MOSFET and has good electrical characteristics even in a high temperature region.

Also, parasitic diodes are connected to the NMOS transistors M1 and M2. The parasitic diode of the NMOS transistor M1 is a body diode Dp1, and the parasitic diode of the NMOS transistor M2 is a body diode Dp2.

Furthermore, for the switching elements T3 and T4, for example, Si IGBTs (Insulated Gate Bipolar Transistors) are used.
On the other hand, since wiring inductors (floating inductors) exist in the wiring of the three-level inverter 100, the wiring inductors are clearly shown in FIG.

Specifically, a wiring inductor Lp is provided in the positive electrode side wiring between the positive terminal of the positive electrode side power source V1 and the positive electrode point P. As shown in FIG. Further, a wiring inductor Ln is provided in the negative wiring between the negative terminal of the negative power supply V2 and the negative terminal N. As shown in FIG.

Further, there is a wiring inductor Lm in the middle pole side wiring between the middle point C at the middle potential between the positive side power supply V1 and the negative side power supply V2 and the emitter of the switching element T3 and the anode of the diode D1.

Regarding the connection relationship of the components of the three-level inverter 100, the positive terminal of the positive power supply V1 is connected to the drain of the NMOS transistor M1 and the cathode of the body diode Dp1 through the wiring inductor Lp.

The negative terminal of the negative power supply V2 is connected to the source of the NMOS transistor M2 and the anode of the body diode Dp2 through the wiring inductor Ln.
The negative terminal of the positive power source V1 is connected to the positive terminal of the negative power source V2, and further connected to the emitter of the switching element T3 and the anode of the diode D1 through the wiring inductor Lm.

The collector of switching element T3 is connected to the cathode of diode D1, the cathode of diode D2 and the collector of switching element T4.
The emitter of switching element T4 is connected to the anode of diode D2, the source of NMOS transistor M1, the anode of body diode Dp1, the drain of NMOS transistor M2 and the cathode of body diode Dp2.

A filter 101 (for example, an LC filter) is connected to the intermediate point (AC output point) U, and a load is connected to the output stage of the filter 101 . A control circuit (not shown) is connected to the gates of the switching elements T1 to T4. An RB (Reverse Blocking)-IGBT configuration may be applied to the switching elements T3 and T4 and the diodes D1 and D2.

Next, the switching pattern of the 3-level inverter 100 will be explained. FIG. 3 is a diagram showing an example of a switching pattern of a 3-level inverter.
[Period t(+)] During the period t(+) in which the reference sine wave (inverter output voltage command) S0 is in the positive period, the amplitude of the reference sine wave S0 is equal to that of the carrier signal S1, which is a triangular wave signal on the positive potential side. If it is larger than the amplitude, the gate drive signal g1 of the switching element T1 becomes a high potential level and the switching element T1 is turned on.

Also, when the amplitude of the reference sine wave S0 is smaller than the amplitude of the carrier signal S1, the gate drive signal g1 becomes a low potential level and the switching element T1 is turned off.
On the other hand, the gate drive signal g3 for the switching element T3 is a signal obtained by inverting the level of the gate drive signal g1. Therefore, when the switching element T1 is on, the switching element T3 is off, and when the switching element T1 is off, the switching element T3 is on.

Furthermore, while the switching elements T1 and T3 are switching (period t(+)), the gate drive signal g2 for the switching element T2 is maintained at a low potential level, and the switching element T2 is turned off.

Furthermore, while the switching elements T1 and T3 are in the switching operation (period t(+)), the gate drive signal g4 of the switching element T4 maintains the high potential level, and the switching element T4 is turned on.

[Period t(-)] During the period t(-) in which the reference sine wave S0 is in the negative period, if the amplitude of the reference sine wave S0 is smaller than the amplitude of the carrier signal S2, which is a triangular wave signal on the negative potential side, switching is performed. The gate drive signal g2 for the element T2 becomes a high potential level, turning on the switching element T2.

Also, when the amplitude of the reference sine wave S0 is greater than the amplitude of the carrier signal S2, the gate drive signal g2 becomes a low potential level and the switching element T2 is turned off.
On the other hand, the gate drive signal g4 for the switching element T4 is a signal obtained by inverting the level of the gate drive signal g2. Therefore, when the switching element T2 is on, the switching element T4 is off, and when the switching element T2 is off, the switching element T4 is on.

Further, while the switching elements T2 and T4 are in the switching operation (period t(-)), the gate drive signal g1 for the switching element T1 maintains the low potential level, and the switching element T1 is turned off.

Furthermore, during the switching operation of the switching elements T2 and T4 (period t(-)), the gate drive signal g3 of the switching element T3 maintains the high potential level, and the switching element T3 is turned on.

As described above, the switching elements T1 and T3 alternately switch during the period when the reference sine wave S0 is positive. At this time, the switching element T2 is kept off, and the switching element T4 is kept on.

Conversely, the switching elements T2 and T4 alternately switch during the period when the reference sine wave S0 is negative. At this time, the switching element T1 is kept off, and the switching element T3 is kept on.

Power is supplied to the load by the switching elements T1 to T4 performing such switching operations. The gate drive signals g1 to g4 described above are generated in a control circuit that controls the driving of the switching elements T1 to T4.

FIG. 4 is a diagram showing output waveforms of a 3-level inverter. Assuming that the total power supply voltage of the 3-level inverter 100 is Ed, the output of the intermediate point U of the 3-level inverter 100 is a PWM (Pulse Width Modulation) pulse waveform of ±Ed/2 and ±Ed centered on zero. .

In this way, the output waveform of the three-level inverter 100 becomes closer to a sine wave, so the filter 101 for converting the output waveform into a sine wave can be made smaller. In addition, since the voltage fluctuation width per switching operation is half that of a 2-level inverter, the switching loss generated in the switching element is roughly halved, and the noise generated by the device is also reduced. .

Next, problems to be solved by the present invention will be described with reference to FIGS. 5 to 7. FIG. FIG. 5 is a diagram showing paths through which load current flows. During the switching operation of the switching element T2 on the negative electrode side (period t(-)), when the switching element T2 is turned on and then turned off, a back electromotive voltage is generated from an inductive load such as a motor. load current flows in

During the switching operation of the switching element T2, when the switching element T2 is off, the switching element T1 is off, the switching element T3 is on, and the switching element T4 is on, as shown in FIG.

When the switching element T2 is turned off, the load current flows along paths r1 and r2. A route r1 is a route from the intermediate point U to the negative electrode N, and a route r2 is a route from the intermediate point U to the intermediate point C.

The load current flowing through path r1 decreases over time (decreases at -di/dt). Also, looking at the voltage polarity of the wiring inductor Ln, since the wiring inductor Ln works to keep the initial current flowing, the power supply side of the wiring inductor Ln has positive polarity, and the switching element T2 side of the wiring inductor Ln has negative polarity. Become.

On the other hand, the load current flowing through the path r2 increases with time (increases by di/dt). Also, looking at the voltage polarity of the wiring inductor Lm, the switching element T3 side of the wiring inductor Lm has positive polarity, and the power supply side of the wiring inductor Lm has negative polarity.

FIG. 6 is a diagram showing a path through which the load current flows when the voltage across the switching element on the negative electrode side exceeds the threshold level.
Here, the power supply voltages of the positive power supply V1 and the negative power supply V2 are both represented by Edc, the load current is di/dt, and the inductances of the wiring inductors Lm and Ln are represented by the same symbols Lm and Ln, respectively. In this case, the voltage VT2 across the switching element T2 is calculated by the following equation (1).

VT2=Edc+(Lm+Ln)×di/dt (1)
A voltage (2×Edc) that is twice the power supply voltage Edc is set as a threshold level. After the negative switching element T2 is turned off, the voltage VT2 across the switching element T2 rises, and when the voltage VT2 exceeds the threshold level, the body diode Dp1 of the switching element T1 is forward biased and becomes conductive. Therefore, as shown in FIG. 6, the load current also flows through the route r3 from the intermediate point U to the positive electrode point P. As shown in FIG.

FIG. 7 is a diagram for explaining the state when the body diode is conducting. When the inductance of the wiring inductors Lm and Ln is large and the current decrease rate of the load current IT2 flowing through the switching element T2 is large, the both-ends voltage VT2 increases according to the above equation (1).

At this time, the body diode Dp1 of the switching element T1 is forward biased and conducts during the period ta when the voltage VT2 across the switching element T2 exceeds twice the power supply voltage Edc (2×Edc).

Then, the load current I1 flows through the body diode Dp1. When the load current I1 returned from the load flows through the body diode Dp1 in this manner, the failure rate of the body diode Dp1 increases, and there is a possibility that the body diode Dp1 will deteriorate. Moreover, since the ON voltage of the body diode Dp1 is high, power loss increases when the load current I1 flows through the body diode Dp1.

SUMMARY OF THE INVENTION In view of the above points, the present invention provides a power conversion device that prevents the body diode from deteriorating by making the load current to the body diode non-conductive, thereby reducing the power loss.

Next, a power converter of the present invention applicable to a 3-level inverter will be described with reference to FIGS. 8 and 9. FIG. FIG. 8 is a diagram showing a configuration example of a power converter. The power converter 1-1 includes an orthogonal transformer 10 and a control circuit 20, and a load 3 is connected to an intermediate point U of the orthogonal transformer 10 via a filter (not shown).

The orthogonal converter 10 includes switching elements T1 to T4, diodes D1 and D2, a positive power supply V1 and a negative power supply V2. The switching element T1 includes an NMOS transistor M1 and a body diode Dp1, and the switching element T2 includes an NMOS transistor M2 (second transistor) and a body diode Dp2 (second body diode). Since the basic circuit configuration of the orthogonal converter 10 is the same as that of the three-level inverter 100 shown in FIG. 2, the description of the circuit configuration is omitted.

The control circuit 20 inputs gate drive signals g1 to g4 to the gates of the switching elements T1 to T4 to control the switching of the switching elements T1 to T4.
Here, in the three-level inverter 100 shown in FIG. 2, the switching element T1 is continuously off during the off period from when the switching element T2 is in the switching operation and when the switching element T2 is turned off until it is turned on. rice field.

On the other hand, during this OFF period, the power conversion device 1-1 applies a high potential level gate drive signal to the switching element T1, which is normally in a continuous OFF state, to turn it ON for a predetermined period. to control. More specifically, a high potential level gate drive signal is applied to the gate of the NMOS transistor M1 in the switching element T1 to turn on the NMOS transistor M1 for a predetermined period.

FIG. 9 is a diagram for explaining the operation of the power converter.
[Period t0] The control circuit 20 applies a high potential level gate drive signal g2 to the gate of the switching element T2. At this time, the switching element T2 is turned on. Also, the control circuit 20 applies a low potential level gate drive signal g1 to the gate of the NMOS transistor M1. At this time, the NMOS transistor M1 (switching element T1) is turned off.

The switching elements T3 and T4 are also switched based on the gate driving signals g3 and g4 output from the control circuit 20. FIG. In this case, the switching element T3 is on and the switching element T4 is off.

On the other hand, in the period t0 in which the switching element T1 is off and the switching element T2 is on, the voltage VT2 across the switching element T2 (the voltage across the switching element T2 between the intermediate point U and the negative point N) is 0V. Also, assume that the load current IT2 flowing through the switching element T2 at this time has a current value Imax. Furthermore, no load current flows to the switching element T1.

[Time t1] The control circuit 20 applies a low potential level gate drive signal g2 to the gate of the switching element T2 to turn off the switching element T2.
[Period t2] The voltage VT2 begins to rise.

[Time t3] While the voltage VT2 is increasing, the load current IT2 flowing through the switching element T2 starts to decrease from the current value Imax. At this timing, the control circuit 20 applies a high potential level gate drive signal g1 to the gate of the NMOS transistor M1 in the switching element T1.

[Period t4] Both-end voltage VT2 is increasing, and load current IT2 flowing through switching element T2 is decreasing. Also, the NMOS transistor M1 is turned on (the gate drive signal g1 maintains the high potential level).

[Time t5] The both-ends voltage VT2 reaches 2×Edc (threshold level), which is the total voltage of the power supply voltage of the positive power supply V1 and the power supply voltage of the negative power supply V2. Also, the NMOS transistor M1 is kept on.

In this case, the load current I1 flowing through the path r3 does not flow through the body diode Dp1 in the switching element T1, but flows through the NMOS transistor M1 in the switching element T1. Even if the NMOS transistor M1 is turned on, the switching element T2 has already turned off, so the power supply will not be short-circuited.

[Time t6] The both-ends voltage VT2 begins to drop from its peak and reaches the voltage (2×Edc), ending the time period in which the both-ends voltage VT2 is equal to or higher than the voltage (2×Edc). At this timing, the control circuit 20 applies the low potential level gate drive signal g1 to the gate of the NMOS transistor M1 to turn off the NMOS transistor M1.

As described above, according to the power conversion device 1-1 of the present invention, the control circuit 20 controls the switching element T1 (NMOS transistor M1) during the off period from when the switching element T2 is turned off to when it is turned on. turn on for a period of time.

Then, the control circuit 20 causes the load current directed to the switching element T1 to flow through the NMOS transistor M1 in the switching element T1, thereby making the load current non-conductive to the body diode Dp1 in the switching element T1. This makes it possible to suppress deterioration of the body diode Dp1 and reduce power loss.

In the above description, the positive-side switching element is turned on for a predetermined period while the negative-side switching element is turned off. A configuration in which the element is turned on for a predetermined period can also be used.

Next, a modification of the power converter will be described with reference to FIGS. 10 and 11. FIG. FIG. 10 is a diagram showing a configuration example of a power conversion device according to a modification. The power conversion device 1-2 of the modification includes an orthogonal converter 10a and a control circuit 20a.

The orthogonal converter 10a includes switching elements T1 to T4, a switch circuit SW, diodes D1 and D2, a positive power supply V1 and a negative power supply V2. The switching element T1 includes an NMOS transistor M1 and a body diode Dp1, and the switching element T2 includes an NMOS transistor M2 and a body diode Dp2.

Also, the switch circuit SW includes an NMOS transistor Ms (third transistor) and a diode D3 (third diode), which are connected in parallel to the switching element T1.
The connection relationship around the switch circuit SW is as follows. Connect to cathode.

The cathode of diode D3 is connected to the drain of NMOS transistor Ms. The source of the NMOS transistor Ms is connected to the positive terminal of the positive power source V1, the drain of the NMOS transistor M1, and the cathode of the body diode Dp1. The rest of the circuit configuration is the same as that of the orthogonal converter 10 of the power converter 1-1 shown in FIG. 8, so description thereof will be omitted.

The control circuit 20a inputs gate drive signals g1 to g4 to the gates of the switching elements T1 to T4 to control the switching of the switching elements T1 to T4. The control circuit 20a also inputs a gate drive signal gs to the gate of the NMOS transistor Ms in the switch circuit SW to switch the switch circuit SW (switch the NMOS transistor Ms).

Here, the power converter 1-2 keeps the switching element T1 in a continuously off state during the OFF period from turning off to turning on during the switching operation of the switching element T2, and the switch circuit SW is set to a predetermined value. Control to turn on for a period of time. That is, a high potential level gate drive signal gs is applied to the gate of the NMOS transistor Ms in the switch circuit SW to turn on the switch circuit SW for a predetermined period.

FIG. 11 is a diagram for explaining the operation of the power converter of the modification.
[Period t10] The control circuit 20a applies the gate drive signal g2 at a high potential level to the gate of the switching element T2. At this time, the switching element T2 is turned on. Also, the control circuit 20a applies a gate drive signal gs at a low potential level to the gate of the NMOS transistor Ms in the switch circuit SW. At this time, the NMOS transistor Ms is turned off.

The switching elements T1, T3 and T4 are also switched based on the gate drive signals g1, g3 and g4 output from the control circuit 20a. In this case, the switching element T1 is off, the switching element T3 is on, and the switching element T4 is off.

On the other hand, in the period t10 in which the switching element T1 is off and the switching element T2 is on, the voltage VT2 between both ends is 0V. Also, assume that the load current IT2 flowing through the switching element T2 at this time has a current value Imax. Furthermore, no load current flows to the switching element T1.

[Time t11] The control circuit 20a applies the low potential level gate drive signal g2 to the gate of the switching element T2 to turn off the switching element T2.
[Period t12] The voltage VT2 begins to rise.

[Time t13] While the voltage VT2 is increasing, the load current IT2 flowing through the switching element T2 starts to decrease from the current value Imax. At this timing, the control circuit 20a applies a high potential level gate drive signal gs to the gate of the NMOS transistor Ms to turn on the NMOS transistor Ms.

[Period t14] Both-end voltage VT2 is increasing, and load current IT2 flowing through switching element T2 is decreasing. Also, the NMOS transistor Ms is on (the gate drive signal gs maintains the high potential level).

[Time t15] The both-ends voltage VT2 reaches 2×Edc (threshold level), which is the total voltage of the power supply voltage of the positive power supply V1 and the power supply voltage of the negative power supply V2. Also, the NMOS transistor Ms is kept on.

In this case, the load current I1 flowing through the path r3 does not flow through the body diode Dp1 in the switching element T1, but flows through the NMOS transistor Ms in the switch circuit SW. Even if the switch circuit SW is turned on, the power supply is not short-circuited because the switching element T2 has already turned off.

[Time t16] The both-ends voltage VT2 begins to drop from its peak and reaches the voltage (2×Edc), ending the time period in which the both-ends voltage VT2 exceeds the voltage (2×Edc). At this timing, the control circuit 20a applies a low potential level gate drive signal gs to the gate of the NMOS transistor Ms to turn off the NMOS transistor Ms.

As described above, according to the power conversion device 1-2 of the modified example of the present invention, the control circuit 20a is connected in parallel to the switching element T1 during the off period from when the switching element T2 is turned off to when it is turned on. The switch circuit SW is turned on for a predetermined period.

Then, the control circuit 20a commutates the load current directed to the switching element T1 to the switch circuit SW, and makes the load current non-conductive with respect to the body diode Dp1 in the switching element T1. This makes it possible to suppress deterioration of the body diode Dp1 and reduce power loss.

Although not shown in FIGS. 8 and 10, the power converters 1-1 and 1-2 switch from a load 3 connected via an intermediate point U where the switching element T1 and the switching element T2 are connected. A current monitor circuit for monitoring the load current flowing through the element T2 and a voltage monitor circuit for monitoring the voltage across the switching element T2 are provided.

For example, a current transformer can be used as the current monitor circuit (the current transformer is installed on the wiring leading from the intermediate point U to the load 3). A comparator using an operational amplifier can be used as the voltage monitor circuit. A voltage monitor circuit monitors the voltage between the intermediate point U and the negative point N. FIG.

Based on the monitor results sent from these monitor circuits, the control circuits 20 and 20a recognize the timing at which the load current flowing through the switching element T2 begins to decrease, and recognize whether or not the voltage across the switching element T2 is equal to or higher than the threshold level. can do.

Although the embodiment has been exemplified above, the configuration of each part shown in the embodiment can be replaced with another one having the same function. Also, any other components or steps may be added.

1 power converter 1a quadrature converter 1b control circuit 3 load T1 to T4 switching element M1 NMOS transistor Dp1 body diode D1, D2 diode V1 positive side power supply V2 negative side power supply U middle point

Claims (5)

a positive-side first switching element including a first body diode; a negative-side second switching element connected in series with the first switching element; and a switch circuit connected in parallel with the first switching element. an orthogonal transform unit including
After the second switching element turns off and before it turns on, the switch circuit is turned on for a predetermined period , and the first switching element and the second switching element are connected in series. a control circuit that causes a load current directed from a load connected via an intermediate point to the first switching element to flow through the switch circuit to make the load current non-conductive to the first body diode ;
A power conversion device having The control circuit turns on the switch circuit during a period in which the voltage across both ends of the second switching element is equal to or higher than a threshold, and after turning on the switch circuit until the period ends, 2. The power converter according to claim 1, wherein said switch circuit is kept on. The orthogonal transform unit further includes a positive power supply and a negative power supply as power supplies, and the control circuit sets the sum of the power supply voltage of the positive power supply and the power supply voltage of the negative power supply as the threshold. The power converter according to claim 2. The orthogonal transform unit includes the first switching element including the first transistor and the first body diode, the second switching element including the second transistor and the second body diode, third and fourth switching elements. switching element, first and second diodes, a positive power supply, a negative power supply, and the switch circuit including a third transistor and a third diode,
a positive terminal of the positive power supply is connected to the drain of the first transistor, the cathode of the first body diode and the source of the third transistor;
the negative terminal of the negative power supply is connected to the source of the second transistor and the anode of the second body diode;
the negative terminal of the positive power supply is connected to the positive terminal of the negative power supply, the emitter of the third switching element and the anode of the first diode;
the collector of the third switching element is connected to the cathode of the first diode, the cathode of the second diode and the collector of the fourth switching element;
The emitter of the fourth switching element is connected to the anode of the second diode, the source of the first transistor, the anode of the first body diode, the anode of the third diode, and the drain of the second transistor. , connected to the cathode and midpoint of said second body diode;
the cathode of the third diode connects to the drain of the third transistor;
The power converter according to claim 1. a positive-side first switching element including a first body diode; a negative-side second switching element connected in series with the first switching element; and a switch circuit connected in parallel with the first switching element. an orthogonal transform unit including
a control circuit that turns on the switch circuit for a predetermined period during a period from when the second switching element turns off until it turns on;
has
The orthogonal transform unit includes the first switching element including the first transistor and the first body diode, the second switching element including the second transistor and the second body diode, third and fourth switching elements. switching element, first and second diodes, a positive power supply, a negative power supply, and the switch circuit including a third transistor and a third diode,
a positive terminal of the positive power supply is connected to the drain of the first transistor, the cathode of the first body diode and the source of the third transistor;
the negative terminal of the negative power supply is connected to the source of the second transistor and the anode of the second body diode;
the negative terminal of the positive power supply is connected to the positive terminal of the negative power supply, the emitter of the third switching element and the anode of the first diode;
the collector of the third switching element is connected to the cathode of the first diode, the cathode of the second diode and the collector of the fourth switching element;
The emitter of the fourth switching element is connected to the anode of the second diode, the source of the first transistor, the anode of the first body diode, the anode of the third diode, and the drain of the second transistor. , connected to the cathode and midpoint of said second body diode;
the cathode of the third diode connects to the drain of the third transistor;
Power converter.

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