JP5489937B2 - Driving circuit, optical print head, image forming apparatus, and display device - Google Patents

Description

  The present invention selectively selects a group of driven elements (for example, a row of LEDs in an electrophotographic printer or the like using a light emitting diode (hereinafter referred to as “LED”) as a light source, a row of display elements in a display device, etc.). The present invention also relates to a drive circuit that cyclically drives, an optical print head having the drive circuit, an image forming apparatus such as an electrophotographic printer having the optical print head, and a display device having the drive circuit.

  2. Description of the Related Art Conventionally, some image forming apparatuses such as electrophotographic printers have an exposure portion formed by arranging a large number of light emitting elements. In addition to LEDs, organic electroluminescence (hereinafter referred to as “organic EL”), light-emitting thyristors, and the like are used as the light-emitting elements.

  In the case of using an LED, the drive circuit and the LED are provided so as to correspond to 1: 1 or 1: N (where N> 1), and the drive circuit allows a drive current to be generated between the anode and cathode of the LED. The light emission / non-light emission state is switched depending on whether or not to flow. The light output of the LED in the light emitting state is determined by the drive current value, and the amount of exposure energy to the exposure unit is adjusted by adjusting the drive current.

  As an LED driving circuit, a configuration is known in which a constant current characteristic is provided by operating a driving MOS transistor in a saturation region to drive the LED at a constant current. In this driving circuit, in order to operate the driving MOS transistor in the saturation region, a predetermined control voltage is applied between the gate and the source, and the control voltage value is a control circuit including an operational amplifier (hereinafter referred to as “op-amp”). Can be generated.

  Further, based on the control voltage value, a plurality of levels of control voltage close to the control voltage value are created, and one control voltage is selected from the plurality of control voltages by an analog multiplexer, and the gate of the driving MOS transistor is selected. A configuration is known in which the light amount of an LED is corrected by applying it as a source-to-source voltage (for example, Patent Document 1).

JP 2001-54959 A

  However, the conventional drive circuit described in Patent Document 1 has the following problems.

  The driving circuit described in Patent Document 1 includes an analog multiplexer for selecting one control voltage from among a plurality of control voltages in order to change the gate-source voltage applied to the driving MOS transistor. Yes.

  For example, considering the case where the drive current value is changed in 16 steps in increments of 2% with respect to the standard value by correction data for correcting the light amount of the LED, the correction data is 4 bits. In this case, the analog multiplexer is configured to select and output one of 16 levels of control voltage based on the correction data. For example, the analog multiplexer is referred to as a complementary MOS transistor (hereinafter referred to as “CMOS”). ) Four analog switches are connected in series.

  Although the on-resistance of the analog switch is desirably small, for this purpose, it is necessary to arrange a transistor having a large chip occupation area, which is contrary to the demand for cost reduction. In addition, the analog multiplexer has a circuit configuration in which four analog switches having a CMOS configuration are connected in series. Therefore, the on-resistance of the analog multiplexer is further quadrupled, and a monolithic integrated circuit (hereinafter referred to as “IC”) chip. As a result, the on-resistance of the analog multiplexer must be large considering the restrictions on the chip size that can be realized and the economic efficiency.

  In the conventional driving circuit, the charge / discharge current of the capacitance accompanying the gate of the driving MOS transistor when the LED driving is turned on / off flows through the analog multiplexer. However, since the on-resistance of the analog multiplexer is large, the time constant when the LED drive is turned on and off increases, the rise time of the LED drive current increases, and there is a problem that high-speed operation cannot be performed. In addition, it is inevitable that the on-resistance of the analog multiplexer varies due to the semiconductor manufacturing process, but this also causes the rise time of the LED drive current to vary. As a result, even if the LED light amount can be corrected by paying attention to the LED drive current, if the rise time of the LED drive current fluctuates due to the above factors, the substantial drive current pulse width changes and print density unevenness occurs. There was a problem that it would end up.

  Thus, the conventional driving circuit includes an analog multiplexer for selecting a predetermined control voltage from among a plurality of potential control voltages in order to change the gate-source voltage applied to the driving MOS transistor. Since the on-resistance of this analog multiplexer is large, the rise time of the LED drive current is large and high-speed operation cannot be performed, and since the on-resistance varies, the substantial drive current pulse width changes and print density unevenness occurs. There was a problem.

According to a first aspect of the present invention , there is provided a driving circuit for driving a driven element, a potential generating circuit for generating a plurality of different potentials, and a plurality of potentials generated by the potential generating circuit. A multiplexer that selects one of the control voltage, a control voltage generation circuit that generates a control voltage based on a reference voltage, the control voltage is input, and either the control voltage or the power supply voltage is input based on grayscale data A gate circuit that outputs signals having substantially the same value and a first conductivity type switch element are provided. The switch element of the first conductivity type includes a first terminal connected to a power supply that supplies the power supply voltage, and a second terminal that supplies a drive current supplied from the power supply through the first terminal to the driven element. And a control terminal for conducting / interrupting between the first terminal and the second terminal based on an output signal of the gate circuit, and a substrate terminal connected to the output terminal of the multiplexer. The current value of the drive current supplied from the second terminal to the driven element can be adjusted based on the voltage between the control terminal and the first terminal and the voltage of the substrate terminal. It is characterized by.

An optical print head according to a second aspect of the invention is characterized in that the driven element is a light emitting element, and the driving circuit according to the first aspect of the invention is provided, wherein the plurality of light emitting elements are arranged substantially linearly.

According to a third aspect of the present invention, there is provided an image forming apparatus comprising: the optical print head according to the second aspect of the present invention; and a photoconductor that forms a latent image based on the light irradiated by the optical print head.

According to a fourth aspect of the present invention, there is provided a display device including the drive circuit according to the first aspect , wherein the driven element is a display element, and the plurality of display elements are arranged in a two-dimensional matrix.

According to the driving circuit and the print head of the second invention of the first invention, it is possible to small enough so the rise time and fall time of the waveform of the driving current for driving a driven element, High-speed switching operation can be expected. Furthermore, the rise time and fall time of the waveform of the drive current can be made substantially equal, and the driven element can be driven with a time width according to the command value. In addition, the rise time and fall time of the drive current waveform are sufficiently small, so even if the rise time and fall time vary due to the semiconductor manufacturing process, the effect on the actual drive time is negligible. In addition, it is possible to solve the problem that the print density unevenness is caused by the change in the substantial drive current pulse width due to the fluctuation of the rise time of the drive current.

According to the image forming apparatus of the third invention, since the optical print head of the second invention is employed, a high quality image forming apparatus excellent in space efficiency and light extraction efficiency can be realized.

According to the display device of the fourth invention, since the display element is driven using the drive circuit of the first invention, a high-quality display device excellent in space efficiency and display efficiency can be realized.

FIG. 1 is a circuit diagram showing the main part of the drive circuit in FIG. 6 according to Embodiment 1 of the present invention. FIG. 2 is a schematic configuration diagram illustrating the image forming apparatus according to the first exemplary embodiment of the present invention. FIG. 3 is a schematic sectional view showing the structure of the optical print head 13 in FIG. FIG. 4 is a block diagram showing the configuration of the printer control circuit in the image forming apparatus 1 of FIG. FIG. 5 is a block diagram showing a circuit configuration of the optical print head 13 in FIG. FIG. 6 is a block diagram showing a detailed circuit configuration of the driver IC 100 in FIG. FIG. 7 is a circuit diagram showing a configuration of the write control circuit 145 in FIG. FIG. 8 is a circuit diagram showing the configuration of the driver 181 in FIG. FIG. 9 is a circuit diagram showing a configuration of control voltage generating circuit 160 in FIG. FIG. 10 is a time chart showing correction data transfer processing performed for the optical print head 13 and the driver IC 100 in FIG. 5 after the image forming apparatus 1 according to the first embodiment of the present invention is turned on. FIG. 11 is a time chart showing a state of gradation print data transfer performed after the correction data transfer process. FIG. 12 is a waveform diagram schematically showing the drive current waveform of FIG. FIG. 13 is a block diagram showing a detailed circuit configuration of the driver IC 100A according to the second embodiment of the present invention. FIG. 14 is a circuit diagram showing the configuration of the driver 351 in FIG. FIG. 15 is a circuit diagram showing a configuration of control voltage generating circuit 330 in FIG. FIG. 16 is a circuit diagram showing a configuration of the bias circuit 340 in FIG. FIG. 17 is a characteristic diagram of the PMOS in the PMOSs 410 to 413 and the like in FIG. FIG. 18 is a circuit diagram showing a main part of the drive circuit in FIG. 13 according to the second embodiment of the present invention. FIG. 19 is a waveform diagram schematically showing the drive current waveform of FIG. FIG. 20 is a schematic configuration diagram showing a display device in Embodiment 3 of the present invention.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Image Forming Apparatus of Example 1)
FIG. 2 is a schematic configuration diagram illustrating the image forming apparatus according to the first embodiment of the present invention.

  The image forming apparatus 1 is an electrophotographic color printer equipped with an optical print head using a light emitting element (for example, LED) as a driven element, and is black (K), yellow (Y), magenta (M). And four process units 10-1 to 10-4 for forming images of each color of cyan (C), and these are arranged in order from the upstream side of the conveyance path of the recording medium 20 (for example, paper). ing. Since the internal configurations of the process units 10-1 to 10-4 are common, for example, the magenta process unit 10-3 will be described as an example.

  In the process unit 10-3, a photoconductor (for example, photoconductor drum) 11 as an image carrier is disposed so as to be rotatable in the arrow direction in FIG. Around the photosensitive drum 11, a charging device 12 that supplies electric charges to the surface of the photosensitive drum 11 and charges the surface of the photosensitive drum 11 in order from the upstream side in the rotation direction, and selectively applies light to the surface of the charged photosensitive drum 11. An exposure device (for example, an optical print head) 13 that forms an electrostatic latent image by irradiation is provided. Further, a developing device 14 for generating a visible image by attaching magenta (predetermined color) toner to the surface of the photosensitive drum 11 on which the electrostatic latent image is formed, and a visible image of the toner on the photosensitive drum 11. A cleaning device 15 for removing toner remaining after the transfer to the paper 20 is provided. Note that the drums or rollers used in these devices rotate by receiving power from a drive source (not shown) via a gear or the like.

  A paper cassette 21 for storing the paper 20 in a stacked state is mounted at the bottom of the image forming apparatus 1, and a hopping roller 22 for separating and transporting the paper 20 one by one is disposed above the paper cassette 21. Yes. On the downstream side of the hopping roller 22 in the transport direction of the paper 20, the paper 20 is sandwiched together with the pinch rollers 23 and 24, thereby correcting the skew of the paper 20 and the transport roller 25 for transporting the paper 20. A registration roller 26 to be conveyed to 10-1 is disposed. The hopping roller 22, the conveyance roller 25, and the registration roller 26 are rotated by receiving power from a driving source (not shown) via a gear or the like.

  At the positions facing the respective photosensitive drums 11 of the process units 10-1 to 10-4, transfer units 27 formed of semiconductive rubber or the like are respectively disposed. Each transfer device 27 has a potential difference between the surface potential of each photoconductor drum 11 and the surface potential of each of these transfer devices 27 at the time of transferring the visible image by the toner attached on the photoconductor drum 11 to the paper 20. A potential for applying the voltage is applied.

  A fixing device 28 is disposed downstream of the process unit 10-4. The fixing device 28 includes a heating roller having a built-in heater and a backup roller, and is a device that fixes the toner transferred onto the sheet 20 by pressurizing and heating. 30, pinch rollers 31 and 32 of a discharge unit, and a paper stacker unit 33 are provided. The discharge rollers 29 and 30 sandwich the paper 20 discharged from the fixing device 28 together with the pinch rollers 31 and 32 of the discharge unit and convey the paper 20 to the paper stacker unit 33. The fixing device 28, the discharge roller 29, and the like rotate when power is transmitted from a driving source (not shown) via a gear or the like.

The image forming apparatus 1 configured as described above operates as follows.
First, the sheets 20 stored in a stacked state in the sheet cassette 21 are separated and transported one by one from the top by the hopping roller 22. Subsequently, the sheet 20 is sandwiched between the conveyance roller 25, the registration roller 26, and the pinch rollers 23 and 24, and is conveyed between the photosensitive drum 11 and the transfer unit 27 of the process unit 10-1. Thereafter, the sheet 20 is sandwiched between the photosensitive drum 11 and the transfer unit 27, and the toner image is transferred to the recording surface thereof, and at the same time, the sheet 20 is conveyed by the rotation of the photosensitive drum 11. Similarly, the paper 20 sequentially passes through the process units 10-2 to 10-4, and in the passing process, the electrostatic latent images formed by the optical print heads 13 are developed by the developing units 14 for the respective colors. The toner images are sequentially transferred and superimposed on the recording surface.

  After the toner images of the respective colors are superimposed on the recording surface in this way, the paper 20 on which the toner image is fixed by the fixing device 28 is sandwiched between the discharge rollers 29 and 30 and the pinch rollers 31 and 32 to form an image. The paper is discharged to a paper stacker unit 33 outside the apparatus 1. Through the above process, a color image is formed on the paper 20.

(Structure of optical print head)
FIG. 3 is a schematic sectional view showing the structure of the optical print head 13 in FIG.

  The optical print head 13 has a base member 13a, and a printed wiring board 13b is fixed on the base member 13a. On the printed wiring board 13b, a plurality of driving circuits (for example, chip-shaped driver ICs) 100 and a plurality of driven element arrays (for example, chip-shaped light emitting element arrays) 200 are arranged to face each other, and are thermoset. It is fixed on the printed wiring board 13b with a conductive resin or the like. The plurality of driver ICs 100 and the plurality of light emitting element arrays 200 are connected by bonding wires or the like (not shown). On the plurality of light emitting element arrays 200, a rod drains array 13c in which a large number of columnar optical elements are arranged is arranged, and the rod drains array 13c is fixed by a holder 13d. The base member 13a, the printed wiring board 13b, and the holder 13d are fixed by clamp members 13e and 13f.

  In FIG. 3, the driver IC 100 and the light emitting element array 200 are arranged to face each other and are connected to each other with a bonding wire or the like. As another configuration, for example, the light emitting element array 200 is illustrated. It is also possible to form an epitaxial layer for forming the light emitting layer in the form of a film, peel it from the wafer base material, and apply it to the upper surface or side surface of the driver IC 100 to connect the required portions of the two by thin film wiring.

(Printer control circuit)
FIG. 4 is a block diagram showing the configuration of the printer control circuit in the image forming apparatus 1 of FIG.

  The printer control circuit has a print control unit 40 disposed inside the printing unit in the image forming apparatus 1. The print control unit 40 includes a microprocessor, a read-only memory (hereinafter referred to as “ROM”), a readable / writable memory (hereinafter referred to as “RAM”), an input / output port for inputting and outputting signals, a timer, and the like. And has a function of performing a printing operation by controlling the entire image forming apparatus in sequence by a control signal SG1 from an image processing unit (not shown) and a video signal (one-dimensionally arranged dot map data) SG2. Yes. The print control unit 40 includes four optical print heads 13 of the process units 10-1 to 10-4, a heater 28a of the fixing device 28, drivers 41 and 43, a paper suction port sensor 45, a paper discharge port sensor 46, and a paper. A remaining amount sensor 47, a paper size sensor 48, a fixing device temperature sensor 49, a charging high-voltage power source 50, a transfer high-voltage power source 51, and the like are connected. The driver 41 has a development / transfer process motor (PM) 42, the driver 43 has a paper feed motor (PM) 44, the charging high-voltage power supply 50 has a developing device 14, and the transfer high-voltage power supply 51 has a transfer device 27. Are connected to each other.

The printer control circuit having such a configuration performs the following operation.
When the printing control unit 40 receives a printing instruction in response to a control signal SGl from an image processing unit (not shown), first, the temperature sensor 49 detects whether or not the heater 28a in the fixing device 28 is within a usable temperature range. If not in the temperature range, the heater 28a is energized to heat the fixing device 28 to a usable temperature. Next, the development / transfer process motor 42 is rotated via the driver 41, and at the same time, the charging high-voltage power supply 50 is turned on by the charge signal SGC to charge the developing device 14.

  2 is detected by the remaining paper amount sensor 47 and the paper size sensor 48, and paper feeding suitable for the paper 20 is started. Here, a planetary gear mechanism (not shown) is connected to the paper feed motor 44 and can be rotated in both directions via a driver 43. Therefore, by changing the rotation direction of the paper feed motor 44, different paper feed transport rollers 25 and the like inside the image forming apparatus can be selectively driven.

  Each time a page of paper is printed, the paper feed motor 44 is first reversed to feed the set paper 20 by a preset amount until the paper inlet sensor 45 detects it. Subsequently, the sheet 20 is rotated forward and conveyed to a printing mechanism inside the image forming apparatus.

  When the paper 20 reaches a printable position, the print control unit 40 transmits a timing signal SG3 (including a main scanning synchronization signal and a sub scanning synchronization signal) to an image processing unit (not shown), and a video signal SG2. Receive. The video signal SG2 edited for each page in the image processing unit (not shown) and received by the print control unit 40 is transferred to each optical print head 13 as gradation print or correction data HD-DATA3 to HD-DATA0. Each optical print head 13 has a plurality of LEDs arranged for printing one dot (pixel) on a line.

  When the print control unit 40 receives the video signal SG2 for one line, the print control unit 40 transmits a latch signal HD-LOAD to each optical print head 13, and supplies gradation print or correction data HD-DATA3 to HD-DATA0 to each optical print head. 13 to hold. Further, the print control unit 40 prints the gradation print data HD-DATA3 to HD-DATA0 held in each optical print head 13 even while the next video signal SG2 is being received from the image processing unit (not shown). can do.

  A clock signal (hereinafter simply referred to as “clock”) HD-CLK and a drive on / off command signal (for example, print drive signal) HD-STB-N transmitted from the print controller 40 to each optical print head 13. (However, “−N” means a negative logic signal.) The clock HD-CLK is a signal for transmitting gradation printing or correction data HD-DATA3 to HD-DATA0 to the optical print head 13. is there.

  Transmission / reception of the video signal SG2 is performed for each print line. Light emitted from the optical print head 13 is irradiated onto the photosensitive drum 11 charged to a negative potential. As a result, the information to be printed is converted into a latent image on the photosensitive drum 11 as dots having an increased potential. In the developing unit 14, the toner for image formation charged to a negative potential is sucked to each dot by an electric suction force, and a toner image is developed and formed.

  Thereafter, the toner image is sent to the transfer device 27, and on the other hand, the transfer high voltage power supply 51 is turned on to a positive potential by the transfer signal SG4, and the transfer device 27 passes through the interval between the photosensitive drum 11 and the transfer device 27. A toner image is transferred onto the paper 20. The sheet 20 having the transferred toner image is conveyed in contact with a fixing device 28 including a heater 28 a, and is fixed to the sheet 20 by the heat of the fixing device 28. The sheet 20 having the fixed image is further conveyed and discharged from the printing mechanism of the image forming apparatus 1 through the sheet discharge port sensor 46 to the outside of the image forming apparatus.

  In response to detection by the paper size sensor 48 and the paper inlet sensor 45, the print control unit 40 supplies the voltage from the high-voltage power supply 51 for transfer to the transfer device 27 only while the paper 20 passes through the transfer device 27. Apply. When printing is finished and the paper 20 passes through the paper discharge port sensor 46, the application of voltage to the developing device 14 by the charging high-voltage power supply 50 is finished, and at the same time, the rotation of the development / transfer process motor 42 is stopped. Thereafter, the above operation is repeated.

(Circuit configuration of optical print head)
FIG. 5 is a block diagram showing a circuit configuration of the optical print head 13 in FIG.

  For example, the optical print head 13 is configured to print on an A4 size paper at a resolution of 600 dots per inch.

  The optical print head 13 has a printed wiring board 13b in FIG. 3, and a plurality of (for example, 26) driver ICs 100 (= 100-1, 100-2,...) On the printed wiring board 13b. A plurality of (for example, 26) light emitting element arrays 200 (= 200-1, 200-2,...) Are arranged adjacent to each other. FIG. 5 shows only two driver ICs 100 (= 100-1, 100-2) and two light emitting element arrays 200 (= 200-1, 200-2).

  In each light emitting element array 200, a plurality of (for example, 192) LEDs 210 (= 210-1 to 210-192) are arranged substantially linearly. The total number of LEDs 210 is 4992 dots (pieces). The cathodes of 192 LEDs 210 constituting each light emitting element array 200 are connected to a fixed potential node (for example, ground) GND, and each anode is connected to the DO1 terminal to DO192 terminal of each driver IC 100 by a bonding wire or the like. Yes.

  The 26 driver ICs 100 (= 100-1, 100-2,...) Are configured by the same circuit, and adjacent driver ICs 100-1, 100-2,. ing.

  Each driver IC 100 has DATAI3 to DATAI0 terminals for inputting gradation printing or correction data HD-DATA3 to HD-DATA0, a LOAD terminal for inputting a latch signal HD-LOAD, a CLK terminal for inputting a clock HD-CLK, and a reference voltage VREF. The VREF terminal for inputting the STB terminal, the STB terminal for inputting the print drive signal HD-STB-N which is the strobe signal, the VDD terminal for inputting the power supply voltage VDD, the GND terminal connected to the ground GND, and the data DATAO3 to DATAO0 in the next stage. It has DATAO3 to DATAO0 terminals that output to the driver IC 100 and output terminals DO1 to DO192 that output LED drive currents to the anodes of the LEDs 210 in each light emitting element array 200.

  Here, the reference voltage VREF input to the VREF terminal is a reference voltage for instructing a drive current value for LED driving, and is supplied from a reference voltage generation circuit (not shown) provided in the optical print head 13. Is done.

The operation of the optical print head 13 of FIG. 5 configured as described above will be described.
In the configuration shown in FIG. 5, there are four gradation printing or correction data HD-DATA3 to HD-DATA0, and gradation printing or correction data HD-DATA3 to HD-DATA0 for each LED is supplied for each clock HD-CLK. Are sent simultaneously. Therefore, the gradation print or correction data HD-DATA3 to HD-DATA0 output from the print control unit 40 in FIG. 4 is input to the DATAI3 to DATAI0 terminals of the driver IC 100-1 together with the clock HD-CLK, and the total number of 4992 dots. Minute bit data is sequentially transferred in a shift register including a flip-flop circuit (hereinafter referred to as “FF”) in each driver IC 100 described later.

  Next, the latch signal HD-LOAD is input to the LOAD terminals of all the driver ICs 100, and the bit data stored in the shift register is provided corresponding to each FF constituting the shift register in each driver IC 100. It is latched by the latch circuit. Subsequently, when the print drive signal HD-STB-N is input to the STB terminals of all the driver ICs 100, the output terminals DO1, in which the gradation print data HD-DATA3 to HD-DATA0 among the LEDs 210 are at "H" level. The LED 210 connected to DO2,.

  As shown in FIG. 5, since a large number of light emitting element arrays 200 are mounted on the optical print head 13, if there is a characteristic variation due to manufacturing variations in each of these light emitting element arrays 200, Even between the LEDs 210 in the same light emitting element array 200, the light emission power fluctuates, resulting in different exposure energy amounts on the photosensitive drum 11.

  Such a phenomenon appears as fluctuations in the dot area when developing the photosensitive drum 11, and is undesirable because it causes uneven printing density. Therefore, it is usual to adjust the drive current of each LED 210 in the light emitting element array 200 so that the light emission power becomes constant, and each driver IC 100 in FIG. Means.

(Overall configuration of driver IC)
FIG. 6 is a block diagram showing a detailed circuit configuration of the driver IC 100 in FIG.

  The driver IC 100 includes a shift register 110 including a plurality of cascade-connected (for example, 193) FF units 111 (= 111−192 to 111−0). The shift register 110 is a circuit that captures and shifts gradation print or correction data HD-DATA3 to HD-DATA0 input from the DATAI3 to DATAI0 terminals in synchronization with the clock HD-CLK input from the CLK terminal. Each FF unit 111 includes four FFs therein, four data input terminals D0 to D3, four data output terminals Q0 to Q3, and a clock terminal commonly connected to the four FFs. CK is provided.

  Here, in the cascade-connected FF units 111-192 to 111-0, the DATAI0 terminal of the driver IC 100 is connected to the data input terminal D0 of the FF units 111-192, and the FF units 111-1 and 111-0. The input terminals A0 and B0 of the selector (SEL) 120 are connected to the data output terminal Q0. The output terminal Y0 of the selector 120 is connected to the DATAO0 terminal of the driver IC 100. Similarly, the DATAI1, DATAI2, and DATAI3 terminals of the driver IC 100 are connected to the data input terminals D1, D2, and D3 of the FF units 111-192, respectively. The data output terminals Q1, Q2, Q3 of the FF units 111-1, 111-0 are also connected to the input terminals A1, A2, A3, B1, B2, B3 of the selector 120, respectively. The output terminals Y1, Y2 of the selector 120 , Y3 are connected to the DATAO1, DATAO2, and DATAO3 terminals of the driver IC 100, respectively. Therefore, the FF units 111-192 to 111-0 as a whole constitute a 193-stage shift register 110, and the selector 120 can switch the number of shift stages of the shift register 110 between 192 stages and 193 stages.

  As shown in FIG. 5, the DATAO0 to DATAO3 terminals in the first stage driver IC 100-1 are connected to the DATAI0 to DATAI3 terminals of the next stage driver IC 100-2, respectively. Therefore, the shift registers 110,... Composed of all of the driver ICs 100-1 to 100-26 have the gradation printing or correction data HD-DATA0 to HD-DATA0 input from the print control unit 40 to the first driver IC 100-1. A shift register circuit of 192 × 26 = 4992 stages or 193 × 26 = 5018 stages for shifting HD-DATA 3 in synchronization with the clock HD-CLK is configured.

  The input side of the latch unit 130 and the correction memory unit 150 is connected to the data output terminals Q0 to Q3 of the FF units 111-192 to 111-1. The latch unit 130 is a grayscale output from the FF units 111-192 to 111-1 based on a latch signal LOAD-P (where "-P" means a positive logic signal) input from the LOAD terminal. This is a circuit for latching print data, and is composed of a plurality (for example, 192) of latch circuit units 131 (= 131-192 to 131-1). Each latch circuit unit 131 includes four latch circuits therein, four data input terminals D0 to D3 for inputting gradation print data, four data output terminals Q0 to Q3, and a latch signal LOAD. In order to input −P, a latch terminal G commonly connected to the four latch circuits is provided.

  The correction memory unit 150 is a circuit that stores correction data output from the FF units 111-192 to 111-0 based on the write command signal WR output from the control unit 140, and a plurality of (eg, 193) correction data. The correction memory circuit unit 151 (= 151 to 192 to 151-0) is included. Each correction memory circuit unit 151 includes four latch circuits therein, four data input terminals D0 to D3 for inputting correction data, four data output terminals Q0 to Q3, and a write command signal WR. Are latch terminals G connected in common to the four latch circuits. Here, dot correction data for each LED is stored in each of the correction memory circuit units 151-192 to 151-1, and chip correction data is stored in the correction memory circuit unit 151-0.

  Each correction memory circuit unit 151 is configured by a latch circuit, but may be configured using a memory circuit similar to a static RAM.

  Based on the print drive signal HD-STB-N input from the STB terminal and the latch signal LOAD-P input from the LOAD terminal, the control unit 140 generates a drive on / off control signal DRV-ON-P for the LED 210. , A circuit for generating a write command signal WR for the correction memory unit 150, a pull-up resistor 141 for pulling up the STB terminal to the power supply voltage VDD, inverters 142 and 143 for signal inversion, and a 2-input logical product circuit (hereinafter referred to as an AND circuit). 144 and a write control circuit (CTRL) 145.

  The negative logic print drive signal HD-STB-N input from the STB terminal is inverted by the inverter 142 and converted into a positive logic signal STB-P. The positive logic latch signal LOAD-P input from the LOAD terminal is inverted by the inverter 143 and converted into a negative logic latch signal LOAD-N. The latch signal LOAD-N and the signal STB-P are AND circuits. The logical product is obtained by 144 to generate the drive on / off control signal DRV-ON-P. The write control circuit 145 has an STB terminal, a LOAD terminal, and a WR terminal. Based on the signal STB-P input from the STB terminal and the latch signal LOAD-P input from the LOAD terminal, the write control circuit 145 receives the write command signal WR as WR. This circuit outputs from the terminal.

  Among the correction memory circuit units 151-0 to 151-192, the data output terminals Q0 to Q3 of the correction memory circuit unit 151-0 are connected to the input side of the control voltage generation circuit (ADJ) 160, and the correction memory circuit unit 151 is connected. The input side of the multiplexer unit 170 is connected to the data output terminals Q0 to Q3 of −192 to 151-1 and the output side of the control signal generation circuit 160. Furthermore, the input side of the driver unit 180 is connected to the data output terminals Q0 to Q3 of the latch circuit units 131-192 to 131-1 and the output side of the multiplexer unit 170.

  The control voltage generation circuit 160 includes input terminals S3 to S0 for inputting chip correction data output from the correction memory circuit unit 151-0, a VREF terminal for inputting a reference voltage VREF, and a control voltage for LED driving. V15 to V0 terminals for outputting V15 to V0, and a voltage for LED driving based on a predetermined reference voltage VREF input from the VREF terminal and chip correction data input from the input terminals S3 to S0 This circuit generates V15 to V0 from terminals V15 to V0. The reference voltage VREF is generated by a regulator (not shown) or the like, and is held at a predetermined voltage value even in a situation where the power supply voltage VDD drops for a moment as in the case where the LED 210 is fully turned on.

  The multiplexer unit 170 selects one of the voltages V0 to V15 supplied from the control voltage generation circuit 160 based on the dot correction data output from the correction memory circuit units 151-192 to 151-1. This is a circuit provided to the driver unit 180, and is constituted by a plurality (eg, 192) of multiplexers (MUX) 171 (= 171-192 to 171-171-1). Each multiplexer 171 has four input terminals S0 to S3 for inputting dot correction data, 16 input terminals P0 to P15 for inputting voltages V0 to V15, and an output terminal Y for outputting a selected control voltage. The driver unit 180 is connected to the output terminal Y side.

  The driver unit 180 is turned on / off by a drive on / off control signal DRV-ON-P output from the control unit 140, and the gradation print data output from the latch unit 130 and output from the multiplexer unit 170. This is a circuit for outputting an LED drive current for driving the light emitting element array 200 based on the control voltage, and a plurality of (for example, 192) drivers (DRV) 181 (= 181 to 192 to 181-1). It is comprised by. Each driver 181 has an input terminal S for inputting a drive on / off control signal DRV-ON-P, an input terminal B for inputting a control voltage, and four input terminals D3 to D3 for inputting gradation print data. D0 and an output terminal DO for outputting the LED drive current to the output terminal DO (= DO192 to DO1).

  A circuit block BK1 surrounded by a broken line in FIG. 6 includes an FF unit 111-192, a latch circuit unit 131-192, a correction memory circuit unit 151-192, a multiplexer 171-192, and a driver 181-192. This is a drive circuit for one dot for driving the individual LEDs 210. A circuit block BK2 surrounded by a broken line is configured by an FF unit 111-0, a correction memory circuit unit 151-0, and a control voltage generation circuit 160, and supplies a control voltage to be applied to the entire multiplexer unit 170. Circuit.

(Write control circuit in the driver IC)
FIG. 7 is a circuit diagram showing a configuration of write control circuit 145 in FIG.

  The write control circuit 145 has a LOAD terminal for inputting a latch signal LOAD-P, an STB terminal for inputting a signal STB-P, and a WR terminal for outputting a write command signal WR, and two stages of FFs 145a and 145b. And a two-input NAND circuit (hereinafter referred to as “NOR circuit”) 145c.

  The first-stage FF 145a is connected to the data input terminal D connected to the output terminal of the NOR circuit 145c, the negative logic reset terminal R connected to the LOAD terminal and the latch signal LOAD-P, and the STB terminal. A clock terminal CK to which the signal STB-P is input and a data output terminal Q. The second-stage FF 145b includes a data input terminal D connected to the output terminal Q of the first-stage FF 145a, a negative logic reset terminal R connected to the LOAD terminal and receiving the latch signal LOAD-P, and an STB terminal And a data output terminal Q for outputting a write command signal WR to the WR terminal. Further, the NOR circuit 145c has an input side connected to the output data terminals Q of the two-stage FFs 145a and 145b, and an output side connected to the data input terminal D of the FF 145a, and performs a negative OR operation on output data of the two-stage FFs 145a and 145b. Is returned to the data input terminal D of the FF 145a.

(Driver in the driver IC)
FIG. 8 is a circuit diagram showing a configuration of driver 181 in FIG.

  The driver 181 includes an input terminal S for inputting a drive on / off control signal DRV-ON-P, an input terminal B for inputting a control voltage (one of V0 to V15), and a latch circuit unit 131. It has four input terminals D3 to D0 for inputting the gradation print data DATA3 to DATA0 to be output, and an output terminal DO for outputting a drive current to the LED 210 in FIG.

  The input terminals S and the input terminals D0 to D3 are connected to the input sides of two-input NAND circuits (hereinafter referred to as “NAND circuits”) 300 to 303, respectively. The power supply terminals of the NAND circuits 300 to 303 are connected to the VDD terminal, and the ground terminals are connected to the ground (= 0V). Control terminals (for example, gates) in a plurality of (for example, four) first switch elements (for example, P-channel MOS transistors, hereinafter referred to as “PMOS”) 310 to 313 are input terminal B. The sources of these PMOSs 310 to 313 are connected to the VDD terminal. The gates of the four first conductive type second switch elements (for example, PMOS) 320 to 323 are connected to the output sides of the four NAND circuits 300 to 303, respectively. The sources of the PMOSs 320 to 323 are connected in series to the drains of the PMOSs 310 to 313, respectively, and the drains are commonly connected to the output terminal DO.

  Here, the voltage difference between the power supply voltage VDD at the VDD terminal and the voltage at the input terminal B is equal to the gate-source voltage Vgs of the PMOSs 313 to 310, and the PMOS 313 to 310 is changed by changing the gate-source voltage Vgs. The drain current can be adjusted.

The driver 181 configured as described above operates as follows.
It is assumed that the gradation print data DATA3 input to the input terminal D3 among the gradation print data DATA3 to DATA0 input to the input terminals D3 to D0 is at “H” level, for example. When the drive ON / OFF control signal DRV-ON-P input to the input terminal S becomes “H” level and the LED drive ON is commanded, the output signal of the NAND circuit 303 becomes “L” level. As a result, the PMOS 323 is turned on, and the drain current output from the PMOS 313 is output from the output terminal DO. Similarly for the other input terminals D2 to D0, the PMOSs 322 to 320 are turned on in accordance with the “H” level of the gradation print data DATA2 to DATA0 input to the input terminals D2 to D0, and are output from the PMOSs 312 to 310. The drain current can be output from the output terminal DO.

  That is, the PMOSs 323 to 320 are selectively driven according to the “H” level of the gradation print data DATA3 to DATA0 input to the input terminals D3 to D0, and a drive current obtained by adding the drain currents of the PMOSs 313 to 310 is output. It is output from the terminal DO and supplied to the LED 210 in FIG.

  In this case, for example, by setting the gate width of the PMOSs 313 to 310 to a ratio of 8: 4: 2: 1, the drain current of the PMOSs 313 to 310 can be set to a ratio of 8: 4: 2: 1. The output current of the output terminal DO can be changed in 16 steps according to the gradation print data DATA3 to DATA0 input to the input terminals D3 to D0.

(Control voltage generation circuit in FIG. 6)
FIG. 9 is a circuit diagram showing a configuration of control voltage generating circuit 160 in FIG.

  The control voltage generation circuit 160 includes input terminals S3 to S0 for inputting chip correction data output from the correction memory circuit unit 151-0, a VREF terminal for inputting a reference voltage VREF, and voltages V15 to V0 for LED driving. V15 to V0 terminals for outputting LEDs, and based on a predetermined reference voltage VREF inputted from the VREF terminal and chip correction data inputted from the input terminals S3 to S0, voltages V15 to V0 for LED driving are provided. Is generated from the V15 to V0 terminals, and is provided for each driver IC 100. The reference voltage VREF is generated by a regulator (not shown) or the like, and is held at a predetermined voltage value even in a situation where the power supply voltage VDD drops for a moment as in the case where the LED 210 is fully turned on.

  The control voltage generation circuit 160 has an operational amplifier 161 in which a VREF terminal for inputting a reference voltage VREF is connected to an inverting input terminal, and a voltage dividing circuit 162 is connected to an output terminal of the operational amplifier 161. The voltage dividing circuit 162 has a plurality of resistors 162-0 to 162-15 for generating a plurality of voltages V0 to V15, which are connected in series between the VDD terminal and the output terminal of the operational amplifier 161. Yes. V0 to V14 terminals are connected to the connection portions of the resistors 162-0 to 162-15, respectively, and a V15 terminal is connected to a connection portion between the resistors 162-15 and the output terminal of the operational amplifier 161.

  The gate of the PMOS 163 is connected to the V7 terminal, the source of the PMOS 163 is connected to the VDD terminal, and the drain is connected to the non-inverting input terminal of the operational amplifier 161. The PMOS 163 has the same gate length as the PMOSs 310 to 313 in FIG. The R terminal of the resistance switching circuit 164 is further connected to the non-inverting input terminal of the operational amplifier 161. The resistance switching circuit 164 has S0 to S3 terminals connected to the input terminals S3 to S0 for inputting chip correction data, and an R terminal. The logic level in the four chip correction data input to the S0 to S3 terminals. According to the 16 combinations, the internal resistance is switched to 16 levels, and the resistance value between the terminal R and the ground can be adjusted to 16 levels.

  A feedback circuit is configured by a circuit including the operational amplifier 161, the PMOS 163, and the resistance switching circuit 164, and the voltage at the non-inverting input terminal of the operational amplifier 161 is controlled to be substantially equal to the reference voltage VREF. Therefore, the drain current Iref of the PMOS 163 is determined from the resistance value (for example, R0 to R15) between the R terminal of the resistance switching circuit 164 and the ground and the reference voltage VREF input to the operational amplifier 161. Become.

For example, when the logical value of the input terminals S3 to S0 is “1111” and the correction state is commanded to be maximum, the drain current Iref of the PMOS 163 is determined from the resistance value R15 between the terminal R of the resistance switching circuit 164 and the ground. Is
Iref = VREF / R15
It becomes.

When the logic value of the input terminals S3 to S0 is “0111” and the center of the correction state is commanded, the drain current of the PMOS 163 is determined from the resistance value R7 between the terminal R of the resistance switching circuit 164 and the ground. Iref is
Iref = VREF / R7
Become

Further, when the logical values of the input terminals S3 to S0 are “0000” and the minimum correction state is instructed, the drain of the PMOS 163 is determined from the resistance value R0 between the terminal R of the resistance switching circuit 164 and the ground. The current Iref is
Iref = VREF / R0
It becomes.

  The PMOS 163 and the PMOS 310 to 313 in FIG. 8 are configured to have the same gate length, and these transistors are controlled so as to operate in the saturation region. Therefore, when the gate-source voltages of the transistors are equal, When the PMOSs 310 to 313 are turned on due to the mirror relationship, each of the PMOSs 163 generates a drain current proportional to Iref.

  On the other hand, since the drain current Iref can be adjusted in 16 steps according to the logic value state of the chip correction data applied to the input terminals S3 to S0, the drain current of the PMOS 310 to 313 in FIG. 8 can also be adjusted in 16 steps. Can do.

  The above is true when the V7 terminal in FIG. 9 and the input terminal B in FIG. 8 are in a connection relationship, but the voltages V0 to V15 in FIG. 9 are set to a potential relationship close to the V7 terminal potential. Thus, the drain currents of the PMOSs 310 to 313 can be made substantially proportional to the drain current Iref of the PMOS 163. As a result, by changing the gate voltages of the PMOSs 310 to 313 (the voltage at the input terminal B in FIG. 8) to V0 to V15, the drain currents of the PMOSs 310 to 313 can be changed according to these voltage values.

(Operation of optical print head)
FIG. 10 is a time chart showing correction data transfer processing performed for the optical print head 13 and the driver IC 100 in FIG. 5 after the image forming apparatus 1 according to the first embodiment of the present invention is turned on. Further, FIG. 11 is a time chart showing a state of gradation print data transfer performed after the correction data transfer process.

  In the time charts of FIGS. 10 and 11, only the one-chip driver IC 100 is illustrated for the sake of simplicity.

(1) Correction Data Transfer in FIG. 10 In section A in FIG. 10, prior to the start of transfer of correction data DATA3 to DATA0 input from DATAI3 to DATAI0 terminals, to indicate that subsequent data transfer is correction data DATA3 to DATA0. The latch signal LOAD is set to the “H” level.

  In part B, dot correction data DOT1-b3, DOT1-b2, DOT1-b1, DOT1-b0,... Consisting of 4 bits of bit3 to bit0 per dot are synchronized with the clock CLK from the DATAI3 to DATAI0 terminals. input.

  The clock CLK is shown as 0, 1, 2,..., 192 in FIG. 10, and is at the head of the dot correction data string DOT1-b3, DOT1-b2, DOT1-b1, DOT1-b0,. Chip correction data CHIP-b3, CHIP-b2, CHIP-b1, and CHIP-b0 are arranged, and the chip correction data CHIP-b3, CHIP-b2, CHIP-b1, and CHIP are synchronized with the 0th clock pulse. -B0 is input.

  Next, dot correction data DOT1-b3, DOT1-b2, DOT1-b1, DOT1-b0 of dot number 1 are input in synchronization with the first clock pulse, and dot number 2 is synchronized with the second clock pulse. The dot correction data DOT2-b3, DOT2-b2, DOT2-b1, and DOT2-b0 are input.

  Similarly, dot correction data DOT192-b3, DOT192-b2, DOT192-b1, and DOT192-b0 with dot number 192 are input in synchronization with the 192nd clock pulse.

  The correction data strings CHIP-b3, CHIP-b2, CHIP-b1, CHIP-b0, DOT1-b3, DOT1-b2, DOT1-b1, DOT1-b0,..., DOT192-b3, DOT192-b2, DOT192- b1 and DOT192-b0 are shifted into the shift register 110 configured by the FF units 111-192 to 111-0 in FIG.

  When the shift input is completed, three pulses of the print drive signal STB-N are input to the STB terminal in the C section, and the write control circuit 145 in FIG. 7 in the control section 140 operates as follows. That is, when the first pulse of the print drive signal STB-N is input to the write control circuit 145, the data output terminal Q of the FF 145a rises, and at the second pulse of the print drive signal STB-N, the data output terminal of the FF 145b. As Q rises, a write command signal WR as shown in part D is generated.

  In the D section, when a write command signal WR is generated from the write control circuit 145, the write command signal WR is input to the latch terminal G of the correction memory section 150, and the correction data temporarily stored in the shift register 110 is stored in the correction memory. Data is written in the correction memory circuit units 151-192 to 151-0 in the unit 150.

  When the write command signal WR is generated in the D section, the output signal of the NOR circuit 145c is “L” level in the write control circuit 145, so that the data output terminal Q of the FF 145a returns to “L” level again. Yes. Next, when the third pulse of the print drive signal STB-N is input, the output signal of the data output terminal Q in the FF 145b rises, and the write command signal W returns to the “L” level again.

  Thereafter, in the E section, the latch signal LOAD becomes “L” level, so that the FFs 145a and 145b are reset, the correction data transfer is completed, and the write control circuit 145 has the same initial state as that shown in the A section. Return to.

(2) Gradation print data transfer in FIG. 11 In the F part in FIG. 11, gradation print data HD-DATA3 to HD-DATA0 consisting of 4 bits of bit3 to bit0 per dot are transferred from the DATAI3 to DATAI0 terminals to the clock CLK. Input synchronously. The clock pulses of the clock CLK are shown as 1, 2,... 192 in FIG.

  First, the gradation print data DOT1-b3, DOT1-b2, DOT1-b1, DOT1-b0 of dot number 1 are input in synchronization with the first clock pulse, and dot number 2 is synchronized with the second clock pulse. Gradation print data DOT2-b3, DOT2-b2, DOT2-b1, and DOT2-b0 are input.

  Similarly, gradation print data DOT192-b3, DOT192-b2, DOT192-b1, and DOT192-b0 with dot number 192 are input in synchronization with the 192nd clock pulse. These gradation print data strings DOT1-b3, DOT1-b2, DOT1-b1, DOT1-b0,... Are input into the shift register 110 configured by the FF units 111-192 to 111-0 in FIG. Shift input.

  When the transfer of the gradation print data strings DOT1-b3, DOT1-b2, DOT1-b1, DOT1-b0,... Is completed, the pulse of the latch signal LOAD is input to the G section and shifted to the shift register 110. The data is latched by the latch circuit units 131-192 to 131-1 in the latch unit 130.

  Next, in the H part, the print drive signal STB-N input to the STB terminal transits to the “L” level. Then, the drive ON / OFF control signal DRV-ON-P is output from the AND circuit 144 and input to the input terminals S of the drivers 181-192 to 181-1 in the driver unit 180. In each driver 181 in FIG. 8, the NAND circuits 303 to 300 are opened, and the PMOSs 323 to 320 are selectively turned on in accordance with the gradation print data DATA3 to DATA0 input from the input terminals D3 to D0. When the gradation print data DATA3 to DATA0 command the LED 210 to emit light, the LED is driven by the drive current output from the output terminal DO, and the LED 210 is lit during the “L” level period of the print drive signal STB-N. When the print drive signal STB-N returns to the “H” level, the light is turned off.

(Drive circuit operation)
FIG. 1 is a circuit diagram showing a main part of a drive circuit in a circuit block BK1 surrounded by a broken line in FIG. 6 in Embodiment 1 of the present invention.

  In FIG. 1, the connection relationship between the control voltage generation circuit 160, the driver 181 and its peripheral circuits in FIG. 6 is extracted for one dot. The resistance switching circuit 164 in the control voltage generation circuit 160 is indicated by an equivalent resistance Rref in a simplified manner. The equivalent resistor Rref has one end connected to the drain of the PMOS 163 and the non-inverting input terminal of the operational amplifier 161, and the other end connected to the ground GND.

  In the other circuits in FIG. 1, only one NAND circuit 300 among the NAND circuits 300 to 303 in FIG. 8 is shown as a representative. Although not shown, the NAND circuit 300 has a power supply terminal connected to the VDD terminal and a ground terminal connected to the ground (= 0V). Also, the PMOSs 310 to 313 and 320 to 323 in FIG. 8 are only representative of one PMOS 310 and one PMOS 320. The gate of the PMOS 310 is connected to the output terminal Y of the multiplexer 171 through the input terminal B. From the output terminal Y, one voltage Vcontrol selected from the voltages V0 to V15 is output. The gate of the PMOS 320 is connected to the output terminal of the NAND circuit 300.

  A feedback control circuit is configured by a circuit including an operational amplifier 161, a PMOS 163, and an equivalent resistor Rref. A drive current Iref flowing through the PMOS 163 and the equivalent resistor Rref is only a value of the reference voltage VREF and the equivalent resistor Rref regardless of the power supply voltage VDD. Determined by.

  When the LED 210 is turned off, the output signal of the NAND circuit 300 becomes “H” level (≈power supply voltage VDD), and the PMOS 320 is turned off. When the LED 210 is lit, the output signal of the NAND circuit 300 becomes “L” level (≈0 V), and the PMOS 320 is turned on. On the other hand, the gate of the PMOS 310 is at the voltage Vcontrol and remains at a fixed voltage regardless of whether the LED 210 is turned on or off, and is independent of whether the LED 210 is driven on or off.

Here, consider the case where the LED 210 is driven to turn on and off.
In order to turn on the LED 210, the print drive signal STB-N input to the STB terminal in FIG. 6 transits from the “H” level to the “L” level. Then, the drive on / off control signal DRV-ON-P output from the AND circuit 144 changes from the “L” level to the “H” level, and the output signal of the NAND circuit 300 in FIG. = Transition from power supply voltage VDD) to “L” level (= 0V).

  As a result, a charging current I1 indicated by a broken line flows through the gate capacitance associated with the gate of the PMOS 320. This charging current I1 flows from the output terminal of the NAND circuit 300 to the ground side through the NAND circuit 300. . That is, the charging current I1 does not flow to the output terminals of the multiplexer 171, the voltage dividing circuit 162, and the operational amplifier 161. As a result, it is possible to solve the problems of the prior art such as the rise time of the LED drive current, its fluctuation, and the resulting variation in the amount of exposure energy.

Next, the operation of the PMOS 310 will be described.
The gate width of the PMOS 310 is W, the gate length is L, the gate-source voltage is Vgs, the threshold voltage is Vt, and the drain current is Id. When this PMOS 310 is operating in the saturation region, the drain current 1d is Indicated.
Id = (β / 2) × (W / L) × (Vgs−Vt) ²
Where β is a constant

As shown by this equation, the LED drive current as the drain current Id can be changed by adjusting the gate-source voltage Vgs of the PMOS 310. This gate-source voltage Vgs is a difference voltage between the power supply potential VDD and the voltage Vcontrol,
Vgs = VDD-Vcontrol
It is. Therefore, when the voltage Vcontrol is slightly increased, the gate-source voltage Vgs is slightly decreased, and the LED driving current as the drain current Id is also slightly decreased. Further, when the voltage Vcontrol is slightly decreased, the gate-source voltage Vgs is slightly increased, and the LED driving current as the drain current Id is slightly increased.

  On the other hand, the multiplexer 171 receives the dot correction data input to the input terminals S3 to S0 and passes between the terminal selected from the input terminals P0 to P15 to which the voltages V0 to V15 are applied and the output terminal Y. Conduct. For example, when the input terminals S3 to S0 become “0111” and the input terminal P7 is selected, a voltage Vcontrol substantially equal to the voltage V7 applied to the input terminal P7 is output from the output terminal Y.

Here, when the dot correction data inputted to the input terminals S3 to S0 is “0000”, the gate-source voltage of the PMOS 310 is Vgs0, and when the dot correction data is “0001”, the gate-source voltage of the PMOS 310 is Vgs1. Similarly, the gate-source voltage of the PMOS 310 when the dot correction data is “1111” is Vgs15. If the drain current of the PMOS 310 in each case is Id0 to Id15, the relationship between the two is given by the following relational expression.
Id0 = (β / 2) × (W / L) × (Vgs0−Vt) ²
Id1 = (β / 2) × (W / L) × (Vgs1-Vt) ²
:
Id15 = (β / 2) × (W / L) × (Vgs15−Vt) ²

As previously mentioned,
Vgs = VDD-Vcontrol
Since the voltage Vcontrol output from the output terminal Y of the multiplexer 171 changes from V0 to V15 according to the dot correction data input to the input terminals S3 to S0, the following equation is obtained.
When S3 to S0 = “0000”, Id0 = (β / 2) × (W / L) × (VDD−V0−Vt) ²
When S3 to S0 = “0001”, Id1 = (β / 2) × (W / L) × (VDD−V1−Vt) ²
:
When S3 to S0 = “1111”, Id15 = (β / 2) × (W / L) × (VDD−V15−Vt) ²

  Thus, it can be seen that the drain current Id of the PMOS 310 can be adjusted in 16 steps according to the dot correction data input to the input terminals S3 to S0.

  Although the above description is about the PMOS 310, as shown in FIG. 8, the PMOSs 310 to 313 are connected to the output terminal DO that outputs the LED driving current, and the gate lengths L of the PMOSs 310 to 313 are equal. The gate width W is set to a ratio of 1: 2: 4: 8, and the drain currents Id of the PMOSs 310 to 313 are merged to become an LED driving current.

Considering the case where the gate width of the PMOS 310 is changed to W0 and the dot correction data input to the input terminals S3 to S0 is “0111”, the drain current Id of each of the PMOS 310 to 313 is
PMOS 313; Id = (β / 2) × (8 × W0 / L) × (Vgs7−Vt) ²
PMOS 312; Id = (β / 2) × (4 × W0 / L) × (Vgs7−Vt) ²
PMOS 311; Id = (β / 2) × (2 × W0 / L) × (Vgs7−Vt) ²
PMOS 310; Id = (β / 2) × (1 × W0 / L) × (Vgs7−Vt) ²
It becomes.

By combining the above relationships, the following equation is obtained for the gradation print data DATA3 to DATA0 input to the input terminals D3 to D0 and the LED drive current output from the output terminal DO in FIG.
D3 to D0 = "0000";
Id = 0
D3 to D0 = "0001";
Id = (β / 2) × (1 × W0 / L) × (Vgs7−Vt) ²
D3 to D0 = "0010";
Id = (β / 2) × (2 × W0 / L) × (Vgs7−Vt) ²
D3 to D0 = "0011";
Id = (β / 2) × (3 × W0 / L) × (Vgs7−Vt) ²
:
D3 to D0 = "1110";
Id = (β / 2) × (14 × W0 / L) × (Vgs7−Vt) ²
D3 to D0 = "1111";
Id = (β / 2) × (15 × W0 / L) × (Vgs7−Vt) ²

  As described above in detail, in the drive circuit according to the first embodiment, the following (a) to (d) are possible.

  (A) In order to correct the amount of LED light, the dot correction data input to the input terminals S3 to S0 of the multiplexer 171 is changed to change the voltage Vcontrol output from the output terminal Y to V0 to V15. The current value can be adjusted in 16 steps.

  (B) By changing the gradation print data DATA3 to DATA0 input to the input terminals D3 to D0 for gradation driving, the above-described substantial gate width W is set to 0, W0, 2 × W0,. , 15 × W0 and 16 steps, and the drive current value of the LED 210 can be adjusted to 16 steps.

  (C) As is clear from the above description, the drive current adjustment (that is, dot correction of the LED light amount) performed by changing the gate-source voltage Vgs of the PMOS 310 to 313 and the total gate width of the PMOS 310 to 313 are changed. This can be done independently of the drive current adjustment (ie, gradation drive).

  (D) As shown in FIG. 9, by changing the equivalent resistance value of the resistance switching circuit 164 in 16 steps, the drain current Iref can be changed in 16 steps, and the drive current adjustment (that is, the LED light quantity chip). Correction) can also be performed independently of the adjustment function.

  For this reason, after the dot correction of the LED light amount is performed in the state of the predetermined gradation print data value, even if the gradation print data value is different from that, the dot correction state of the LED light amount does not change, and another dot There is an effect that it is not necessary to prepare correction data and store it again.

FIG. 12 is a waveform diagram schematically showing the drive current waveform of FIG.
In the waveform diagram of FIG. 12, the print drive signal STB-N is a negative logic waveform commanding the drive of the LED 210, and the pulse width is Tw. Io0 is a waveform indicating the LED drive current of the comparative example. Io1 is a waveform indicating the LED drive current of the first embodiment.

  In the LED drive current Io0 of the comparative example, the waveforms of the rise time Tr and the fall time Tf are transitioned from the print drive signal STB-N, and the substantial pulse width is Tw0. On the other hand, in the LED drive current Io1 of the first embodiment, the waveforms of the rise time Tr and the fall time Tf are shifted from the print drive signal STB-N. The rise time Tr and the fall time Tf are changed. Is shorter than the comparative example, the substantial pulse width Tw1 is larger than the pulse width Tw0 of the comparative example.

  The charge / discharge current I1 of the gate capacitance of the PMOS 320 that flows in association with the on / off operation of the LED does not flow through the multiplexer 171, and is thus independent of the on-resistance. On the other hand, the ground terminal of the NAND circuit 300 is 0V.

  As a typical design example, when the power supply voltage VDD = 5V and the gate-source voltage Vgs = 2V of the PMOS 310, the voltage Vcontrol = 3V, and the operating voltage of the NAND circuit 300 of the first embodiment is the operation of the comparative example. The voltage is larger than the voltage (for example, 2V) and 5V, and sufficient driving ability can be exhibited. As a result, the rise time Tr and the fall time Tf of the drive current Io1 of the first embodiment in FIG. 12 can be made sufficiently smaller than those of the comparative example, and a high-speed switching operation can be performed.

In addition, in the comparative example, the waveform of the LED drive current Io0 is
Rise time Tr> Fall time Tf
Reflecting this, the pulse width Tw0 of the LED drive current waveform is
Tw0 = Tw− (Tr−Tf)
As a result, the substantial pulse width Tw is reduced, which causes the exposure energy amount to fluctuate. On the other hand, in the drive circuit of the first embodiment, the waveform of the LED drive current Io1 is
Tr = Tf
And the pulse width Twl is also
Twl ≒ Tw
Thus, driving according to the command value of the print control unit 40 in FIG. 4 can be performed. Furthermore, since the rise time Tr and the fall time Tf of the waveform of the LED drive current Io1 are sufficiently small compared to the comparative example, even if the rise time Tr and the fall time Tf vary due to the semiconductor manufacturing process, The influence on the pulse width Twl is slight. For this reason, in the first embodiment, as in the comparative example, the rise time Tr of the LED drive current Io0 varies and the substantial drive current pulse width Tw0 changes, resulting in uneven print density. Can be solved.

(Effect of Example 1)
As described above, according to the drive circuit and the print head 13 of the first embodiment, the following effects (1) to (3) are obtained.

  (1) In the drive circuit of FIG. 1, a PMOS 310 (corresponding to the PMOS 310 to 313 in FIG. 8) and a PMOS 320 (corresponding to the PMOS 320 to 323 in FIG. 8) are connected in series and output from the multiplexer 171 to the gate of the PMOS 310. The dot correction of the LED 210 is performed by applying the voltage Vcontrol and adjusting the gate-source voltage Vgs of the PMOS 310. Therefore, the charge / discharge current I1 of the gate capacitance generated in the PMOS 320 when the LED drive is turned on / off does not flow through the multiplexer 171, and a problem caused by the on-resistance in the multiplexer 171 (that is, the LED drive current Io0). The problem that the rise time Tr of the waveform becomes large and high-speed operation cannot be performed) can be solved, and the rise time Tr and the fall time Tf of the waveform of the LED drive current Io1 can be made sufficiently small, so Switching operation can be expected.

  (2) In (1), the rise time Tr and the fall time Tf of the waveform of the LED drive current Io1 can be made substantially equal, and the LED 210 is driven with a time width according to the command value of the print control unit 40. be able to.

  (3) In the above (1), the rise time Tr and the fall time Tf of the waveform of the LED drive current Io1 are sufficiently small, so that the rise time Tr and the fall time Tf fluctuate due to the semiconductor manufacturing process. However, the influence on the actual driving time is slight, and the rise time Tr of the LED driving current Io0 varies and the substantial driving current pulse width Tw changes as in the comparative example, resulting in uneven printing density. This problem can be solved.

Furthermore, according to the image forming apparatus 1 of the first embodiment, the following effect (4) is obtained.
(4) Since the optical print head 13 is used in the image forming apparatus 1 of the first embodiment, a high-quality image forming apparatus (printer, copier, facsimile machine, excellent in space efficiency and light extraction efficiency) Multi-function devices, etc.). That is, the use of the optical print head 13 is effective not only in the above-described full-color image forming apparatus 1 but also in a monochrome or multi-color image forming apparatus, but in particular, a large number of optical print heads 13 serving as exposure apparatuses. Greater effects can be obtained in the required full-color image forming apparatus.

  The second embodiment of the present invention has the same configuration as the image forming apparatus 1 of FIG. 2 showing the first embodiment, the optical print head 13 of FIG. 3, and the printer control circuit of FIG. In place of the driver IC 100 in FIG. 5, a driver IC 100A having a different configuration is provided.

(Overall configuration of driver IC)
FIG. 13 is a block diagram illustrating a detailed circuit configuration of the driver IC 100A according to the second embodiment of the present invention. Elements common to those in the driver IC 100 of FIG. 6 illustrating the first embodiment are denoted by common reference numerals. ing.

  In the driver IC 100A according to the second embodiment, instead of the control voltage generation circuit 160 according to the first embodiment, a control voltage generation circuit (ADJ) 330 and a potential generation circuit (for example, a bias circuit (VB)) 340 having different configurations are used. Furthermore, instead of the driver unit 180 of the first embodiment, a driver unit 350 having a different configuration is provided. The input side of the control voltage generation circuit 330 is connected to the output side of the correction memory circuit unit 151-0, and the driver unit 350 is connected to the output side of the control voltage generation circuit 330. Instead of the control voltage generation circuit 160 of the first embodiment, the output side of the bias circuit 340 is connected to the input side of the multiplexer unit 170.

  The control voltage generation circuit 330 includes input terminals S3 to S0 for inputting chip correction data output from the correction memory circuit unit 151-0, a VREF terminal for inputting a reference voltage VREF, and a control voltage for LED driving. And a control voltage for LED driving based on a predetermined reference voltage VREF input from the VREF terminal and chip correction data input from the input terminals S3 to S0. This is a circuit generated from the output terminal V and applied to the driver unit 350. As in the first embodiment, the reference voltage VREF is generated by a regulator (not shown) or the like, and is maintained at a predetermined voltage value even in a situation where the power supply voltage VDD drops momentarily as in the case of driving all the LEDs on. .

  The bias circuit 340 has a plurality of (for example, 16) V15 to V0 terminals, outputs 16 different voltages V15 to V0 from these V15 to V0 terminals, and a multiplexer (MUX) in the multiplexer unit 170. 171 to 192 to 171-1.

  The driver unit 350 is turned on / off by a drive on / off control signal DRV-ON-P output from the control unit 140, and the gradation print data DATA 3 to DATA 0 output from the latch unit 130 and the multiplexer unit 170. This is a circuit that outputs an LED drive current for driving the light emitting element array 200 based on the output control voltage and the control voltage output from the control voltage generation circuit 330. ) Drivers (DRV) 351 (351-192 to 351-1). Each driver 351 has an input terminal S for inputting a drive on / off control signal DRV-ON-P output from the control unit 140, and an input terminal V for inputting a control voltage output from the control voltage generation circuit 330. An input terminal B for inputting a control voltage output from the multiplexer unit 170, four input terminals D3 to D0 for inputting gradation print data DATA3 to DATA0, and an LED drive current to an output terminal D0 (= And an output terminal DO for outputting to DO192 to DO1).

A circuit block BK1A surrounded by a broken line in FIG. 13 includes an FF unit 111-192, a latch circuit unit 131-192, a correction memory circuit unit 151-192, a multiplexer 171-192, and a driver 351-192. This is a drive circuit for one dot for driving the individual LEDs 210. A circuit block BK2A surrounded by a broken line is configured by an FF unit 111-0, a correction memory circuit unit 151-0, and a control voltage generation circuit 330, and supplies a control voltage to be applied to the entire driver unit 350. Circuit.
Other configurations are the same as those of the first embodiment.

(Driver in Fig. 13)
FIG. 14 is a circuit diagram showing a configuration of driver 351 in FIG.

  The driver 351 according to the second embodiment includes a plurality of (for example, four) 2-input NAND circuits 400 to 403 connected to the input terminals S and D3 to D0 and a plurality of (for example, four) connected to the output side. ) Of the first conductivity type switch elements (for example, PMOS) 410 to 410.

  The first input terminals of the NAND circuits 403 to 400 are commonly connected to the input terminal S of the drive on / off control signal DRV-ON-P, and the second input terminals are input terminals of the gradation print data DATA3 to DATA0. Connected to D3 to D0, respectively. The power supply terminals of the NAND circuits 403 to 400 are connected to the VDD terminal, and the ground terminal is connected to the input terminal V of the voltage Vcontrol.

  The sources of the PMOSs 413 to 410 are commonly connected to the VDD terminal, the drain is commonly connected to the output terminal DO of the LED drive current, and the gates are connected to the output terminals of the NAND circuits 403 to 400, respectively. . The substrate terminals of the PMOSs 413 to 410 are commonly connected to the control voltage input terminal B.

  The driver 181 according to the first embodiment illustrated in FIG. 8 is configured to apply a control voltage for light amount correction between the gates and sources of the PMOSs 313 to 310. In contrast, the driver 351 according to the second embodiment is configured to apply a control voltage for light amount correction between the source and substrate terminals of the PMOSs 413 to 410. Therefore, in the driver 351 of the second embodiment, the potential difference between the VDD terminal and the input terminal B is equal to the source-substrate terminal voltage Vsb of the PMOSs 413 to 410, and by changing this voltage Vsb, The drain current can be adjusted.

The driver 351 configured in this manner operates as follows.
For example, it is assumed that the gradation print data DATA3 input to the input terminal D3 is at “H” level. When the drive ON / OFF control signal DRV-ON-P input to the input terminal S becomes “H” level and the LED drive ON is commanded, the output signal of the NAND circuit 403 becomes “L” level. As a result, the PMOS 413 is turned on and outputs this drain current from the output terminal DO. Similarly for the other input terminals D2 to D0, the PMOSs 412 to 410 are turned on in accordance with the gradation print data DATA2 to DATA0 input to the input terminals D2 to D0, and the drain currents from these PMOSs 412 to 410 are supplied. It can output from the output terminal DO.

  That is, the PMOSs 413 to 410 are selectively driven according to the gradation print data DATA3 to DATA0 input to the input terminals D3 to D0, and the LED drive current obtained by adding the drain currents of the PMOSs 413 to 410 is output to the output terminal DO. Is supplied to the LED 210 in FIG. As a result, for example, by setting the gate width of the PMOSs 413 to 410 to a ratio of 8: 4: 2: 1, the output from the output terminal DO according to the gradation print data DATA3 to DATA0 input from the input terminals D3 to D0. The LED driving current can be changed in 16 steps.

(Control voltage generating circuit in FIG. 13)
FIG. 15 is a circuit diagram showing a configuration of control voltage generating circuit 330 in FIG.

  The control voltage generation circuit 330 is provided for each driver IC 100A, and includes an operational amplifier 331, a PMOS 332, and a resistance switching circuit 333.

  The operational amplifier 331 has an inverting input terminal to which the reference voltage VREF input from the VREF terminal is applied, a non-inverting input terminal, and an output terminal. The non-inverting input terminal includes the drain of the PMOS 332 and the resistance switching circuit 333. To the R terminal. The output terminal of the operational amplifier 331 is connected to the gate of the PMOS 332 and the output terminal V. The source and substrate terminal of the PMOS 332 are connected to the VDD terminal. The PMOS 332 has the same gate length as the PMOSs 410 to 413 in FIG.

  The resistance switching circuit 333 has four S3 to S0 terminals connected to the chip correction data input terminals S3 to S0 and an R terminal, and four logics in the chip correction data input from the S3 to S0 terminals. According to 16 combinations of signal levels, an internal resistance (not shown) is switched to 16 levels, and the resistance value between the terminal R and the ground can be adjusted to 16 levels.

  A feedback control circuit is configured by a circuit including the operational amplifier 331, the resistance switching circuit 333, and the PMOS 332, and the voltage at the non-inverting input terminal of the operational amplifier 331 is controlled to be substantially equal to the reference voltage VREF. Therefore, the drain current Iref of the PMOS 332 is determined from the resistance value between the R terminal of the resistance switching circuit 333 and the ground (for example, R0 to R15) and the reference voltage VREF input to the operational amplifier 331.

For example, when the logical value of the chip correction data input to the input terminals S3 to S0 is “1111” and the correction state is commanded to be maximum, the resistance value R15 between the R terminal of the resistance switching circuit 333 and the ground. From the above, the drain current Iref of the PMOS 332 is
Iref = VREF / R15
It becomes.

When the logical value of the chip correction data input to the input terminals S3 to S0 is “0111” and the center of the correction state is commanded, the resistance value R7 between the R terminal of the resistance switching circuit 333 and the ground is determined. The drain current Iref of the PMOS 332 is
Iref = VREF / R7
It becomes.

Further, when the logical value of the chip correction data input to the input terminals S3 to S0 is “0000” and the minimum correction state is instructed, the resistance value between the R terminal of the resistance switching circuit 333 and the ground. From R0, the drain current Iref of the PMOS 332 is
Iref = VREF / R0
It becomes.

  As described above, the PMOSs 410 to 413 and the PMOS 332 in FIG. 14 are configured to have the same gate length, and the PMOSs 410 to 413 and 332 are controlled to operate in the saturation region. Since the gate-source voltages are set equal and the PMOSs 410 to 413 and 332 are in a current mirror relationship, when the PMOSs 410 to 413 are turned on, each of the PMOSs 410 to 413 has a drain current proportional to Iref. Arise.

  As a result, the drain current Iref can be adjusted to 16 levels according to the logic value state of the chip correction data applied to the input terminals S3 to S0, and the drain currents of the PMOSs 410 to 413 in FIG. 14 are also adjusted to 16 levels. Can be possible.

  The above is true when the source potentials of the PMOSs 410 to 413 in FIG. 14 are equal to the substrate terminal potential, that is, when the potential of the input terminal B is equal to the power supply voltage VDD. As is well known in the theory of electronic properties, when the potential of the input terminal B in FIG. 14 is slightly higher than the power supply voltage VDD, the PMOSs 410 to 413 have a substrate bias effect, and the threshold voltage is Slightly increases. Thereby, by adjusting the voltage of the input terminal B, the ratio between the drain current of the PMOSs 410 to 413 and the 1ref can be adjusted to a predetermined value.

(Bias circuit in FIG. 13)
FIG. 16 is a circuit diagram showing a configuration of bias circuit 340 in FIG.

  The bias circuit 340 includes a voltage dividing circuit 341. The voltage dividing circuit 341 includes a plurality of resistors 341-0 to 341-15, which are connected in series between the VCC terminal and the VDD terminal. Connection portions of the resistors 341-0 to 341-15 are connected to the V0 to V15 terminals, respectively, and are connected to the input terminals P0 to P15 in each multiplexer 171 in FIG.

  The purpose of providing the bias circuit 340 of the second embodiment is to give a substrate bias effect to the PMOSs 410 to 413 in FIG. 14. The voltages at the V0 to V15 terminals are connected to the PMOSs 410 to 413 via the multiplexer 171. Applied to the substrate terminal. Therefore, as a typical design example, when the power supply voltage VDD of the VDD terminal is set to 3.3V, the power supply voltage VCC of the VCC terminal is set to 5V higher than the power supply voltage VDD, and the 5V and 3.3V are divided. By dividing the voltage by the voltage circuit 341, the voltage of the V0 to V15 terminals can be generated.

  Further, as described above, in the PMOSs 410 to 413 in FIG. 14, the threshold voltage can be increased by applying the substrate bias effect by setting the substrate terminal to a higher potential than the source. At this time, since the substrate bias effect is not generated in the PMOS 332 in FIG. 15, the gate-source voltage Vgs of the PMOSs 410 to 413 in FIG. 14 is not changed. For this reason, as a result of the increase of the threshold voltages of the PMOSs 410 to 413, the drain current of the PMOSs 410 to 413 decreases.

  Returning to the description of FIG. 16 again, when the voltage of the V15 terminal (= power supply voltage VDD) is selected and applied to the input terminal B of the driver 351 of FIG. 14, no substrate bias effect is produced in the PMOSs 410 to 413. Therefore, there is no change in the drain currents of the PMOSs 410 to 413. Next, when the voltage at the V14 terminal in FIG. 16 is selected and applied to the input terminal B in FIG. 14, the substrate terminal voltages of the PMOSs 410 to 413 are slightly higher than their source voltages, and the threshold voltage is slightly lower. As a result, the drain current of the PMOSs 410 to 413 is slightly reduced.

  Similarly, when the voltage at the V0 terminal in FIG. 16 is selected and applied to the input terminal B in FIG. 14, the voltage at the substrate terminal of the PMOSs 410 to 413 becomes the highest than its source voltage, and the threshold voltage increases. And the drain current of the PMOSs 410 to 413 can be minimized.

(PMOS characteristics)
FIG. 17 is a characteristic diagram of the PMOS in the PMOSs 410 to 413 and the like in FIG. 14 and shows the relationship between the gate voltage and the drain current.

  In FIG. 17, the horizontal axis represents the gate-source voltage Vgs, and the vertical axis represents the square root of the drain current as SQRT (Id). In FIG. 17, the gate voltage and the drain current are entered as positive values in order to simplify the description.

  The driver 351 of FIG. 14 of the second embodiment is configured to apply a control voltage for light amount correction between the source and substrate terminals of the PMOSs 413 to 410, and the characteristics of the PMOSs 410 to 413 will be described. .

  In FIG. 17, for example, the curve a changes substantially linearly with an increase in the gate-source voltage Vgs, and the intersection of the tangent to the curve a and the horizontal axis is the PMOS threshold voltage Vt. .

  A curve a in FIG. 17 shows a case where there is no potential difference between the source and substrate terminal of the PMOS, which is equal to the characteristics of a normal transistor, and the signal “1111” is applied to the input terminals S3 to S0 of the multiplexer 171. This corresponds to a state where the power supply voltage VDD is applied to the substrate terminal of the PMOS.

  As another case, consider a case where the signal “0111” is applied to the input terminals S3 to S0 of the multiplexer 171 and the voltage of the V7 terminal is applied to the PMOS substrate terminal.

  As shown in FIG. 16, the voltage at the V7 terminal is higher than the power supply voltage VDD, and the substrate terminal voltage of the PMOS is higher than the source voltage VDD. In this case, as shown by the curve b in FIG. 17, the characteristics shift in the direction in which the threshold voltage Vt increases. Such characteristic variation is a phenomenon known as a substrate bias effect.

  When the substrate terminal voltage of the PMOS is set higher than the source voltage VDD, the state of the curve c in FIG. 17 is obtained. This state corresponds to, for example, a state where the signal “1111” is applied to the input terminals S3 to S0 of the multiplexer 171 and the voltage of the V0 terminal is applied to the PMOS substrate terminal. As shown in FIG. 16, the voltage at the V0 terminal is higher than the voltage at the V7 terminal, and the substrate terminal voltage of the PMOS is the highest than the source voltage VDD.

(Drive circuit operation)
FIG. 18 is a circuit diagram showing the main part of the drive circuit in the circuit block BK1A surrounded by the broken line in FIG. 13 in the second embodiment of the present invention.

  In FIG. 18, the connection relationship between the control voltage generation circuit 330, the driver 351, and the peripheral circuits in FIG. 13 is extracted for one dot. The resistance switching circuit 333 in the control voltage generation circuit 330 is indicated by an equivalent resistance Rref in a simplified manner. One end of the equivalent resistor Rref is connected to the drain of the PMOS 332 and the non-inverting input terminal of the operational amplifier 331, and the other end is connected to the ground GND.

  In the other circuits in FIG. 18, only one NAND circuit 400 among the NAND circuits 400 to 403 in FIG. 14 is shown as a representative. In the NAND circuit 400, the power supply terminal is connected to the VDD terminal, and the ground terminal is connected to the input terminal V to which the voltage Vcontrol is input. As for the PMOSs 410 to 413 in FIG. 14, only one PMOS 410 is shown as a representative. The substrate terminal of the PMOS 410 is connected to the output terminal Y of the multiplexer 171 through the input terminal B. From the output terminal Y, one voltage selected from the voltages V0 to V15 is output. The gate of the PMOS 410 is connected to the output terminal of the NAND circuit 400.

  A feedback control circuit is configured by a circuit including an operational amplifier 331, a PMOS 332, and an equivalent resistor Rref. A current Iref flowing through the PMOS 332 and the equivalent resistor Rref is determined only by the value of the reference voltage VREF and the equivalent resistor Rref regardless of the power supply voltage VDD. It is determined.

  As described above, the voltage V15 applied to the input terminal P15 of the multiplexer 171 is the power supply voltage VDD as shown in FIG. 16, which is equal to the source voltage VDD of the PMOS 410, and is 3 in a typical design example. .3V. The voltage V0 applied to the input terminal P0 of the multiplexer 171 is the power supply voltage VCC as shown in FIG. 16, which is a voltage higher than the source voltage VDD of the PMOS 410. In a typical design example, 5V.

  For example, consider the gate voltage of the PMOS 410 when the LED 210 is driven on and off. When the LED 210 is turned off, the output signal of the NAND circuit 400 is at the “H” level, the voltage is substantially equal to the power supply voltage VDD, and the PMOS 410 is off. When the LED 210 is lit, the output signal of the NAND circuit 400 becomes “L” level and the voltage becomes Vcontrol.

Here, a transition process for turning on the driving of the LED 210 is considered.
In order to turn on the LED 210, the print drive signal STB-N in FIG. 13 transits from the “H” level to the “L” level. Then, the drive on / off control signal DRV-ON-P output from the AND circuit 144 changes from the “L” level to the “H” level, and the output signal of the NAND circuit 400 in FIG. 18 changes from the “H” level. Transition to the “L” level, that is, from the power supply voltage VDD to the voltage Vcontrol. As a result, a charging current I1 indicated by a broken line flows through the gate capacitance associated with the gate of the PMOS 410. This charging current I1 is output from the output terminal of the NAND circuit 400 through the NAND circuit 400 and output from the operational amplifier 331. Flows to the terminal side. That is, the charging current I1 does not flow to the multiplexer 171 side.

A transition process for turning off the driving of the LED 210 will be considered.
In order to turn off the LED 210, the print drive signal STB-N in FIG. 13 transits from the “L” level to the “H” level. Then, the drive on / off control signal DRV-ON-P output from the AND circuit 144 changes from the “H” level to the “L” level, and the output signal of the NAND circuit 400 in FIG. 18 changes from the “L” level. Transition to the “H” level, that is, from the voltage Vcontrol to the power supply voltage VDD. At this time, the charging current I1 for the gate capacitance of the PMOS 410 flows from the output terminal of the NAND circuit 400 to the gate side of the PMOS 410 and does not flow to the multiplexer 171 side.

  As described above, since the charge / discharge current I1 for the gate capacitance of the PMOS 410 is mainly determined only by the NAND circuit 400, the charge / discharge time can be easily set to a desired value. As a result, it is possible to solve the problem of an increase in the rise time of the LED drive current, a variation thereof, and a variation in the exposure energy amount due to the increase in the LED drive current, which is a problem in the prior art.

Next, the operation of the PMOS 410 will be described.
When the gate width of the PMOS 410 is W, the gate length is L, the gate-source voltage is Vgs, the threshold voltage is Vt, and the drain current is 1d, when the PMOS 410 is operating in the saturation region, the drain current 1d is Indicated by
Id = (β / 2) × (W / L) × (Vgs−Vt) ²
However, β: constant As shown in this equation, the drain current of the PMOS 410, that is, the driving current of the LED 210 can be changed by adjusting the gate-source voltage Vgs of the PMOS 410. The gate-source voltage Vgs is a difference voltage between the power supply voltage VDD and the voltage Vcontrol,
Vgs = VDD-Vcontrol
It is. Therefore, when the voltage Vcontrol is slightly increased, the gate-source voltage Vgs is slightly decreased, and the drain current of the PMOS 410, that is, the driving current of the LED 210 is also slightly decreased. On the other hand, when the voltage Vcontrol is slightly decreased, the gate-source voltage Vgs is slightly increased, and the drain current of the PMOS 410, that is, the driving current of the LED 210 is slightly increased.

  On the other hand, the multiplexer 171 receives the dot correction data input to the input terminals S3 to S0 and conducts between the input terminal selected from the input terminals P0 to P15 and the output terminal Y.

  For example, in the multiplexer 171, when the dot correction data input to the input terminals S3 to S0 is “1111” and the input terminal P15 is selected, a voltage substantially equal to the voltage V15 applied to the input terminal P15. That is, the power supply voltage VDD is output from the output terminal Y, and the substrate terminal of the PMOS 410 is substantially equal to the source voltage.

  Here, when the dot correction data input to the input terminals S3 to S0 is “0000”, the voltage between the source and substrate terminals of the PMOS 410 is Vsb0, and between the source and substrate terminals when the dot correction data is “0001”. Similarly, the voltage is Vsb1, and similarly, the source-substrate terminal voltage when the dot correction data is “1111” is Vsb15.

  As described above, applying a voltage between the source and substrate terminals of the PMOS 410 causes a substrate bias effect, and the threshold voltage Vt of the PMOS 410 increases.

When the dot correction data input to the input terminals S3 to S0 of the multiplexer 171 is 0 to 15, the threshold voltage of the PMOS 410 is Vt0 to Vt15, and the drain current at that time is Id0 to Id15. It is given by the formula.
S3 to S0 = "0000";
Id0 = (β / 2) × (W / L) × (Vgs−Vt0) ²
S3 to S0 = "0001";
Id1 = (β / 2) × (W / L) × (Vgs−Vt1) ²
:
S3 to S0 = "1111";
Id15 = (β / 2) × (W / L) × (Vgs−Vt15) ²

  As described above, Vgs = VDD−Vcontrol, and the threshold voltage Vt changes according to the dot correction data input to the input terminals S3 to S0, so that the drain current of the PMOS 410 is changed according to the dot correction data. It can be seen that it can be adjusted to 16 levels.

  Although the above is for the PMOS 410, as shown in FIG. 14, the PMOSs 410 to 413 are connected to the LED drive output terminal DO, and the gate lengths L of the PMOSs 410 to 413 are set equal to each other. The width W is set to a ratio of 1: 2: 4: 8, and the drain currents of the PM0S 410 to 413 are merged to become an LED driving current.

Considering the case where the gate width of the PMOS 410 is changed to W0 and the dot correction data input to the input terminals S3 to S0 is “0111”, the drain current of each of the PMOSs 410 to 413 is
PMOS 413; Id = (β / 2) × (8 × W0 / L) × (Vgs−Vt7) ²
PMOS 412; Id = (β / 2) × (4 × W0 / L) × (Vgs−Vt7) ²
PMOS 411; Id = (β / 2) × (2 × W0 / L) × (Vgs−Vt7) ²
PMOS 410; Id = (β / 2) × (1 × W0 / L) × (Vgs−Vt7) ²
It becomes.

By combining the above relationships, the following equations are obtained for the gradation print data DATA3 to DATA0 input to the input terminals D3 to D0 and the drive current output from the output terminal DO in FIG.
D3 to D0 = "0000";
Id = 0
D3 to D0 = "0001";
Id = (β / 2) × (1 × W0 / L) × (Vgs−Vt7) ²
D3 to D0 = "0010";
Id = (β / 2) × (2 × W0 / L) × (Vgs−Vt7) ²
D3 to D0 = "0011";
Id = (β / 2) × (3 × W0 / L) × (Vgs−Vt7) ²
:
D3 to D0 = "1110";
Id = (β / 2) × (14 × W0 / L) × (Vgs−Vt7) ²
D3 to D0 = "1111";
Id = (β / 2) × (15 × W0 / L) × (Vgs−Vt7) ²

  As described in detail above, the following (a) to (d) are possible in the drive circuit of the second embodiment.

  (A) By changing the dot correction data input to the input terminals S3 to S of the multiplexer 171 in order to correct the LED light amount, the substrate terminal voltages of the PMOSs 410 to 413 are changed to V0 to V15, and the LED 210 The drive current value can be adjusted in 16 steps.

  (B) By changing the gradation print data DATA3 to DATA0 for gradation driving, the substantial gate width W of the PMOSs 410 to 413 is set to 16 levels of 0, W0, 2 × W0,..., 15 × W0. The driving current value of the LED 210 can be adjusted to 16 levels.

  (C) Driving current adjustment performed by changing the source-substrate terminal voltage Vsb of the PMOSs 410 to 413 (LED light amount dot correction) and driving current adjustment performed by changing the total gate width of the PMOSs 410 to 413 ( (Gradation driving) can be performed independently.

  (D) The reference current 1ref can be changed by changing the equivalent resistance value of the resistance switching circuit 333 of FIG. 15 in 16 steps. That is, by changing the gate-source voltage Vgs of the PMOSs 410 to 413 in 16 steps, the drive current adjustment (chip correction of the LED light amount) can also be performed independently of the adjustment function.

  For this reason, after the dot correction of the LED light amount is performed in the state of the predetermined gradation print data value, even if the gradation print data value is different from that, the dot correction state of the LED light amount does not change, and another dot There is an effect that it is not necessary to prepare correction data and store it again.

  FIG. 19 is a waveform diagram schematically showing the drive current waveform of FIG. 18. Elements common to those in FIG. 12 showing the first embodiment are denoted by common reference numerals.

  In the waveform diagram of FIG. 19, the print drive signal STB-N is a negative logic waveform instructing driving of the LED 210, and the pulse width is Tw. Io0 is a waveform indicating the LED drive current of the comparative example. Io2 is a waveform indicating the LED drive current of the second embodiment.

  In the LED drive current Io2 of the second embodiment, the waveforms of the rise time Tr and the fall time Tf transition from the print drive signal STB-N. The rise time Tr and the fall time Tf are from the comparative example. Therefore, the substantial pulse width Tw2 is larger than the pulse width Tw0 of the comparative example.

  Since the charge / discharge current I1 of the gate of the PMOS 410 that flows along with the on / off of the LED drive does not flow through the multiplexer 171, it does not depend on the on-resistance. Thereby, the problem of the time constant due to the discharge current flowing through the multiplexer 171 is solved. As a result, the rise time Tr and fall time Tf of the LED drive current Io2 in FIG. 19 can be made sufficiently small, and a high-speed switching operation can be expected.

In addition, in the comparative example,
Tr> Tf
The pulse width Tw0 of the LED drive current waveform reflects the above,
Tw0 = Tw− (Tr−Tf)
Thus, the substantial pulse width is reduced, which causes the amount of exposure energy to fluctuate. In the configuration of the second embodiment,
Tr ≒ Tf
The pulse width Tw2 of the LED drive current waveform is also
Tw2 ≒ Tw
And drive according to the command value of the print control unit 40.

  Furthermore, since the rise time Tr and the fall time Tf are sufficiently small, even if the rise time Tr and the fall time Tf vary due to the semiconductor manufacturing process, the influence on the pulse width Tw2 is slight, and LED driving It is possible to solve the problem that unevenness in print density occurs due to fluctuations in the rise time of the current and changes in the substantial drive current pulse width.

(Effect of Example 2)
As described above, according to the driving circuit and the print head 13 of the second embodiment, there are the following effects (1) to (3).

  (1) In the drive circuit of FIG. 18, the output voltage of the multiplexer 171 is applied to the substrate terminal of the PMOS 410 (corresponding to the PMOSs 410 to 413 in FIG. 14), and the source-substrate terminal voltage of the PMOS 410 for each output terminal DO. By changing Vsb, the threshold voltage of the PMOS 410 is changed by the substrate bias effect, and the dot correction of the LED 210 is performed by adjusting the drive current. Therefore, in substantially the same manner as in the first embodiment, the charge / discharge current I1 of the gate capacitance generated in the PMOS 410 as the LED drive is turned on / off does not flow through the manoplexer 171 and is caused by the on-resistance in the multiplexer 171. The problem (that is, the problem that the rise time Tr of the waveform of the LED drive current Io0 becomes large and high speed operation cannot be performed) can be solved, and the rise time Tr and the fall time Tf of the waveform of the LED drive current Io2 are made sufficiently small. And a high-speed switching operation can be expected.

  (2) In the above (1), the rise time Tr and the fall time Tf of the waveform of the LED drive current Io2 can be made substantially equal, and the LED 210 is driven with a time width according to the command value of the print control unit 40. be able to.

  (3) In the above (1), the rise time Tr and the fall time Tf of the waveform of the LED drive current Io2 are sufficiently small, and it is assumed that the rise time Tr and the fall time Tf fluctuate due to the semiconductor manufacturing process. However, the influence on the substantial drive time is slight, and the rise time Tr of the LED drive current IoO varies as in the comparative example, and the substantial drive current pulse width Tw changes, resulting in uneven print density. This problem can be solved.

  Furthermore, according to the image forming apparatus 1 of the second embodiment, there is an effect similar to the effect (4) of the first embodiment.

FIG. 20 is a schematic configuration diagram showing a display device in Embodiment 3 of the present invention.
The display device 500 is, for example, a device configured using a plurality of driver ICs 100 (= 100-1, 100-2,...) And a plurality of LEDs 210 of the first embodiment shown in FIG. 510. The display panel 510 includes a plurality of data lines 511 and a plurality of scanning lines 512 arranged so as to intersect the data lines 511, and is driven at intersections between the data lines 511 and the scanning lines 512. Display elements (for example, LEDs) 210 as elements are connected to each other and arranged in a matrix. A driver IC 100 (= 100-1, 100-2,...) Is connected to the plurality of data lines 511. Further, a scanning unit 520 is connected to the plurality of scanning lines 512.

  In this display device 500, an LED drive current is supplied from the driver IC 100 to the data line 511, and a plurality of scanning lines 512 are sequentially connected to the ground by the scanning unit 520, thereby causing the LEDs 210 at predetermined locations to emit light and display an image. be able to.

  According to the display device 500 of the third embodiment, since the LED 210 is driven using the driver IC 100 of the first embodiment, there are almost the same effects as the first embodiment. If the driver IC 100A of the second embodiment is used, the same effect as that of the second embodiment is obtained.

(Modification)
The present invention is not limited to the above-described embodiments, and various usage forms and modifications are possible. For example, the following forms (a) to (d) are used as the usage form and the modified examples.

  (A) In the embodiment, the case where the LED 210 is applied to a light emitting element used as a light source has been described. However, the present invention is not limited to this, and voltage application control to other driven elements (for example, organic EL elements). It is also applicable when performing the above. For example, it can be used in a printer including an organic EL head composed of an organic EL element array, a display device including a display panel composed of an organic EL array, and the like.

  (B) The present invention is not limited to a driven element such as the LED 210 having a two-terminal structure, but a four-terminal thyristor SCS having first and second gates in addition to a light-emitting thyristor having a three-terminal structure. The present invention is also applicable when driving a (Silicon Semiconductor controlled Switch).

  (C) As will be apparent from consideration of the gist and technical idea of the present invention, the present invention is not limited to a driver of a driven element array composed of a continuous arrangement of the same components, and a plurality or a single drive The present invention can be widely applied to an arbitrarily shaped IC chip having a terminal output, a unit device including these, and the like.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 13 Optical print head 100,100A, 100-1,100-2 Driver IC
DESCRIPTION OF SYMBOLS 110 Shift register 120 Selector 130 Latch part 140 Control part 150 Correction | amendment memory part 160,330 Control voltage generation circuit 170 Multiplexer part 180 Driver part 181,181-1 -181-192 Driver 200,200-1,200-2 Light emitting element array 210, 210-1 to 210-192 LED
300 to 303, 400 to 403 NAND circuit 310 to 313, 320 to 323, 410 to 413 PMOS
340 Bias circuit 500 Display device 510 Display panel 520 Scan unit

Claims (6)

In a drive circuit for driving a driven element,
A potential generating circuit for generating a plurality of different potentials;
A multiplexer that selects any one of the plurality of potentials generated by the potential generation circuit;
A control voltage generation circuit for generating a control voltage based on a reference voltage;
A gate circuit that inputs the control voltage and outputs a signal having a value substantially equal to either the control voltage or the power supply voltage based on gradation data;
Based on a first terminal connected to a power supply for supplying the power supply voltage, a second terminal for supplying a drive current supplied from the power supply through the first terminal to the driven element, and an output signal of the gate circuit A switch terminal of a first conductivity type having a control terminal for conducting / interrupting between the first terminal and the second terminal, and a substrate terminal connected to the output terminal of the multiplexer;
With
The current value of the drive current supplied from the second terminal to the driven element is adjustable based on the voltage between the control terminal and the first terminal and the voltage of the substrate terminal. A drive circuit characterized by that. The drive circuit according to claim 1, wherein the multiplexer selects the potential corresponding to the correction data based on correction data for correcting the current value of the drive current. 3. The drive circuit according to claim 1, wherein the switch element is a MOS transistor, and the control terminal is a gate. An optical print head comprising the drive circuit according to claim 1, wherein the driven element is a light emitting element, and the plurality of light emitting elements are arranged substantially linearly. An optical print head according to claim 4,
A photoreceptor that forms a latent image based on the light irradiated by the optical print head;
An image forming apparatus comprising: The display device comprising the drive circuit according to claim 1, wherein the driven element is a display element, and the plurality of display elements are arranged in a two-dimensional matrix.

Images