JP3231297B2 - Drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of driven elements, for example, L as a light source in an electrophotographic printer.
A group of EDs, a row of heating resistors in a thermal printer,
Alternatively, the present invention relates to a driving device for selectively driving a row of display elements in a display device.

[0002]

2. Description of the Related Art Conventionally, for example, in an electrophotographic printer, a surface of a charged photosensitive drum is selectively irradiated with light in accordance with print data to form an electrostatic latent image on the surface.
The electrostatic latent image is developed by attaching toner to it, and printing is performed by transferring the resulting toner image to paper. Hereinafter, a conventional driving circuit in an electrophotographic printer will be described with reference to the drawings.

FIG. 23 is a block diagram of a control circuit in a conventional electrophotographic printer, and FIG. 24 is a time chart of the conventional electrophotographic printer. 23 and 24,
The print control unit 1 includes a microprocessor, ROM, RA
M, an input / output port, a timer, and the like, and are provided inside the printing unit of the printer. The print control unit 1 includes a control signal SG1 from a higher-level controller (not shown) and a video signal (one-dimensionally arranged dot map data).
The entire printer is sequence-controlled by SG2 or the like, and a printing operation is performed.

When a print instruction is received by the control signal SG1, the print control unit 1 first detects whether or not the fixing device 22 having the built-in heater 22a is in a usable temperature range by the fixing device temperature sensor 23. If the temperature is not within the temperature range, the heater 22a is heated to reach a usable temperature.
Heat. Next, the printing control unit 1 rotates the developing and transfer process motor (PM) 3 via the driver 2, and simultaneously turns on the charging voltage power supply 25 by the charge signal SGC to charge the developing device 27.

[0005] The presence or absence and the type of paper (not shown) set are detected by the paper remaining amount sensor 8 and the paper size sensor 9, and a paper feed suitable for the paper is started. Here, the paper feed motor (PM) 5 is a driver 4
, And can be rotated in the opposite direction, and then reversely rotated first to feed the set sheet by a preset amount until the sheet inlet sensor 6 detects it. Subsequently, the paper feed motor 5 is rotated forward to convey the paper to a printing mechanism inside the printer.

When the paper is conveyed to a printable position, the print control unit 1 transmits a timing signal SG3 (including a main scanning synchronization signal and a sub-scanning synchronization signal) to the host controller, and outputs a video signal SG2. To receive. The print control unit 1 is edited for each page in the host controller.
Is transmitted to the LED head 19 as print data signals HD-DATA3 to HD-DATA3. The LED head 19 is configured by linearly arranging a plurality of LEDs provided for printing one dot (pixel). LED head 19 used here
Is capable of printing gradation data consisting of 4 bits per pixel. For this purpose, the LED head 19 has four data lines.

When the print control unit 1 receives a video signal for one line, it sends a latch signal H to the LED head 19.
D-LOAD is transmitted, and the print data signal HD-DATA is transmitted.
3 to 0 are held in the LED head 19. As a result, the print control unit 1 can control the LED head 1 even while receiving the next video signal SG2 from the host controller.
9 can be printed with respect to the print data signals HD-DATA 3 to 0 held. HD-CLK is a clock signal for transmitting the print data signals HD-DATA3 to HD-DATA to the LED head 19. HD-STB-
N is a strobe signal.

The transmission and reception of the video signal SG2 is performed for each print line. The information printed by the LED head 19 is converted into a latent image as a dot having an increased potential on a photosensitive drum (not shown) charged to a negative potential.
Then, in the developing unit 27, the image forming toner charged to the negative potential is electrically attracted to each dot by an attractive force to form a toner image.

Thereafter, the toner image is sent to a transfer unit 28,
On the other hand, the transfer high voltage power supply 26 having a positive potential is turned on by the transfer signal SG4, and the transfer unit 28 transfers the toner image onto the sheet passing through the gap between the photosensitive drum and the transfer unit 28.

The sheet having the transferred toner image is conveyed in contact with a fixing unit 22 having a built-in heater 22a, and the toner image is fixed on the sheet by the heat of the fixing unit 22. The sheet on which the toner image is fixed is further conveyed, and is discharged from the printing mechanism of the printer through the sheet discharge port sensor 7 to the outside of the printer.

The print control unit 1 controls the transfer of the sheet to the transfer unit 28 in response to the detection of the sheet size sensor 9 and the sheet inlet sensor 6.
The voltage from the transfer high-voltage power supply 26 is applied to the transfer device 28 only during the passage through the transfer device. Then, when printing is completed and the sheet passes through the sheet discharge sensor 7, the charging high-voltage power supply 25
And the rotation of the motor 3 for development and transfer processes is stopped at the same time. When printing is further performed, the above operation is repeated.

Next, the LED head 19 will be described. FIG. 25 is a diagram showing the structure of a conventional LED head. As shown in the figure, the print data signal HD-DATA3
0 to LED head 1 together with clock signal HD-CLK
Is inputted to 9, for example, in the printer having the A4 size paper resolution possible is 600 dots per inch printing of 4992 dots of bit data flip-flop circuit FF _1a ~FF _1d, FF _2a ~FF _2d ,
.., _Are sequentially transferred in a shift register _including FF _{4992a to} FF _4992d . Next, the latch signal HD-LOAD is inputted to the LED head 19, the bit data latch circuits _{LT 1a ~LT 1d, LT 2a ~LT} 2d, ..., LT
_{4992a to} LT _4992d . Subsequently, among the light emitting elements LD ₁ , LD ₂ ,..., LD ₄₉₉₂ , High is generated by the bit data and the print drive signal HD-STB-N.
The one corresponding to the (high) level dot data is lit. G ₀ is an inverter circuit, CNT is an LED
Control circuit, G _1, G ₂ for controlling the driving time, ..., G
₄₉₉₂ is a pre-buffer circuit, Tr ₁ , Tr ₂ ,.
₄₉₉₂ is a switch element, and V _DD is a power supply.

FIG. 26 is a circuit diagram showing a pre-buffer circuit G ₁ corresponding to dot 1. In Figure 26, the four AND circuits 100a to 100d, one end of an input terminal connected to the output LT _1a to LT _1d of the latch circuit, the other end is a control circuit for controlling the LED driving time They are connected to the signals Sa to Sd for instructing the driving ON / OFF of the LED output from a certain CNT. The outputs of the four AND circuits 100a to 100d are connected to an OR circuit 101, the outputs of which are input to an inverter circuit 102, logically inverted and output, and then connected to a transistor Tr1 which is an LED driving element. You.

FIG. 27 is a time chart showing control for driving the LED head. In FIG. 27, print data HD-DATA3 consisting of 4 bits per pixel.
~ 0 together with the clock signal HD-CLK,
A latch signal HD-LOAD is generated to latch outgoing data. Next, a negative logic strobe signal HD-STB-N for driving the LED is transmitted.

The conventional LED drive realizes gradation printing by changing the amount of exposure energy and changing the accumulated drive time for each drive dot in accordance with a plurality of drive signals having different drive times. there were. 27, different pulse widths T8, T4, T2, T1
The strobe signal HD-STB-N having the above-mentioned signal is input from the CNT circuit of FIG.
The signals Sd, Sc, Sb, and Sa corresponding to the respective pulse widths of 8, T4, T2, and T1 are generated. These signals and the outputs LT _1d , LT _1c , LT _1b ,
LT _1a is logically ANDed to generate an LED drive signal. FIG. 27 shows the output L from the latch circuit.
_{T 1d, LT 1c, LT 1b} , the LT _1a, it is assumed that the drive signal is generated corresponding to T8, T1.

FIG. 28 is a time chart showing the actual driving current waveform of the LED in association with the strobe signal.
In this case, as shown in the figure, different pulse widths T8, T8
Four LED drive current pulses are generated in accordance with each of 4, T2, and T1.

FIG. 29 is a block diagram showing the configuration inside the LED head. In the example shown in FIG.
11, 192 LED elements can be driven per chip, and 26 driver ICs 111 are connected in cascade so that print data input from the outside can be serially transferred. The strobe signal HD-STB-N of the LED head is connected to each driver IC 111. The LED head 19 has an LED array chip (hereinafter referred to as L) in which 192 LED elements are arranged.
Each of the driver ICs 111 includes a reference voltage generating circuit 112 for supplying a predetermined reference voltage V _REF to each of the driver ICs 111. Each driver IC 111 is formed of the same circuit, and is cascaded with an adjacent driver IC 111.

The driver IC 111 includes a shift register circuit 113, a latch circuit 114, a control circuit 11
5, an AND circuit 116, an LED driving circuit 117,
And a control voltage generation circuit 118. The shift register circuit 113 is composed of 192 flip-flop circuits, and is configured to shift-input the print data HD-DATA3 to 0 in synchronization with the clock signal HD-CLK. The latch circuit 114 latches the output signal of the shift register circuit 113 by a latch signal HD-LOAD. The control circuit 115 controls the strobe signal HD-S
According to TB-N, the print data signals HD-DATA3 to 0
In accordance with the logical level of the output signal composed of a plurality of bits obtained by latching the data, different drive signals are generated for each dot.

A logical product (AND) circuit 116 inputs the output signals of the latch circuit 114 and the control circuit 115 and performs a logical product. The LED drive circuit 117 supplies a drive current from the power supply VDD to the LED array 110 according to the output of the AND circuit 116. The control voltage generation circuit 118 is the LED drive circuit 1
At step 17, a command voltage is generated so that the drive current becomes constant. Each of the print data signals HD-DATA3 to 0, the clock signal HD-CLK, the latch signal HD-LOAD, and the strobe signal HD-STB-N is sent from the print control unit 1 during printing.

FIG. 30 is a circuit diagram showing a pre-buffer circuit, a control voltage generating circuit and its peripheral circuits. In the figure, a portion surrounded by a broken line shows a pre-buffer circuit G _1, the pre-buffer circuit G _1, the AND circuit AD1, OR circuit OR
1, a P-channel MOS transistor TP1 and an N-channel MOS transistor TN1 are provided. An inverter circuit is constituted by the P-channel MOS transistor TP1 and the N-channel MOS transistor TN1. Pre-buffer circuit G ₁ is corresponds to the circuit shown of FIG. 26, one of the AND circuits Sc as a representative of the four AND circuits in FIG. 30 is shown.

The portion surrounded by one-dot chain line is a control voltage generating circuit 118, which is provided for each driver IC1 chip to drive the pre-buffer circuit G _1. The control voltage generation circuit 118 includes an operational amplifier 120, a P-channel MOS
A transistor 121 and a resistor Rref are provided.
The output of operational amplifier 120 is connected to all of the pre-buffer circuit in the driver IC chip, in particular is connected to the source terminal of the N-channel MOS transistor TN1 of the pre-buffer circuit G _1. P channel MO
The S transistor 121 is a switch element T shown in FIG.
, Tr _4992, and the gate length is equal to r ₁ , Tr ₂ ,..., Tr ₄₉₉₂ .

The input terminal of the operational amplifier 120 is connected to a reference voltage V _REF generated from a reference voltage circuit (not shown). A feedback control circuit is configured by a circuit including the operational amplifier 120, the P-channel MOS transistor 121, and the resistor Rref, and the current flowing through the resistor Rref, that is, the current flowing through the P-channel MOS transistor 121 is independent of the VDD voltage and the reference voltage V _REF. And resistance Rr
The configuration is determined only by the value of ef. Reference numeral 122 is an output electrode pad provided to drive the LED elements LD _1.

FIG. 31 shows the structure of the LED head and the variation of the LED light quantity (light emission power) for each dot in comparison. In the figure, 26 driver ICs 11
1 drives the corresponding LED array chips 110 respectively. 192 LED elements are integrated on the LED array chip 110, and each LED element and the driver IC are integrated.
The output terminal 111 is connected by wire bonding. That is, one chip of the driver IC 111 has 19
Two LED elements can be driven, and these 26-chip driver ICs 111 are connected in cascade to serially transfer print data input from the outside.

The graph below the figure shows the light emission power for each LED array chip. The horizontal axis shows the position of each dot of each LED array chip, and the vertical axis shows the light emission power. As shown in the graph, the emission power varies among the dots in each LED array chip, and also varies between the LED array chips. Variations in light emission power appear as variations in exposure energy during exposure of the photosensitive drum, and variations in dot size after development.

When printing an image composed of characters and the like, the difference in dot size can be almost ignored even if there is a difference in dot size. However, when printing an image such as a photograph, there is a difference in dot size. This causes variations in the print density, resulting in poor print quality.

[0026]

In FIG. 28, LE
The drive current waveform of D is divided into four according to the command pulses T8, T4, T2, T1 of the strobe signal HD-STB-N. The rise time and fall time of the LED drive current are determined by the pulse widths T8, T4, T2, T
There is no problem if it is sufficiently smaller than 1, but if it is not so as in the case of FIG.
Due to the influence of the transition time of the ED current waveform, the contribution ratio of each drive pulse to the exposure energy amount to the photosensitive drum varies.

As a result, a large difference occurs between the gradation data to be printed and the actual print result. This phenomenon depends on the transition time of the LED drive current, and must be designed and controlled, such as the lead inductance of the power cable that supplies power to the LED head and the capacitance deviation of the decoupling capacitor connected to the power supply system. This is due to the fact that the transition time of the LED drive current greatly changes due to factors that are difficult to perform, and the amount of exposure energy generated by the LED fluctuates. This is undesirable for the purpose of printing with good reproducibility using gradation data.

On the other hand, there was another problem. In the above-described conventional method of correcting the light emission power, the correction amount of the light emission power for each dot is obtained by causing the LED elements to emit light one dot at a time and measuring the light output generated at that time with an optical power meter. In this case, a method is employed in which the print data is gradation data composed of a plurality of bits, and the accumulated driving time of the LED is changed for each dot to correct the exposure energy amount of the photosensitive drum to a practically sufficient level. I was

Considering the case where the manufacturing variation of the LED elements is corrected by such a method, there is no problem in the case of printing with binary data, but in the case of printing gradation data, the gradation of each dot is considered. Correction data appropriate to the key data must be calculated. In the worst case, it is necessary to prepare a plurality of correction data corresponding to each gradation data.

[0030]

According to the present invention, there is provided a driving apparatus for driving a plurality of driven elements provided in a driving body, wherein a plurality of driving elements are provided for one driven element. Driving means for selectively driving the plurality of driving elements based on grayscale data to drive the driven elements, and driving currents to all the driving elements of the driving body by the first correction data. First correction means for correcting the drive current to the plurality of drive elements at a predetermined rate for each of the driven elements based on second correction data. The driving unit selectively drives each of the plurality of driving elements at a predetermined ratio based on the first and second correction data, based on grayscale data, so that the driven element is Current flowing through Characterized in that the variable at a predetermined ratio.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals. FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a circuit block diagram illustrating a driving device according to an embodiment.
The drive device according to the first embodiment performs printing by adjusting the drive current value of the LED for each dot in multiple stages according to the gradation data. The driver IC according to the present embodiment also has 192 drive terminals for driving LEDs, and 192 drive circuits having the same configuration are provided for each of the drive terminals, similarly to the above-described conventional driver IC. ing.

In FIG. 1, the driver IC 200 has the following terminals. DATAI3 to DATAI0 are data input terminals and have four terminals for inputting 4-bit gradation data and 4-bit correction data per pixel. On the other hand, DATAO3 to DATAO0 are data output terminals and have four terminals for outputting 4-bit gradation data and 4-bit correction data per pixel.

CLKI is a clock signal input terminal.
LKO is a clock signal output terminal. Also LOAD
I is an input terminal of a latch signal, and LOAD is an output terminal of a clock signal. The clock signal input to CLKI is logically inverted by the inverter circuit 201 and
The latch signal output from O and input from LOADI is logically inverted by the inverter circuit 202 and
Output from O. The SEL terminal is connected to each driver IC 20
31 is used to set the operation logic (positive logic / negative logic) of the clock signal and the latch signal input to 0. Among the driver ICs in FIG. 31, DRV1, DRV3,.
In a chip corresponding to an odd number of the cascade connection such as DRV25, this terminal is opened, and DRV2, DRV2,
V4,..., DRV26, etc., are connected to ground in chips corresponding to even-numbered cascade connections.

The SEL terminal signal is connected to one input terminal of two EX-NOR circuits 203 and 204,
A clock signal and a latch signal are supplied to the other input terminals of the X-NOR circuits 203 and 204, respectively. The output signals of the EX-NOR circuits 203 and 204 are supplied to respective parts of the driver IC 200 and used as clock signals for internal operation and latch signals. SEL
The purpose of providing the terminals is to convert the clock signal and the latch signal, which have been logically inverted by the inverter circuits 201 and 202 of the driver IC of the preceding stage and input, into correct logical values again and use them inside each driver IC. Even if the propagation delay time of the inverter circuit at each stage is different between the signal rising and the signal falling, the pulse width is changed during averaging during the propagation through the multi-stage connection circuit of the driver IC. This is because it can prevent.

The STB terminal is a strobe signal input terminal to which a negative logic strobe signal is input. VREF
Is a reference voltage input terminal to which a reference voltage corresponding to the set value of the LED drive current is applied.

Reference numeral 205 denotes a flip-flop circuit which constitutes a shift register for transferring gradation print data consisting of 4 bits per pixel, and these are connected in a 193-stage cascade. Reference numeral 206 denotes a latch circuit for latching gradation print data consisting of 4 bits per pixel, and its input is connected to the first 192 stages of the 193-stage shift register circuit.

On the other hand, a latch circuit 207 also has an input to the shift register 20 similar to the latch circuit 206.
5 output. As will be described later, these latch circuits are provided for storing correction data for manufacturing variations of LEDs each consisting of 4 bits per pixel.

Reference numeral 208 denotes an analog multiplexer circuit (MUX
16), wherein 4 is output from the latch circuit 207.
Bit signals are input from the terminals S3 to S0, and 16 analog input terminals (P
15 to P0), one of the analog voltages is selected, and the selected voltage is output from the analog output terminal Y to the drive circuit (DRV) 209.

Further, 210 and 211 are inverter circuits,
Reference numeral 212 denotes a NAND circuit, reference numeral 213 denotes a control voltage generation circuit (ADJ) for generating a 16-stage analog voltage described later, reference numeral 214 denotes a selector circuit (SEL), and reference numeral 215 denotes a control circuit (CTRL). 216 and 217 are pull-up resistors.

Next, the internal configuration of each block in FIG. 1 will be described. FIG. 2 shows an internal circuit of the control voltage generation circuit 213, in which 221 is an operational amplifier, r0 to r15 are resistors,
222 is a P-channel MOS transistor. 223
Is a decoder circuit (RDEC) described later.

The output voltage VREF from the reference voltage generation circuit (indicated by reference numeral 112 in FIG. 29) is applied to the inverting input terminal (-) of the operational amplifier 221, and the non-inverting input terminal (+) is connected to the P-channel MOS transistor 222. It is connected to the drain terminal and the R terminal of the decoder circuit 223, respectively. The output terminal of the operational amplifier 221 is connected to one end of a series connection circuit of resistors r0 to r15, and is output to the analog multiplexer 208 as V15.

The other end of the series connection of the resistors r0 to r15 is connected to the power supply VDD together with the source terminal of the P-channel MOS transistor 222. The connection node voltages of the series connection circuit of the resistors r0 to r15 are V0 to V
15 is output to the analog multiplexer 208. The node indicated by V7, which is the middle point of the potential, is connected to the gate terminal of the P-channel MOS transistor 222. The STBY terminal which is the remaining input terminal of the operational amplifier 221 is connected to a control circuit 215 described later.

FIG. 3 shows the internal configuration of the decoder circuit 223. R0 to R15 are resistors having different resistance values, 230 to 245 are N-channel MOS transistors, and 246 to 249 are inverter circuits. A portion indicated by a broken line is a decoder circuit configured by using 16 4-input NOR circuits. Four signals are input to the NOR circuit from S0 to S3 and four inverter circuit outputs.
Output signals from the R circuit are respectively connected to gate terminals of N-channel MOS transistors. In addition, 230-2
The source terminal of each of the 45 N-channel MOS transistors is connected to the ground, and the drain terminal of each transistor is connected to the R terminal via resistors R0 to R15.

FIG. 4 shows the internal configuration of the analog multiplexer 208. In the figure, 301 to 308 are inverter circuits, 309 to 348 are P-channel MOS transistors, and 349 to 388 are N-channel MOS transistors. According to the logic signal levels input to the S0 to S3 terminals, one of the 16 voltages applied to the 16 input terminals P0 to P15 is selected, and the voltage level is set as an analog value to the output terminal Y. From the analog switch.

FIG. 5 shows the internal structure of the LED drive circuit 209. In the figure, 404 is an inverter circuit,
400 to 403 are NAND circuits, 405 to 416 are P-channel MOS transistors, 417 to 424 are N-channel MOS transistors, and 425 is an LED driving electrode pad for connecting to an LED electrode pad.

A command signal for driving the LED corresponding to the strobe signal is connected to the S terminal of the drive circuit 209, and the signal is logically inverted by the inverter circuit 404.
It is supplied to one input terminal of the NAND circuits 400 to 403. The other input terminals of the four NAND circuits 400 to 403 are connected to four signals output from the latch circuit 206. Signals for this are described in the figure as D3 to D0. On the other hand, an inverter circuit is constituted by P-channel MOS transistors and N-channel MOS transistors arranged above and below, of which the source terminal of the P-channel MOS transistor is connected to the power supply VDD and the source terminal of the N-channel MOS transistor is Connected to potential V. This potential is obtained from the output terminal Y of the analog multiplexer 208 described above.

The two-stage inverter circuit composed of the P-channel MOS transistor and the N-channel MOS transistor is connected in cascade, and drives the gate terminals of the P-channel MOS transistors 413 to 416, respectively. The source terminals of the P-channel MOS transistors 413 to 416 are connected to the power supply VDD,
The drain terminal is connected to a DO output pad for driving the LED. Here, the P-channel MOS transistor 4
13 to 416 and the gate lengths of the P-channel MOS transistors 222 shown in FIG.
The gate widths at 3 to 416 are 8, 4, 2,
The ratio is set to 1.

FIG. 6 shows the internal configuration of the control circuit 215.
In the figure, reference numerals 430 to 432 denote flip-flop circuits,
433 is a NOR circuit, and 434 and 435 are AND circuits. The flip-flop circuits 430 and 431 and the NOR circuit 433 constitute a ring counter circuit, and the flip-flop circuit 432 is connected so as to perform a toggle operation by an output signal from the ring counter. AN
One input terminals of the D circuits 434 and 435 are respectively connected to two output terminals of a flip-flop circuit 432 which is a toggle counter, and the other input terminals of the AND circuits 434 and 435 are connected to output terminals of a ring counter. I have.

Then, the two AND circuits 434 and 435
Are supplied to the latch circuit 207 and the control voltage generation circuit 213 as WR and STBY, respectively. As described later, the WR signal is a write command signal of dot correction data for performing dot correction of the LED, ST
The BY signal is a standby command signal for reducing current consumption during standby of the LED head.

FIG. 7 shows the internal configuration of the operational amplifier 221 provided in the control voltage generation circuit 213. In the figure, 4
40 to 445 are P-channel MOS transistors, 446
450 to N channel MOS transistors, 451 and 4
52 is an inverter circuit, 453 and 454 are resistors, 455
Is a capacitor. Operational amplifier 221 of the present embodiment
, An STBY terminal is provided in addition to the terminal normally provided, and when the logic signal level of this terminal becomes High, the P-channel MOS transistor 440 is turned on, the N-channel MOS transistor 446 is turned off, and the 449 is turned on. As a result, the current consumption of the operational amplifier becomes almost zero, while its output terminal is in a high impedance state.

Next, the operation of the first embodiment will be described. Prior to this, the static characteristics of the P-channel MOS transistor will be described. FIG. 8 is a graph showing static characteristics of the LED driving P-channel MOS transistor Tr1.

In FIG. 8, the horizontal axis of the graph is the gate-source voltage V _GS of the transistor, and the vertical axis is the drain current I
D shows the static characteristics under the condition that the drain-source voltage V _DS is constant. The operating point of the P-channel MOS transistor Tr1 is set so as to operate in a saturation region of MOS characteristics. In this situation, the following equation holds between the gate-source voltage V _GS of the transistor Tr1 and the drain current ID.
That is, ID = β (W / L) (V _GS −Vt) ² (1) where β is a constant, W is the gate width of Tr1, L is the gate length of Tr1, and Vt is the threshold voltage of the MOS transistor.

Returning to FIG. 5, it is assumed that the output signal D0 of the latch circuit 206 for driving the LED is at a high level, and the S terminal has transitioned to a low level. At this time, the output of the inverter circuit 404 becomes High level, and the output of the NAND circuit 400 transits to Low level.
The gate terminal level of the channel MOS transistor 416 has a low voltage level, and has a value almost equal to the voltage value of the terminal V.

As a result, the gate-source voltage V _GS applied to P-channel MOS transistor 416 becomes VD
It is a value obtained by subtracting the potential of the terminal V from the D voltage. for that reason,
When the LED is driven, a drive current value corresponding to the _VGS voltage in FIG. 8 flows through the P-channel MOS transistor 416.

Returning to (Equation 1), a quantitative discussion will be made.

The gate lengths of the P-channel MOS transistors 413 to 416 shown in FIG. 5 are L, and the gate widths are denoted by W3, W2, W1, and W0, respectively. The gate length of P-channel MOS transistor 222 in FIG.
The gate width may be appropriately determined. So let's call that gate width w.

As described above, the following relationship exists between them. That is, W3 = 8W0 W2 = 4W0 W1 = 2W0 W0 = Kw where K is a mirror ratio.

On the other hand, P-channel MOS transistor 41
Considering the case of No. 6, when the gate-source voltage is V _GS0 , the drain current is given as ID0 = β (W0 / L) (V _GS0 −Vt) ² (2) When the source-to-source voltage is changed from V _GS0 to V _GS15 in 16 ways, each V _GS
In contrast, the drain current can be changed in 16 ways, and ID0 = β (W0 / L) (V _GS1 −Vt) ² (Equation 3) ID0 = β (W0 / L) (V _GS7 −Vt ) ² (Equation 4) ID0 = β (W0 / L) (V _GS15 −Vt) ² (Equation 5) is obtained.

Similarly, the following equation is obtained for the other P-channel MOS transistors 413 to 415 for the same gate-source voltage V _GS7 . That is, ID0 = 8β (W0 / L) (V _GS7 −Vt) ² (transistor 413) ID0 = 4β (W0 / L) (V _GS7 −Vt) ² (transistor 414) ID0 = 2β (W0 / L) (V _GS7- Vt) ² (transistor 415).

FIG. 9 shows a driver IC according to the present embodiment.
5 is a time chart showing the print data transfer method, and describes the operation of a single driver IC chip alone. In the figure, a latch signal LOWADI is set to a low level, and gradation data consisting of 4 bits per pixel is DA
Input via each terminal of TAI3 to DATAI0, 19
Shift transfer is performed by two clock signal (CLKI) pulses. When the transfer is completed, a latch signal LOADI is generated, and the data transferred to the shift register is latched by the latch circuit 206. Next, the strobe signal ST
When BN is input, an LED drive current is generated according to the pulse width of the strobe signal STB-N.

FIG. 10 shows a driver I according to this embodiment.
6 is a time chart showing a method of transferring the correction data of C, and describes the operation of a single driver IC chip alone. In the figure, a latch signal LOWADI is set to a high level, dot correction data consisting of 4 bits per pixel is input via each terminal of DATAI3 to DATAI0, and shift transfer is performed by 193 clock signal (CLKI) pulses. At this time, the data transferred at the first clock of the data transfer is the chip correction data for performing the correction in units of the LED chips, and the 192 pieces of data subsequently transmitted are the dots corresponding to the 192 dots of the LED. It is correction data.

When the transfer is completed, a three-pulse signal is input to the STB terminal, a one-pulse signal is generated at the terminal indicated by WR by the control circuit in FIG. 6, and the data transferred to the shift register is corrected. Writing to the latch circuit 207 for storage. In FIG. 10, this signal is described as an internal signal (correction data WR). At this time, the inverter circuits 210 and 211 in FIG.
The strobe signal STB−
Even if N is input, it is designed so that no driving current is generated in the LED.

Next, a method of generating the above-mentioned gate-source voltage _VGS will be considered. Here, as an example, both the chip correction data and the dot correction data are “7” (2
"0111" in binary system, and the gradation data is "8" (2
Let us consider the case of "1000" in the binary system.

Since the chip correction data is "7", the decoder circuit shown by the broken line in FIG.
Becomes high, and the N-channel MOS transistor 237 is turned on. On the other hand, since the other MOS transistors are off, the R terminal in FIG. 3 is thereby connected to the ground via the resistor R7.

Returning to FIG. 2, the non-inverting input terminal of the operational amplifier 221 is connected to the resistor R7 by the operation of the decoder circuit 223.
Is connected to the ground. At this time, the operational amplifier 2
By the action of 21, the potential of the non-inverting input terminal becomes VREF. Therefore, the current flowing through the resistor R7, that is, the P channel MOS transistor 222 is obtained as VREF / R7.

A product obtained by multiplying eight times the current value by the mirror ratio K is the P-channel MOS transistor 413 in FIG.
Current. That is, ID = 8K (VREF / R7). At this time, P-channel MOS transistor 413
Is equivalent to V7 in FIG. Therefore, the following equation also holds. That is, ID = 8Kβ (w / L) (V _GS7 −Vt) ² On the other hand, since the currents flowing through the resistors r0 to r15 are equal, the potentials of the output voltages V0 to V15 in FIG. A relationship in which the potential drops monotonously is obtained.

For this purpose, any one of the potentials of the output voltages V0 to V15 is selected and output from the terminal Y in FIG. 4, and is set as the potential V in FIG.
By applying the drain current as the gate potential of the channel MOS transistor 413, the drain current can be adjusted in 16 steps. In this way, the driving current of the LED is set to 1 for each dot by the dot correction data.
It can be seen that the adjustment can be made in six stages.

Although the above discussion has been directed to the case where the chip correction data is "7" which is the center value, the case where the chip correction data is changed to "8"("1000") in the same manner is considered. The N-channel MOS transistor 238 connected to the signal line 8 is turned on by the decoder circuit surrounded by the broken line in FIG. As a result, the terminal R of FIG. 3 is connected to the ground via the resistor R8.
The current flowing through the P-channel MOS transistor 222 in FIG. 5 changes to VREF / R8, and the current value multiplied by 8 and multiplied by the mirror ratio K is the P-channel M transistor in FIG.
The current becomes the current of the OS transistor 413, and the following equation is obtained. ID = 8K (VREF / R8) As described above, the drive current of each dot of the driver IC can be changed at once.

Finally, the gradation data input to the driver IC
Let us consider the change in the drive current due to data. In the earlier discussion
Is the case of “8” (“1000”).
Was. Next, assuming that the gradation data is “9” (“1001”)
Like. Find the LED drive current in the same way as the previous discussion
ID = 8Kβ (w / L) (V_GS7-Vt)^Two+ Kβ (w / L) (V_GS7-Vt) ^Two  = 9Kβ (w / L) (V_GS7-Vt)^Two  Is found.

As is apparent from the above discussion, in the circuit configuration according to the present embodiment, the dot correction and the chip correction can be adjusted independently at a predetermined ratio, and the gradation data can be independently adjusted at a predetermined ratio. It can be changed by the ratio of

FIG. 11 is a graph showing the relationship between the amount of exposure energy applied to the photosensitive drum by the LED element and the resulting print density after printing. FIG. 12 shows the relationship between the gradation data input for gradation printing and the LED driving current obtained by the gradation data in the driver IC of the present embodiment.

In this embodiment, the driving time of each dot of the LED head is equal. Further, since the light emission power is obtained according to the driving current of the LED, the amount of exposure energy is also determined in accordance with the driving current value of the LED. Therefore Figure 1
1 and FIG. 12 illustrate the numerical axis of the exposure energy amount and the drive current value axis in association with each other.

[0073]

[Table 1]

Table 1 shows the operation of correcting the drive current in chip units by the driver IC according to the first embodiment. It can be seen that the drive current changes in 16 steps based on the 16 types of chip correction data, centering on the case of the chip correction data “0111”.

[0075]

[Table 2]

Table 2 shows the operation of correcting the drive current in dot units by the driver IC according to the first embodiment. With the dot correction data “0111” as the center, it can be seen that the drive current changes in 16 steps according to the 16 types of dot correction data.

[0077]

[Table 3]

On the other hand, Table 3 shows how the driver IC according to the present embodiment changes the drive current according to the gradation data. It can be seen that the drive current is changed in 16 steps including the case where the current is zero, based on the 16 kinds of gradation data, centering on the print gradation data “1000”.

As described above, in the driver IC according to the first embodiment, in addition to the chip correction and the dot correction for the LED manufacturing variation correction, four pixels per pixel are provided.
The LED drive current can be varied also by the gradation data composed of bits. Furthermore, the above-described current varying method can vary the driving current value of the LED for the three objective variable elements independently and at the same percentage.

As a result, manufacturing variations of the LED are reduced.
It can be corrected by changing the drive current,
After correcting the light emission power of all the dots constituting the LED head to be constant, it is possible to change the drive current for each dot in accordance with the gradation data to change the density of the print dots. It is. Note that, as is clear from the circuit method in the present embodiment, the effect of correcting LED manufacturing variations is kept constant regardless of the gradation data input to the LED head.

More specifically, the effects described above are as follows. The LED drive is performed with the gradation data of all the dots set to “8”, the light emission power of the LED at that time is measured, and the light emission power of each dot of the LED is determined by appropriately determining the chip correction and dot correction data. Suppose that it was uniform. Next, LED drive is performed by changing the gradation data of all dots to “9”.
Let's say that the light emission power of was measured again. At this time, L
Each dot of the ED head has been corrected by setting the gradation data to “8”.
Although there is a difference that the emission power of the ED is increased as a whole, it is still kept uniform.

Next, a second embodiment of the present invention will be described. FIG. 13 is a circuit diagram showing a driving circuit according to the second embodiment of the present invention, and corresponds to FIG. 5 in the first embodiment.

In the drive circuit shown in FIG. 13, the following circuit elements are newly added to the drive circuit of the first embodiment shown in FIG. 502 is a NAND circuit, 501 is an OR circuit, 503 to 505 are P-channel MOS transistors,
506 and 507 are N-channel MOS transistors. The four input terminals of the OR circuit 501 are connected to the latch circuit 20
6 is connected to each of the grayscale data D3 to D0 latched, and its output is connected to one input terminal of the NAND circuit 502, and the other end of the NAND circuit 502 is connected to the output of the inverter circuit 404. .

The output of NAND circuit 502 is P channel M
It is connected to a first inverter circuit composed of an OS transistor 503 and an N-channel MOS transistor 506. This output is then connected to a second inverter circuit composed of a P-channel MOS transistor 504 and an N-channel MOS transistor 507. The output is connected to the gate terminal of P-channel MOS transistor 505. P channel MOS transistor 50
The drain terminal 5 is commonly connected to the drain terminals of the other P-channel MOS transistors 413 to 416. Other configurations are the same as those of the first embodiment.

Next, the operation of the second embodiment will be described.
FIGS. 14 and 15 are graphs for explaining the operation of the second embodiment of the present invention.
1 and FIG.

FIG. 14 is a graph showing the relationship between the amount of exposure energy applied to the photosensitive drum by the LED element and the resulting print density after printing. On the other hand, FIG. 15 shows the driver IC according to the second embodiment in which the gradation data input for gradation printing and the LE obtained therefrom are obtained.
4 shows the relationship between D drive currents.

In this embodiment, the driving time of each dot of the LED head is equal, and the light emission power corresponding to the driving current of the LED can be obtained. Therefore, the exposure energy is also determined in accordance with the driving current value of the LED. Have been. Therefore, FIGS. 14 and 15 illustrate the numerical axes of the respective exposure energy amounts and the drive current value axes in association with each other.

In FIG. 15, the point that the driving current of the LED is set to zero when the gradation data is "0" is the same as in the first embodiment. On the other hand, the difference from FIG. 12 is that the change curve of the drive current due to the change in the gradation data is shifted in the direction in which the drive current increases, while the change rate is reduced. is there.

[0089]

[Table 4]

Table 4 is a table showing how the drive current changes in the driver IC according to the second embodiment depending on the gradation data. In all cases where the drive current is changed in 16 steps including the case where the current is zero according to the 16 types of grayscale data and drive of a non-zero LED is obtained, Im
It can be seen that the current in is added.

As described above, in the second embodiment, when the LED is driven by the gradation data, the print density is small with a small amount of exposure energy with respect to the relationship between the amount of exposure energy obtained and the print density. Focusing on the fact that there is a dead zone that is zero, L
The ED drive current value area is skipped.

As a result, the substantial LED drive current change range Imin to Imax can be matched with the density change area in the characteristic graph of the amount of exposure energy to the photosensitive drum and the print density, and the gradation data can be reduced. In spite of the number (that is, a small number of bits), it is possible to generate a print density change with a smaller step value.

Next, the third embodiment will be described. Before that, the characteristics of the circuit according to the first embodiment will be examined. FIG. 16 shows a P-channel MO for driving an LED.
5 is a graph showing static characteristics of the S transistor Tr1,
This corresponds to FIG. 8 in the first embodiment.
The horizontal axis of this graph shows the gate-source voltage V _GS of the transistor, and the vertical axis shows the drain current ID, and shows the static characteristics under the condition that the drain-source voltage V _DS is constant. Temperature of 0 ° C, 25 ° C, 50 ° C
The curve group obtained by changing the temperature to 75 ° C, 100 ° C, and the like is shown.

As is apparent from FIG. 16, in a situation where the drain current ID of the MOS transistor flows, as the temperature is increased, the drain current ID decreases accordingly. As a result, the ratio of the change ΔID of the drain current when the gate-source voltage is changed by ΔV _GS (that is, the slope of the graph of FIG. 16) ΔID / ΔV _GS becomes smaller as the temperature of the driver IC increases. I have.

The P-channel MOS transistor Tr1
Is set to operate in a saturation region of MOS characteristics. In this situation, the transistor Tr1
Is established between the gate-source voltage _VGS and the drain current ID. ID = β (W0 / L) (V _GS −Vt) ² where β is a constant, W0 is the gate width of Tr1, L is Tr
The gate length of 1 and Vt is the threshold voltage of the MOS transistor.

[0096] In the first embodiment was achieved, the V _GS in the above formula is increased or decreased by [Delta] V _GS to a drain current ID variable. Here, even if a temperature rise occurs, the reference current in FIG.
The current flowing through the transistor 222 does not change. However, since the static characteristics of a MOS transistor have temperature dependence, the operating point of the MOS transistor is shifted to a higher gate-source voltage.

On the other hand, the amount of change in the LED drive current for one step change of the dot correction data is assumed to be 2%.
In order to obtain this change amount, a necessary change amount ΔV _GS of the gate-source voltage is obtained at a certain temperature, and the potentials V0 to V15 in FIG. 2 are determined based on this voltage value. For this reason, when the operating point of the gate-source voltage moves due to a rise in temperature, there is no problem in the LED drive transistor to which a potential close to V7, which is the correction center, is supplied, but the potential far from the center value such as V0 or V15 is not affected. In the given LED drive transistor, there arises a problem that the drive current value changes depending on the temperature.

FIG. 17 shows dot correction data input to the driver IC in the configuration of the first embodiment,
The relative change rate of the drive current obtained at that time is measured by changing the temperature of the driver IC. In FIG. 17, the temperature of the driver IC is 0 ° C., 25 ° C., 50 ° C.
The measurement was performed while changing the temperature to 75 ° C, 75 ° C, and 100 ° C.

As is apparent from FIG. 17, in the configuration of the first embodiment, the change rate of the drive current value due to the change in the correction data varies due to the change in the temperature of the driver IC. It turns out that there is.
That is, in the circuit according to the first embodiment, the necessary gate-source voltage is set by extrapolating from the center of dot correction based on the characteristics of the MOS transistor at a certain temperature. For this reason, it is assumed that although the drive current for correcting the manufacturing variation of the LED is negligible, the LED is corrected at a certain temperature and the light emission power can be corrected uniformly. Also LED
If the temperature of the driver IC rises due to an unavoidable factor such as driving, the effect of correction will be reduced by the rise in temperature.

That is, suppose that there is an LED dot which is appropriately corrected by the dot correction data "7" which is the center of correction. In this case, even if the temperature of the driver IC rises, there is almost no change in the drive current. Therefore, the drive current value of the LED of this dot does not change, and the light emission power is kept unchanged.

On the other hand, it is assumed that there is an LED dot that is appropriately corrected by the dot correction data “15”. In this case, when the temperature of the driver IC rises, the driving current relatively decreases. For this reason, the drive current value of the LED of this dot decreases, and the light emission power also decreases.

As described above, even if the light emission power can be appropriately corrected at a certain temperature, the drive current fluctuates with a temperature coefficient depending on the value of the dot correction data due to a change in the temperature of the driver IC. In spite of the correction, the light emission power will again show a variation between dots.

This is negligible with respect to the change in the drive current for correcting the manufacturing variations of the LEDs, but is not desirable from the standpoint of demanding higher quality printing results. The third embodiment has been made in consideration of the above points.

FIG. 18 is a circuit diagram showing a control voltage generating circuit according to the third embodiment of the present invention, which corresponds to FIG. 2 in the first embodiment. In FIG. 18, while the resistor r0 in FIG. 2 is deleted, the following circuit element is newly added. That is, 603 and 606 are decoder circuits, and correspond to the decoder circuit 223 in FIG. Reference numerals 601 and 604 denote operational amplifiers.
Corresponds to 1. 602 and 605 are P-channel MOSs
It is a transistor and corresponds to 222 in FIG. The difference between FIG. 18 and FIG. 2 is that the resistance r
Of one end of the series connection circuit consisting of
1 is connected to the output terminal of the operational amplifier 604.

FIG. 19 shows a decoder circuit (RDEC2) 60.
3 is a circuit diagram showing a configuration of the third embodiment, and corresponds to FIG. 3 in the first embodiment. FIG. 20 is a circuit diagram showing a configuration of the decoder circuit (RDEC1) 606, and corresponds to FIG. 3 in the first embodiment.

In FIG. 19, R0 to R15 are resistors having different resistance values, 610 to 625 are N-channel MOS transistors, and 626 to 629 are inverter circuits. A portion indicated by a broken line is a decoder circuit constituted by using 16 four-input NOR circuits. The four signals from S3 to S0 and the four inverter circuits are input to the NOR circuit, and the output from each NOR circuit is output. The signal is N channel MO
Each is connected to the gate terminal of the S transistor. The source terminals of the N-channel MOS transistors 610 to 625 are connected to the ground, and the drain terminals of the respective transistors are connected to the R terminal via resistors R0 to R15, respectively.

In FIG. 20, R100 to R115 are resistors having different resistance values, and 710 to 725 are N
Channel MOS transistors 726 to 729 are inverter circuits. A portion indicated by a broken line is a decoder circuit configured by using 16 4-input NOR circuits.
And the four signals after the four inverter circuits by the NOR
Input signals to the circuits and output signals from the respective NOR circuits are respectively connected to gate terminals of N-channel MOS transistors. The source terminals of the N-channel MOS transistors 710 to 725 are connected to the ground, and the drain terminals of the respective transistors are connected to the R terminal via resistors R100 to R115, respectively.

FIG. 21 is a circuit diagram showing the configuration of the operational amplifiers 601 and 604.
It corresponds to. The difference between FIG. 21 and FIG. 7 is that the N-channel MOS transistor 449 is moved to the output terminal side of the operational amplifier and is connected as 800 between the output terminal and the ground.

Next, the operation of the third embodiment will be described.
First, the decoder circuits (RDEC2) 603 and (RDEC2)
1) The method of setting the resistance value in 606 will be described. The upper and lower limits of the current adjustment range required for dot correction are set as Imax and Imin, and the P-channel MOS transistor 413 will be considered. Here, as an example, the chip correction data is “7” (“011 in binary system”).
1)) and the gradation data is “8” (“100” in binary system).
0 ").

First, consider the case of Imax, that is, the case where the dot correction data is “15” (“1111” in binary). Since the chip correction data is "7", the logic level of the signal line corresponding to "7" becomes High by the decoder circuit shown by the broken line in FIG. 19, and the N-channel MOS transistor 617 connected thereto is turned on. On the other hand, since the other MOS transistors are off, the R terminal in FIG. 19 is connected to the ground via the resistor R7.

Returning to FIG. 18, the non-inverting input terminal of the operational amplifier 601 is connected to the resistor R by the operation of the decoder circuit 603.
7 is connected to the ground. At this time, the potential of the non-inverting input terminal becomes VREF due to the operation of the operational amplifier 601.
Becomes Therefore, the current flowing through the resistor R7, that is, the current flowing through the P-channel MOS transistor 602 is obtained as VREF / R7.

A product obtained by multiplying the current value by eight times the mirror ratio K is the P-channel MOS transistor 413 in FIG.
Current. That is, ID = 8K (VREF / R7) = Imax.

At this time, P-channel MOS transistor 4
The gate potential of 13 corresponds to V15 in FIG. Therefore, the following equation is also satisfied. That is, ID = 8Kβ (w / L) (V _GS15 −Vt) ² = Imax Next, a method of generating a control voltage corresponding to Imin will be considered. The dot correction data at this time is “0” (“0000” in binary). Chip correction data is "7"
Therefore, the logic level of the signal line corresponding to “7” is set to Hi by the decoder circuit indicated by the broken line in FIG.
gh, and the N-channel MOS transistor 717 connected thereto is turned on. On the other hand, since the other MOS transistors are off, the R terminal in FIG. 20 is connected to the ground via the resistor R107.

Returning to FIG. 18, the non-inverting input terminal of the operational amplifier 604 is connected to the resistor R by the operation of the decoder circuit 606.
107 is connected to the ground. At this time, the potential of the non-inverting input terminal becomes VR due to the operation of the operational amplifier 604.
It becomes EF. Therefore, the current flowing through the resistor R107, that is, the P channel MOS transistor 605 is VREF / R
107 is obtained.

A product obtained by multiplying the current value by eight times the mirror ratio K is the P-channel MOS transistor 413 in FIG.
Current. That is, ID = 8K (VREF / R107) = Imin.

At this time, P-channel MOS transistor 4
The gate potential of No. 13 corresponds to V0 in FIG. Therefore, the following equation also holds. ID = 8Kβ (w / L) (V _GS0 −Vt) ² = Imin On the other hand, since the currents flowing through the resistors r0 to r15 are equal, the potential of each output voltage V0 to V15 in FIG.
And V15 are given as an interpolated relationship based on the potentials at both ends.

Similarly to the above discussion, in the LED driving transistor using the potentials V0 and V15,
The driving current is kept constant even when the temperature of the driver IC changes. On the other hand, an LED using the potential of V1 to V14
In the driving transistors, they are V0 and V15.
The driving current is kept substantially constant even if the temperature of the driver IC changes due to the interpolated relationship based on the potentials at both ends of the driving IC.

As described above, in the third embodiment, with respect to the LED driving based on the grayscale data, the correction data is used for the temperature rise of the driver IC which is generated by the driving of the LED. It is possible to keep the drive current correction ratio constant.

FIG. 22 shows the effect of the third embodiment. The relative change rate between the dot correction data input to the driver IC and the driving current obtained at that time is shown in FIG.
Was measured by changing the temperature. In FIG. 22, the temperature of the driver IC is 0 ° C., 25 ° C., 50 ° C., 7 ° C.
The measurement is performed while changing the temperature to 5 ° C. and 100 ° C.

As is apparent from FIG. 22, in the configuration of the present embodiment, even if the temperature of the driver IC changes, the problem that the drive current value changes due to the temperature change is almost eliminated. The above-described effect can be obtained not only when the change rate of the drive current value due to the change in the dot correction data is kept constant, but also when the chip correction data and the gradation data are similarly changed.

As is clear from the circuit system in the third embodiment, the circuit in the present embodiment is similar to the first and second embodiments in that the gradation data inputted to the LED head is not changed. In spite of this, the effect of correcting variations in LED production is kept unchanged. here,
More specifically, the effects described above are as follows.

At a certain temperature (for example, room temperature), the LED drive is performed by setting the gradation data of all the dots to “8”.
Measure the light emission power of the LED at that time, chip correction,
By properly determining dot correction data, LE
It is assumed that the light emission power of each dot of D is uniform. Next, it is assumed that the temperature of the LED head and, consequently, the driver IC has increased due to continuous printing. Let us assume that the light emission power of the LED is measured again under such a temperature rise.

At this time, each dot of the LED head has been corrected with the gradation data set to “8” at a certain temperature (for example, room temperature). Even when the temperature rises, the light emission power is uniform. It is kept in. Further, let us assume that the LED drive is performed while changing the gradation data of all the dots to “9”, and the emission power of the LED at that time is measured again. At this time, each dot of the LED head has been corrected by setting the gradation data to "7". However, even if the gradation data is changed to "9", there is a difference that the light emission power of the LED increases as a whole. Is also kept uniform.

In addition, even if the temperature of the driver IC changes, it is possible to add a new effect that the correction effect corrected at a certain temperature is maintained as it is.

In the first, second and third embodiments, the case of an electrophotographic printer using an LED as a light source as a drive circuit has been described. It can also be applied to the case of driving the columns of the display elements in.

[0126]

As described above in detail, according to the present invention, in addition to the chip correction and the dot correction for correcting the manufacturing variation of the LED, the LED driving current can be controlled by the gradation data consisting of 4 bits per pixel. Can be made variable. This makes it possible to correct the manufacturing variation of the LED by making the drive current variable, to correct the emission power of all the dots constituting the LED head to be constant, and to further correct each dot according to the gradation data. It is possible to change the density of print dots by making the drive current variable every time.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a driving device according to a first embodiment.

FIG. 2 is a circuit diagram illustrating a control voltage generation circuit according to the first embodiment.

FIG. 3 is a circuit diagram illustrating a decoder circuit according to the first embodiment.

FIG. 4 is a circuit diagram illustrating an analog multiplexer according to the first embodiment.

FIG. 5 is a circuit diagram showing a drive circuit according to the first embodiment.

FIG. 6 is a circuit diagram illustrating a control circuit according to the first embodiment.

FIG. 7 is a circuit diagram showing the operational amplifier according to the first embodiment.

FIG. 8 is a graph showing static characteristics of a P-channel MOS transistor.

FIG. 9 is a time chart illustrating a print data transfer method according to the first embodiment.

FIG. 10 is a time chart illustrating a method of transferring correction data according to the first embodiment.

FIG. 11 is a graph showing a relationship between an exposure energy amount and a print density.

FIG. 12 is a graph showing a relationship between gradation data and a drive current according to the first embodiment.

FIG. 13 is a circuit diagram illustrating a drive circuit according to a second embodiment.

FIG. 14 is a graph showing a relationship between an exposure energy amount and a print density.

FIG. 15 is a graph showing a relationship between gradation data and a drive current according to the second embodiment.

FIG. 16 is a graph showing static characteristics of a P-channel MOS transistor.

FIG. 17 is a graph illustrating a relationship between dot correction data and a drive current according to the first embodiment.

FIG. 18 is a circuit diagram illustrating a control voltage generation circuit according to a third embodiment.

FIG. 19 is a circuit diagram illustrating a decoder circuit according to a third embodiment.

FIG. 20 is a circuit diagram illustrating a decoder circuit according to a third embodiment.

FIG. 21 is a circuit diagram illustrating an operational amplifier according to a third embodiment.

FIG. 22 is a graph illustrating a relationship between dot correction data and drive current according to the third embodiment.

FIG. 23 is a block diagram showing a control circuit of a conventional electrophotographic printer.

FIG. 24 is a time chart showing print control of a conventional electrophotographic printer.

FIG. 25 is a view showing the structure of a conventional LED head.

FIG. 26 is a circuit diagram showing a conventional prebuffer circuit.

FIG. 27 is a time chart showing a conventional LED head drive control.

FIG. 28 is a time chart showing a driving current waveform of an LED.

FIG. 29 is a block diagram showing a configuration inside the LED head.

FIG. 30 is a circuit diagram showing a conventional prebuffer circuit and control voltage generation circuit.

FIG. 31 is a graph showing variations in LED light amounts.

[Explanation of symbols]

 200 Driver IC 205 Flip-flop circuit 206 Latch circuit 207 Latch circuit 208 Analog multiplexer 209 Drive circuit 213 Control voltage generation circuit 215 Control circuit 223 Decoder circuit

Claims (3)

(57) [Claims] 1. A driving device for driving a plurality of driven elements provided in a driving body, comprising: a plurality of driving elements for one driven element, wherein the plurality of driving elements are selectively driven by gradation data. A driving unit that drives the driven element, and a first correction unit that collectively corrects a driving current to all the driving elements of the driving body at a predetermined ratio based on first correction data; Second correction means for correcting a drive current to a plurality of drive elements at a predetermined ratio for each of the driven elements using second correction data, wherein the drive means performs the plurality of drive operations based on grayscale data. By selectively driving each of the elements at the respective predetermined ratios based on the first and second correction data, a current value flowing through the driven element can be varied at a predetermined ratio. Drive Location. 2. A driving apparatus for driving a plurality of driven elements provided in a driving body, wherein a first control value for selecting a first control value for correcting outputs of the plurality of driven elements as a whole of the driving body. And control value output means for outputting a plurality of second control values based on the first control value selected by the first selection means; and one of the plurality of second control values. A second selecting means for selecting a plurality of driven elements for each of the plurality of driven elements; and a plurality of driving elements for one driven element, wherein the plurality of driving elements are selectively driven by gradation data composed of a plurality of bits. And driving means for driving the driven element based on the second control value selected by the second selecting means, wherein the driving means changes the output range of the driven element in small steps. A drive device characterized by the above-mentioned. 3. A driving device for driving a plurality of driven elements provided in a driving body, wherein a first control value for selecting a first control value for correcting outputs of the plurality of driven elements as a whole of the driving body. And control value output means for outputting a plurality of second control values based on the first control value selected by the first selection means; and one of the plurality of second control values. A second selecting means for selecting a plurality of driven elements for each of the plurality of driven elements; and a plurality of driving elements for one driven element, wherein the plurality of driving elements are selectively driven by gradation data composed of a plurality of bits. And driving means for driving the driven element based on the second control value selected by the second selecting means, wherein the first control value is a reference current value, and A plurality of reference current value generating means for generating The second control value is a control voltage value, the control value output means is a control voltage value generation means for generating a control voltage value, and the control voltage value generation means is a series connection of a plurality of resistors. To generate a plurality of control voltage values, wherein the control voltage value generating means is inserted into the plurality of reference current value generating means to generate a plurality of control voltage values. Drive.