JP5476642B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a reference voltage generation circuit.

  As a method for generating a reference voltage (Vref) and a common voltage (Vcom) of an analog circuit, resistance division is often used (for example, see Non-Patent Document 1). This generation method has a small circuit scale and can be easily realized, but has low resistance to power transmitted with power from the power supply (Power Supply Rejection: PSR).

  In order to mitigate the effects of noise, the reference node from which the reference voltage or common voltage is output is not only connected to the capacitor inside the chip, but is often a capacitor with a large capacitance value provided outside the chip. Connected. In order to bring the potential of the reference node to a predetermined voltage level, it is necessary to charge this capacitor.

  For this reason, after the power-down of the analog circuit is released until the reference node potential reaches a predetermined voltage level, the charging time determined by the time constant based on the resistance value and the capacitance value, and the reference node potential at the predetermined voltage level. Time until asymptotic accuracy is required.

  Here, the period after the power-down is canceled until the potential of the reference node converges to a predetermined voltage level is a period during which the analog circuit does not operate with high accuracy. For this reason, the waiting time in a system including this analog circuit becomes a mute period in a system for music use, for example, and often becomes a problem. That is, this waiting time becomes very long, such as several seconds, as the capacitance value is set to be large for noise countermeasures, and the mute period at the start of the system increases, which causes a problem in system construction.

  An example of a configuration for shortening the time until the output voltage reaches a predetermined constant voltage by rapidly charging the noise prevention capacitor is disclosed in Japanese Patent Laid-Open No. 2006-42524 (Patent Document 1). Yes. That is, a constant voltage circuit that converts an input voltage into a predetermined constant voltage according to a control signal input from the outside and outputs the same, and converts the input voltage into a predetermined constant voltage according to the control signal. A constant voltage generating circuit section for outputting, a first capacitor connected to an output terminal of the constant voltage generating circuit section for outputting the constant voltage, a second capacitor for charging the first capacitor, and the control signal And a switch circuit unit that performs charge / discharge control of the second capacitor. The switch circuit unit applies the input voltage to the second capacitor to charge the second capacitor when the constant voltage generation circuit unit stops outputting the predetermined constant voltage by the control signal, and charges the second capacitor. Cut off the discharge to the first capacitor. When the constant voltage generation circuit starts to output a predetermined constant voltage in response to the control signal, the switch circuit block cuts off the application of the input voltage to the second capacitor and is charged to the second capacitor. The first capacitor is charged by discharging the electric charge to the first capacitor.

JP 2006-42524 A

"Delta-Sigma Data Converters Theory, Design, and Simulation", IEEE Press (ISBN 0-7803-1045-4)

  However, in the configuration described in Patent Document 1, a capacitor for quick charging is required separately, and there is a problem that the chip area increases or the number of external components of the chip increases.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of generating a voltage of a predetermined level at an early stage and preventing an increase in circuit scale. .

  In summary, a semiconductor device according to an embodiment of the present invention includes a resistor and a switch connected in series between a first power supply node and a reference node, or between the first power supply node and the reference node. A charge accelerating circuit that includes a connected transistor and that allows the capacitor to be charged faster than the reference voltage generation circuit by flowing a current from the first power supply node to the capacitor via the reference node.

  Further, in summary, the semiconductor device according to another embodiment of the present invention includes a first element that forms a path of a current flowing from the first power supply node to the reference node, and a current flowing from the reference node to the second power supply node. A reference voltage generation circuit for generating a reference voltage smaller than the first power supply voltage and larger than the second power supply voltage at the reference node, and a first and a first element in the first period. Two transistors are simultaneously turned on to pass a current from the first power supply node to the reference node via the first transistor, and a current is supplied from the reference node to the second power supply node via the second transistor. And a charge accelerating circuit that simultaneously turns off the first and second transistors in the second period.

  According to the embodiment of the present invention, the period for charging the capacitor can be shortened without separately providing a capacitor for rapid charging. Therefore, it is possible to generate a predetermined level of voltage early and to prevent an increase in circuit scale.

1 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the structure of the comparative example of the reference voltage generation part which concerns on the 1st Embodiment of this invention. FIG. 4 is a diagram illustrating each control signal and a reference node potential in the reference voltage generation unit 100. It is a figure which shows the structure of the reference voltage generation part which concerns on the 1st Embodiment of this invention. FIG. 3 is a diagram illustrating each control signal and a reference node potential in a reference voltage generation unit 101. It is a figure which shows the structure of the reference voltage generation part which concerns on the 2nd Embodiment of this invention. It is a figure which shows each control signal in the reference voltage production | generation part 102, a reference node potential, and an electric current. 3 is a diagram conceptually showing a layout of a reference voltage generation unit 102. FIG. 3 is a diagram conceptually illustrating another example of the layout of the reference voltage generation unit 102. FIG. It is a figure which shows the structure of the modification of the reference voltage generation part which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the modification of the reference voltage generation part which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the reference voltage generation part which concerns on the 3rd Embodiment of this invention. It is a figure which shows each control signal in the reference voltage generation part 103, a reference node electric potential, and an electric current. It is a figure which shows the structure of the modification of the reference voltage generation part which concerns on the 3rd Embodiment of this invention. FIG. 15 is a diagram illustrating each control signal, reference node potential, and current in the reference voltage generation unit illustrated in FIG. 14. It is a figure which shows the structure of the reference voltage generation part which concerns on the 4th Embodiment of this invention. It is a figure which shows the structure of the reference voltage generation part which concerns on the 5th Embodiment of this invention. It is a figure which shows each control signal and reference node electric potential in the reference voltage production | generation part 105. FIG. 3 is a diagram conceptually showing a layout of a reference voltage generation unit 105. FIG. It is a figure which shows the structure of the reference voltage generation part which concerns on the 6th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a diagram showing a configuration of a semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 1, a semiconductor device 201 includes an A / D converter 1, a signal processing unit 2, a D / A converter 3, a logic controller 4, reference voltage generating units 101A and 101B, and external terminals. EXTIN, EXTOUT, EXTC1, EXTC2, and EXTC3.

  Capacitors C <b> 1 and C <b> 2 are provided outside the semiconductor device 201. Capacitor C1 has a first end connected to external terminal EXTC1 and a second end connected to ground node Vss. Capacitor C2 has a first end connected to external terminals EXTC2 and EXTC3, and a second end connected to ground node Vss. Capacitance values of the capacitors C1 and C2 are, for example, about 100 μF.

  The reference voltage generation units 101A and 101B generate reference voltages Vref1 and Vref2, respectively.

  The A / D converter 1 converts an analog signal AIN received from the outside via the external terminal EXTIN into a digital signal and outputs the digital signal to the signal processing unit 2. The A / D converter 1 performs the analog / digital conversion using the reference voltage Vref1 received from the reference voltage generation unit 101A. The analog signal AIN is, for example, a signal obtained by digital / analog conversion of music media reproduction data. Specifically, the A / D converter 1 includes an operational amplifier (so-called operational amplifier). A reference voltage Vref1 is applied to one input terminal of the operational amplifier, and an analog signal is applied to the other input terminal.

  The signal processing unit 2 performs various signal processing on the digital signal received from the A / D converter 1 and outputs the digital signal obtained by this signal processing to the D / A converter 3.

  The D / A converter 3 converts the digital signal received from the signal processing unit 2 into an analog signal AOUT, and outputs the analog signal AOUT to the outside via the external terminal EXTOUT. The D / A converter 3 performs the digital / analog conversion using the reference voltage Vref2 received from the reference voltage generation unit 101B via the external terminals EXTC2 and EXTC3. Specifically, the D / A converter 3 includes an operational amplifier (so-called operational amplifier). A reference voltage Vref2 is applied to one input terminal of the operational amplifier, and an analog signal is applied to the other input terminal.

  The logic controller 4 controls each functional block in the semiconductor device 201. The logic controller 4 outputs a control signal such as a power down signal to the A / D converter 1, the signal processing unit 2, the D / A converter 3, the logic controller 4, and the reference voltage generation units 101A and 101B.

  Hereinafter, each of the reference voltage generation units 101A and 101B may be referred to as a reference voltage generation unit 101. Further, each of the capacitors C1 and C2 may be referred to as a capacitor C. In addition, each of external terminals EXTC1 and EXTC2 may be referred to as external terminal EXTC. In addition, each of the reference voltages Vref1 and Vref2 may be referred to as a reference voltage Vref.

[Comparative example (reference voltage generator 100)]
FIG. 2 is a diagram showing a configuration of a comparative example of the reference voltage generation unit according to the first embodiment of the present invention.

  Referring to FIG. 2, reference voltage generation unit 100 includes a reference voltage generation circuit 11. Reference voltage generation circuit 11 includes resistors R1 and R2 and switches SW1 and SW2. The reference voltage generation unit 100 is a comparative example of the reference voltage generation units 101A and 101B in the semiconductor device 201.

  In FIG. 2, PD indicates a power down signal output from the logic controller 4. PDB represents a signal obtained by inverting the logic level of the power-down signal PD.

  Reference voltage generation unit 100 has a reference node Ref to which capacitor C is to be electrically connected. The reference voltage generation circuit 11 is connected between a power supply node Vdd supplied with the power supply voltage Vdd and a ground node Vss supplied with a ground voltage Vss lower than the power supply voltage Vdd. The reference voltage generation circuit 11 charges the capacitor C by flowing a current from the power supply node Vdd to the reference node Ref, and sets the potential of the reference node Ref to a predetermined voltage level. The voltage at the reference node Ref is the reference voltage Vref.

  The resistor R1 and the switch SW1 are connected in series between the power supply node Vdd and the reference node Ref. The resistor R2 and the switch SW2 are connected in series between the ground node Vss and the reference node Ref. More specifically, switch SW1 has a first end connected to power supply node Vdd and a second end. Resistor R1 has a first end connected to the second end of switch SW1 and a second end connected to external terminal EXTC via reference node Ref. Resistor R2 has a first end connected to external terminal EXTC via reference node Ref, and a second end. Switch SW2 has a first end connected to the second end of resistor R2, and a second end connected to ground node Vss.

  The switch SW1 is a P-channel MOS transistor, for example, and is turned on when the power down signal PDB is at a logic low level and turned off when the power down signal PDB is at a logic high level. Switch SW2 is an N-channel MOS transistor, for example, and is turned on when power down signal PD is at a logic high level and turned off when at a logic low level.

  Each of the resistor R1 and the resistor R2 has a sufficiently large resistance value so that power consumption can be reduced in a normal time after the reference node Ref has converged to a predetermined level.

  FIG. 3 is a diagram illustrating each control signal and reference node potential in the reference voltage generation unit 100.

  Referring to FIG. 3, at time t1, power down is released, power down signal PD transitions to a logic high level, and power down signal PDB transitions to a logic low level. Then, the switches SW1 and SW2 are turned on, whereby a current flows from the power supply node Vdd to the reference node Ref via the resistor R1, the capacitor C is charged, and the potential of the reference node Ref becomes the resistance value of the resistor R1 and the resistor R2. It is controlled to a voltage value determined by a ratio of resistance values.

  The period T1 for charging the capacitor C and the potential of the reference node Ref are accurately set to the predetermined voltage level after the power-down of the reference voltage generation unit 100 is released until the potential of the reference node Ref reaches the predetermined voltage level. A period T2 until asymptotically well is required, and a long time is required.

  Here, the length of the period T1 is determined by a time constant based on a resistance value and a capacitance value. That is, if the resistance values of the resistors R1 and R2 are R1 and R2, and the capacitance value of the capacitor C is C, this time constant is determined by (R1 // R2) × C. However, (R1 // R2) indicates a parallel combined resistance value of the resistors R1 and R2.

  The waiting time, that is, the periods T1 and T2 in the system including the reference voltage generation unit 100 becomes a mute period in a system for music use, for example, and often becomes a problem. This waiting time becomes very long, such as several seconds, as the capacitance value of the capacitor C is set to be large for noise countermeasures, and the mute period at the start of the system increases, which causes a problem in system construction.

  The reference voltage generation unit 101 according to the first embodiment of the present invention solves the problems of the reference voltage generation unit 100 as described above.

[Reference Voltage Generation Unit 101]
Next, the reference voltage generation unit according to the first embodiment of the present invention will be described with reference to the drawings. In the first embodiment of the present invention, the same or corresponding parts as those of the reference voltage generation unit 100 are denoted by the same reference numerals as those of the reference voltage generation unit 100, and description thereof will not be repeated. That is, it is the same as the reference voltage generation unit 100 except for the contents described below.

FIG. 4 is a diagram showing a configuration of the reference voltage generation unit according to the first embodiment of the present invention.
Referring to FIG. 4, reference voltage generation unit 101 further includes a charge acceleration circuit 10 as compared to reference voltage generation unit 100. The charge acceleration circuit 10 includes a resistor R11 and a switch SW11. In FIG. 4, STUP_P indicates a control signal output from the logic controller 4.

  The charge acceleration circuit 10 is connected between the power supply node Vdd and the reference node Ref. The charge accelerating circuit 10 can charge the capacitor C faster than the reference voltage generation circuit 11 by flowing a current from the power supply node Vdd to the capacitor C via the reference node Ref.

  The resistor R11 is connected in parallel with the resistor R1 and the switch SW1 between the power supply node Vdd and the reference node Ref, and has a resistance value smaller than that of the resistor R1. The switch SW11 is connected in series with the resistor R11 between the power supply node Vdd and the reference node Ref. More specifically, switch SW11 has a first end connected to power supply node Vdd and a second end. The resistor R11 has a first end connected to the second end of the switch SW11 and a second end connected to the external terminal EXTC via the reference node Ref.

  The switch SW11 is a P-channel MOS transistor, for example, and is turned on when the control signal STUP_P is at a logic low level and turned off when the control signal STUP_P is at a logic high level.

  FIG. 5 is a diagram illustrating each control signal and reference node potential in the reference voltage generation unit 101.

  Referring to FIG. 5, charge accelerating circuit 10 includes reference voltage generation circuit 11 from power supply node Vdd via reference node Ref in period T1 during which capacitor C is charged so that the potential of reference node Ref reaches a predetermined voltage level. To pass a current through the capacitor C. For example, the charging acceleration circuit 10 starts a current supply operation to the capacitor C in synchronization with the power-down cancellation, that is, when the control signal STUP_P changes from the logic high level to the logic low level. Then, the charge accelerating circuit 10 stops the operation of flowing a current to the capacitor C after the potential of the reference node Ref reaches a predetermined voltage level.

  More specifically, at time t1, the power down is released, the power down signal PD transitions to a logic high level, the power down signal PDB transitions to a logic low level, and the control signal STUP_P transitions to a logic low level. Then, the switches SW1 and SW2 are turned on, whereby a current flows from the power supply node Vdd to the reference node Ref via the resistor R1, the capacitor C is charged, and the potential of the reference node Ref becomes the resistance value of the resistor R1 and the resistor R2. It is controlled to a voltage value determined by a ratio of resistance values. Further, when the switch SW11 is turned on, a current flows from the power supply node Vdd to the reference node Ref via the resistor R11, and the capacitor C is charged. That is, in the period T1 from time t1 to time t2, the reference node Ref is charged by the reference voltage generation circuit 11 and the charge acceleration circuit 12.

  Next, at time t2 when the potential of the reference node Ref has sufficiently increased, the control signal STUP_P transitions to a logic high level. Then, the switch SW11 is turned off, and the current supply to the capacitor C by the charge acceleration circuit 10 is stopped. At this time, the potential of the reference node Ref remains controlled to be a predetermined voltage level by the reference voltage generation circuit 11, and the potential of the reference node Ref converges to the predetermined voltage level at time t3. A period T2 from time t2 to time t3 is a convergence period of the reference node Ref to a predetermined level.

  By the way, in the configuration described in Patent Document 1, a capacitor for quick charging is required separately, and there is a problem that the chip area increases or the number of external components of the chip increases. However, in the reference voltage generation unit according to the first embodiment of the present invention, the charge accelerating circuit 10 causes a current to flow from the power supply node Vdd to the capacitor C via the reference node Ref, so that the reference voltage generation unit 11 is more than the reference voltage generation circuit 11. The capacitor C is charged quickly. With such a configuration, a period T1 for charging the capacitor C can be shortened as compared with the reference voltage generation unit 100 as shown in FIG. Therefore, the reference voltage generation unit according to the first embodiment of the present invention can generate a voltage of a predetermined level at an early stage and prevent an increase in circuit scale.

  In the reference voltage generation unit 101 according to the first embodiment of the present invention, the charge accelerating circuit 10 includes a resistor R11 and a switch SW11 connected in series between the power supply node Vdd and the reference node Ref. Although there is, it is not limited to this. The charge accelerating circuit 10 may include an N-channel MOS transistor M15 connected in series between a power supply node Vdd and a reference node Ref, as shown in FIG. The N channel MOS transistor M15 also serves as the resistor R11 and the switch SW11.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a semiconductor device in which the configuration of the charge acceleration circuit is changed as compared with the semiconductor device according to the first embodiment. The contents other than those described below are the same as those of the semiconductor device according to the first embodiment.

  Compared with the reference voltage generation unit 100, the reference voltage generation unit 101 can shorten the period T1 for charging the capacitor C. However, it is difficult for the reference voltage generation unit 101 to control the charge level of the capacitor C. For example, as shown in FIG. 5, overcharge or the like may occur, and the period T2 until the potential of the reference node Ref converges to a predetermined voltage level may become longer.

  The reference voltage generation unit 102 according to the second embodiment of the present invention solves the problems of the reference voltage generation unit 101 as described above.

[Reference voltage generator 102]
Next, a reference voltage generation unit according to a second embodiment of the present invention will be described with reference to the drawings. Note that in the second embodiment of the present invention, the same or corresponding parts as those of the reference voltage generation unit 101 are denoted by the same reference numerals as those of the reference voltage generation unit 100, and description thereof will not be repeated. That is, it is the same as the reference voltage generation unit 101 except for the contents described below.

FIG. 6 is a diagram illustrating a configuration of a reference voltage generation unit according to the second embodiment of the present invention.
Referring to FIG. 6, reference voltage generation unit 102 includes charge acceleration circuit 12 instead of charge acceleration circuit 10, as compared to reference voltage generation unit 101. The charge acceleration circuit 12 includes resistors R11 and R12 and switches SW11 and SW12.

  The resistor R1 (first element) is connected between the power supply node Vdd to which the power supply voltage Vdd is supplied and the reference node Ref to which the capacitor C is to be electrically connected. The resistor R1 forms a path for a current flowing from the power supply node Vdd to the reference node Ref. The resistor R2 (second element) is connected between the reference node Ref and the ground node Vss to which the ground voltage Vss is supplied. The resistor R2 forms a path for a current flowing from the reference node Ref to the ground node Vss. The reference voltage generation circuit 11 generates a reference voltage smaller than the power supply voltage Vdd and larger than the ground voltage Vss at the reference node Ref.

In FIG. 6, STUP_N indicates a control signal output from the logic controller 4.
The charge acceleration circuit 12 is connected between the power supply node Vdd and the ground node Vss. The charge accelerating circuit 12 can charge the capacitor C faster than the reference voltage generation circuit 11 by flowing a current from the power supply node Vdd to the capacitor C via the reference node Ref. Furthermore, when charging the capacitor C, the charging acceleration circuit 12 branches the current from the power supply node Vdd to the capacitor C and the ground node Vss (via the resistor R12).

  The resistor R11 is connected in parallel with the resistor R1 and the switch SW1 between the power supply node Vdd and the reference node Ref, and has a resistance value smaller than that of the resistor R1. The resistor R12 is connected in parallel with the resistor R2 between the ground node Vss and the reference node Ref, and has a resistance value smaller than that of the resistor R2. The switch SW11 is connected in series with the resistor R11 between the power supply node Vdd and the reference node Ref. The switch SW12 is connected in series with the resistor R12 between the ground node Vss and the reference node Ref. More specifically, switch SW11 has a first end connected to power supply node Vdd and a second end. The resistor R11 has a first end connected to the second end of the switch SW11 and a second end connected to the external terminal EXTC via the reference node Ref. Resistor R12 has a first end connected to external terminal EXTC via reference node Ref, and a second end. Switch SW12 has a first end connected to the second end of resistor R12, and a second end connected to ground node Vss.

  The switch SW11 is a P-channel MOS transistor, for example, and is turned on when the control signal STUP_P is at a logic low level and turned off when the control signal STUP_P is at a logic high level. The switch SW12 is, for example, an N-channel MOS transistor, and is turned on when the control signal STUP_N is at a logic high level and turned off when the control signal STUP_N is at a logic low level.

  FIG. 7 is a diagram illustrating each control signal, reference node potential, and current in the reference voltage generation unit 102.

  In FIG. 7, I1 indicates a current flowing through the resistor R1 from the power supply node Vdd toward the reference node Ref, I11 indicates a current flowing through the resistor R11 from the power supply node Vdd toward the reference node Ref, and I2 indicates a reference. A current flowing through the resistor R2 from the node Ref to the ground node Vss is shown, and I12 denotes a current flowing through the resistor R12 from the reference node Ref to the ground node Vss.

  Referring to FIG. 7, current I11 flowing through switch SW11 in period T1 is larger than current I1 flowing through resistor R1 in period T2. Further, the current I12 flowing through the switch SW12 in the period T1 is larger than the current I2 flowing through the resistor R2 in the period T2.

  When the currents I1 and I2 are saturated, they have the same current value i1. Further, when the currents I11 and I12 are saturated, they have the same current value i0.

  The charge accelerating circuit 12 simultaneously turns on the switches SW11 and SW12 in the period T1 to flow a current from the power supply node Vdd to the reference node Ref via the switch SW11 and to supply a current from the reference node Ref to the ground node Vss via the switch SW12. Shed. In addition, the charging acceleration circuit 12 turns off the switches SW11 and SW12 at the same time in the period T2.

  More specifically, the charge accelerating circuit 12 is connected to the capacitor from the power supply node Vdd via the reference node Ref in the period T1 in which the reference voltage generation circuit 11 charges the capacitor C so that the potential of the reference node Ref reaches a predetermined voltage level. Current is passed to C. For example, the charge accelerating circuit 12 supplies current to the capacitor C in synchronization with the power-down cancellation, that is, when the control signal STUP_P changes from a logic high level to a logic low level and the control signal STUP_N changes from a logic low level to a logic high level. Start operation. Then, the charge accelerating circuit 12 stops the operation of passing a current to the capacitor C after the potential of the reference node Ref reaches a predetermined voltage level.

  Further, when the power-down is instructed again and the reference voltage generation circuit 11 stops the operation of flowing the current to the reference node Ref, the charge acceleration circuit 12 causes the current to flow from the capacitor C to the ground node Vss through the resistor R12. Capacitor C is discharged. Thereby, the discharge of the capacitor C can be accelerated.

  More specifically, at time t1, the power-down is released, the power-down signal PD transitions to a logic high level, the power-down signal PDB transitions to a logic low level, and the control signal STUP_P transitions to a logic low level. The signal STUP_N transitions to a logic high level. Then, the switches SW1 and SW2 are turned on, whereby a current flows from the power supply node Vdd to the reference node Ref via the resistor R1, the capacitor C is charged, and the potential of the reference node Ref becomes the resistance value of the resistor R1 and the resistor R2. It is controlled to a voltage value determined by a ratio of resistance values. Further, when the switches SW11 and SW12 are turned on, a current flows from the power supply node Vdd via the resistor R11 to the reference node Ref, the capacitor C is charged, and the potential of the reference node Ref becomes the resistance value of the resistor R11 and the resistor R12. It is controlled to a voltage value determined by a ratio of resistance values. That is, in the period T1 from time t1 to time t2, the reference node Ref is charged toward the predetermined voltage level by the reference voltage generation circuit 11 and the charge acceleration circuit 12.

  Next, at time t2 when the potential of the reference node Ref sufficiently rises, the control signal STUP_P transitions to a logic high level, and the control signal STUP_N transitions to a logic low level. Then, the switches SW11 and SW12 are turned off, and the current supply to the capacitor C by the charge acceleration circuit 12 is stopped. At this time, the potential of the reference node Ref remains controlled to be a predetermined voltage level by the reference voltage generation circuit 11, and the potential of the reference node Ref converges to the predetermined voltage level at time t3.

  Next, at time t4, power down is instructed again, the power down signal PD transits to a logic low level, the power down signal PDB transits to a logic high level, and the control signal STUP_N transits to a logic high level. Then, the switches SW1 and SW2 are turned off, and the potential control of the reference node Ref by the reference voltage generation circuit 11 is stopped. In addition, when the switch SW11 is turned on while the switch SW11 is turned off, the charge stored in the capacitor C is discharged to the ground node Vss via the external terminal EXTC, the resistor R12, and the switch SW12.

  Next, at time t5 when the charge of the capacitor C is sufficiently discharged, the control signal STUP_N transitions to a logic low level. Then, the switch SW12 is turned off, and the discharging operation of the capacitor C by the charge acceleration circuit 12 is stopped.

  The charge accelerating circuit 12 has the same circuit configuration as the reference voltage generation circuit 11, and allows a larger amount of current to flow to the reference node Ref for a certain period after the power-down is canceled. For example, when the charge accelerating circuit 12 is configured using a plurality of resistance elements connected in series as shown in FIG. 6, the resistance ratio in the charge accelerating circuit 12 is substantially the same as the resistance ratio of the reference voltage generating circuit 11. The circuit constants are set so as to have a resistance value lower than that of the reference voltage generation circuit 11. That is, regarding the resistance value, the resistance R1 is larger than the resistance R11, and the resistance R2 is larger than the resistance R12. Regarding the resistance value, the ratio of the resistance R2 to the resistance R1 is substantially equal to the ratio of the resistance R12 to the resistance R11.

  Specifically, assuming that the resistance values of the resistors R1, R2, R11, and R12 are R1, R2, R11, and R12, respectively, the relationship of R1: R2 = R11: R12, R11 << R1, and R12 << R2 is satisfied. Thus, the resistance values of the resistors R1, R2, R11, and R12 are set.

  As described above, in the reference voltage generation unit 102, the charging acceleration circuit 12 has a resistance ratio substantially the same as the resistance ratio of the reference voltage generation circuit 11, and therefore, at time t2, the potential of the reference node Ref immediately after the charging acceleration is set to a predetermined value. It becomes possible to accurately control the level, that is, a value close to the originally expected voltage value. Therefore, the period T2 until the potential of the reference node Ref is set to a predetermined level can be shortened.

  Therefore, in the semiconductor device according to the second embodiment of the present invention, the external capacitor connected to the reference node Ref can be rapidly charged, and the potential of the reference node Ref immediately after the rapid charge is set to a predetermined voltage level. Since it becomes possible to control to a close value, the waiting time when the system is constructed can be shortened.

  At first glance, the PMOS transistor M1 and NMOS transistor M3 in FIG. 2 of Patent Document 1 correspond to the switches SW11 and SW12 shown in FIG. However, in FIG. 2 of Patent Document 1, when the PMOS transistor M1 and the NMOS transistor M3 are turned on, the NMOS transistor M2 is in the off state, so that the supply node of the input voltage Vdd passes through the PMOS transistor M1 and the NMOS transistor M2. Thus, there is no path for flowing current to the node B corresponding to the reference node Ref.

  On the other hand, in reference voltage generation unit 102, capacitor C is charged by a current flowing from power supply node Vdd through switch SW11 and resistor R11. When only the path of the switch SW11 and the resistor R11 is provided as in the reference voltage generation unit 101 illustrated in FIG. 4, if the capacitor C is charged too much, the reference node Ref exceeds a predetermined voltage level, and the charge acceleration circuit 10 is not turned on. It takes time for the reference voltage generation circuit 11 to return the reference node Ref to a predetermined voltage level after activation (after t2 in FIG. 5).

  On the other hand, in the reference voltage generation unit 102, a current flows from the power supply node Vdd through the switch SW11 and the resistor R11 to the reference node Ref, and at the same time, a route from the reference node Ref to the ground node Vss through the resistor R12 and the switch SW12. The overcharge can be suppressed by passing the current.

  The reference voltage generation unit according to the second embodiment of the present invention is applied to, for example, a circuit block that generates a reference voltage for an A / D converter and a D / A converter, and is particularly suitable for high precision A / D such as for audio. It is effective for D converters and D / A converters.

FIG. 8 is a diagram conceptually showing the layout of the reference voltage generation unit 102.
Referring to FIG. 8, resistance R1 includes a plurality of unit resistance elements UR arranged in the horizontal direction of the drawing, and each unit resistance element UR is connected via a wiring LN. Similarly, the resistor R2 includes a plurality of unit resistance elements UR arranged in the horizontal direction of the drawing, and each unit resistance element UR is connected via a wiring LN. The unit resistance elements UR of the resistors R1 and R2 are arranged in alignment in the horizontal direction on the paper surface.

  Unit resistance elements UR having the same shape as the resistors R1 and R2 are arranged as the resistors R11 and R12. Thereby, the potential shift due to the mismatch of the unit resistance elements can be alleviated, and the charge / discharge time of the capacitor C can be accelerated.

  The resistor R11 is arranged on the left side of the resistor R1 in alignment with each unit resistance element UR of the resistor R1. The resistor R12 is arranged on the right side of the resistor R2 in alignment with the unit resistor elements UR of the resistor R2.

  The switches SW1 and SW11 are constituted by transistors having a gate electrode G, for example, and are arranged in the vicinity of the resistors R1 and R11 so as to be aligned in the horizontal direction in the drawing. The switches SW2 and SW12 are constituted by, for example, a transistor having a gate electrode G, and are arranged in the vicinity of the resistors R2 and R12 so as to be aligned in the horizontal direction on the paper surface.

  The resistor R1, the resistor R11, the switch SW1, and the switch SW11, and the resistor R2, the resistor R12, the switch SW2, and the switch SW12 are arranged in line symmetry with respect to the wiring LN corresponding to the reference node Ref.

  With the above layout, the reference voltage generation unit 102 can be realized with a small area.

FIG. 9 is a diagram conceptually illustrating another example of the layout of the reference voltage generation unit 102.
Referring to FIG. 9, reference voltage generating unit 102 has a plurality of polysilicon layers arranged side by side. The plurality of polysilicon layers constitute resistors R1, R2, R11, and R12 and dummy elements DM1 to DM6 disposed so as to sandwich the resistors R1, R2, R11, and R12. That is, the reference voltage generation unit 102 includes dummy elements DM1 to DM3 arranged in the vicinity of the resistor R1, and dummy elements DM4 to DM6 arranged in the vicinity of the resistor R2. The dummy elements DM1 to DM3 are arranged in alignment with the unit resistance elements UR of the resistor R1 on the left side of the resistor R1. The dummy elements DM4 to DM6 are arranged on the right side of the resistor R2 in alignment with the unit resistance elements UR of the resistor R2. The resistor R11 is formed by a dummy element DM3 that is closest to the resistor R1. The resistor R12 is formed by a dummy element DM6 that is closest to the resistor R2.

  As described above, the configuration using the dummy element makes it possible to generate the reference voltage with high accuracy. Further, by using the dummy elements for the resistors R11 and R12, the reference voltage generating unit 102 can be realized with a small area.

  Since other configurations and operations are the same as those of the semiconductor device according to the first embodiment, detailed description thereof will not be repeated here.

  The dummy elements DM1 to DM6 are connected to the ground node Vss, but may be connected to the power supply node Vdd.

  Further, the arrangement of the switches and the resistors in the reference voltage generation unit is not limited to the arrangement shown in FIG. 6, and may be as shown in FIGS. 10 and 11 below, for example.

  FIG. 10 is a diagram illustrating a configuration of a modification of the reference voltage generation unit according to the second embodiment of the present invention.

  Referring to FIG. 10, this reference voltage generation unit has a configuration that does not include switch SW <b> 2, as compared with reference voltage generation unit 102. With such a configuration, noise generated by the switch can be reduced.

  FIG. 11 is a diagram showing a configuration of a modification of the reference voltage generation unit according to the second embodiment of the present invention.

  Referring to FIG. 11, in reference voltage generation circuit 11, resistor R1 has a first end connected to power supply node Vdd, and a second end. Switch SW1 has a first end connected to the second end of resistor R1, and a second end connected to external terminal EXTC via reference node Ref. Switch SW2 has a first end connected to external terminal EXTC via reference node Ref, and a second end. Resistor R2 has a first end connected to the second end of switch SW2 and a second end connected to ground node Vss.

  In charge accelerating circuit 12, resistor R11 has a first end connected to power supply node Vdd, and a second end. Switch SW11 has a first end connected to the second end of resistor R11, and a second end connected to external terminal EXTC via reference node Ref. Switch SW12 has a first end connected to external terminal EXTC via reference node Ref, and a second end. Resistor R12 has a first end connected to the second end of switch SW12, and a second end connected to ground node Vss.

  Thus, by arranging each switch on the reference node Ref side, it is possible to reduce noise generated by each switch.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Third Embodiment>
The present embodiment relates to a semiconductor device in which a method for realizing a reference voltage generation unit is changed as compared with the semiconductor device according to the second embodiment. The contents other than those described below are the same as those of the semiconductor device according to the second embodiment.

FIG. 12 is a diagram illustrating a configuration of a reference voltage generation unit according to the third embodiment of the present invention.
Referring to FIG. 12, reference voltage generation unit 103 includes a reference voltage generation circuit 31, a charge acceleration circuit 13, and an interface circuit 21. Reference voltage generating circuit 31 includes P channel MOS transistors M1, M3 and N channel MOS transistors M2, M4, M5, M6. Charge acceleration circuit 13 includes P-channel MOS transistors M11 and M13 and N-channel MOS transistors M12, M14, M15, and M16. Interface circuit 21 includes diodes D1 and D2 and resistor R21. The reference voltage generation unit 103 is not limited to a configuration including a MOS transistor, and may be a configuration including a field effect transistor.

  The chip in the semiconductor device according to the third embodiment of the present invention is provided with a pad PDC, and this pad PDC is connected to an external terminal EXTC provided in the package of the semiconductor device through wire bonding.

  In reference voltage generation circuit 31, P channel MOS transistor M1 has a source connected to power supply node Vdd, a drain, and a gate for receiving power down signal PDB. N channel MOS transistor M2 has a drain connected to the drain of P channel MOS transistor M1, a source connected to ground node Vss, and a gate for receiving power down signal PDB. P-channel MOS transistor M3 has a source connected to reference node Ref, a drain, and a gate for receiving power-down signal PDB. N channel MOS transistor M4 has a drain connected to the drain of P channel MOS transistor M3, a source connected to ground node Vss, and a gate for receiving power down signal PDB. N-channel MOS transistor M5 (first element) has a drain connected to power supply node Vdd, a source connected to reference node Ref, and a gate connected to the drain of P-channel MOS transistor M1. N-channel MOS transistor M6 (second element) has a drain connected to reference node Ref, a source connected to ground node Vss, and a gate connected to the drain of P-channel MOS transistor M3.

  In charge accelerating circuit 13, P-channel MOS transistor M11 has a source connected to power supply node Vdd, a drain, and a gate for receiving control signal STUP_P. N-channel MOS transistor M12 has a drain connected to the drain of P-channel MOS transistor M11, a source connected to ground node Vss, and a gate for receiving control signal STUP_P. P-channel MOS transistor M13 has a source connected to reference node Ref, a drain, and a gate for receiving control signal STUP_N. N-channel MOS transistor M14 has a drain connected to the drain of P-channel MOS transistor M13, a source connected to ground node Vss, and a gate for receiving control signal STUP_N. N-channel MOS transistor M15 has a drain connected to power supply node Vdd, a source connected to reference node Ref, and a gate connected to the drain of P-channel MOS transistor M11. N-channel MOS transistor M16 has a drain connected to reference node Ref, a source connected to ground node Vss, and a gate connected to the drain of P-channel MOS transistor M13.

  In interface circuit 21, diode D1 has a cathode connected to power supply node Vdd and an anode connected to pad PDC. Diode D2 has a cathode connected to pad PDC and an anode connected to ground node Vss. Resistor R21 has a first end connected to reference node Ref and a second end connected to pad PDC.

  Each of P-channel MOS transistor M5 and N-channel MOS transistor M6 has a sufficiently large on-resistance value so that power consumption can be reduced in a normal time after reference node Ref has converged to a predetermined level.

  FIG. 13 is a diagram illustrating each control signal, reference node potential, and current in the reference voltage generation unit 103.

  In FIG. 13, I5 indicates a current flowing through the N channel MOS transistor M5 from the power supply node Vdd toward the reference node Ref, and I15 indicates a current flowing through the N channel MOS transistor M15 from the power supply node Vdd toward the reference node Ref. I6 indicates a current flowing through the N channel MOS transistor M6 from the reference node Ref to the ground node Vss, and I16 indicates a current flowing through the N channel MOS transistor M16 from the reference node Ref to the ground node Vss.

  Referring to FIG. 13, current I15 flowing through N channel MOS transistor M15 in period T1 is larger than current I5 flowing through N channel MOS transistor M5 in period T2. The current I16 flowing through the N channel MOS transistor M16 in the period T1 is larger than the current I6 flowing through the N channel MOS transistor M6 in the period T2.

  When the currents I5 and I6 are saturated, they have the same current value i1. Further, when the currents I15 and I16 are saturated, they have the same current value i0.

  Charge accelerating circuit 13 forms a connection path between power supply node Vdd and the control electrode of N channel MOS transistor M15 in period T1, and forms a connection path between reference node Ref and the control electrode of N channel MOS transistor M16. That is, charge accelerating circuit 13 causes N channel MOS transistors M15 and M16 to conduct simultaneously in period T1 so that current flows from power supply node Vdd to reference node Ref via N channel MOS transistor M15 and through N channel MOS transistor M16. Then, a current flows from the reference node Ref to the ground node Vss. In addition, charging acceleration circuit 13 simultaneously turns off N-channel MOS transistors M15 and M16 during period T2.

  More specifically, at time t1, the power down is released, the power down signal PDB transitions to a logic low level, the control signal STUP_P transitions to a logic low level, and the control signal STUP_N transitions to a logic low level. Then, N channel MOS transistors M5 and M6 are diode-connected. That is, since the P-channel MOS transistor M1 is turned on and the N-channel MOS transistor M2 is turned off, the N-channel MOS transistor M5 is turned on. Since P channel MOS transistor M3 is turned on and N channel MOS transistor M4 is turned off, N channel MOS transistor M6 is turned on. As a result, a current flows from power supply node Vdd to reference node Ref via N channel MOS transistor M5, capacitor C is charged, and the potential of reference node Ref is set to the ON resistance value of N channel MOS transistor M5 and the N channel MOS transistor. It is controlled to a voltage value determined by the ratio of the on-resistance value of M6.

  N channel MOS transistors M15 and M16 are diode-connected, respectively. That is, since the P-channel MOS transistor M11 is turned on and the N-channel MOS transistor M12 is turned off, the N-channel MOS transistor M15 is turned on. Since P channel MOS transistor M13 is turned on and N channel MOS transistor M14 is turned off, N channel MOS transistor M16 is turned on. As a result, a current flows from power supply node Vdd to reference node Ref via N channel MOS transistor M15, capacitor C is charged, and the potential of reference node Ref is set to the ON resistance value of N channel MOS transistor M15 and the N channel MOS transistor. It is controlled to a voltage value determined by the ratio of the on-resistance value of M16.

  That is, in the period T1 from time t1 to time t2, the reference node Ref is charged toward the predetermined voltage level by the reference voltage generation circuit 31 and the charge acceleration circuit 13.

  Next, at time t2 when the potential of the reference node Ref has sufficiently increased, the control signal STUP_P transitions to a logic high level, and the control signal STUP_N transitions to a logic high level. Then, P channel MOS transistor M11 is turned off and N channel MOS transistor M12 is turned on, so that N channel MOS transistor M15 is turned off. Since P channel MOS transistor M13 is turned off and N channel MOS transistor M14 is turned on, N channel MOS transistor M16 is turned off. Thereby, the current supply to the capacitor C by the charging acceleration circuit 13 is stopped. At this time, the potential of the reference node Ref remains controlled to be a predetermined voltage level by the reference voltage generation circuit 31, and the potential of the reference node Ref converges to the predetermined voltage level at time t3.

  Next, at time t4, power down is instructed again, the power down signal PDB transitions to a logic high level, and the control signal STUP_N transitions to a logic low level. Then, P channel MOS transistor M1 is turned off and N channel MOS transistor M2 is turned on, so that N channel MOS transistor M5 is turned off. Since P channel MOS transistor M3 is turned off and N channel MOS transistor M4 is turned on, N channel MOS transistor M6 is turned off. Thereby, the potential control of the reference node Ref by the reference voltage generation circuit 31 is stopped. N channel MOS transistor M16 is diode-connected. That is, since the P-channel MOS transistor M13 is turned on and the N-channel MOS transistor M14 is turned off, the N-channel MOS transistor M16 is turned on. When N channel MOS transistor M16 is turned on while N channel MOS transistor M15 is turned off, the charge stored in capacitor C is transferred to ground node Vss via external terminal EXTC, pad PDC, interface circuit 21 and N channel MOS transistor M16. Is discharged.

  Next, at time t5 when the charge of the capacitor C is sufficiently discharged, the control signal STUP_N transitions to a logic high level. Then, N channel MOS transistor M16 is turned off, and the discharging operation of capacitor C by charging acceleration circuit 13 is stopped.

  The charge accelerating circuit 13 has the same circuit configuration as the reference voltage generation circuit 31, and allows a larger amount of current to flow to the reference node Ref for a certain period after the power-down is canceled. For example, when the charge acceleration circuit 13 is configured by using a plurality of transistors connected in series as shown in FIG. 10, the charge acceleration circuit 13 has a resistance ratio substantially the same as the resistance ratio of the reference voltage generation circuit 31. The circuit constant is set so as to have a resistance value lower than that of the reference voltage generation circuit 31.

  Specifically, assuming that the on-resistance values of the N-channel MOS transistors M5, M6, M15, and M16 are R5, R6, R15, and R16, respectively, R5: R6 = R15: R16, R15 << R5, and R16 << R6 The on-resistance values of N-channel MOS transistors M5, M6, M15, and M16 are set so as to satisfy this relationship.

  That is, regarding the value of (gate length / gate width), N-channel MOS transistor M15 is smaller than N-channel MOS transistor M5, and N-channel MOS transistor M16 is smaller than N-channel MOS transistor M6. Regarding the value of (gate length / gate width), the ratio of N channel MOS transistor M16 to N channel MOS transistor M15 is substantially equal to the ratio of N channel MOS transistor M6 to N channel MOS transistor M5.

  Specifically, when the gate widths of the N-channel MOS transistors M5, M6, M15, and M16 are W5, W6, W15, and W16, and the gate lengths are L5, L6, L15, and L16, respectively, L5 / W5: L6 / W6 = L15 / W15: The gate widths of the N-channel MOS transistors M5, M6, M15, and M16 so as to satisfy the relations of L16 / W16, L15 / W15 << L5 / W5, and L16 / W16 << L6 / W6 The gate length is set.

  As described above, in the reference voltage generation unit 103, the charging acceleration circuit 13 has a resistance ratio substantially the same as the resistance ratio of the reference voltage generation circuit 31, and therefore, at time t2, the potential of the reference node Ref after the acceleration of charging is set to a predetermined value. It becomes possible to accurately control the level, that is, a value close to the originally expected voltage value. Therefore, the period T2 until the potential of the reference node Ref is set to a predetermined level can be shortened.

  Therefore, in the reference voltage generation unit according to the third embodiment of the present invention, the external capacitor connected to the reference node Ref can be rapidly charged, and the potential of the reference node Ref immediately after the quick charge is set to a predetermined voltage. Since it becomes possible to control the value close to the level, the waiting time when the system is constructed can be shortened.

  At first glance, the PMOS transistor M1 and the NMOS transistor M3 in FIG. 2 of Patent Document 1 correspond to the N-channel MOS transistors M15 and M16 shown in FIG. However, in FIG. 2 of Patent Document 1, when the PMOS transistor M1 and the NMOS transistor M3 are turned on, the NMOS transistor M2 is in the off state, so that the supply node of the input voltage Vdd passes through the PMOS transistor M1 and the NMOS transistor M2. Thus, there is no path for flowing current to the node B corresponding to the reference node Ref.

  On the other hand, in reference voltage generation unit 103, capacitor C is charged by a current flowing from power supply node Vdd through N channel MOS transistor M15. When only the path of the switch SW11 and the resistor R11 is provided as in the reference voltage generation unit 101 illustrated in FIG. 4, if the capacitor C is charged too much, the reference node Ref exceeds a predetermined voltage level, and the charge acceleration circuit 10 is not turned on. It takes time for the reference voltage generation circuit 11 to return the reference node Ref to a predetermined voltage level after activation (after t2 in FIG. 5).

  In contrast, in reference voltage generation unit 103, a current flows from power supply node Vdd through N channel MOS transistor M15 to reference node Ref, and at the same time, a path from reference node Ref to N channel MOS transistor M16 to ground node Vss. The overcharge can be suppressed by passing the current. The same applies to each reference voltage generation unit shown in FIGS.

  In the reference voltage generation unit 103, the N-channel MOS transistors M 5, M 6, M 15, and M 16 also serve as a switch for performing power down by using a diode-connected transistor. Thus, there is no need to provide a separate switch. As a result, an error in the on-resistance of the switch can be removed, so that the potential of the reference node Ref can be accelerated and charged to a value closer to a desired level.

  In FIG. 12, N channel MOS transistors M15 and M16 are each shown as one transistor. However, N channel MOS transistors M15 and M16 may each be composed of a plurality of transistors connected in parallel. For example, when each of the N-channel MOS transistors M15 and M16 is composed of a plurality of transistors connected in parallel, the above-mentioned “L5 / W5: L6 / W6 = L15 / W15: L16 / W16, L15 / W15 << L5 / W5 , And L16 / W16 << L6 / W6 ", the effective gate length and gate width will be compared.

  For example, when L15 / W15 = 1/20, if N transistors are connected in parallel as the N-channel MOS transistor M15 and (gate length / gate width) = 1/4 of each transistor, effective L15 / W W15 is 1/20.

  FIG. 14 is a diagram illustrating a configuration of a modification of the reference voltage generation unit according to the third embodiment of the present invention.

  Referring to FIG. 14, the reference voltage generation unit has a configuration in which the gates of P channel MOS transistor M3 and N channel MOS transistor M4 in reference voltage generation circuit 31 do not receive power down signal PDB and are connected to ground node Vss. It is.

  P-channel MOS transistor M3 is always on, and N-channel MOS transistor M4 is always off.

  Thereby, when capacitor C is discharged, current can flow to ground node Vss via P-channel MOS transistor M3 and N-channel MOS transistor M4, so that the discharge time of capacitor C can be shortened.

  FIG. 15 is a diagram showing each control signal, reference node potential, and current in the reference voltage generation unit shown in FIG.

  Referring to FIG. 15, the reference voltage generation unit shown in FIG. 14 may employ the power down signal and the control signal as shown in FIG. 13, but as described above, P channel MOS transistor M3 and N channel MOS Since a current can flow through the transistor M4 to the ground node Vss, it is not necessary to shift the control signal STUP_N to a logic high level at time t4. Thereby, the control of the logic controller 4 can be simplified.

  Further, after time t4, the N-channel MOS transistor M6 having a small current driving capability flows a current I6 for discharging the capacitor C, so that the waveform of the reference node Ref becomes gentle compared to FIG. 13, that is, the reference node Ref. The potential drop of becomes more moderate as compared with FIG.

  Since other configurations and operations are the same as those of the semiconductor device according to the second embodiment, detailed description thereof will not be repeated here.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Fourth embodiment>
The present embodiment relates to a semiconductor device in which the configuration of the reference voltage generation unit is changed as compared with the semiconductor device according to the third embodiment. The contents other than those described below are the same as those of the semiconductor device according to the third embodiment.

FIG. 16 is a diagram illustrating a configuration of a reference voltage generation unit according to the fourth embodiment of the present invention.
Referring to FIG. 16, reference voltage generation unit 104 includes a reference voltage generation circuit 32, charge acceleration circuit 14, and interface circuits 21 and 22. Reference voltage generating circuit 32 includes a P-channel MOS transistor M21, a resistor R24 (first element), and a resistor R25 (second element). Compared to charge acceleration circuit 13, charge acceleration circuit 14 further includes a resistor R 26 connected between the source of N channel MOS transistor 15 and reference node Ref.

  The chips in the semiconductor device according to the fourth embodiment of the present invention are provided with pads PDC1 and PDC2, and the pads PDC1 and PDC2 are connected to external terminals EXTC11 and EXTC12 provided in the package of the semiconductor device through wire bonding. Each is connected. Capacitor C has a first end connected to external terminals EXTC11 and EXTC12, and a second end connected to ground node Vss.

  In reference voltage generation circuit 32, P channel MOS transistor M21 has a source connected to power supply node Vdd, a drain, and a gate for receiving power down signal PDB. Resistor R24 has a first end connected to the drain of P-channel MOS transistor M21, and a second end connected to reference node Ref. Resistor R25 has a first end connected to reference node Ref and a second end connected to ground node Vss.

  In interface circuit 21, diode D1 has a cathode connected to power supply node Vdd and an anode connected to pad PDC1. Diode D2 has a cathode connected to pad PDC1 and an anode connected to ground node Vss. Resistor R21 has a first end connected to reference node Ref and a second end connected to pad PDC1.

  In interface circuit 22, diode D3 has a cathode connected to power supply node Vdd and an anode connected to pad PDC2. Diode D4 has a cathode connected to pad PDC2 and an anode connected to ground node Vss. Resistor R22 has a first end and a second end connected to pad PDC2. The voltage at the first end of the resistor R22 is the reference voltage Vref.

  Each of resistor R24 and resistor R25 has a sufficiently large resistance value so that power consumption can be reduced in a normal time after reference node Ref has converged to a predetermined level. Resistor R24 and resistor R25 have resistance values larger than the on-resistance values of N-channel MOS transistors M15 and M16. Resistor R24 and resistor R25 have, for example, substantially the same resistance value. The resistor R26 is provided to correct the influence of the on-resistance of the P-channel MOS transistor M21, and has a resistance value much smaller than that of the resistors R24 and R25. If necessary, the resistor R26 may be eliminated and the N-channel MOS transistor M15 may be directly connected to the reference node Ref.

  Each control signal and reference node potential in the reference voltage generation unit 104 are the same as those shown in FIG. The operation of the reference voltage generation unit 104 will be described only with respect to differences from the reference voltage generation unit 103 with reference to FIG.

  Referring to FIG. 13, at time t1, power down is released, power down signal PDB transitions to a logic low level, control signal STUP_P transitions to a logic low level, and control signal STUP_N transitions to a logic low level. Then, when P channel MOS transistor M21 is turned on, a current flows from power supply node Vdd to P node MOS transistor M21 and resistor R24 to reference node Ref, capacitor C is charged, and the potential of reference node Ref The voltage value is determined by the ratio of the resistance value of R24 and the resistance value of resistor R25.

  Next, at time t4, power down is instructed again, the power down signal PD transitions to a logic low level, the power down signal PDB transitions to a logic high level, and the control signal STUP_N transitions to a logic low level. Then, P channel MOS transistor M21 is turned off, and the potential control of reference node Ref by reference voltage generating circuit 32 is stopped.

  Since other configurations and operations are the same as those of the semiconductor device according to the third embodiment, detailed description thereof will not be repeated here.

  In the case where a potential of Vdd / 2 is generated as the reference voltage Vref by resistance division, a configuration like the reference voltage generation unit 104 can be adopted.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Fifth embodiment>
The present embodiment relates to a semiconductor device in which the configuration of the charge acceleration circuit is changed as compared with the semiconductor device according to the second embodiment. The contents other than those described below are the same as those of the semiconductor device according to the second embodiment.

  In the reference voltage generation unit 102, although the influence due to the variation of the resistance elements is allowed to some extent, it is difficult to match the on-resistance of each switch, and thus it is difficult to set the value of the reference voltage Vref accurately. There is.

  The reference voltage generation unit 105 according to the fifth embodiment of the present invention solves the problems of the reference voltage generation unit 102 as described above.

  In the fifth embodiment of the present invention, the same or corresponding parts as those of the reference voltage generation unit 102 are denoted by the same reference numerals as those of the reference voltage generation unit 102, and description thereof will not be repeated. That is, it is the same as the reference voltage generation unit 102 except for the contents described below.

FIG. 17 is a diagram illustrating a configuration of a reference voltage generation unit according to the fifth embodiment of the present invention.
Referring to FIG. 17, reference voltage generation unit 105 includes charge acceleration circuit 15 instead of charge acceleration circuit 12, as compared with reference voltage generation unit 102. The charge acceleration circuit 15 includes replica circuits K1 to Kn. Each of the replica circuits K1 to Kn has the same circuit configuration and the same circuit constant as the reference voltage generation circuit 11, and is connected in parallel to each other. Replica circuits K1-Kn are connected between power supply node Vdd and ground node Vss.

  FIG. 18 is a diagram illustrating each control signal and reference node potential in the reference voltage generation unit 105.

  Referring to FIG. 18, at time t1, power down is released, power down signal PD transitions to logic high level, power down signal PDB transitions to logic low level, and control signal STUP_P transitions to logic low level. , The control signal STUP_N transits to a logic high level. Then, the switches SW1 and SW2 are turned on, whereby a current flows from the power supply node Vdd to the reference node Ref via the resistor R1, the capacitor C is charged, and the potential of the reference node Ref becomes the resistance value of the resistor R1 and the resistor R2. It is controlled to a voltage value determined by a ratio of resistance values. Further, when the switches SW11 and SW12 in each of the replica circuits K1 to Kn are turned on, a current flows from the power supply node Vdd to the reference node Ref via the resistor R11 in each of the replica circuits K1 to Kn, and the capacitor C is charged. The potential of the reference node Ref is controlled to a voltage value determined by the ratio of the resistance value of the resistor R11 and the resistance value of the resistor R12. That is, in the period T1 from time t1 to time t2, the reference node Ref is charged toward the predetermined voltage level by the reference voltage generation circuit 11 and the charge acceleration circuit 15.

  Next, at time t2 when the potential of the reference node Ref sufficiently rises, the control signal STUP_P transitions to a logic high level, and the control signal STUP_N transitions to a logic low level. Then, the switches SW11 and SW12 in each of the replica circuits K1 to Kn are turned off, and the current supply to the capacitor C by the charge acceleration circuit 15 is stopped. At this time, the potential of the reference node Ref remains controlled to be a predetermined voltage level by the reference voltage generation circuit 11, and the potential of the reference node Ref converges to the predetermined voltage level at time t3.

  Next, at time t4, power down is instructed again, the power down signal PD transits to a logic low level, the power down signal PDB transits to a logic high level, and the control signal STUP_N transits to a logic high level. Then, the switches SW1 and SW2 are turned off, and the potential control of the reference node Ref by the reference voltage generation circuit 11 is stopped. Further, when the switch SW12 is turned on in the state where the switch SW11 in each of the replica circuits K1 to Kn is turned off, the charge stored in the capacitor C is transferred to the external terminal EXTC, the resistor R12 and the switch SW12 in each of the replica circuits K1 to Kn. To the ground node Vss.

  Next, at time t5 when the charge of the capacitor C is sufficiently discharged, the control signal STUP_N transitions to a logic low level. Then, the switch SW12 in each of the replica circuits K1 to Kn is turned off, and the discharging operation of the capacitor C by the charging acceleration circuit 15 is stopped.

FIG. 19 is a diagram conceptually showing the layout of the reference voltage generation unit 105.
Referring to FIG. 19, the resistor R1 includes a plurality of unit resistance elements UR arranged in the horizontal direction on the paper surface, and each unit resistance element UR is connected via a wiring LN. Similarly, the resistor R2 includes a plurality of unit resistance elements UR arranged in the horizontal direction of the drawing, and each unit resistance element UR is connected via a wiring LN. The unit resistance elements UR of the resistors R1 and R2 are arranged in alignment in the horizontal direction on the paper surface.

  In each of the replica circuits K1 to Kn, a plurality of unit resistance elements UR having the same shape as the resistors R1 and R2 and arranged in the horizontal direction of the drawing are arranged as resistors R11 and R12. Thereby, the potential shift due to the mismatch of the unit resistance elements can be alleviated, and the charge / discharge time of the capacitor C can be accelerated.

  The reference voltage generation circuit 11 and the replica circuits K1 to Kn are connected to each other via a wiring LN corresponding to the reference node Ref, a wiring LN corresponding to the power supply node Vdd, and a wiring LN corresponding to the ground node Vss. Are arranged in line.

  The switches SW1 and SW11 are constituted by transistors having a gate electrode G, for example, and are arranged near the resistors R1 and R11, respectively. The switches SW2 and SW12 are constituted by transistors having a gate electrode G, for example, and are arranged in the vicinity of the resistors R2 and R12, respectively.

  In the reference voltage generation circuit 11, the resistor R1 and the switch SW1, and the resistor R2 and the switch SW2 are arranged symmetrically with respect to the wiring LN corresponding to the reference node Ref. In each of the replica circuits K1 to Kn, the resistor R11 and the switch SW11, and the resistor R12 and the switch SW12 are arranged symmetrically with respect to the wiring LN corresponding to the reference node Ref.

  Since other configurations and operations are the same as those of the semiconductor device according to the second embodiment, detailed description thereof will not be repeated here.

  In the reference voltage generation unit according to the fifth embodiment of the present invention, the replica circuit K1 to Kn is used as the charge accelerating circuit 15 so that the potential of the reference node Ref immediately after the charge acceleration depends on conditions such as process and temperature. The desired potential can be set without doing so. That is, as compared with the reference voltage generation unit 102, the potential of the reference node Ref immediately after the acceleration of charging can be controlled with higher accuracy, and the waiting time when the system is constructed can be shortened. Further, the discharge time can be further shortened by increasing the number of discharge paths.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Sixth Embodiment>
The present embodiment relates to a semiconductor device in which the configuration of the charge acceleration circuit is changed as compared with the semiconductor device according to the third embodiment. The contents other than those described below are the same as those of the semiconductor device according to the third embodiment.

  In the reference voltage generation units 103 and 104, ON resistance can be adjusted under standard process conditions, but an error due to process variation may occur. That is, it may be difficult to accurately match the set potential of the reference node Ref by the reference voltage generation circuit 11 and the set potential of the reference node Ref by the charge acceleration circuit 10.

  The reference voltage generation unit 105 according to the sixth embodiment of the present invention solves the problems of the reference voltage generation units 103 and 104 as described above.

  In the sixth embodiment of the present invention, the same or corresponding parts as those of the reference voltage generation unit 103 are denoted by the same reference numerals as those of the reference voltage generation unit 103, and description thereof will not be repeated. That is, it is the same as the reference voltage generation unit 103 except for the contents described below.

FIG. 20 is a diagram illustrating a configuration of a reference voltage generation unit according to the sixth embodiment of the present invention.
Referring to FIG. 20, reference voltage generation unit 106 includes charge acceleration circuit 16 instead of charge acceleration circuit 13, as compared with reference voltage generation unit 103. The charge acceleration circuit 16 includes replica circuits K1 to Kn. Each of the replica circuits K1 to Kn has the same circuit configuration and the same circuit constant as the reference voltage generation circuit 31, and is connected in parallel to each other. Replica circuits K1-Kn are connected between power supply node Vdd and ground node Vss.

  Each control signal and reference node potential in the reference voltage generation unit 106 are the same as those shown in FIG. The operation of the reference voltage generation unit 106 will be described with reference to FIG.

  Referring to FIG. 13, at time t1, power down is released, power down signal PDB transitions to a logic low level, control signal STUP_P transitions to a logic low level, and control signal STUP_N transitions to a logic low level. Then, N channel MOS transistors M5 and M6 are diode-connected. That is, since the P-channel MOS transistor M1 is turned on and the N-channel MOS transistor M2 is turned off, the N-channel MOS transistor M5 is turned on. Since P channel MOS transistor M3 is turned on and N channel MOS transistor M4 is turned off, N channel MOS transistor M6 is turned on. As a result, a current flows from power supply node Vdd to reference node Ref via N channel MOS transistor M5, capacitor C is charged, and the potential of reference node Ref is set to the ON resistance value of N channel MOS transistor M5 and the N channel MOS transistor. It is controlled to a voltage value determined by the ratio of the on-resistance value of M6.

  N channel MOS transistors M15 and M16 in each of replica circuits K1 to Kn are diode-connected. That is, since the P-channel MOS transistor M11 is turned on and the N-channel MOS transistor M12 is turned off, the N-channel MOS transistor M15 is turned on. Since P channel MOS transistor M13 is turned on and N channel MOS transistor M14 is turned off, N channel MOS transistor M16 is turned on. As a result, a current flows from power supply node Vdd to reference node Ref via N channel MOS transistor M15 in each of replica circuits K1 to Kn, capacitor C is charged, and the potential of reference node Ref becomes the same as that of N channel MOS transistor M15. It is controlled to a voltage value determined by the ratio between the on-resistance value and the on-resistance value of N channel MOS transistor M16.

  That is, in the period T1 from time t1 to time t2, the reference node Ref is charged toward the predetermined voltage level by the reference voltage generation circuit 11 and the charge acceleration circuit 16.

  Next, at time t2 when the potential of the reference node Ref has sufficiently increased, the control signal STUP_P transitions to a logic high level, and the control signal STUP_N transitions to a logic high level. Then, in each of replica circuits K1 to Kn, P channel MOS transistor M11 is turned off and N channel MOS transistor M12 is turned on, so that N channel MOS transistor M15 is turned off. In each of replica circuits K1 to Kn, P channel MOS transistor M13 is turned off and N channel MOS transistor M14 is turned on, so that N channel MOS transistor M16 is turned off. Thereby, the current supply to the capacitor C by the charge acceleration circuit 16 is stopped. At this time, the potential of the reference node Ref remains controlled to be a predetermined voltage level by the reference voltage generation circuit 31, and the potential of the reference node Ref converges to the predetermined voltage level at time t3.

  Next, at time t4, power down is instructed again, the power down signal PDB transitions to a logic high level, and the control signal STUP_N transitions to a logic low level. Then, P channel MOS transistor M1 is turned off and N channel MOS transistor M2 is turned on, so that N channel MOS transistor M5 is turned off. Since P channel MOS transistor M3 is turned off and N channel MOS transistor M4 is turned on, N channel MOS transistor M6 is turned off. Thereby, the potential control of the reference node Ref by the reference voltage generation circuit 31 is stopped. N-channel MOS transistor M16 in each of replica circuits K1 to Kn is diode-connected. That is, since the P-channel MOS transistor M13 is turned on and the N-channel MOS transistor M14 is turned off, the N-channel MOS transistor M16 is turned on. When the N-channel MOS transistor M16 is turned on while the N-channel MOS transistor M15 is turned off, the charge stored in the capacitor C is transferred to the N-channel in each of the external terminal EXTC, the pad PDC, the interface circuit 21, and the replica circuits K1 to Kn. Discharge to ground node Vss through MOS transistor M16.

  Next, at time t5 when the charge of the capacitor C is sufficiently discharged, the control signal STUP_N transitions to a logic high level. Then, N channel MOS transistor M16 in each of replica circuits K1 to Kn is turned off, and discharging operation of capacitor C by charging acceleration circuit 16 is stopped.

  Since other configurations and operations are the same as those of the semiconductor device according to the third embodiment, detailed description thereof will not be repeated here.

  In the reference voltage generation unit according to the sixth embodiment of the present invention, the replica circuit K1 to Kn is used as the charge accelerating circuit 16 so that the potential of the reference node Ref immediately after the charge acceleration depends on conditions such as process and temperature. The desired potential can be set without doing so. That is, as compared with the reference voltage generation unit 103, the potential of the reference node Ref immediately after the acceleration of charging can be controlled with higher accuracy, and the waiting time when the system is constructed can be shortened. Further, the discharge time can be further shortened by increasing the number of discharge paths.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 A / D converter, 2 signal processing unit, 3 D / A converter, 4 logic controller, 10, 12, 14, 15, 16 charge acceleration circuit, 11, 32 reference voltage generation circuit, 21, 22 interface circuit, 31 reference voltage generation circuit, 100, 101A, 101B, 102, 103, 104, 105, 106 reference voltage generation unit, 201 semiconductor device, EXTIN, EXTOUT, EXTC, EXTC1, EXTC2, EXTC11, EXTC12 external terminals, R1, R2, R11, R12, R21, R24, R25, R26 resistance, SW1, SW2, SW11, SW12 switch, UR unit resistance element, LN wiring, DM1-DM6 dummy element, M1, M3, M11, M13, M21 P-channel MOS transistor, M2, M4, M5, M6, M 12, M14, M15, M16 N-channel MOS transistor, D1-D4 diode, PDC, PDC1, PDC2 pad, K1-Kn replica circuit.

Claims (15)

A capacitor is connected between a first power supply node to which a first power supply voltage is supplied and a second power supply node to which a second power supply voltage lower than the first power supply voltage is supplied. A reference voltage generation circuit for charging the capacitor by causing a current to flow to a reference node to be electrically connected to bring the potential of the reference node to a predetermined voltage level;
A resistor and a switch connected in series between the first power supply node and the reference node, or a transistor connected between the first power supply node and the reference node; A charge accelerating circuit capable of charging the capacitor faster than the reference voltage generating circuit by flowing a current to the capacitor via a node ;
With
The charge acceleration circuit includes:
A semiconductor device connected between the first power supply node and the second power supply node, wherein when charging the capacitor, a current from the first power supply node is branched to flow to the capacitor and the second power supply node. . A capacitor is connected between a first power supply node to which a first power supply voltage is supplied and a second power supply node to which a second power supply voltage lower than the first power supply voltage is supplied. A reference voltage generation circuit for charging the capacitor by causing a current to flow to a reference node to be electrically connected to bring the potential of the reference node to a predetermined voltage level;
A resistor and a switch connected in series between the first power supply node and the reference node, or a transistor connected between the first power supply node and the reference node; A charge accelerating circuit capable of charging the capacitor faster than the reference voltage generating circuit by flowing a current to the capacitor via a node;
With
The charge acceleration circuit includes:
The reference voltage generation circuit allows a current to flow through the capacitor during a period of charging the capacitor to cause the reference node potential to reach a predetermined voltage level, and after the reference node potential reaches the predetermined voltage level, A semiconductor device that stops an operation of passing a current to a capacitor. The charge acceleration circuit includes:
2. The semiconductor according to claim 1 , wherein after the reference voltage generation circuit stops an operation of flowing a current to the reference node, the capacitor is discharged by flowing a current from the capacitor to the second power supply node through the capacitor. apparatus. The charge acceleration circuit includes:
4. The semiconductor device according to claim 1 , comprising a plurality of circuits connected in parallel to each other having the same circuit configuration and the same circuit constant as the reference voltage generation circuit. 5. A first power supply node to which a first power supply voltage is supplied and a reference node to which a capacitor is to be electrically connected are connected, and a first current path is formed from the first power supply node to the reference node. And a second element that is connected between the reference node and a second power supply node to which a second power supply voltage is supplied, and that forms a path of current flowing from the reference node to the second power supply node. A reference voltage generation circuit that generates a reference voltage that is smaller than the first power supply voltage and larger than the second power supply voltage at the reference node;
A first transistor connected between the first power supply node and the reference node in parallel with the first element; and between the reference node and the second power supply node in parallel with the second element. A second transistor connected to the first transistor, and in the first period, the first transistor and the second transistor are simultaneously turned on to pass a current from the first power supply node to the reference node via the first transistor. through the second transistor supplying a current to said second power supply node from the reference node with flow comprises a charging accelerating circuit to simultaneously non-conducting said first and second transistors in the second period, the Semiconductor device. The current flowing through the first transistor during the first period is greater than the current flowing through the first element during the second period, and the current flowing through the second transistor during the first period is The semiconductor device according to claim 5 , wherein the semiconductor device has a current larger than a current flowing through the second element in a second period. The semiconductor device according to claim 5, wherein the first transistor and the second transistor are field effect transistors of the same conductivity type. The charge accelerating circuit forms a connection path between the first power supply node and the control electrode of the first transistor in the first period, and a connection path between the reference node and the control electrode of the second transistor. The semiconductor device according to claim 7 , wherein: The charge acceleration circuit includes:
A third transistor having a first conduction electrode connected to the first power supply node and a second conduction electrode connected to a control electrode of the first transistor;
A first conduction electrode connected to the control electrode of the first transistor; a second conduction electrode connected to the second power supply node; and a control electrode connected to the control electrode of the third transistor. A fourth transistor;
A fifth transistor having a first conduction electrode connected to the reference node and a second conduction electrode connected to a control electrode of the second transistor;
Having said a first conducting electrode coupled to the control electrode of the second transistor, and a second conductive electrode coupled to said second power supply node, and said fifth control electrode and a control electrode connected to the transistor The semiconductor device according to claim 5 , comprising a sixth transistor. The charge acceleration circuit includes:
A first resistance element connected in series with the first transistor between the first power supply node and the reference node;
The semiconductor device according to claim 5 , further comprising: a second resistance element connected in series with the second transistor between the reference node and the second power supply node. The first and second elements are third and fourth resistance elements, respectively.
11. The semiconductor device according to claim 10 , wherein the third resistance element is larger than the first resistance element and the fourth resistance element is larger than the second resistance element with respect to a resistance value. The semiconductor device according to claim 11 , wherein the ratio of the fourth resistance element to the third resistance element is substantially equal to the ratio of the second resistance element to the first resistance element with respect to a resistance value. The semiconductor device includes a plurality of polysilicon layers arranged side by side,
Wherein the plurality of polysilicon layers constituting the first to fourth resistive elements, and a plurality of dummy elements arranged so as to sandwich the first to fourth resistive elements, and claim 11 Semiconductor device. The first and second transistors are first and second field effect transistors, respectively.
The first and second elements are third and fourth field effect transistors, respectively;
Relates the value of (a gate length / gate width), the first field effect transistor is smaller than the third field effect transistor, said second field effect transistor is the fourth field effect transistor is less than, claim 5 Alternatively, the semiconductor device according to claim 6 . Regarding the value of (gate length / gate width), the ratio of the second field effect transistor to the first field effect transistor is substantially equal to the ratio of the fourth field effect transistor to the third field effect transistor. The semiconductor device according to claim 14 .

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