JPH06104654A - Signal output circuit - Google Patents

Abstract

PURPOSE:To reduce power noise by connecting a resistor and a capacitor in parallel with a ground side of a discharge transistor(TR) when a charge stored in a load is discharged to allow the output circuit to cope with a periodic input voltage change. CONSTITUTION:A drain of a discharge TR N3 is connected to outputs of buffer TRs N1, N2, a discharge signal DIS is inputted to its gate, a resistor R and a capacitor C connected in parallel are connected to the source, and the other terminal of the resistor R and the capacitor C is connected to ground. After an output voltage in response to an input voltage VIN is charged in a capacitive load 1, the discharge signal DIS is set to a VDD level in response to a change in the periodic input voltage VIN to turn on the discharge TR N3 thereby discharging the charge stored in the load 1. In this case, a current is not steeply supplied from the load 1 to ground by the time constant comprising the resistance R and the capacitance C.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal output circuit for outputting a drive signal to a capacitive load such as a liquid crystal display device.

[0002]

2. Description of the Related Art The structure of a conventional signal output circuit is shown in FIG. In the figure, N1 and N2 are N-channel transistors of a buffer including a source follower, N3 is a discharge transistor, 1 is a capacitive load, and 2 is an output terminal. The discharge transistor N3 is a capacitive load 1
It is for discharging the electric charge charged in the.

Conventionally, a voltage corresponding to the input voltage VIN is output and the capacitive load 1 is charged. Note that Vb is a bias voltage. Then, in order to respond to the periodical change of the input voltage VIN, the discharge signal DIS is set to VD.
The discharge transistor N3 is turned on at the D level to discharge the charge accumulated in the load 1.

[0004]

However, in the above-mentioned conventional signal output circuit, when the load is discharged, if the discharge transistor is made large and a large current is made to flow in order to shorten the discharge period, the current is reduced. Since a current several times the value output flows into the brand at once, there is a drawback that large power supply noise occurs.

An object of the present invention is to solve the above problems and to provide a signal output circuit with less power supply noise.

[0006]

In order to achieve the above object, the signal output circuit of the present invention is a signal output circuit having a discharge transistor, wherein a resistor and a capacitor are connected in parallel to the ground side of the discharge transistor. The other end of the resistor and the capacitor is connected to the ground.

[0007]

[Operation] When the output voltage corresponding to the input voltage is output and the load is charged and then the charge accumulated in the load is discharged in order to respond to the change in the input voltage, when the resistor and the capacitor are connected in parallel. Due to the constant, excessive current does not flow sharply and power supply noise is reduced.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a signal output circuit according to the present invention. In the figure, N1 and N2 are N-channel transistors (VIN is an input voltage, Vb is a bias voltage) of a buffer including a source follower, N3 is a discharge transistor (DIS is a discharge signal), 1 is a capacitive load, and 2 is an output terminal. Is. The discharge transistor N3 is for discharging the electric charge charged in the capacitive load 1. A resistor R and a capacitor C are connected in parallel on the ground side of the discharge transistor N3, and the other ends of the resistor R and the capacitor C are branded. It is connected to the. That is, the drain of the discharge transistor N3 is connected to the output of the buffer (N1, N2), the discharge signal DIS is input to the gate, and the resistor R and the capacitor C connected in parallel are connected to the source side. The other ends of the resistor R and the capacitor C are connected to the ground. For the resistor R,
It can also be realized with a transistor.

Next, the operation of the signal output circuit will be described. After the capacitive load 1 is charged with the output voltage corresponding to the input voltage VIN, the discharge signal DIS is set to the VDD level in response to the periodic change of the input voltage, the discharge transistor N3 is turned on, and the load 1 is loaded. Discharge the accumulated charge. At this time, due to the time constant of the resistor R and the capacitor C connected in parallel, the current from the load 1 to the ground does not steeply flow at the time of discharging, so that the power supply noise can be reduced.

[0011]

As described above in detail, according to the signal output circuit of the present invention, when the charge accumulated in the load is discharged in order to deal with the periodic change of the input voltage, By connecting a resistor and a capacitor in parallel to the ground side, an excessive current does not flow steeply, and it is possible to reduce power supply noise.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a signal output circuit according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a conventional signal output circuit.

[Explanation of symbols]

 N3 discharge transistor R resistance C capacitor

Claims (1)

[Claims] 1. A signal output circuit having a discharge transistor, wherein a resistor and a capacitor are connected in parallel to the ground side of the discharge transistor, and the other ends of the resistor and the capacitor are connected to the ground. Signal output circuit.