JP3636736B2 - Voltage memory circuit - Google Patents

Description

【０１３２】
次に、動作の第２位相に於いて、第１位相で生成されたデジタルデータに基づいて、入力電圧Ｖ_i は、次の表２に図示される式に依ってＶ_i と関連するアナログ変換電圧Ｖ_C を生成するために変換される。
【０１３３】
【表２】

【０１３４】
次の変換動作で、このアナログ変換電圧Ｖ_C はアナログ入力電圧として用いられ、変換電圧Ｖ_C は次の該動作に於いてゼロに収斂する。各々次の変換動作は３ステート・ロジックデジタルデータ（＋１、０、−１）の１つの“ビット”を生成す。通常の２進（２ステート）論理で表される出力ワードは適切なデジタル論理回路に依る組み合わせの３ステート・ビットの全てから導かれ、Ｒ・３ステート・ビットは（Ｒ＋１）ビットから成る２進論理出力ワードを生成することができる。
【０１３５】
従来の３ステート・ロジックＡＤＣの動作の詳細な説明については、K. Gotoh とO.Kobayashi に依る“Fujitsu Fact: ３ステート・ロジックはMB87020に用いられているCMOSサイクルA/Dコンバーターを制御する”と前述のEP−B −0214831 に記載されていて、その文書は共にここで参照されている。
図１０のＡＤＣは直列に接続されているＮ個の電圧変換ステージＳＴ₁ 、ＳＴ₂ 、…ＳＴ_N を搭載していて、その各々が表１と２から前述の電圧変換動作を行うことができる。ＡＤＣの最初の２つの該電圧変換ステージＳＴ₁ とＳＴ₂ だけ図１０に図示されている。
【０１３６】
ステージＳＴ_i の各々は図９用いて既に説明されたように一般的に倍電圧回路５０′に基づいていて、倍電圧回路５０′の入力ノードＩ₁ とＩ₂ はステージの入力ノードを与え、倍電圧回路５０′の入力ノードＯ₁ とＯ₂ は同様にステージの出力ノードを与える。
各々ステージＳＴ_i の倍電圧回路５０′は、しかし、図９の回路の１つのスイッチエレメント５５の代わりに、倍電圧回路５０′が、回路の２つの電圧記憶回路ＶＳＣ₁ とＶＳＣ₂ の各々の共通ターミナルＣＯＭ₁ とＣＯＭ₂ の間に直列に接続されている、２つの制御可能なスイッチエレメント５５と５６と電圧調整手段５８を搭載しているところが、図９の倍電圧回路と異なっている。
【０１３７】
各々ステージＳＴ_i に於いて、スイッチエレメント５１乃至５６は前述の入力構成（スイッチエレメント５５と５６がオフ状態の時にスイッチエレメント５１乃至５４がオン状態）または出力構成（スイッチエレメント５１乃至５４がオフ状態の時にスイッチエレメント５５と５６がオン状態）になることができる。
図９の倍電圧回路50のケースのように、各々ステージＳＴ_i のスイッチエレメント５１乃至５６は制御信号φ₁ とφ₂ に依って制御される。しかし、図１０のＡＤＣの場合、全てのステージに共通する制御手段６０′は各ステージの第１と第２の制御信号を生成するために与えられていて、なおかつ、φ₁ がアクティブの時に、スイッチエレメント５１乃至５６の奇数番号のステージＳＴ₁ 、ＳＴ₃ 、ＳＴ₅ …は入力構成に保持されるが、スイッチエレメント５１乃至５６の偶数番号のステージＳＴ₂ 、ＳＴ₄ 、ＳＴ₆ …は出力構成に保持され、なおかつ、φ₂ がアクティブの時に逆になる。
【０１３８】
各々電圧変換ステージＳＴ_i は、ステージに加えられる入力電圧Ｖ_i を受けるためにステージの第１と第２の入力ノードＩ₁ とＩ₂ に接続されていて且つ前述の比較電位Ｖ_r ／４を受けるためにも接続されている比較手段７０を搭載している。比較手段７０は、その出力に於いて３ステート・ロジックデジタルデータａ（＋１、０、−１）を与え、ステージのデジタル出力として、前述の表２に従って作動する。各々ステージのデジタルデータは、デジタル出力ワードを生成する処理のためにデータ処理手段８０に加えられる。デジタルデータａはその動作を制御する電圧調整手段５８にも加えられる。
【０１３９】
電圧調整手段は、スイッチエレメント５５と５６がオンの時に、ステージの電圧記憶回路の各々の共通ターミナルＣＯＭ₁ とＣＯＭ₂ の間で、３つの異なる可能性のある電圧の１つから、比較手段に依って生成されるデジタルデータに依って、選ばれたオフセット電圧Ｖ_OSを加えるように作動する。ａ＝＋１のケース（Ｖ_r ／４≦Ｖ_i のケースに対応している）の時に、選ばれたオフセット電圧は Ｖ_OS＝−Ｖ_r になる。ａ＝０（−Ｖ_r ／４≦Ｖ_i ＜Ｖ_r ／４のケースに対応している）の時に、選ばれたオフセット電圧はＶ_OS＝０になる。ａ＝−1 （Ｖ_i ＜−Ｖ_r ／４のケースに対応している）の時に、選ばれたオフセット電圧はＶ_OS＝+ Ｖ_r になる。
【０１４０】
図１０に図示されているＡＤＣの動作に於いて、デジタル化されるアナログ入力電圧Ｖ_i1は第１電圧比較ステージＳＴ_i の第１と第２の入力ノードＩ₁ とＩ₂ の間に加えられる。最初に、制御手段６０′は制御信号φ₁ を作動するので、第１電圧変換ステージＳＴ_i は入力構成（そのスイッチエレメント５１乃至５４がオン）に保持される。この構成に於いて、スイッチエレメント５５と５６は共にオフに保持されるので、電圧調整手段５８は回路の残りの部分から分離される。
【０１４１】
φ₁ がアクティブの間に、第１ステージＳＴ_i の比較手段７０は、加えられる入力電圧Ｖ_i と比較電位Ｖ_r ／４を比較して、３ステート・ロジックデジタルデータを比較の結果に基づいて生成する。
φ₁ がアクティブの時の周期の終わりの前に、スイッチング信号ＣＫは、制御手段６０′に依って第１ステージＳＴ_i の各々スイッチ駆動手段４、５に印加されて、ステージＳＴ_i の電圧記憶回路ＶＳＣ₁ とＶＳＣ₂ の各々のスイッチエレメント１がオフに切り替えられるようにするので、第１ステージＳＴ_i の入力電圧Ｖ_i1がこれらの回路の各々の記憶コンデンサー２の各々に記憶される結果になる。
【０１４２】
制御手段６０′は、次にφ₁ の作動をオフにしてφ₂ を作動し第１ステージＳＴ_i を出力構成に切り替える。この構成に於いて、ステージのスイッチエレメント５１乃至５４はオフ条件になり、ステージのスイッチエレメント５５と５６はオン条件になる。電圧調整手段５８は従って電圧記憶回路ＶＳＣ₁ とＶＳＣ₂ の各々記憶コンデンサー２の間で直列に接続されるので、選ばれたオフセット電圧Ｖ_OS（デジタルデータａに基づいて −Ｖ_r ，０，＋Ｖ_r ）が電圧記憶回路ＶＳＣ₁ とＶＳＣ₂ の各々共通ターミナルＣＯＭ₁ とＣＯＭ₂ の間に加えられる。そこで、アナログ変換電圧Ｖ_C は、電圧調整手段５８に依って電圧記憶回路ＶＳＣ₁ とＶＳＣ₂ の各々の共通ターミナルＣＯＭ₁ とＣＯＭ₂ の間に加えられる選ばれたオフセット電圧Ｖ_OSに依って記憶されていた入力電圧Ｖ_i1の２倍と異なる（すなわち、Ｖ_C1＝２Ｖ_i1＋Ｖ_OS）ステージＳＴ_i の第１と第２の出力ノードＯ₁ とＯ₂ の間に生成される。
【０１４３】
従って、前述の表２に従って、電圧変換ステージＳＴ_i に依って生成される変換電圧Ｖ_C1は、Ｖ_i1と比較電位Ｖ_r ／４の間の比較の結果に基づいて、２Ｖ_i1−Ｖ_r 、２Ｖ_i1、または２Ｖ_i1＋Ｖ_r になることができる。
図１０に図示されているように、ＡＤＣの電圧変換ステージは直列に接続されているので、第２電圧変換ステージＳＴ₂ はその入力電圧Ｖ_i2として第１電圧変換ステージＳＴ_i に依って生成されるアナログ変換電圧Ｖ_C1を受ける。前述のように、第２ステージＳＴ₂ のスイッチエレメント５１乃至５６は、第１ステージＳＴ_i のスイッチエレメント５１乃至５６が出力構成の時に入力構成にφ₂ が制御されるので、第２ステージＳＴ₂ は、第１ステージＳＴ_i に依って生成される比較電圧Ｖ_C1のその比較動作を、遅れることなく始めることができる。第２ステージＳＴ₂ のスイッチ駆動手段４乃至５のスイッチング信号ＣＫは、（φ₁ がアクティブの間のスイッチ駆動手段４、５のケースのような第１変換ステージＳＴ_i よりむしろ）そこでφ₂ がアクティブの間に生成されるので、第１ステージＳＴ_i のアナログ変換電圧Ｖ_C1が第２ステージＳＴ₂ に記憶される。φ₂ がアクティブの時の周期の終わりの後で、φ₁ は、再びアクティブになり、第２ステージＳＴ₂ を出力構成に切り替える。それは、従って、アナログ変換電圧Ｖ_C2を前の（第１）ステージのアナログ変換電圧Ｖ_C1に基づいて生成する。
【０１４４】
アナログ変換電圧Ｖ_C2は、次のステージＳＴ₃ の入力に加えられ且つ順に（φ₁ がアクティブの次の周期に於いて）アナログ変換電圧Ｖ_C3に変換される。次の電圧変換動作は従って制御信号φ₁ とφ₂ の作動の各々“スワップ”で行われる。制御信号φ₁ とφ₂ が各々アクティブの周期ｔ₁ とｔ₂ はコンバーターの第１と第２のクロック位相を構成し、第２の位相はコンバーターの各々次のクロック周期の第１クロック位相の終わりの後に始まる。
【０１４５】
第１ステージＳＴ_i は第２ステージＳＴ₂ が出力構成に切り替えられた後に（第１ステージに依って与えられたばかりのアナログ変換電圧Ｖ_C1をアナログ変換電圧Ｖ_C 2に変換するために）入力構成に切り替えられて戻るので、新しいアナログ入力電圧は、φ₁ が再び作動されるたびに、コンバーターに依って受けられることができる。このようにして、ＡＤＣは新しい変換結果（Ｎ個の３ステート・ビットに基づくデジタル出力ワード）を全てのクロック周期に生成することができる。
【０１４６】
与えられたステージの比較手段７０がステージの印加入力電圧と比較電位を直接比較することは不可欠な要素でない。比較は、一方で、コンパレーターの電位と、他方で、電圧記憶回路に記憶されている入力電圧、または比較の前にステージに依って与えられている初期アナログ変換電圧の間で行われると思われる（そこでアナログ変換電圧は補正される）。
【０１４７】
図１０に用いられているＮ個のステージの代わりに、各々が交互に他の出力を抽出して繰り返し動作する、ちょうど２つの電圧変換ステージを代わりに使用できると思われる。この構成は、１つのクロック周期（すなわち２つのクロック位相）を用いて、３ステート・ロジック・デジタルデータの全ての２つのビットを生成することになる。従って、Ｎビット変換を行うために、構成はＮ／２クロック周期をとることになり、これはＮ個のステージを使用するコンバーターより遥かに遅くなる。要求される回路の大きさは、しかし小さくなると思われる。
【０１４８】
本発明の異なる態様では、反復して動作する１個の電圧変換ステージだけを有する３状態（３ステート）論理ＡＤＣを作ることも可能である。但しこの場合、以下に図１１を参照して説明するように、電圧変換ステージは図１０のＡＤＣの変換ステージＳＴ_i における電圧記憶回路とは異なる構成の電圧記憶回路を有する必要がある。
【０１４９】
図１１において、３ステート論理ＡＤＣで使用される電圧変換ステージ９０は、電圧変換ステージ９０の第１及び第２入力ノードＩ₁ とＩ₂ にそれぞれ接続された第１及び第２の変形した電圧記憶回路ＶＳＣ₁ ′とＶＳＣ₂ ′を有する。
各変形電圧記憶回路は、これまでに図１乃至図７を参照して説明した入力スイッチエレメント１と、単一利得の増幅器エレメント３と、ブートストラップスイッチ駆動手段４、５を有する。しかしながら、各変形電圧記憶回路は、図１の電圧記憶回路における１個のコンデンサー２の代わりに、第１の変形電圧記憶回路ＶＳＣ₁ ′の場合にはＣ₁ とＣ₃ のラベルを付けた２個のコンデンサーを、第２の変形電圧記憶回路ＶＳＣ₂ ′の場合にはＣ₂ とC₄の２個のコンデンサーを有する。コンデンサーＣ₁ 乃至C₄は、通常同一の静電容量であるが、これは電圧変換ステージ９０の正確な動作のために必須ではない。
【０１５０】
各変形電圧記憶回路は、更に数個のスイッチエレメント９１乃至１０６を有し、コンデンサーＣ₁ 乃至C₄のそれぞれに４個のスイッチエレメントが関係している。すなわち、スイッチエレメント９１、９２、９５及び９６はコンデンサーＣ₁ に関係し、スイッチエレメント１０１、１０２、１０５及び１０６はコンデンサーＣ₂ に関係し、スイッチエレメント９３、９４、９７及び９８はコンデンサーＣ₃ に関係し、スイッチエレメント９９、１００、１０３及び１０４はコンデンサーC₄に関係する。
【０１５１】
スイッチエレメント９１乃至１０６は、以下により詳細に説明するように、ブートストラップスイッチ駆動手段により生成される制御信号φ₁ とφ₂ に応じてオン状態とオフ状態になる。
各電圧記憶回路ＶＳＣ₁ ′とＶＳＣ₂ ′に関係して、入力スイッチエレメント１と電圧変換ステージ９０の関連する入力ノードI₁又はI₂との間で、入力スイッチエレメントに直列に接続された入力分離スイッチエレメント４６、及び（増幅器エレメント３の出力ターミナルの）変形電圧記憶回路の出力ノードと入力スイッチエレメント１の入力側との間に接続されたフィードバックスイッチエレメント４８がある。入力分離スイッチエレメント４６とフィードバックスイッチエレメント４８は、図８の電圧加算回路における同一の名称及び参照番号のスイッチエレメントに対応し、同一の働きを行う。フィードバックスイッチエレメント４８はいずれにしろ抵抗に置き換えることが可能である。
【０１５２】
電圧調整手段５８は、ほぼ図１０の電圧調整手段５８に類似しており、第１及び第２変形電圧記憶回路ＶＳＣ₁ ′とＶＳＣ₂ ′の間に接続される。更に、コンパレーター手段７０は、図１０の各電圧変換ステージSTi のコンパレーター手段に類似しており、変形電圧記憶回路の各出力ノード間に接続される。
電圧調整手段５８は、更なる複数のスイッチエレメント５８１乃至５８８を有する。６個のスイッチエレメント５８２乃至５８４と、５８６乃至５８８はそれぞれペアでコンパレーター手段によって生成される３ステートデータ「ビット」a _i の論理レベルに応じて活性化される。この場合、a _i ＝−１の時に、スイッチエレメント５８２と５８６が活性化され、その結果電圧調整手段５８の出力ターミナルの間に生成されるオフセット電圧Ｖ_OSは、あらかじめ定められた基準電圧＋Ｖr に等しくなる。a _i ＝０の時に、スイッチエレメント５８３と５８７が活性化され、オフセット電圧Ｖ_OSはゼロになる。a _i ＝＋１の時に、スイッチエレメント５８４と５８８が活性化され、オフセット電圧Ｖ_OSは−Ｖr に等しくなる。
【０１５３】
ステージ９０の第２及び第１入力ノードＩ₂ とＩ₁ にそれぞれ接続される電圧調整手段５８の他の２個のスイッチエレメント５８１と５８５の活性化について、以下に説明する。
制御手段６１は、図１０の制御手段６０′にほぼ類似しており、主（マスタ）制御信号φ_1Mとφ_2Mを生成するだけでなく、それぞれ更にマスタ制御信号ＳＡＭ_M とＣＯＮ_M も生成する。マスタ制御信号φ_1M、φ_2M及びＳＡＭ_M は、各変形電圧記憶回路のブートストラップスイッチ駆動手段４、５に印加される。各変形電圧記憶回路のブートストラップスイッチ駆動手段は、マスタ制御信号φ_1M、φ_2M及びＳＡＭ_M に対応し関連する変形電圧記憶回路のスイッチエレメントに印加されるブートストラップ制御信号φ₁ 、φ₂ 及びＳＡＭＰＬＥを発生させる。ブートストラップ制御信号の電位は、変形電圧記憶回路の増幅器エレメント３の出力ターミナル電位に追従する。変形電圧記憶回路に関係するフィードバックスイッチエレメント４８を活性化するのに使用される制御信号ＣＯＮＶＥＲＴは、マスタ制御信号ＣＯＮ_M から導出されるブートストラップ制御信号であってもよいが、それはブートストラップされるフィードバックスイッチエレメント４８に印加される信号として基本的ではないため、マスタ制御信号ＣＯＮ_M を直接与えることもできる。
【０１５４】
図１１の電圧変換ステージ９０による変換動作の開始時には、等価のデジタル信号に変換されるアナログ入力電圧が、電圧変換ステージ９０の第１及び第２入力ノードＩ₁ とＩ₂ の間に印加される。印加されたアナログ電圧のサンプリングを容易にするために、制御手段６１は、各変形電圧記憶回路において入力ノードＩ₁ とＩ₂ をスイッチエレメント１と４６を介して変形電圧記憶回路の増幅エレメント３の各入力に接続させるように関係するブートストラップ制御信号ＳＡＭＰＬＥを活性化させるマスタ制御信号ＳＡＭ_M を発生する。この時、ＣＯＮＶＥＲＴ制御信号は非活性化され、フィードバックスイッチエレメント４８はオフ状態である。
【０１５５】
電圧調整手段５８のスイッチエレメント５８１と５８５は、更に制御信号ＳＡＭＰＬＥによっても活性化され、電圧調整手段の出力ターミナル電位はそれぞれ第２及び第１入力ノードＩ₂ とＩ₁ の電位に等しい。この時、他のスイッチエレメント５８２乃至５８４と５８６乃至５８８は、オフ状態に保持される。
入力電圧のサンプリング中に制御信号φ₁ が活性であると仮定すると、スイッチエレメント９１、９５、１０１及び１０５はオン状態であり、第１の変形電圧記憶回路ＶＳＣ₁ ′におけるコンデンサーＣ₁ は、上側のプレートが第１入力ノードＩ₁ に接続され、下側のプレートが第２入力ノードＩ₂ に接続される。同様に、第２の変形電圧記憶回路ＶＳＣ₂ ′は、上側のプレートが第２入力ノードＩ₂ に接続され、下側のプレートが第１入力ノードＩ₁ に接続される。従って、各コンデンサーＣ₁ とＣ₂ は印加されたアナログ入力電圧のサンプリングを行うように印加されたアナログ入力電圧を記憶する。
【０１５６】
制御信号φ₁ が活性である間、スイッチエレメント９４、９８、１００及び１０４は、オン状態にあり、コンデンサーＣ₃ とＣ₄ は増幅器エレメント３の各出力ターミナルの間に交互に平行に接続される。増幅器エレメントは単一の利得を有しているため、サンプル化されたアナログ入力電圧はφ₁ の間各コンデンサーＣ₃ とＣ₄ にも記憶される。
【０１５７】
次に、ＳＡＭＰＬＥ制御信号は入力電圧のサンプリングを終了するように非活性化され、制御信号φ₁ は活性化されたままである。
ＳＡＭＰＬＥ制御信号が非活性化された後、ＣＯＮＶＥＲＴ制御信号は変換動作の残りの部分のために、活性化される。単位利得の増幅器エレメント３の入力及び出力ターミナル電位は常に等しいため、入力スイッチエレメント１の入力側及び出力側ターミナルは、同一電位に保持され、エレメント１は、関係する入力ノードＩ₁ 又はＩ₂ の電位で付随して生じる変化にかかわらず、オフ状態に安定的に保持される。
【０１５８】
コンデンサーＣ₃ とＣ₄ で保持されるサンプル化された入力電圧は、コンパレーター手段７０により、図１０のＡＤＣにおけるのと同様の方法で、あらかじめ定められた比較電位Ｖ_r ／４と比較される。３ステート論理デジタルデータ（＋１、０、−１）の第１ビットａ₁ は、コンパレーター手段７０により比較結果に基づいて生成される（表１参照のこと。）。
【０１５９】
第１データビットａ₁ が得られた後、電圧調整手段５８のスイッチエレメント５８２乃至５８４と５８６乃至５８８の各ペアは、第１データビットａ₁ に従って活性化される。このようにして、電圧調整手段５８は、出力ターミナルの間に、あらかじめ定められたオフセット電圧Ｖ_OS（デジタルデータビットａ₁ に対応した−Ｖ_r ，０，＋Ｖ_r ）の１つを生成する。制御信号φ₁ はまだ活性化したままであり、スイッチエレメント９１、９５、１０１、及び１０５はすべてオン状態のままであり、スイッチエレメント３の各入力ターミナルの間に、第１の列の接続が存在することになる。この第１の列がコンデンサーＣ₁ 、電圧調整手段５８及びコンデンサーＣ₂ を構成する。このように、増幅器エレメント３の各入力ターミナルの間の電圧は、コンデンサーＣ₁ とＣ₂ に記憶されたサンプル化されたアナログ入力電圧に第１データビットａ₁ により選択されたオフセット電圧Ｖ_OSを加えたものの２倍に等しい第１変換電圧Ｖ_C1である。このように、電圧変換動作は、表２に従って行われる。
【０１６０】
増幅器エレメント３の入力ターミナル電位は、増幅器エレメント３によってバッファされており、第１の変換電圧Ｖ_C1が増幅器エレメント３の各出力ターミナルの間に再生される。
スイッチエレメント９４、９８、１００及び１０４はすべてオン状態のままであり、コンデンサーＣ₃ とＣ₄ は増幅器エレメント３の各出力ターミナル間に相互に平行に接続され、それぞれが第１の変換電圧Ｖ_C1を記憶する。
【０１６１】
第１の変換電圧Ｖ_C1は、コンパレーター７０によって基準電位Ｖ_r ／４と比較され、第２データビットａ₂ が比較結果に応じて生成される。
次に、制御手段は制御信号φ₁ を非活性化し、制御信号φ₂ を活性化する。同時に、第２データビットａ₂ が電圧調整手段に印加され、このデータビットａ₂ に応じて新しいオフセット電圧Ｖ_OSが選択される。制御信号φ₂ を活性化することにより、スイッチエレメント９３、９７、９９及び１０３がオン状態になる。その結果コンデンサーＣ₃ とＣ₄ は電圧調整手段５８に直列に接続され、増幅器エレメント３の各入力ターミナルの間に第２の列接続（Ｃ₃ −Ｖ_OS− Ｃ₄ ）が形成され、上記の第１の列接続（Ｃ₁ −Ｖ_OS− Ｃ₂ ）と置き換わる。従って、この結果得られる増幅器エレメント３の各出力ターミナルの間に生成される新しい変換電圧Ｖ_C2は、第１の変換電圧Ｖ_C1に新しく選択されたオフセット電圧Ｖ_OSを加えた値の２倍に等しくなる。制御信号φ₂ を活性化することにより、スイッチエレメント９２、９６、１０２及び１０６はオン状態になり、この新しい変換電圧Ｖ_C2は増幅器エレメント３の各出力ターミナル間に平行に接続されるコンデンサーＣ₁ とＣ₂ に記憶される。
【０１６２】
新しい変換電圧Ｖ_C2は、コンパレーター手段７０で基準電位Ｖ_R ／４と比較され、次のデータビットａ₃ を生成する。次いで、制御信号φ₂ は非活性化され、制御信号φ₁ が活性化され、更に、データビットａ₃ が電圧調整手段に印加され、新しいオフセット電圧Ｖ_OSが選択される。制御信号φ₁ が活性化されるので、第１の列接続（Ｃ₁ −Ｖ_OS− Ｃ₂ ）が増幅器エレメント入力ターミナルの間の第２の列接続（Ｃ₃ −Ｖ_OS− Ｃ₄ ）に置き換わり、コンデンサーＣ₃ とＣ₄ はその結果得られる新しい変換電圧Ｖ_C3を記憶する。
【０１６３】
その後、制御信号φ₁ とφ₂ が交互に活性化され、新しいデータビットａ_i と新しい変換電圧がそれぞれ連続した制御信号位相の間生成される。
図１０をを参照して説明したように、データビットａ_i はＡＤＣのデータ処理手段８０（図示せず）に印加され、もともと印加されたアナログ電圧を表すデジタル出力ワードを生成するように処理される。図１１の電圧変換ステージは、Ｎ個の３ステートビットに基づくデジタル出力ワードを生成するのにＮ個のクロック位相が必要であることがわかる。
【０１６４】
各増幅器エレメント３において、入力ターミナル電位は出力ターミナル電位に等しいため、制御信号φ₁ 又はφ₂ のいずれかが活性である時には、第１変形電圧記憶回路ＶＳＣ₁ ′のスイッチエレメント１、４８、９１、９２、９３及び９４、及び第２変形電圧記憶回路ＶＳＣ₂ ′の対応するスイッチエレメント１、４８、１０３、１０４、１０５及び１０６の各スイッチエレメントは、２個のターミナルにわたって電圧を有しないことが理解される。
【０１６５】
コンデンサーの上側のプレートに接続されるスイッチエレメント９１乃至９４と１０３乃至１０６は、オーバーラップ無しに切り換えできる（すなわち、スイッチオフの後遅延無しに切り換えられる。例えば、スイッチエレメント９２がオンになる前にスイッチエレメント９２はオフする。）。これは、これらのスイッチエレメントが接続される４個のノード（増幅器エレメントの入力ターミナル、増幅器エレメントの出力ターミナル、及び２個のコンデンサーのそれぞれの上側のプレート）は、切り換えの前後（すなわち、各制御信号位相がφ₁ からφ₂ に変化する等）で同一の電圧を有するためである。この上側のプレートに関係するスイッチ９１乃至９４と１０３乃至１０６がオーバーラップすることなしに切り換わることにより、制御信号の発生が簡単になる。
【０１６６】
ここで、コンデンサーの下側のプレートに接続されるスイッチ９５乃至１０２は、電荷注入効果を避けるため、コンデンサーの上側のプレートに接続されるスイッチエレメント９１乃至９４と１０３乃至１０６の切り換えの後、所定の短時間で切り換えられることが重要である。この所定の短時間は、この時間の間各増幅器エレメント３の入力ターミナルが他の増幅器エレメント３の出力ターミナルに効果的に組み合わされるという観点から最小化され、正のフィードバックが生じる。この正のフィードバックの効果は、増幅器エレメントが単位利得を有する場合にはあまり重要でないが、電圧変換ステージ９０をこの状態にする必要がある絶対的に必要な時間より長くこの状態にするのを避けるのが望ましい。これにより、上側のプレートに接続されるスイッチエレメント９１乃至９４と１０３乃至１０６が設定されると同時に、下側のプレートに接続されるスイッチエレメント９５乃至１０２が切り換わる。
【０１６７】
第１の変形電圧記憶回路ＶＳＣ₁ ′は、基板を覆う材料の導電性と逆の導電性の１個以上のウエルに形成されることが望ましく、そのウエル又は各ウエルの電位は第１の変形電圧記憶回路の増幅器エレメント３の出力ターミナル電位に対して固定される。これと同様のことが、第２の変形電圧記憶回路のＶＳＣ₂ ′のスイッチエレメント１と１０３乃至１０６にも適用される。このスイッチエレメントの配置により、図１乃至図７の電圧記憶回路に関連して既に説明したのと同一の基本的な方法で、変形電圧記憶回路の寄生静電容量をブートストラップすることが可能になる。
【０１６８】
図１２の電圧変換ステージでは、第１の電圧変換動作が、最初のクロック位相中にアナログ入力電圧がサンプリングされ、このサンプリングは直ちに終了する。これにより、変換動作が高速化されるが、サンプリング中にコンデンサーＣ₁ とＣ₂ の下側のプレートを入力ノード電位に充電するためのべつのスイッチエレメント（電圧調整手段５８と一体に示されているエレメント５８１と５８５）を備える必要がある。これらのスイッチエレメント５８１と５８５を除いて単に最初のクロック位相で（ａ₁ を得るために）比較動作を行うことも可能であり、第１の電圧変換動作は次のクロック位相で実行される。
【０１６９】
図１０又は１１を参照して既に説明した電圧変換ステージは、適当な変形を加えることにより、倍電圧及びオフセット動作を必要とするほかのアナログ・デジタル・コンバーターに適用可能である。
図１０を参照して既に説明した電圧変換ステージの列を有するＡＤＣでの電力消費を最低にするため、「スケール化」した連続ステージにするのが効果がある。この点は、図１２を参照してより詳しく説明される。
【０１７０】
図１２に、図１０に図示されているＡＤＣの最初の３つのステージが概略的に描かれている。第１ステージの記憶コンデンサー２は各々静電容量Ｃをもっていて、増幅器エレメント３のトランジスターは各々チャンネル幅Ｗであり、増幅器エレメント３のこれらのトランジスターの各々に流れる電流はＩである。
第２ステージに於いて、記憶コンデンサー２は各々静電容量がＫＣであり、ここで１／ｋが予め設定されたスケーリング・ファクター（ｋ＜１）の時に、増幅器エレメント３のトランジスターは各々幅がｋＷであり、各々トランジスターを流れる電流はｋＩになる。同様に、第３ステージに於いて、静電容量はｋ² Ｃ、トランジスター・チャンネル幅はｋ² Ｗ、トランジスターの電流はｋ² Ｉになる。
【０１７１】
従って、各々次のステージは、少なくともこれらの３つのパラメータがスケーリング・ファクター１／ｋに依って関係されている限りスケールされる。その結果、第１ステージで消費される電流に関して表される、デバイスで消費される総電流は、１＋ｋ＋ｋ² ＋ｋ³ ＋…… になる。
各々ステージは１／ｋのノイズパワーをその自らの入力にもっているが、しかし、ＡＤＣの入力ターミナルに対して、これは前のステージの利得の積に依って減少される。例えば、第２ステージのノイズパワー＝１／ｋ、前のステージの電圧利得（このケースでは第１ステージの電圧利得）＝２、従ってノイズパワーは、入力ノイズパワーに対して、１／ｋになる。
【０１７２】
従って、全てのステージの入力の総ノイズパワーは、１＋１／４ｋ＋１／１６ｋ² ＋１／６４ｋ³ ＋……になる。例えば、ｋ＝１／２の時には、総ノイズ＝１＋１／２＋１／４＋１／８＋……＝２になる。
同様に、ｋ＝１／２を前述の総電流の式に代入すると、総電流＝１＋１／２＋１／４＋１／８＋……＝２になる。
【０１７３】
全パワー一定の場合、全てのサイズはパワー加算の結果に依って割り算されなければならない、すなわち、入力ノイズは同じファクターで掛け算され、次式のように表される。
【０１７４】
【数１】

【０１７５】
入力ノイズは、ｍ＝１、すなわちｋ＝１／２の時に最小になる。
前述の分析から、ＡＤＣの最小総消費電力の最適のスケーリング・ファクターは２になることが明らかである。これは、最小ノイズレベルを与えられた消費電力に、または最小消費電力レベルを与えられノイズレベルに提供する。従って、各々ステージは前のステージのサイズの実質的に半分になる。この場合、総消費電力は第１ステージの消費電力の２倍に等しくなり、なおかつ、総ノイズパワーは第１ステージのノイズパワーの２倍に等しくなる。
【０１７６】
図１３は、16ステージＡＤＣの場合にスケーリング・ファクター１／ｋをもつ総電流とノイズの変化の様子を示している。図１３に示すように、与えられたパワー消費に対して最小のノイズと与えられノイズレベルに対して最小のパワー消費は各々スケーリング・ファクター１／ｋ＝２の時に現れる。
前述の分析は変換ステージのスケーリングがＡＤＣの全てのステージに適用されることを示しているが、実際に、ステージのスケーリングは、１６ステージ列（１７ビットＡＤＣ）の場合、これは、最後のステージが第１ステージのサイズの１／２¹⁶＝１／６５５３６倍だったことを意味しているので、最終ステージまで続けることができない。
【０１７７】
シリーズの特定のステージに於いて、ステージ・サイズが適度に小さくなる時に、全ての次のステージは同じサイズにされる、すなわち、これは、ノイズを少し大きくするが、広い範囲のサイズが要求されないことを意味している。
例えば、スケーリングが６つのステージの後に停止する場合、最小ステージのサイズ（６番目と全ての次のステージに用いられる）は第１ステージのサイズに対して１／３２になる。この場合、全パワー＝１＋１／２＋１／４＋１／８＋１／１６＋１／３２＋１／３２＋１／３２＋……になる。
【０１７８】
いちど最小ステージサイズが選択されると、該サイズのステージは、最大のステージを形成するために平行にされる（またはレイアウトで“ストレッチされる”）ことができる“ユニット”ステージとしてデザインされることができる。例えば、ユニットステージが第１ステージに対して１／３２のサイズになる場合、第１ステージ＝３２の平行ユニット、第２ステージ＝１６の平行ユニット、第３ステージ＝８の平行ユニットになる。
【０１７９】
サイズが 1/32 のユニットステージを使用するＡＤＣのチップに関して１つの考えられるレイアウトが図１４に図示されている。
表３は与えられた最小サイズのステージの場合、最適スケーリング・ファクター１／ｋは、１５ステージＡＤＣ（１６ビット）のケースの異なる最小ステージに最適のスケーリング・ファクターを示す表である。表３から明らかなように、最適のスケーリング・ファクターは非常に２に近い。
【０１８０】
【表３】

【０１８１】
スケーリングが停止されない時の最適ノイズパワー値４．０と比べると、１／３２の最小ステージサイズは約１０％または０．４６dBの全てのパワーの増加またはノイズの増加の結果になるが、１／１６の最小ステージサイズは、パワーまたはノイズを約２５％または０．９９dBだけ増加する結果になる。これらの２つの最小ステージ・サイズは好ましい対策になると思われる。
【０１８２】
前述のようなスケーリングは、本発明の別の態様に於いて、電圧変換ステージの列を有する任意の適切なタイプのアナログ・デジタル・コンバーターに効果的に応用されることができる。例えば、スケーリングを前述のEP−B −0214831 に説明されている電圧変換回路に、その文献に前述の複数のステージが直列に互いに接続されていたケースに、応用することも可能と思われる。
【０１８３】
図１０のＡＤＣに依って費やされる電流は、記憶コンデンサー２の静電容量に直接比例し且つ変換率に逆比例する。これは、高い分解能と高い変換率に対してもパワーがとうぜん増加されることを意味している。しかし、１６ビット１０Ｍｓ／ｓのコンバーターは０．５Ｗ未満しか消費しないことが推定される。これは、変換率を１Ｍｓ／ｓに下げると、パワーは５０ｍＷまたは１００ｋｓ／ｓで５ｍＷに減少されることを示唆している。
【０１８４】
低い分解能（例えば１２ビット）の場合、パワーと面積は、静電容量が非常に小さいので急激に減少する。１２ビット５０Ｍｓ／ｓのコンバーターは、異なる変換ステージに依って与えられるデジタルデータを処理するために要求されるデジタル論理回路の消費電力を含めて２００ｍＷを消費すると推定される。
これは、従来のコンバーターと比べると遥かに改善された電力／速度のつりあいのとれた関係を示している。その１つの主な理由は、直列の各々ステージが、前のステージのサイズと電力の半分になり、第１ステージの約２倍となるコンバーターの総電力を与えることができるためである。これは大幅な減少をチップサイズに提供し、１６ビットＭｓ／ｓのコンバーターは適切な処理で１０mm² より狭い面積しか占めないと推定される。
【０１８５】
倍電圧回路と比較手段に他に、Ｎビット出力ワードのＡＤＣのデジタル論理回路は（Ｎ−１）² のＤ型タイプ・フリップフロップと（Ｎ−１）フルアダーを搭載していて、全てが変換率でクロック計時される。１６ビット分解能の場合、これは、約２０００の基本セル・カウントと、１６ビット分解能で推定アナログ消費電力の約２５％の消費電力を５Ｖと１０ＭＨｚで与える（１５ビット分解能の場合、アナログ消費電力は４のファクターだけ減少されると思われる）。
【０１８６】
前述のように、ＡＤＣの電圧変換ステージの増幅器エレメント３の各々の利得は完全に単位値になる。そうでない場合、利得エラーを伝搬機能に導くこととは別に、更なる利得エラーが、寄生静電容量が完全にブートストラップされないので生じる結果になる。これらのエラーに起因する非直線性は、各々ステージで用いられる基準電圧Ｖ_r を列のステージと共に少し調整すれば補正されることができる。例えば、０．１％の利得エラーを補正するには、Ｖ_r を各々次のステージに対して０．１％だけ減少すればよい。
【０１８７】
代わりに、または更に、デジタルデータを各々ステージから受けるデジタルデータ処理手段８０は、次のステージのデジタルデータを機能的に調整すれば、アナログ回路の電圧変換エラーに対して任意に要求される補正を実施できる。
高速動作が可能なＡＤＣを生成するには、スイッチエレメントおよびステージの増幅器エレメントの動作が十分に高速であることが基本条件になる。単位利得増幅器エレメント３は通常の演算増幅器より遥かに高速にデザインされることができて、なおかつ、ＳＰＩＣＥシミュレーションは５０ｎｓの安定時間（１０Ｍｓ／ｓの変換率に対応している）は適切な処理で１６ビットの精度に具体的に相応していることを示していた。デプレションモードＮＭＯＳバッファを用いて且つ一部の分解能を犠牲にすると、１０ｎｓの安定時間が、１２ビットの精度に対して可能になる。これは、図１０のデザインに基づくＡＤＣはＨＤＴＶのようなアプリケーションに使用可能であることを示唆している。
【０１８８】
回路のノイズは図１０のＡＤＣでは重要な問題でない、何故ならば、増幅器エレメントに起因するノイズは、それが増幅器エレメントに達する前に、アナログ入力電圧の倍圧に依って効果的に減少されるからである。増幅器エレメントは、それらが kT/C ノイズより少ないノイズに関連するようにデザインされることができるが考えられる。この kT/C ノイズは、任意に切り替えられるコンデンサー回路に於いて与えられ記憶されている電圧サンプルの精度を制約する熱ノイズが原因であり、なおかつ、非常に小さいコンデンサーが用いられることを妨げる。１６ビットの信号とノイズの比率の場合、少なくとも１０ｐＦの記憶コンデンサーが次のステージに要求され、各々後のステージで半分に減少することが推定される。
【０１８９】
最高の特性とするために、図１０のＡＤＣは、ｐ−ウェル（ｎ−基板）ＣＭＯＳプロセスに依って、望ましくはデプレション・モード・デバイスを用いて好都合に生成される。
十分に大きい電圧スイングを得ることは単独の５Ｖ電源を用いても難しい（小さい電圧スイングは、低いノイズ・レベルが異なるステージを形成する回路に要求されることを意味している）、なおかつ、この問題は３．３Ｖのような低い電源電圧で益々難しくなる。
【０１９０】
しかし、ＡＤＣのデバイスは、それらが直列に接続されているので、完全に電源電圧に印加されるわけでない。すなわち、ソース／ドレイン・ダイオードだけが高電圧に印加されるが、これでさえも電源電圧と同じ大きさでない。最大電圧（５Ｖ）はウェル基板の接合部に生成される。この観点から、±３Ｖ（または±３．３Ｖ）正負両電源を、０Ｖ〜＋３Ｖの範囲で作動する（最小限の幾何学的形状の）デジタル回路と、±3Vを使用するアナログ回路と共に使用することが望ましいと思われる。この正負両電源アプローチは、入力信号が０Ｖの何れかの側にスイングできるので直流結合されることができる大きな長所も有している。デジタルの消費電力も実効デジタル論理電源電圧の低下に従って減少され、なおかつ、これは十分な減少を総消費電力に与えると思われる。
【０１９１】
より小規模の幾何学的形状は、最大クロック周波数の向上を、これがアナログ消費電力に依って制限されない場合でも可能にすることができる。分割式電源装置の主な長所は、従って、ＡＤＣの動作の最高速度を向上すると思われる向上されるデジタル速度と減少される消費電力にある。
【０１９２】
【発明の効果】
本発明により、増幅器エレメントの浮遊容量のために生じるコンデンサと増幅器エレメントとの間の電流が低減されるため、コンデンサに蓄積される電荷により生じる電圧の変動が低減され、電圧記憶回路の精度が向上する。
【図面の簡単な説明】
【図１】本発明を具体的に実施する電圧記憶回路の回路図を示している。
【図２】図１の回路に搭載されている増幅器エレメントの１つの設計例を示している。
【図３】図１の回路で使用している増幅器エレメントの別の設計例を示している。
【図４】図１の回路に搭載されている入力スイッチ・エレメントを更に詳細に示している。
【図５】増幅器エレメントの別の設計を、図１の回路で使用している、スイッチ・ドライブ手段の事例と共に示している。
【図６】図１の回路の集積回路基板上での考えられるレイアウトの１つを示す図であり、（Ａ）が平面図を、（Ｂ）が断面図を示している。
【図７】図１の回路の集積回路基板上での考えられるレイアウトの別つの例を示す図であり、（Ａ）が平面図を、（Ｂ）が断面図を示している。
【図８】図１に図示されている電圧記憶回路を使用する電圧加算回路の回路図を示している。
【図９】図１に図示されている２つの電圧記憶回路を使用する倍電圧回路の回路図を示している。
【図１０】複数の変換ステージを備えていて、各々が図９の倍電圧回路に基づいている、アナログ・デジタル・コンバーターの一部の回路図を示している。
【図１１】単一の変換ステージを有する前述の本発明の第２の態様のアナログ・デジタル・コンバーターの部分的な回路図を示す図である。
【図１２】図１０のコンバーターにおいてステージを或る値から次の値にスケーリング・ファクターに依ってスケーリングする長所を示す、図１０のコンバーターの部品の略図である。
【図１３】 16のステージをもつ図１０に図示されているコンバーターのケースに於いて、コンバーターの総消費電力とスケーリング・ファクターの間の関係と、コンバーターの総ノイズ量とスケーリング・ファクターの間の関係を示すグラフである。
【図１４】チップに関して図１０のコンバーターのレイアウトの１つの例を示す略図である。
【図１５】従来の電圧記憶回路の回路図を示している。
【図１６】図１５の従来例の回路に搭載されている増幅器エレメントを更に詳細に示している。
【符号の説明】
１…スイッチエレメント
２…記憶コンデンサー
３…増幅器エレメント
４…電位生成回路（スイッチ駆動手段）
５…セレクター回路（スイッチ駆動手段）
31…カスケードソースフォロア
32…電流ソース
33…入力トランジスター
34…カスケードトランジスター
35…バイアス発生器
44…ブートストラップコンデンサー[0001]
[Industrial application fields]
The present invention relates to a voltage storage circuit used in an analog to digital converter, for example, to store an applied analog value before converting it to its digital equivalent value.
[0002]
[Prior art]
FIG. 15 of the accompanying drawings shows a conventional voltage storage circuit equipped with an input switch element 1, a storage capacitor 2, and a high impedance unity gain amplifier element 3. Originally, the analog input voltage V applied between the input terminals of the circuit when the switch element 1 is in a closed position (hereinafter referred to as a closed position)._iIs applied to the storage capacitor 2, the potential difference between the plates of the storage capacitor is the input voltage V_iFollow. Time t_switchSince the input switch element 1 is switched to the open position (hereinafter referred to as the open position) at the moment set in advance, the potential difference between the plates of the capacitor immediately before the switch is stored until the time when the input switch element 1 is closed again. Is done. During the period when the switch element is in the open position, the stored voltage is the output voltage V_OThe amplifier element 3 functions to prevent loading of the storage capacitor by the circuit connected to the output terminal.
[0003]
FIG. 16 shows the input of the amplifier element 3 in more detail. This input is connected to the positive power supply line V of the amplifier element._ddThe drain electrode connected to the element and the negative power supply line V of the element_ssA FET input transistor 33 having a source electrode connected via a current source 32 and a gate electrode connected to one plate of the storage capacitor 2 (upper plate in FIG. 15) is mounted. It can be seen that the FET input transistor 33 is connected in a so-called source follower configuration.
[0004]
Although not shown in FIG. 16, the source electrode potential is buffered between the source electrode of the FET input transistor 33 and the output of the amplifier element to output the output potential V._OStill another circuit is usually inserted to generate.
[0005]
[Problems to be solved by the invention]
Using the amplifier element 3 of FIG. 16, the current source 32 causes the current to flow through the drain-source channel of the FET input transistor 33, so that its source electrode potential V_SIs the gate electrode potential, that is, the stored potential V of the upper plate of the storage capacitor 2_CIt will conform to. Therefore, the input part of the amplifier element 3 is actually the source electrode potential V_SIs the potential V of the upper plate of the storage capacitor 2_CAlthough it is always a little lower, it will have a substantially single voltage gain.
[0006]
Since the input section employs an FET input transistor with a very small gate current, the input impedance of the amplifier element is very high. Thus, after the input switch element 1 of the voltage storage circuit of FIG. 15 is opened, the storage capacitor will not be discharged to a sufficient level by the amplifier element 3.
[0007]
However, the amplifier element 3 of FIG._CWhen the potential of the capacitor fluctuates, charge inflow (or in the reverse direction) from the storage capacitor 2 to the input portion occurs. After the input switch element 1 is opened, this variation in the upper plate potential will not normally appear, but as will be described later in this specification, the upper plate potential V_CT at the moment when the input switch element 1 opens_switchHowever, it fluctuates inevitably due to the instantaneous charge inflow due to the input switch element 1 itself. This charge inflow by the input switch element 1 induces fluctuations in the voltage stored in the storage capacitor 2. This variation is slight but significant in the case of high accuracy. In other words, this charge inflow at the moment when the switch element is opened causes some variation to occur on the potential V of its upper plate._CTo occur.
[0008]
The reason why charge inflow at the amplifier element input corresponds to fluctuations in the upper plate potential of the storage capacitor 2 will now be explained. As shown in FIG. 16, since the FET input transistor 33 inevitably has a slight parasitic capacitance between its electrodes, the gate-source parasitic capacitance C between the gate and the source electrode._gsGate-drain parasitic capacitance C between the gate and drain electrodes_gd, Drain-source parasitic capacitance C between drain and source electrode_dsExists. Whenever the potentials of these three electrodes fluctuate correspondingly, charge will flow into or out of the parasitic capacitance, and the combination of these charge flows into and out of the amplifier element input. Will result.
[0009]
In the case of the amplifier element of FIG. 16, since the input transistor 33 is connected in the above-described source follower configuration, its gate source potential is the upper plate potential V of the storage capacitor 2._CThe gate-source parasitic capacitance C is substantially constant regardless of_gsThe charge inflow due to s can generally be ignored. However, the gate-drain potential and the drain-source potential of the input transistor 33 are V_dd-V_cAnd V_dd-V_sSince it is not constant, the upper plate potential V_cFluctuate based on So V_cIs always changed, the charge is the gate-drain parasitic capacitance C_gdAnd drain-source parasitic capacitance C_dsIn either case, charge will flow into or out of the input of the amplifier element.
[0010]
When the input switch element is open, the flowing charge must charge or discharge the storage capacitor 2 based on the direction of flow. This charging or discharging causes an error in the voltage stored between the plates of the storage capacitor 2.
The influence of the parasitic capacitance of the input part of the amplifier element is particularly problematic when the capacitance of the storage capacitor 2 is not large relative to the capacitance of the parasitic capacitance itself. This seems to be the case when it is necessary to shorten the achievement time.
[0011]
[Means and Actions for Solving the Problems]
According to a first aspect of the invention, the voltage storage circuit has a storage capacitor and an amplifier element. The storage capacitor has one plate connected to the input terminal of the circuit via the input switch element and the other plate connected to the common terminal of the circuit, so that the input signal stored is when the circuit is in operation Applied between the input and the common terminal. The amplifier element has an input connected to one plate and an output connected to the output terminal of the circuit for providing an output signal between the output terminal and the common terminal based on the voltage stored in the storage capacitor. Have. The amplifier element has a controllable current path provided between each of the first and second current path electrodes of the device, and the potential controls the magnitude of the current in the current path. An electrical input device also comprising a control electrode applied for said control electrode, said control electrode being connected to one plate, and said first and second current path electrodes being a first current path Since the electrode potential and the second current path electrode potential are both connected to the potential tracking means so as to be able to follow the control electrode potential, the current flows through the controllable current path, so that the first and second current path electrode Each potential is held substantially fixed with respect to the potential of one plate.
[0012]
Using this design of the amplifier element, the potentials of the control electrode of the input device, the electrodes of the first and second current paths are all substantially fixed relative to each other and to one plate when the circuit is in operation. The parasitic capacitance that exists between these electrodes does not significantly affect the operation of the circuit. This prevents charge from flowing into or out of the amplifier element and consequently preventing charging / discharging of the storage capacitor due to the operation of the amplifier element connected to the one plate of the storage capacitor. Become. In this way, errors occurring in the voltage stored as a result of this charge / discharge are eliminated.
[0013]
The potential follower includes a current source connected to the first current path electrode to cause the first current path electrode potential to follow the control electrode potential, and the second current path electrode potential to the first current path electrode potential. It is desirable to have active follower means operatively connected between the first and second current path electrodes for tracking.
In this configuration, the first current path electrode is automatically tracked to one plate potential, so that the active follower means is functionally between the first and second current path electrodes, i.e. the input device. Connected exclusively on the output side, the required tracking of the second current path electrode can be achieved.
[0014]
The electrical input device is preferably a FET input transistor, the control electrode is the gate electrode of the FET input transistor, the first current path electrode is the source electrode of the FET input transistor, and the second current path is The electrode becomes the drain electrode of the FET input transistor and the controllable current path is provided by the drain-source channel of the FET input transistor.
[0015]
The FET input transistor has an amplifier element with a high input impedance that prevents the storage capacitor from discharging after the input switch element is opened, thereby unavoidably presenting the FET input transistor between gate and source. The parasitic capacitance between the gate and the drain and between the source and the drain does not affect the circuit operation.
[0016]
When the input device is a FET, the active follower means may have a cascaded FET transistor whose drain-source channel is connected in series with the drain-source channel of the FET input transistor, thereby The source electrode potential of the cascade connection transistor can follow the gate electrode potential. In addition, the active follower means includes a bias generator functionally connected between the source electrode of the FET input transistor and the gate electrode of the cascade connection transistor, in order to maintain a substantially constant potential difference therebetween. Can also have.
[0017]
Since this cascaded configuration is simple but effective, the series connection of the cascaded FET transistor and the FET input transistor ensures that the source electrode potential of the cascaded transistor automatically follows its gate electrode.
The amplifier element is advantageously composed of first and second substantially identical circuit parts, the first part having the input device and the active follower means and the second part being Current source.
[0018]
The symmetry of this circuit can provide high stability and predictability during operation of the amplifier element, particularly with respect to the relationship between the input and output potential of the amplifier element, and is advantageous for manufacturing.
The input switch element is preferably an electrical input switch element and operates based on the potential of its switching electrode, and the circuit causes the switching electrode potential to follow the input terminal when the input switch element is in its on state. In order to maintain the switching electrode potential in a substantially fixed state with respect to the input terminal potential, the switching electrode potential is varied in accordance with the input terminal potential. The input switch element is changed from its on state to its off state.
[0019]
In this circuit, since the control electrode potential is fixed with respect to the input terminal potential, the amount of charge flowing into the electrical switch element at the moment of switching to the OFF state is substantially independent of the level of the input signal. Thus, the error in the stored voltage due to this charge inflow will be substantially constant or at least linear for different input signal voltages, so that appropriate measures can be taken to compensate for this error. Will be given.
[0020]
The switching electrode potential is preferably derived from the output signal, which can be achieved without loading or affecting the input signal.
The switch driving means is preferably operatively connected to the output terminal, and on the basis of a switching signal received there, an on-potential is applied to the switching electrode and the input switch element. In order to hold the input switch element in the off state, and the on and off potentials are applied to the output terminal. Each of the potentials is substantially fixed but differs depending on a preset value.
[0021]
In this configuration, since both the on and off potentials are fixed with respect to the input signal potential, the charge inflow due to the input switch element is substantially constant regardless of the input signal potential.
The voltage storage circuit is also operatively connected to the output terminal so that each of the first and second bias lines is fixed to the potential of the output terminal, and the potential of the second bias line is The potential difference between the first and second bias lines is equal to one of the on and off potentials and may be greater than or equal to the preset value. In this case, the switch driving means comprises a bootstrap capacitor whose one plate is connected to the switching electrode to provide the switching electrode potential, and both plates of the bootstrap capacitor The one plate of the bootstrap capacitor is connected to the bias line and the switching electrode potential is changed from the one of its on and off potentials to another of these potentials. From a charging configuration that connects to the second bias line and operates to connect another plate to the first bias line, the one plate is separated from the second bias line and the other plate is Switch to a floating configuration that operates to connect to the second bias line of Since also has connecting means which can be, can be changed by a preset value of the its potential different from the potential of the potential of said one plate of the second bias line.
[0022]
In this configuration, one of the on and off potentials can be located outside the circuit power line, if desired.
In any case, the voltage storage circuit has first, second, and third bias lines operatively connected to the output terminal, respectively, in order to bring each fixed potential with respect to the output terminal potential. Is the third bias line potential equal to one of the on and off potentials and is the potential difference between the first and second bias lines greater than the preset value? Will be equal. In this case, the switch driving means comprises a bootstrap capacitor whose one plate is connected to the switching electrode to provide the switching electrode potential, and both of the bootstrap capacitors are provided. Said one plate of the bootstrap capacitor connected to the plate and said bias line and when the switching electrode potential is changed from said one of its on and off potentials to another of these potentials Is connected to the third bias line but separates the one plate from the third bias line from a charging arrangement that operates to connect another plate to the first bias line, but the other Floating configuration that operates to connect the plate to the second bias line Since also comprises a connecting means which can be switched, it is possible to change the potential of said one plate of only the preset value of its potential different from the third bias line potential.
[0023]
In this example, from the output terminal potential when the switch element is in one of its on and off states at the control electrode potential, the switch element is in another state of its on and off states. The required change from the output terminal potential to a different potential by the preset value is not suitable for directly applying the on and off potential, or the potential is preset from the output terminal potential It can be achieved using an internal bias line that is less than a different value or both.
[0024]
The electrical input switch element is preferably a MOSFET transistor, in which case one of the on and off potentials is substantially the same as the output terminal potential. For example, if the MOSFET transistor is an n-channel enhancement type MOSFET, the off potential can be substantially the same as the output terminal potential. When this MOSFET transistor is used as an electrical switch element, the generation of appropriate on and off potentials is preferably simplified, especially in the above case where the on and off potentials are the output terminal potential as the control electrode. It can be obtained by applying directly.
[0025]
The voltage storage circuit is formed on a single substrate, and the input switch element of the amplifier element and the input device are one or more of the opposite conductivity of the material covering the substrate. It is preferable that there is a means which is placed inside a well and causes the potential of the well or each well to follow the potential of the one plate. By controlling the well potential in this way, the parasitic capacitance of the circuit (including the capacitance of the switch element and the capacitance of any internal connections) can be bootstrapped. The well can be electrically connected to the output terminal of the circuit, for example. This allows the well potential to follow the output terminal potential.
[0026]
Since the storage capacitor is also placed in the well, the parasitic capacitance associated with it can be bootstrapped.
Preferably, one or more conductive shields extend the portion of each or each well, and there is means for causing the shield potential or each shield potential to follow the potential of the one plate. This helps to eliminate the effects of residual parasitic capacitance. In this case, since the conductive shield is also generally electrically connected to the output terminal of the circuit, the potential of the shield can follow the potential of the output terminal.
[0027]
When the amplifier element of the voltage storage circuit has the two substantially identical circuit parts, the first part of the amplifier element is located inside the one or more wells. And the second portion of the amplifier element is formed within one or more additional wells, each of the conductivity being located opposite the periphery of the substrate, wherein the well Alternatively, the potential of each further well is substantially fixed with respect to the potential of the power supply line of the circuit.
[0028]
The voltage storage circuit is disposed between the input terminal and the input side of the input switch element, and the input side potential of the input switch element is changed to the state of the storage capacitor after the element is changed to an off state. It is preferable to further include input potential holding means for holding the plate in a substantially fixed state with respect to the potential of one plate.
[0029]
This prevents the input switch element from being accidentally switched on when the input signal potential changes sufficiently corresponding to the control electrode potential after the element is switched off.
The input potential holding means is connected in series with the input switch element, and after the input switch element is changed to an OFF state, the input side of the element is separated from the input terminal. It is also possible to have a switch element that can be actuated to Thus, the fluctuation of the input signal potential after the opening of the further switch element does not affect the input side potential of the input switch element.
[0030]
The input potential holding means includes an auxiliary capacitor connected between an input side of the input switch element and another plate of the storage capacitor, or an input side of the amplifier element and the input switch element. Either or both of the feedback switch elements connected in between and operable to apply a potential derived therefrom to the potential of the one plate of the storage capacitor, the input side of the element being isolated You can also have.
[0031]
The gain of the amplifier element is advantageously substantially unitary. In this case, the control electrode potential and well potential can be conveniently “bootstrapped” to the output terminal potential because it is buffered when the amplifier element has a substantially unity gain. This is because the output terminal potential is substantially equal to the potential of one plate / the potential of the input signal. Thus, the required control electrode potential can be derived from the buffered output signal without affecting the input signal.
[0032]
The voltage storage circuit described above (its amplifier element has unity gain) can be mounted in a useful state in a voltage summing circuit. The voltage adder circuit includes first, second, and third input nodes to which first, second, and third potentials are applied when the circuit is in operation, and an output that is connected to an output terminal of the voltage storage circuit. A node, switching means connected to the input node and the voltage storage circuit. The switching means can switch from the input configuration to the output configuration after the input switch element of the voltage storage circuit is changed to the off state, and the input configuration includes the first and second input nodes. Each of the voltage storage circuits is operative to connect to the input and a common terminal, thereby enabling storage of the potential difference between the first and second potentials of the storage capacitor of the voltage storage circuit, and The output configuration operates to connect a common terminal of the voltage storage circuit to the third input node, so that a memory between the third potential and the first and second potentials is stored at the output node. It is possible to produce an output potential substantially equal to the sum of the differences being made.
[0033]
Since such a voltage addition circuit can perform voltage addition with very high accuracy, the accuracy basically depends only on the influence that the influence of the parasitic capacitance of the voltage storage circuit can be eliminated. It is prescribed. In each voltage storage circuit, various parasitic capacitances of the circuit (switch element capacitance, amplifier element input capacitance, arbitrary internal connection capacitance) are booted using the techniques described above. The only constraint on the removal of the strapped and substantially parasitic capacitance effects results from the gain error of the amplifier element. This gain error can be reduced to a very low level by employing an appropriately designed amplifier element.
[0034]
Each of the first and second voltage storage circuits has been described. However, each of the first and second voltage storage circuits has a unit gain amplifier element and can be mounted in a useful state in the voltage adding circuit. The voltage summing circuit applies a first pair of input voltages to the first and second input nodes and a second pair of input voltages to the third and fourth input nodes when the circuit is in operation. A third pair of input voltages applied to the fifth and sixth input nodes, the first, second, third, fourth, fifth, and sixth input nodes; And a switching means connected to the input node and the voltage storage circuit. The first and second output nodes are connected to the output terminals of the two voltage storage circuits. The switching means can switch from an input configuration to an output configuration after each input switch element of the first and second voltage storage circuits is changed to an off state, and the input configuration is A first input node and a second input node connected to the input and a common terminal of each of the first voltage storage circuits, and the third and fourth input nodes of each of the second voltage storage circuits; Since it operates to connect also to the input and the common terminal, the storage capacitor of the first voltage storage circuit stores the first potential difference between the two input voltages of the first pair. And allowing the storage capacitor of the second voltage storage circuit to store a second potential difference between the two input voltages of the second pair, and the output configuration is 1 Since each common terminal of the second voltage storage circuit is operated to connect to the fifth and sixth input nodes, respectively, the potential difference between the first and second output nodes is the first voltage. This makes it possible to generate a pair of output voltages substantially equal to the potential difference between the two input voltages of the three pairs and the sum of the stored first and second potential differences.
[0035]
  Depending on the anti-parallel connection of the two voltage storage circuits, the individual (fixed) amount of charge that is flowed in by each of the switch elements is different from each other at the moment they are switched off. It should be noted that since the circuit is the same, the difference between the input and output of the circuit is effectively eliminated.
  Although the first and second voltage storage circuits have already been described, each has a unity gain amplifier element and, in another preferred embodiment, can be mounted in a voltage doubler circuit. This voltage doubler circuit is doubledRuFirst and second input nodes to which an input voltage is applied during operation of the circuit; first and second output nodes respectively connected to respective output terminals of the first and second voltage storage circuits; And switching means connected to the input node and the voltage storage circuit. The switching means can switch from the input configuration to the output configuration after each input switch element of the first and second voltage storage circuits is changed to the OFF state, and the input configuration is the first configuration described above. An input node is connected to both the input terminal of the first voltage storage circuit and the common terminal of the second voltage storage circuit, and the second input node is connected to the second voltage storage circuit. Each of the storage capacitors of the voltage storage circuit is charged to the input voltage because the storage capacitor is operative to connect to both the input terminal of the first storage circuit and the common terminal of the first voltage storage circuit. And the output configuration is operative to connect each common terminal of the first and second voltage storage circuits to each other, and the storage capacitor is Since the first and second output nodes are connected in series with each other, it is possible to generate an output voltage between these output nodes that is substantially twice the input voltage. To do.
[0036]
Also, the anti-parallel connection of the two voltage storage circuits removes the charge flowing in by the input switch element, so that the voltage that is doubled becomes very accurate. The circuit has an improved speed / power / noise balance and is probably 10 times better than the same conventional proposal.
This voltage doubler circuit is particularly useful when mounted in an analog-digital converter (A / D converter) that performs voltage doubler operation in those conversion operations. This converter is incorporated in the voltage conversion stage. The voltage conversion stage is connected to the voltage doubler circuit as described above and to receive an operating voltage equal to or derived from the input voltage and also to receive a comparison potential and A voltage doubler circuit operable to perform a comparison between its operating voltage and said comparison potential and to provide digital data indicative of the result of the comparison; and a common terminal for each of said first and second voltage storage circuits Between the terminals and after the switching means is switched from the input configuration to the output configuration, a plurality of presets are made between the terminals according to the digital data. Applying an offset voltage having a value selected from the possible values, an offset voltage that differs between the output nodes by an offset voltage selected from twice the input voltage. Having a voltage adjustment means operable to generate a log conversion voltage.
[0037]
When the above-described high-precision voltage doubler circuit is used for this voltage conversion stage, the analog conversion voltage can be obtained from the input voltage with high accuracy preferable without using a complicated switching configuration because two storage capacitors are internally connected. Can be induced. This analog conversion voltage is one of a number of preselected offset voltages chosen based on the magnitude of the input voltage, as required, for example, by a “3-state logic” type analog-to-digital converter. Thus, it can be offset from twice the input voltage. The voltage adjusting means is connected between the common terminals of the first and second voltage storage circuits and is operable to apply the offset voltage between the terminals. Thus, the voltage adjusting means is connected in series with the two storage capacitors in order to cause a potential difference equal to the selected offset voltage between each of the other plates of the capacitors, and each of the storage capacitors Since each has a potential difference between the plates equal to the input voltage, the required offset of the analog conversion voltage from twice the input voltage is simply and high without the use of complex and low precision voltage adders. Achieved with accuracy.
[0038]
Preferably, the comparator means performs the comparison, but the switching means of the voltage storage circuit provides high speed operation with the input configuration.
In a preferred case, the comparator means is connected to the first and second input nodes, so that the input voltage becomes the operating voltage and the input voltage. Providing the digital data when the comparison potential is less than or equal to the negative comparison potential, and providing the second such digital data when the comparison potential is less than or equal to the input potential, and the third Of the digital data in all other cases, wherein the offset voltage selected according to the second digital data is −V_refAnd + V_refBecomes the offset voltage selected based on the first digital data, and the offset voltage selected based on the third digital data becomes zero, and the comparison potential is V_refSubstantially equal to / 4.
[0039]
By omitting the conversion operation performed at this conversion stage for miscode errors that are likely to arise from the offset voltage of the comparator means, the improvement in the accuracy of the voltage conversion operation performed by that stage will improve the overall conversion. Obtained in the form of improved accuracy.
One particularly good analog-to-digital converter is each of the aforementioned voltage conversion stages, wherein the analog voltage to be digitized is applied between the first and second input nodes of the series of first stages, and A sequence of N stages in which the first and second input nodes of the next stage are connected to the first and second output nodes of the previous stage, respectively, and each of the stages The switching means can then be operated to switch from the input configuration to the output configuration, and in each of the stages, except for the first stage, the switching means of the immediately preceding stage is the output configuration. Therefore, the stage to be switched before this switching is an analog conversion power generated by the immediately preceding stage as its input voltage. And for receiving the digital data provided by the N stages of columns and control means for controlling the analog conversion voltage to be generated when the analog conversion voltage is generated after this switching. And data processing means for comparing each N + 1 bit of the applied analog voltage to operate and derive a digital output word therefrom.
[0040]
This analog-to-digital converter can operate very quickly and generate one complete N + 1 bit digital output word of the clock period.
Preferably, the analog-to-digital converter operates alternately with the first and second clock phases, and the control means has an input configuration for each of the odd stages of the column in the first clock phase. Holding the switching means and operating to hold each switching means of the even stages in the output configuration, but holding each switching means of the even stages in the input configuration in the second clock phase, Operate to hold each switching means of the odd stage in the output configuration.
[0041]
This configuration allows the converter to operate at the aforementioned high speed while keeping the control of the stage as simple as desired.
For at least one pair of adjacent stages of the column, each storage capacitor of the first and second voltage storage circuits of the second stage of the pair is more electrostatic than an equivalent storage capacitor of the first stage of the pair. Preferably, the capacity is reduced and the ratio of the storage capacitors of the two stages of one or each pair is about 2: 1. This reduces the power consumption of the converter.
[0042]
For at least one pair of adjacent stages of the column, each amplifier element input device of the first and second voltage storage circuits of the second stage of the pair is more than the equivalent input device of the first stage of the pair. The width is preferably narrowed, and if the ratio of the width of the input devices of the two stages of one or each pair is about 2: 1, the power consumption will be further reduced.
[0043]
Further, for at least one pair of adjacent stages of the column, each current in the controllable current path of the amplifier element input device of the first and second voltage storage circuits of the second stage of the pair is a pair of It is preferable that the current ratio of the two stages of one or each pair is about 2: 1, which is smaller than the equivalent current of the first stage, and can further help to reduce power consumption.
[0044]
Further, in each of the second to nth stages of the converter, where 2 ≦ n ≦ N, the storage capacitors of the first and second voltage storage circuits of the stage are respectively It is preferred to have a capacitance that is reduced by a constant first scaling factor over these second to nth stages, relative to the capacitance of the equivalent storage capacitor of the stage. Scaling the capacitance in this manner by a constant scaling factor can reduce the power consumption of the converter and reduce the chip area required for the manufacture of the converter.
[0045]
The first scaling factor is preferably 2. The value of this scaling factor is optimal for reduced power consumption.
Furthermore, in each of the second to nth stages of the converter, ie here 2 ≦ n ≦ N, the amplifier element input device of each voltage storage circuit of the stage is equivalent to the previous stage. For these amplifier element input devices, the channel width is reduced by a constant second scaling factor over these second to nth stages.
[0046]
Thus, scaling by a constant factor for a number of subsequent stages can also contribute to a reduction in converter power consumption and the chip area occupied thereby.
The second scaling factor is also preferably 2, which leads to an optimal reduction in power consumption.
[0047]
Furthermore, in each of the second to nth stages of the converter, ie here 2 ≦ n ≦ N, the current in each of the controllable current paths of the amplifier element input device of the stage is Preferably, the current in the immediately controllable current path of the previous stage is controlled to be reduced by a constant third scaling factor from these second to nth stages.
[0048]
This scaling can further contribute to reducing the power consumption of the converter.
The third scaling factor is also preferably 2. This value is optimal for reducing power consumption.
In another preferred embodiment, for at least one pair of adjacent stages of the column, at least one of said preset possible values of the offset voltage in the second stage of the pair is: This is partially adjusted by comparison with a corresponding preset possible value of the offset voltage in the first stage of the pair.
[0049]
This partial adjustment can be used to correct the gain error of the amplifier elements used in each stage so that the overall operation of the converter is accurate despite the imperfections of these amplifier elements. Can be maintained.
Alternatively, or additionally, the data processing means may provide digital data provided by the comparator means of each of the next stages in the column to facilitate correction of these next stage voltage conversion errors. Can operate to adjust partially.
[0050]
Another excellent analog-digital converter has first and second stages, each of which is the aforementioned voltage conversion stage, control means, and data processing means. These first and second stages have first and second output nodes of the first stage connected to first and second input nodes of the second stage, respectively, and the second stage of the second stage. The first and second output nodes are connected to each other so as to be connected to the first and second input nodes of the first stage, respectively, and the digitized analog voltage is used for the repetitive conversion operation of the converter. At the beginning, it is applied between the first and second input nodes of the first stage. The control means operates so that the switching means of the first and second stages starts from the first stage and is alternately switched from the input configuration to the output configuration. Since the switching means of the other stage is in the output configuration, one stage before this switching receives the analog conversion voltage generated by the other stage as its input voltage, and the analog conversion voltage is based on this switching based on it. Control to be performed at a certain stage when it is generated later. A data processing means is connected to receive the digital data applied alternately by the first and second stages during the iterative conversion operation and each digital output of an applied analog voltage Operates to derive a word from it.
[0051]
This analog to digital converter results in a preferred compact and simple design since it is required to perform the conversion operation in only two stages.
The voltage conversion circuit according to the second aspect of the present invention operates alternately at the first and second clock phases, and the first and second analog input voltages to be digitized during the operation of the converter are applied. First and second voltage storage circuits including a second input node, unity gain amplifier elements having first and second storage capacitors and input and output terminals, respectively, input sampling means; First and second output nodes respectively connected to the amplifier element output terminals of the second voltage storage circuit, comparator means, voltage adjusting means, switching means, and data storage means are provided. The amplifier elements of the first and second voltage storage circuits are for controlling a controllable current path provided between each first and second current path electrode of the device and the magnitude of the current in this current path. An electrical input device having a control electrode to which a potential is applied, the control electrode being connected to the input terminal of the amplifier element, the first and second current path electrodes being connected to the potential follower means Connected so that the potentials of both the first and second current path electrodes follow the control electrode potential. While current flows through the controllable current path, the potentials of the first and second current path electrodes are maintained to be substantially constant with respect to the potential of the input terminal. The input sampling means operates to connect the input terminal of the first voltage storage circuit to the first input node and connect the input terminal of the second voltage storage circuit to the second input node during the first phase of the clock. To do. The comparator means is further connected to receive the comparison potential at the first and second output nodes, and compares the potential difference between the first and second output nodes with the comparison potential at each clock phase, and shows the comparison result. Give digital data. The voltage adjusting means has a set of connection terminals and has a value selected from a plurality of predetermined values in each clock phase according to the digital data provided by the comparator means at the immediately preceding clock phase. It operates to apply an offset voltage between these terminals. The switching means connects two first storage capacitors and a connection terminal in series between the input terminals of the amplifier element and connects the second storage capacitor between the first and second output nodes in the first phase of the clock. Operating in parallel, in the second phase of the clock, two second storage capacitors and a connection terminal are connected in series between each input terminal of the amplifier element, and the first storage capacitor is connected The first and second output nodes operate so as to be connected in parallel to each other. The data processing means is connected to receive the digital data provided by the comparator means over a plurality of phases of the clock and operates to derive a digital output word representing an applied analog input voltage therefrom. To do.
[0052]
In order to perform the conversion operation with such an analog-digital converter, only one stage is required, and as a result, a design that can be particularly downsized is possible. The analog-to-digital converter of the third aspect of the present invention has a plurality of similar voltage conversion stages connected in series so that the output of one stage becomes the input of the next stage. Each stage has a storage capacitor that is selectively connected to the input of the stage to store the input voltage of the stage, and a storage capacitor and stage to provide an output voltage of the stage that depends on the stored input voltage. And an amplifier element selectively connected between the outputs. In at least one stage except the first stage of the column, the storage capacitor capacitance is less than the storage capacitor capacitance of the previous stage, or the width of the amplifier element input transistor is the input transistor of the previous stage amplifier element. Less than the width of both, or both.
[0053]
An analog-to-digital converter having such a “scaled” series of voltage conversion stages provides a trade-off that makes the overall improved relationship between noise and power consumption appropriate. The factor (scaling factor) for scaling the storage capacitor capacitance and / or the input transistor width from one stage to the next is preferably close to two. Scaling may be stopped in only the first few stages, for example, sequentially scaled for the first 6 stages, with the remaining stages being a constant size.
[0054]
【Example】
The voltage storage circuit of FIG. 1 is preferably an electrical switch element 1 (hereinafter referred to as a MOSFET transistor), which is a MOSFET transistor, a storage capacitor 2, a unity gain buffer 3, and an output terminal circuit and a gate electrode (control) of the MOSFET transistor 1. The switch driving means 4 and 5 are bootstrapped and connected between the electrodes).
[0055]
FIG. 2 shows a first example of the structure of the amplifier element 3 of the circuit of FIG. The element 3 has two basic parts, that is, a cascade source follower 31 and a current source 32.
The cascade source follower 31 includes an n-channel MOSFET input transistor 33 whose gate electrode is connected to one plate of the storage capacitor 2 (upper plate in FIG. 1). The drain-source channel of the input transistor 33 is connected in series with the drain-source channel of a further n-channel MOSFET transistor, now referred to as the cascade transistor 34. The drain electrode of the cascade transistor 34 is the positive power supply line V of the circuit._ddHowever, the source electrode of the input transistor 33 is connected to the output terminal OUT of the circuit.
[0056]
Also in the cascade source follower 31, a bias generator 35 is connected between the source electrode of the input transistor 33 and the gate electrode of the cascade transistor 34. The bias generator operates to maintain a substantially constant potential difference between the gate electrode of the cascade transistor and the source electrode of the input transistor 33 regardless of variations in the source electrode potential.
[0057]
The current source 32 is configured in substantially the same way as the cascade source follower 31, and the output terminal OUT of the circuit and the negative power supply line V of the circuit._ssTwo n-channel MOSFET transistors 36 and 37 (corresponding to the transistors 33 and 34 of the cascade source follower 31, respectively) connected in series between the gates of the transistor 37 and a substantially constant potential difference. It has an associated bias generator 38 (corresponding to the bias generator 35 of the cascade source follower 31) that operates to hold between the electrode and the source electrode of the transistor 36. In this case, the source electrode of the transistor 36 is the negative power supply line V._ssSince the gate electrode potential of the transistor 37 is fixed to the negative power supply line. The current source 32 has a bias input BIAS connected to the gate electrode of the transistor 36. A bias potential can be applied to the bias input of current source 32 to control the operation of the element, as will be described later.
[0058]
Since the current source 32 is connected in series with the cascade source follower 31, it is connected to the positive and negative power lines V._ddAnd V_ssIt works to complete the current path between.
With respect to the operation of the amplifier element of FIG. 2, the current source operates so that a substantially constant current flows through each of the transistors 33 and 34 of the aforementioned current path or cascade source follower 31. This causes the source electrode potential of the input transistor 33 to follow the gate electrode potential, so that the potential V of the output terminal_OFollows the potential Vc of the upper plate of the storage capacitor 2. Therefore, the voltage gain of the element substantially becomes a unit value.
[0059]
Similarly, the source electrode potential of the cascade transistor 34 is made to follow the gate electrode potential, and the potential is sequentially held by the bias generator 35 so as to be substantially fixed with respect to the source electrode potential of the input transistor 33. . Therefore, the drain electrode potential of the input transistor 33 follows the source electrode potential, and the potential V of the upper plate of the storage capacitor 2._cWill follow.
[0060]
As will become apparent, the potential V of the top plate of the storage capacitor 2_cRegardless of the above, the source and drain electrode potentials of the input transistor 33 are substantially fixed to each other and to the gate electrode potential of the input transistor. Therefore, gate-source, gate-drain, drain-source parasitic capacitance C_gs, C_gd, C_dsAre not charged or discharged even if the potential Vc of the upper plate of the storage capacitor 2 fluctuates, so that these parasitic capacitances do not substantially affect the voltage stored in the storage capacitor 2.
[0061]
Since the input transistor 3 is a FET input transistor, the gate current is substantially zero and the charge stored in the storage capacitor is substantially removed by the operation of the amplifier element 3 after the input switch element 1 is opened. Not.
In the case of the amplifier element of FIG. 2, the actual output terminal potential is the upper plate potential V_cIs not exactly equal, but is slightly reduced according to the gate-source voltage difference when transistor 33 is on, as shown below:
V_O= V_C-(V_T+ V_DSAT)
Where V_TIs the threshold voltage of the input transistor 33 and V_DSATIs the saturation voltage of the input transistor 33.
[0062]
As is apparent from FIG. 2, the cascade source follower 31 and the current source 32 are configured in substantially the same manner. Accordingly, the corresponding portion of the input transistor 33 of the cascade source follower 31 becomes the transistor 36 by the current source 32, and the aforementioned bias potential is applied to the transistor 36. Since the same current flows through the drain-source channel of each of transistors 33 and 36 and these transistors are the same size, the gate-source potential of transistor 33 is to adjust the gate-source potential of transistor 36 of current source 32. Can be controlled accordingly. Since the gate-source potential of this transistor 36 is equal to the difference between the bias potential and the potential of the negative power supply line, when an appropriate constant bias potential is applied to the bias terminal, the output terminal potential Vo and the top of the storage capacitor 2 Plate potential V_CThe difference between can be set to the desired small constant level.
[0063]
In the case of the amplifier element of FIG. 2, the transistors 33, 34, 36, 37 can be depletion or enhancement type.
FIG. 3 shows a more detailed example of the structure of the amplifier element 3 that uses a depletion type n-channel MOSFET transistor to provide high speed operation. In the case of the example of FIG. 3, the amplifier element again carries the cascade source follower 31 and the current source 32, and the FET input transistor 33 of the cascade source follower 31 is the cascade source already described with reference to FIG. Reconnected to the follower configuration, the gate electrode of the transistor 33 is connected to the potential V of the upper plate of the storage capacitor 2._CThe source electrode of the transistor 33 is connected to the output terminal OUT of the circuit, and the drain electrode of the transistor 33 is connected to the circuit via the first and second cascade transistors 341 and 342. Positive power line V_ddIt is connected to the.
[0064]
In this case, the cascade bias generator 35 includes three series-connected transistors 351, 352, and 353 connected to apply an appropriate bias potential to the gate electrodes of the first and second cascade transistors 341 and 342, respectively. Therefore, the gate electrodes of the cascade transistors 341 and 342 are each held at a potential that is substantially fixed with respect to the source electrode potential of the input transistor 33.
[0065]
The current source 32 of the amplifier element in FIG. 3 is configured in the same manner as the cascade source follower 31, and the source electrode of the input transistor 31 and the negative power supply line V_SSThree series-connected transistors 36, 371, and 372 (corresponding to the transistors 33, 341, and 342 of the cascade source follower 31, respectively) connected between are mounted. In this case, the gate electrode potential of the transistor 36 (which is the same as the bias potential applied to the bias input of the amplifier element of FIG._SSThe gate electrode potential of each of the transistors 371 and 372 is applied to the bias generator 38 (configured in the same manner as the bias generator 35 of the cascade source follower 31), which includes three series-connected transistors 381 to 383. Is given by. It can be seen that the bias generators 35 and 38 are connected in series with each other between the positive and negative power supply lines to complete additional current paths therebetween.
[0066]
In the case of the amplifier element of FIG. 3, the gate electrode of the transistor 36 of the current source 32 is connected to the negative power supply line V._SSAre directly connected to each other, the potentials of the gate and the source of the transistor 36 are equal to each other. Since the same drain-source current flows through the input transistor 33 as if it flows through the corresponding transistor 36 of the current source 32, and the cascade source follower 31 and the current source 32 have substantially the same configuration, the cascade source follower 31 The potentials of the gate and source are also substantially the same in terms of potential. Therefore, the voltage gain of the amplifier element of FIG. 3 is closer to the unit value (approximately 0.9995) than the amplifier element of FIG. Similar to the amplifier of FIG. 2, the amplifier element of FIG. 3 can also operate at high speed. In other respects, however, the operation of the element of FIG. 3 is substantially the same as the amplifier element of FIG.
[0067]
Returning now to FIG. 1, the bootstrap switch drive means has an input connected to the output terminal of the circuit, and each of its outputs has a potential V having a fixed offset from the output terminal potential._highAnd V_low(V_high> V_low) Is installed. These two potentials must be at appropriate levels in addition to the gate electrode of MOSFET 1 to hold it in its on and off conditions.
[0068]
Two potentials V_highAnd V_lowIs applied as an input to a selector element 5 which also receives a switching signal CK. The output of the selector circuit 5 is connected to the gate electrode of the MOSFET switch element 1 in order to control its potential. The selector element 5 sets the gate electrode potential to two potentials V._highAnd V_lowSwitching based on the switching signal CK. This signal CK becomes a logic signal given by a digital logic circuit that controls the operation of the voltage storage circuit.
[0069]
In order to prevent accidental charge inflow by the MOSFET input switch element 1 to the storage capacitor 2 when the input switch element is turned off, the control potential applied to the gate electrode of the MOSFET will now be explained using the example of FIG. Thus, at least when the MOSFET is on, it must be substantially fixed with respect to the input terminal potential.
[0070]
FIG. 4 shows in detail the input switch element 1, in this case an n-channel enhancement type MOSFET. MOSFET 1 includes a source electrode that provides an input terminal IN of the switch element, a drain electrode that provides an output terminal OUT of the switch element, and the two control potentials V described above._highAnd V_lowThe gate electrodes are connected so that they can be switched alternately. The drain-source channel of a transistor becomes non-conductive when the potential of its gate channel is zero (or negative), and the applied control potential is V_low(≦ V_O), The output terminal of the switch element is separated from its input terminal, and the off-resistance (R_off) Is generally greater than 10,000 MΩ. Gate potential is V_high(> V_O) Is charged to the on-resistance (R_on) Is in units of 10 or 100 s ohms.
[0071]
In the case of an analog-to-digital converter using a voltage storage circuit as illustrated in FIG. 1, it is usually required that the operation of the switch element 1 be controlled by the converter's digital logic, and in part For this reason, digital logic potentials that are fixed in conventional proposals (eg 0 volts and + V_ddVolts) have been added for convenience to the gate to control the switching of the element.
[0072]
However, problems arise when this digital logic potential is used as described herein.
The MOSFET switch element 1 in FIG. 4 is unavoidably parasitic gate-channel capacitance C_gsBetween the gate electrode and the drain-source channel. This parasitic capacitance has a first component due to the physical overlap between the gate and the channel of the FET and a second component associated with the charge stored in the channel when the FET is on. . This second component together with the channel potential (ie the potential V of the signal to be switched)_iWith) but fluctuates accidentally.
[0073]
The capacitance of the gate channel changes at the instant t._switchCharge inflow to the channel from the gate, which in turn gives an error to the stored voltage. The charge inflow due to the first component of the capacitance of the gate channel is t_switchGate voltage at ΔV_GIs basically dependent on the fluctuations of (eg 0-V_DD= -V_DD) So t_switchChannel potential V at_iIs virtually independent of However, the charge inflow caused by the second component of the capacitance of the gate channel is the potential V of the input signal corresponding to the gate potential at the moment of switching._iWhich results in errors and non-linearities in the operation of the voltage storage circuit described above.
[0074]
Compensating for such charge inflow, eg, by combining the inverted version of the gate signal through a slightly adjustable capacitor, is not a practical method, because the second of the gate channel capacitance described above. This is because the components cannot be accurately predicted.
In the case of a conventional proposal using a fixed control potential, such as a digital logic potential, the instant t of switching_switchThe effect of charge influx on is increased when it is desired to use a storage capacitor with a small capacitance in order to shorten the circuit achievement time.
[0075]
However, in the case of the bootstrapped switch driving means 4, 5 of FIG. 1, at least the control potential applied to the switch element 1 is the potential V of the input terminal in order to keep it in the ON condition._iSo that the amount of charge flowing in by element 1 becomes substantially constant regardless of the input terminal potential when it is switched off. Since this charge inflow is constant, it leads a constant error to the stored voltage, which can be easily compensated.
[0076]
The control potential applied to the switch element 1 in some cases is the input potential V as shown in FIG._iIt may be possible when held in an off condition that is fixed (as opposed to on) rather than changing in This is due to the parasitic capacitance C of the gate channel described above._gcThis is because the first component is a linear characteristic.
Required potential V_highAnd V_lowDepends on the MOSFET NO type used for MOSFET 1 and the threshold voltage. This switch element is an enhancement type or a depletion type and can be an n-channel or a p-channel. For an n-channel MOSFET, V_highIs applied to the gate electrode, turns on the MOSFET (ie V_highBecomes ON potential), V_lowIs added to turn it off (ie V_lowIn the case of a p-channel MOSFET, V_highIs applied to the gate electrode to turn off the MOSFET (ie V_highBecomes OFF potential), V_lowIs turned on (ie V_lowBecomes ON potential).
[0077]
Threshold voltage V_TFor an n-channel MOSFET with a low on-resistance,
V_high-V_i≧ V_T+ V_on
Where V_onIs a preset potential difference.
Similarly, at high off-resistance,
V_low-V_i<V_T+ V_off
Where V_offIs also a preset potential difference.
[0078]
The difference between the on and off potentials is therefore V_on+ V_offWhich must be at least several hundred mV.
Output terminal potential V_ODirectly using the two potentials V_highAnd V_lowCan be given. For example, if MOSFET switch element 1 is an n-channel depletion type switch element, V_highIs simply V_Obecome. Similarly, if MOSFET switch element 1 is an n-channel enhancement type switch element, V_lowIs the output terminal potential V_Obecome.
[0079]
In the voltage storage circuit of FIG. 1, a potential generation circuit 4 is shown inserted between the output terminal and the selector circuit 5. However, this circuit 4 has the required potential V_highAnd V_lowMay be omitted in some cases when it can already be used on the conventional internal bias line of the circuit, in particular on the internal bias line of the amplifier element 3. Instead, as will be explained in more detail later using the example of FIG._highAnd V_lowIs the potential V_highAnd V_lowMay be derived from an internal bias line potential that is not directly suitable to provide
[0080]
In the example of the exact configuration of the amplifier element 3 described above, it is clear that the amplifier element is equipped with bias generators 35 and 38 that provide a gate electrode bias voltage on the internal bias line of the element. These bias voltages follow the potential at the output terminal.
The potential levels of these internal bias lines are suitable for directly providing the required on and off potentials for use in controlling the switching of the switch element 1, in which case the potential of the circuit of FIG. The generation circuit 4 can of course be omitted entirely.
[0081]
In other cases, the amplifier element has a pair of internal bias lines between which the potential difference between the required on and off potentials (V_on+ V_off) Seems to be greater or equal. However, the potential level of each of the paired internal bias lines may not necessarily be suitable for directly providing on and off potentials. Instead, one of the required on and off potentials is, for example, an on potential in the case of an enhancement type MOSFET switch element or an off potential in the case of a depletion type MOSFET switch element. You may need to be located outside.
[0082]
These difficult problems can be solved by adopting a circuit configuration suitable for the amplifier element 3 and the switch driving means 4 and 5, which will be described next with reference to FIG.
In the case of FIG. 5, the amplifier element 3 is mainly made of enhancement-type n-channel MOSFET transistors, but may be configured in a similar state to the example shown in FIGS. Source follower 31 and current source 32 are connected to positive power supply line V_ddAnd negative power line V_ssAre connected in series. As described above, the cascade source follower 31 includes the input transistor 33 and the cascade transistor 341 in addition to the positive power supply line V._ddAnd a transistor 342 connected between the drain electrode of the transistor 331 and the positive power line V_ddA cascade bias generator 35 is mounted between the source electrode of the input transistor 33 and a transistor 351 and 352 connected in series together with a further transistor 353. In this case, the output terminal OUT of the circuit is at substantially the same potential as the gate electrode of the transistor 33 when the amplifier element is in operation, ie the voltage V of the upper plate of the storage capacitor 2 connected to the gate electrode._CIs connected to the drain electrode of the transistor 351. In this regard, transistors 342 and 353 are selected to form a PMOS current mirror that functions to reduce amplifier gain error by ensuring that the current in transistor 351 is the same as input transistor 33. And connected so that the output voltage substantially follows the input voltage. However, it should be noted that this use of the PMOS current mirror is optional.
[0083]
The amplifier element 3 of FIG. 5 is equipped with a first internal bias line L1 connected to the source electrode of the transistor 31. When current is flowing, this internal bias line is connected to the threshold voltage V of transistor 31._TCapacitor voltage V by a magnitude equal to_CLower potential V₁ That is, V₁ = V_C-V_TRetained.
[0084]
Amplifier element 3 carries a further bias line L 'connected to the drain of transistor 351 of the cascade bias generator, where the bias line (described above) is substantially a capacitor when the circuit is in operation. Voltage V_CAlthough being held, the potential difference between the internal bias lines L1 and L ′ is the aforementioned potential difference (V between the on and off potentials required for the control of the switch element 1)._on+ V_off) Is smaller. However, transistor 352 between transistors 351 and 352 of cascade bias generator 35 has a threshold voltage V of transistor 352 in the second bias line L2 of the element._TOutput terminal potential V by a magnitude substantially equal to_OMore always the magnitude potential V₂Operates to generate The potential difference between the first and second bias lines L1 and L2 is the threshold voltage 2V of the two transistors._TWhere the potential difference is the required difference between the on and off potentials of the switch element 1 (V_on+ V_off) Greater than or equal.
[0085]
These potentials V₁ And V₂An example of switch drive means 4 and 5 that can generate the required on and off potentials using is now described. In this example, the switch element 1 is an n-channel enhancement type, so that the OFF potential V_lowIs the output terminal potential V_OThe on potential is V_high≒ V_low+ 2V_TThis on potential becomes the positive power line V in this example._ddCan be higher.
[0086]
In FIG. 5, the potential generating means 4 is connected to the bootstrap capacitor 44 to provide a controllable connection between the plate of the bootstrap capacitor 44, the internal bias lines L1 and L2 and the output terminal OUT. The connection means 45 for mounting the transistors 451 to 453 is mounted.
The transistors 451 to 453 of the connection means 45 each receive a logic signal SW whose logic level is high when the switch element 1 is off and whose logic level is low when the switch element 1 is on.
[0087]
Since the logic signal SW is derived from the switching signal CK used to control the switch element 1, it can be changed from a high logic level to a low logic level based on the switching signal CK.
Since the transistor 451 is a p-type transistor, it is turned on when the logic level of the logic signal SW is low, and the transistors 452 and 453 are n-type transistors and are turned on only when the logic level of the logic signal SW is high.
[0088]
The p-type transistor 451 is connected between the second bias line L2 and the negative plate of the bootstrap capacitor 44, and the n-type transistor 452 is connected between the plate and the first bias line L1. The n-type transistor 453 is connected between the positive plate of the bootstrap capacitor 44 and the output terminal OUT.
[0089]
The positive plate of the bootstrap capacitor 44 is connected to the gate electrode of the switch element 1 in a permanent structure.
The operation of the switch driving means 4 and 5 in FIG. 5 is as follows. Since the n-type transistors 452 and 453 are switched on when the logic signal SW is at a high logic level that causes the switch element to turn off, the positive plate of the bootstrap capacitor 44 and the gate electrode of the switch element 1 are connected to the output terminal V._O(V_low), But the negative plate of the capacitor 44 is the potential V of the first bias line L1.₁(= V_O-V_T). Therefore, the bootstrap capacitor is V_TIs charged to a potential substantially equal to
[0090]
When the logic signal SW is changed from a high logic level to a low logic level in response to the switching signal CK and the switch element is turned on, both the n-type transistors 452 and 453 are turned off, and the p- The type transistor 451 is switched on. Therefore, the negative plate of the bootstrap capacitor 44 is connected to the potential V of the output terminal._OWhen separated from V₁ To V₂Will be changed. As a result, the potential of the positive plate is changed by the fluctuation of the negative plate potential (V₂-V₁≒ 2V_T), And the positive plate potential is V₂-V₁Only changes. As a result, the electrode potential of the gate of the switch element 1 is even if V_O+ 2V_T> V_ddEven in the case of_O(= V_LOW) To V + 2V_T(= V_high).
[0091]
The capacitance of the bootstrap capacitor 44 ensures that the rate of change of the positive plate potential of the bootstrap capacitor 44 at the moment of switching is not unduly small compared to the corresponding change at the negative plate potential. Therefore, it should be noted that it is larger than the capacitance of the gate of the switch element 1.
[0092]
As mentioned above, using a bootstrap capacitor and appropriate connection means that operate based on the switching signal CK used to control the switching, the required on and off potentials are applied to the internal bias line of the circuit. From the potential, these lines can be derived even when they do not have a potential that is suitable for providing their on and off potentials directly. The bootstrap capacitor 44 also allows these on and off potentials to be external to the circuit power line. Furthermore, the use of an internal bias line that is already present in the circuit when generating on and off potentials results in significant savings in the required circuit size.
[0093]
Preferably, the voltage storage circuit of FIG. 1 includes all parasitic capacitances of the circuit, including the capacitance of the switch element 1, the input capacitance of the amplifier element 3, and the capacitance of any internal connections. It is configured as an integrated circuit to allow bootstrap.
To achieve this purpose, the components of the switch element 1, storage capacitor 2 and amplifier element 3 of the circuit of FIG. 1 are of a conductivity type well (represented by 7 in FIG. 1) opposite to the surrounding members of the substrate. ). For example, when the integrated circuit is a CMOS type having an n-substrate, the well 7 in which the switch element 1, the storage capacitor 2, and the buffer element 3 are formed is a p-conductive type. The well has a potential V of the upper plate of the storage capacitor 2._CConnected so as to be substantially fixed. For example, the well can be electrically connected to the output terminal of the circuit, as illustrated in FIG.
[0094]
FIG. 6 shows one possible layout for the voltage storage circuit of FIG. 3 when the amplifier element 3 is substantially configured as shown in FIG. 2 within the integrated circuit. Yes. As shown in FIG. 6, the switch element 1, the storage capacitor 2, the input transistor 33, and the cascade transistor 34 of the amplifier element 3 are formed inside a p-well 7p formed of an n-substrate 8n. . The current source 32, the current source bias generator 33 (both not shown in FIG. 6), the cascade bias generator 35 and the switch driving means 4 and 5 are formed outside the well 7p. The cascade bias generator 35 and the switch driving means 4 and 5 can alternatively be located inside the well.
[0095]
As shown in detail in FIG. 6, the input voltage of the circuit of FIG. 1 is applied between its input terminal (IN) 11 and common terminal (COM) 12, which is the lower plate of the storage capacitor 2. 21 is connected. The upper plate 22 of the storage capacitor 2 is also connected to the gate electrode 33 g of the transistor 33 and the drain electrode 1 d of the switch element 1. A source electrode 1 s of the switch element 1 is connected to an input terminal (IN) 11.
[0096]
The output terminal (OUT) 13 of the circuit is connected to the source electrode 33 s of the transistor 33, and the transistor 33 is formed by mounting a common channel 33 c together with the cascade transistor 34. The drain electrode 34d of the cascade transistor 34 is a positive power rail V_ddThe gate electrode 34g is connected to the output terminal 13 via the cascade bias generator 35. The switch driving means 4 and 5 are connected between the output terminal 13 of the circuit and the gate electrode 1g of the switch element 1.
[0097]
As shown in FIG. 6B, the p-well 7p is n⁺P given inside p-well 7p at that position adjacent to channel 33c⁺The contact portion 9 is electrically connected to the output terminal 13. The contact 10 connects the contact portion 9 to the output terminal 13 as shown in FIG. Also, as shown in FIG. 6B, a shield 15 is optionally provided for the device inside the well, where the shield is electrically connected to the output terminal 13 of the circuit by a contact 16. Connected.
[0098]
It will be appreciated that the MOSFET switch element 1 and transistors 33 and 34 of the amplifier element 3 must be of the n-channel type since they are formed in FIG. 6 with p-wells.
In the case of the amplifier element of FIG. 3, the cascade source follower 31 (including the FET input transistor 33, the cascade transistors 341 and 342, and the transistors 351 to 353 of the cascade bias generator 35) is a circuit on which the storage capacitor 2 and the switch element 1 are mounted. Are formed entirely inside the p-well. As described above, the well is electrically connected to the output terminal OUT of the circuit, for example. The current source 32 of the amplifier element of FIG. 3 is then formed with a second p-well that must be electrically connected to the point of the circuit. The potential is fixed with respect to the power supply line of the circuit, for example, the negative power supply line itself.
[0099]
In the case of the circuit of FIG. 1, it is not essential that the switch element 1, the storage capacitor 2, and the amplifier 3 are formed in one well. In the case of FIG. 7, the switch element 1, the storage capacitor 2, and the amplifier element 3 are formed by different p-wells 71p, 72p, and 73p, respectively.
[0100]
The p-well 71p is electrically connected to the circuit output terminal (OUT) 13 via the auxiliary buffer element 17 and contacts 18 and 19, and is at a potential substantially fixed with respect to the output terminal. Therefore, the potential is substantially fixed with respect to the potential of the upper plate of the storage capacitor 2.
The p-well 72p is electrically connected to the lower plate 21 of the storage capacitor via the contact 23 in order to have a potential that is substantially fixed with respect to the potential of the upper plate when the switch element 1 is in an OFF condition. Connected.
[0101]
Since the p-well 73p is electrically connected to the output terminal (OUT) 13 of the circuit by the contact 18, it also becomes a potential that is substantially fixed with respect to the potential of the upper plate of the storage capacitor 2.
The components 14 and 24 of the internal connection portion between the circuit elements 1 and 2 outside the wells 71P, 72p, and 73p extend to the internal connection shield portions 151 and 152 in which the potential is kept the same as the potential of the well. Therefore, the parasitic capacitance associated with the internal connection can be removed.
[0102]
The well 72p of the storage capacitor 2 is optional.
A particularly good application of the voltage storage circuit already described with reference to FIGS. 1 to 5 will now be described with reference to FIG.
FIG. 8 shows a voltage adder circuit using a voltage memory circuit configured as described above with reference to FIG.
[0103]
The voltage adding circuit includes the input switch element 1 and the first input node I in addition to the components of the voltage storage circuit of FIG.₁ Input isolation switch element 46 connected in series to that element between and on one side, respectively, second and third input nodes I₂And I_ThreeOn the other side, the selection switch element 47 connected between the common terminals COM of the voltage storage circuit, and the feedback switch connected between the output terminal OUT of the voltage storage circuit and the input side of the input switch element 1 The element 48 is mounted.
[0104]
An auxiliary capacitor 49 is also optionally provided connected between the input side of the input switch element 1 and the common terminal COM of the voltage storage circuit, in which case the feedback switch element 48 can be omitted.
When the voltage adding circuit of FIG. 8 is used, both the switch elements 1 and 46 are originally controlled to be on, but the feedback switch element 48 is kept off. At this time, the selection switch element 47 is connected to the second input node I.₂And a common terminal COM of the voltage storage circuit. When the input switch element 1 of the voltage circuit is switched off, the first and second input nodes I₁And I₂Potential difference between₁-V₂Results in being stored in the storage capacitor 2 of the voltage storage circuit at the moment of switching.
[0105]
Thereafter, the input isolation switch element 46 is also turned off and the feedback switch element 48 is turned on. As a result, the potential on the input side of the switch element ON is equal to the potential V of the upper plate of the storage capacitor 2 regardless of the next fluctuation of the potential of the first input node after the input switch element 1 is turned off._CIs held substantially constant.
[0106]
When the auxiliary capacitor 49 is between the input side of the input switch element 1 and the terminal COM of the voltage storage circuit, this auxiliary capacitor is turned off instead of or in addition to the feedback switch element 48. Later, the potential on the input side of the input switch element 1 is the potential V of the upper plate of the storage capacitor 2._CTo be fixed substantially constant.
[0107]
The holdability of the input side potential after the input switch element 1 is switched off is when the potential of the first input node changes sufficiently with respect to the off potential applied to the gate electrode of the input switch element 1. It is desirable to prevent the possibility of being switched on again.
At the same time or after the input isolation switch element 46 is turned off, the configuration of the selection switch element 47 is the third input node I_ThreeThe second input node I to the common terminal COM₂Changed to connect instead of.
[0108]
As a result, the potential of the output terminal is the difference V V stored in the potential V3 of the third input node between the potentials of the first and second input nodes.₁-V₂Is substantially equal to the potential plus
V_O= V₁-V₂+ V_Three+ V_error
Where V_errorIs the stored potential difference V generated by the charge inflow by the input switch element 1 at the moment of turning off.₁-V₂This is an error voltage. As described above, when the ON potential applied to the input switch element 1 follows the potential of the input node, the error voltage V_errorIs substantially constant regardless of the potential applied to the circuit, so that this error voltage can be compensated in the desired simple state.
[0109]
By effectively removing the effects of parasitic capacitance in the voltage storage circuit, the potential of the lower plate of the storage capacitor does not affect the stored potential difference in an unpredictable manner, but the desired potential difference. It will be appreciated that it can be freely changed after storage. This allows a voltage storage circuit configured as already described in FIG. 1 to provide a particularly high accuracy for voltage summing applications.
[0110]
As a further excellent application of the voltage storage circuit of FIG. 1, FIG. 9 shows the first and second voltage storage circuits VSC.₁And VSC₂FIG. 2 shows a voltage doubler circuit 50, each of which is configured as already described in FIG.
Circuit 50 includes first and second input nodes I.₁And I₂And first and second output nodes O₁And O₂It is equipped with. The first controllable switch element 51 is a first voltage storage circuit VSC.₁First input node I of₁And input terminal IN₁Connected between. The second controllable switch element 52 is a first voltage storage circuit VSC.₁Second input node I of₂And common terminal COM₁Connected between.
[0111]
The third controllable switch element 53 is a second voltage storage circuit VSC₂First input node I of₁And common terminal COM₂Connected between. The fourth controllable switch element 54 is a second voltage storage circuit VSC.₂Second input node I of₂And input terminal IN₂Connected between.
The fifth controllable switch element 55 is a voltage storage circuit VSC.₁And VSC₂Each common terminal COM₁, COM₂Connected between.
[0112]
First and second voltage storage circuits VSC₁And VSC₂Each output terminal OUT₁And OUT₂Are the first and second output nodes O of the circuit 50.₁And O₂Is connected to each.
The circuit 50 receives the first control signal φ₁To the switch elements 51 to 54 and the second control signal φ₂Is further provided with control means 60 for applying to the switch element 55. The control means 60 is a voltage storage circuit VSC.₁And VSC₂In addition, the aforementioned switching signal CK used for controlling the switching of each switch element 1 of the voltage storage circuit is also applied. The switch elements 51 to 54 have a control signal φ₁Is controlled to be on when the signal is active, and the switch element 55 is controlled by the control signal φ₂ON condition is controlled when is active. Since the generation of the switching signal CK applied to each switch drive means 4, 5 of the voltage storage circuit is synchronized by the control means 60 to the switching of the control switch elements 51 to 55, the voltage storage circuit VSC.₁And VSC₂Each switch element 1 is held in the on condition when the switch elements 51 to 54 are initially in the on condition, but is turned off before these elements 51 to 54 are switched to the off condition.
[0113]
In the operation of the voltage doubler circuit of FIG.₁Is actuated first, and the controllable switch elements 51 to 54 are first actuated to an on condition, at which time switch element 55 is turned off. Therefore, φ₁Is activated, the switch elements 51 to 55 are connected to the input node I.₁And I₂Input voltage Vi between each input and voltage storage circuit VSC₁And VSC₂It becomes an input configuration that allows it to be added between each common terminal.
[0114]
During this input configuration, the switch elements 51 to 55 are connected to the voltage storage circuit VSC.₁And VSC₂Each switch element 1 is controlled by their associated switch drive means 4, 5 in the on condition. As a result, each storage capacitor 2 has an input voltage V_iAre each charged. In this regard, the input voltage is the first voltage storage circuit VSC.₁The second voltage storage circuit VSC₂It is noted that the polarity is reversed.
[0115]
While the switch elements 51 to 54 are switched on, the control means 60 switches to each switch drive means 4, 5 of the voltage storage circuit to switch off each switch element 1 of the voltage storage circuit. Apply signal CK. As a result, t of switching_switchInput voltage V at the moment_isIs stored in each storage capacitor 2 of the voltage storage circuit.
[0116]
Thereafter, the control means 60 controls the control signal φ₁Switch element 51-54 is switched off, and then the control signal φ₂Switch element 55 is turned on. Under this condition, the switch elements 51 to 56 have an output configuration. In this output configuration, the voltage storage circuit VSC₁And VSC₂Each storage capacitor 2 is connected to a voltage storage circuit VSC.₁And VSC₂Are connected in series between the respective inputs of the amplifier elements 3. Since the amplifier elements 3 of these voltage storage circuits function only to regenerate the potential of their inputs at their respective outputs, the first and second output nodes O₁And O₂Output voltage V generated during_OIs the stored input voltage V_isIe V_O= 2V_isIs substantially equal to twice.
[0117]
Therefore, the circuit 50 has a switching t_switchThe input voltage V applied at the moment of_iOutput voltage V that is substantially twice_OAct to give.
The circuit of FIG. 9 can eliminate the influence of the parasitic capacitance of the circuit, and can give a very high accuracy to the double voltage. This is because, in the voltage storage circuit having the above-described configuration, the parasitic capacitance that affects the applied input signal (that is, the capacitance of the input switch element 1, the capacitance of the input of the amplifier element 3, and the voltage). This is because the capacitance of any internal connection portion of the memory circuit can be bootstrapped. Considering the fact that a voltage storage circuit is conveniently formed in each well (to allow bootstrap of the parasitic capacitance of the internal connections of the voltage storage circuit), the voltage doubler circuit 50 is generally advantageous. Should be formed as an integrated circuit.
[0118]
It should be noted that this voltage doubler approach is fundamentally different from that used in conventional switched capacitor circuits used to implement voltage doublers. In these conventional circuits, circuit operation is such that all nodes of the circuit are driven by the amplifier (to prevent parasitic capacitance from being charged and affecting the amplifier output). Or insensitive to parasitic capacitance by ensuring that it is always returned to the same voltage at all clock phases (the “virtual ground” so that the actual charge does not flow into or out of the parasitic capacitance) It is designed to be. An example of the latter approach is given in European Patent Publication No. 214831 (EP-B-0214831).
[0119]
If the circuit is designed to be insensitive to parasitic capacitance, the problems caused by the parasitic capacitance are essentially eliminated, but removing the parasitic problem will memorize the input voltage. And leads to another problem associated with the unavoidable mismatch between the capacitors used to double, which prevents the desired high accuracy from being achieved.
[0120]
The problem is that, in the case of a conventional voltage doubler circuit based on a switched capacitor, the variation maintained during the operation of the voltage doubler is charged rather than the voltage of the circuit of FIG. 11 (transmitted from one capacitor to another). It occurs because it is.
Considering this problem in more detail, in order to double the voltage when the charge is maintained, a number 2C capacitor (or two in parallel, each number C two capacitors) is connected to the input voltage. It is charged and then all charges are transferred to one capacitor, number C, which may or may not be the first capacitor charged. Charge retention gives the following relational expression.
[0121]
2C ・ V_in= C ・ V_out
V_out= 2V_in
However, in the actual circuit, the output voltage V_outIs exactly the input voltage V_inIt is recognized that this is due to a mismatch between the capacitance of each of the capacitors used to perform the double voltage operation. In this regard, the input voltage V_inThe capacitance of each of the two capacitors charged in the₁And C₂And the capacitance C of the third capacitor that receives the combined charge stored in these two capacitors_ThreeIs C_ThreeThus, retention of electric charge gives the following relational expression.
[0122]
                (C₁+ C₂) ・ V_in  = C_Three・ V_out
V_out = [(C₁+ C₂) / C_Three] V_in
Nominally random mismatches between the same capacitors are typically 0.1% (relatively easy to achieve on an integrated circuit) and 0.01% (extreme attention is divided and pinched on the unit, for example) Required for large capacitors). The capacitance mismatch error results in an equivalent error leading to a double voltage, and when the voltage doubler circuit is used in an analog to digital converter, for example, the linearity of the analog to digital converter is 10 And 13 bits will be limited by the error.
[0123]
Errors due to capacitance mismatch in the conventional charge propagation based on voltage doubler circuits can be eliminated using complex switching configurations. One conventional method is to use a capacitor C₁Is charged to the input voltage and the charge is stored in the storage capacitor C₂The charge C₁Is recharged to the input voltage and then all charges are transferred to C₁It has returned to. This results in an accurate double voltage of the input since the charge starts and ends with the same capacitor, but this method is more complex and slower (and more related to the clock phase), and also to the switching noise of the amplifier. It becomes more sensitive to it.
[0124]
Another conventional method includes an additional circuit that performs "auto calibration", i.e., measures and adjusts capacitor mismatch. The structure of this circuit, however, makes the circuit increasingly complex and slows down the speed of operation.
Furthermore, the conventional voltage doubler circuit that relies on charge propagation also effectively depends on the linearity of the capacitor, so doubling the charge on the capacitor inevitably doubles the voltage. Based on the capacitor's physical structure, the non-linearity of the capacitors used in these conventional voltage doublers will generally limit the linearity of the voltage doubler.
[0125]
In the case of the circuit of FIG. 9, on the other hand, the requirement for a highly linearly matched capacitor with high accuracy is eliminated. If two capacitors are charged in parallel and then connected in series, the input voltage can be reduced regardless of the capacitor's integrity and linearity if the effects of parasitic capacitance are eliminated to a satisfactory level. You can always double exactly.
[0126]
In the case of the circuit of FIG. 9, the switch drive means 4 and 5 of each voltage storage circuit ensure that the charge inflow of the switch element 1 is kept constant, so that the voltage storage circuit has all its parasitic capacitances amplified. If designed to be driven by the output of the element, the only constraint on linearity of operation is essentially the gain error of the amplifier element. This is due to the fact that the parasitic capacitance cannot be removed sufficiently effectively when the gain of the amplifier element of the voltage storage circuit is not exactly a unit value. Gain errors from this exact unity should therefore be minimized.
[0127]
In practice, this gain error can be set as small as required (depending on the desired accuracy of a particular voltage doubler application) (for optimal accuracy, a relatively complex amplifier element). Configuration is required). By using an appropriate amplifier element configuration, this achieves a linearity that is at least better than 1 ppm, and the actual characteristic constraints depend on the amplifier and random noise due to thermal (kT / C) noise Is meant to do. In the case of an analog to digital converter using the voltage doubler circuit, linearity is likely to be maintained beyond 20 bits.
[0128]
Eventually, the voltage storage circuit VSC₁And VSC₂9 is used in the voltage doubler circuit 50 of FIG. 9 so that each amount of charge flowing in by the switch element 1 of the circuit is effectively removed at the moment of switching, The circuit will self-compensate.
One example of using a voltage doubler circuit 50 as illustrated in FIG. 9 will now be described with reference to FIG.
[0129]
FIG. 10 shows a portion of an analog to digital converter (ADC) that uses the voltage doubler circuit shown in FIG. The ADC of FIG. 10 is a “3-state logic” ADC.
The three-state logic ADC performs a series of voltage conversion operations, starting with an applied analog input voltage, each associated with a voltage doubler operation, and performs its analog-to-digital conversion. Digital data is each generated in the voltage conversion operation, and the digital data of the next conversion operation is combined to generate a digital output word indicating the applied analog input voltage.
[0130]
For each voltage conversion operation performed by a three-state logic ADC, the analog input voltage is set to a preset comparison potential V V in the first phase of the operation._r/ 4 (V_rIs a preset reference potential) to generate one of the three digital data values shown in Table 1 below.
[0131]
[Table 1]

[0132]
Next, in the second phase of operation, based on the digital data generated in the first phase, the input voltage V_iAccording to the equation illustrated in Table 2 below._iAnalog conversion voltage V related to_CIs converted to produce
[0133]
[Table 2]

[0134]
In the next conversion operation, this analog conversion voltage V_CIs used as an analog input voltage and converted voltage V_CWill converge to zero in the next operation. Each subsequent conversion operation generates one “bit” of 3-state logic digital data (+1, 0, −1). The output word, expressed in normal binary (two-state) logic, is derived from all three-state bits in combination by appropriate digital logic, and the R.three-state bits are binary consisting of (R + 1) bits. A logic output word can be generated.
[0135]
For a detailed explanation of the operation of a traditional 3-state logic ADC, see “Fujitsu Fact: 3-state logic controls the CMOS cycle A / D converter used in the MB87020” by K. Gotoh and O. Kobayashi. And the aforementioned EP-B-0214831, both of which are referenced here.
The ADC of FIG. 10 includes N voltage conversion stages ST connected in series.₁, ST₂... ST_N, Each of which can perform the voltage conversion operation described above from Tables 1 and 2. The first two voltage conversion stages ST of the ADC₁And ST₂Only shown in FIG.
[0136]
Stage ST_iAre generally based on the voltage doubler circuit 50 'as already described with reference to FIG. 9, and the input node I of the voltage doubler circuit 50'.₁And I₂Gives the input node of the stage and the input node O of the voltage doubler circuit 50 '.₁And O₂Gives the output node of the stage as well.
Each stage ST_iHowever, instead of one switch element 55 of the circuit of FIG. 9, the voltage doubler circuit 50 'is replaced by two voltage storage circuits VSC of the circuit.₁And VSC₂Each common terminal COM₁And COM₂9 is different from the voltage doubler circuit of FIG. 9 in that two controllable switch elements 55 and 56 and voltage adjusting means 58 are connected in series.
[0137]
Each stage ST_iIn this case, the switch elements 51 to 56 have the above-described input configuration (the switch elements 51 to 54 are on when the switch elements 55 and 56 are off) or the output configuration (the switch elements 51 to 54 are off when the switch elements 51 to 54 are off). 55 and 56 can be turned on).
As in the case of the voltage doubler circuit 50 in FIG._iSwitch elements 51 to 56 are connected to a control signal φ₁And φ₂Controlled by However, in the case of the ADC of FIG. 10, the control means 60 'common to all the stages is provided for generating the first and second control signals of each stage, and φ₁Is active, the odd-numbered stages ST of the switch elements 51 to 56₁, ST_Three, ST_FiveAre held in the input configuration, but the even-numbered stages ST of the switch elements 51 to 56₂, ST_Four, ST₆... is held in the output configuration, and φ₂The reverse occurs when is active.
[0138]
Each voltage conversion stage ST_iIs the input voltage V applied to the stage_iFirst and second input nodes I of the stage to receive₁And I₂And the aforementioned comparison potential V_rThe comparison means 70 connected to receive / 4 is mounted. Comparison means 70 provides three-state logic digital data a (+1, 0, -1) at its output and operates according to Table 2 above as the digital output of the stage. Each stage of digital data is applied to data processing means 80 for processing to generate a digital output word. The digital data a is also applied to voltage adjusting means 58 that controls the operation.
[0139]
The voltage adjusting means is configured such that when the switch elements 55 and 56 are on, each common terminal COM of the voltage storage circuit of the stage₁And COM₂Between one of three different possible voltages, the selected offset voltage V depending on the digital data generated by the comparison means_OSActuate to add. a = + 1 case (V_r/ 4 ≦ V_iThe selected offset voltage is V_OS= -V_rbecome. a = 0 (−V_r/ 4 ≦ V_i<V_r/ 4), the selected offset voltage is V_OS= 0. a = −1 (V_i<-V_r/ 4), the selected offset voltage is V_OS= + V_rbecome.
[0140]
In the operation of the ADC shown in FIG. 10, the analog input voltage V to be digitized_i1Is the first voltage comparison stage ST_iFirst and second input nodes I of₁And I₂Added during. First, the control means 60 '₁The first voltage conversion stage ST_iIs held in the input configuration (the switch elements 51 to 54 are on). In this configuration, switch elements 55 and 56 are both held off so that voltage regulator 58 is isolated from the rest of the circuit.
[0141]
φ₁During the first stage ST_iThe comparing means 70 of the input voltage V_iAnd comparison potential V_r/ 4 is compared, and 3-state logic digital data is generated based on the result of the comparison.
φ₁Prior to the end of the period when is active, the switching signal CK is sent to the first stage ST by the control means 60 '._iAre applied to each of the switch driving means 4 and 5, and the stage ST_iVoltage storage circuit VSC₁And VSC₂Each switch element 1 of the first stage ST is switched off._iInput voltage V_i1Is stored in each of the storage capacitors 2 of each of these circuits.
[0142]
Next, the control means 60 '₁Turn off the operation of φ₂1st stage ST_iSwitch to output configuration. In this configuration, the stage switch elements 51 to 54 are in an off condition, and the stage switch elements 55 and 56 are in an on condition. The voltage adjusting means 58 is therefore a voltage storage circuit VSC.₁And VSC₂Are connected in series between the storage capacitors 2, so that the selected offset voltage V_OS(Based on digital data a -V_r, 0, + V_r) Is the voltage storage circuit VSC₁And VSC₂Each common terminal COM₁And COM₂Added during. Therefore, analog conversion voltage V_CThe voltage storage circuit VSC depends on the voltage adjusting means 58.₁And VSC₂Each common terminal COM₁And COM₂Selected offset voltage V applied during_OSThe input voltage V stored according to_i1(Ie, V_C1= 2V_i1+ V_OS) Stage ST_iFirst and second output nodes O of₁And O₂Generated during
[0143]
Therefore, according to Table 2 described above, the voltage conversion stage ST_iThe conversion voltage V generated by_C1Is V_i1And comparison potential V_r2V based on the result of the comparison between / 4_i1-V_r2V_i1Or 2V_i1+ V_rCan be.
As shown in FIG. 10, since the voltage conversion stage of the ADC is connected in series, the second voltage conversion stage ST₂ Is the input voltage V_i2As a first voltage conversion stage ST_iThe analog conversion voltage V generated by_C1Receive. As described above, the second stage ST₂Switch elements 51 to 56 of the first stage ST_iWhen the switch elements 51 to 56 are in the output configuration,₂Is controlled so that the second stage ST₂Is the first stage ST_iThe comparison voltage V generated by_C1The comparison operation can be started without delay. Second stage ST₂The switching signal CK of the switch driving means 4 to 5 is (φ₁The first conversion stage ST as in the case of the switch drive means 4, 5 while is active_iRather) φ₂Is generated while active, so the first stage ST_iAnalog conversion voltage V_C1Is the second stage ST₂Is remembered. φ₂After the end of the cycle when is active, φ₁Becomes active again, the second stage ST₂Switch to output configuration. Therefore, the analog conversion voltage V_C2The analog conversion voltage V of the previous (first) stage_C1Generate based on
[0144]
Analog conversion voltage V_C2Is the next stage ST_Three And in turn (φ₁The analog conversion voltage V_C3Is converted to The next voltage conversion operation is therefore the control signal φ₁And φ₂Each of the operations is performed with a “swap”. Control signal φ₁And φ₂Each has an active period t₁ And t₂Constitutes the first and second clock phases of the converter, the second phase starting after the end of the first clock phase of each next clock period of the converter.
[0145]
First stage ST_iIs the second stage ST₂Is switched to the output configuration (the analog conversion voltage V just given by the first stage V_C1The analog conversion voltage V_CSwitch back to the input configuration (to convert to 2), so the new analog input voltage is φ₁Can be received by the converter each time it is activated again. In this way, the ADC can generate a new conversion result (a digital output word based on N three-state bits) in every clock period.
[0146]
It is not an indispensable element for the comparison means 70 of a given stage to directly compare the applied input voltage of the stage and the comparison potential. The comparison seems to be made on the one hand between the comparator potential and, on the other hand, the input voltage stored in the voltage storage circuit, or the initial analog conversion voltage given by the stage before the comparison. (The analog conversion voltage is corrected there).
[0147]
Instead of the N stages used in FIG. 10, it would be possible to use just two voltage conversion stages, each of which alternately extracts the other outputs and operates repeatedly. This configuration would use one clock period (ie, two clock phases) to generate all two bits of the three-state logic digital data. Thus, to perform N-bit conversion, the configuration will take N / 2 clock periods, which is much slower than a converter using N stages. The required circuit size will however be smaller.
[0148]
In different aspects of the invention, it is also possible to create a three-state logic ADC having only one voltage conversion stage that operates repeatedly. However, in this case, as described below with reference to FIG. 11, the voltage conversion stage is the conversion stage ST of the ADC of FIG._iIt is necessary to have a voltage storage circuit having a configuration different from that of the voltage storage circuit in FIG.
[0149]
In FIG. 11, the voltage conversion stage 90 used in the three-state logic ADC is the first and second input nodes I of the voltage conversion stage 90.₁ And I₂First and second modified voltage storage circuits VSC respectively connected to₁'And VSC₂'.
Each modified voltage storage circuit includes the input switch element 1, the single gain amplifier element 3, and the bootstrap switch driving means 4 and 5 described above with reference to FIGS. However, each modified voltage storage circuit has a first modified voltage storage circuit VSC instead of one capacitor 2 in the voltage storage circuit of FIG.₁In the case of ′, C₁And C_ThreeThe two capacitors labeled with the second modified voltage storage circuit VSC₂In the case of ′, C₂And C_FourWith two capacitors. Condenser C₁To C_FourAre usually the same capacitance, but this is not essential for the correct operation of the voltage conversion stage 90.
[0150]
Each deformation voltage storage circuit further includes several switch elements 91 to 106, and a capacitor C₁To C_FourThere are four switch elements associated with each. That is, the switch elements 91, 92, 95 and 96 are capacitors C₁, Switch elements 101, 102, 105 and 106 are capacitors C₂, Switch elements 93, 94, 97 and 98 are capacitors C_Three, Switch elements 99, 100, 103 and 104 are capacitors C_FourRelated to.
[0151]
The switch elements 91 to 106 are connected to a control signal φ generated by the bootstrap switch driving means, as will be described in more detail below.₁And φ₂Depending on the state, it is turned on and off.
Each voltage storage circuit VSC₁'And VSC₂′ In relation to the input switch element 1 and the associated input node I of the voltage conversion stage 90.₁Or I₂Between the input isolation switch element 46 connected in series with the input switch element and between the output node of the modified voltage storage circuit (of the output terminal of the amplifier element 3) and the input side of the input switch element 1 There is a feedback switch element 48 provided. The input separation switch element 46 and the feedback switch element 48 correspond to the switch elements having the same names and reference numbers in the voltage adding circuit of FIG. 8 and perform the same functions. The feedback switch element 48 can be replaced with a resistor anyway.
[0152]
The voltage adjustment means 58 is substantially similar to the voltage adjustment means 58 of FIG. 10, and the first and second modified voltage storage circuits VSC.₁'And VSC₂Connected between '. Further, the comparator means 70 is similar to the comparator means of each voltage conversion stage STi of FIG. 10, and is connected between the output nodes of the modified voltage storage circuit.
The voltage adjusting means 58 has a plurality of additional switch elements 581 to 588. Six switch elements 582 to 584 and 586 to 588 are each paired with three-state data “bits” a generated by the comparator means._iIt is activated according to the logic level. In this case, a_i= −1, the switch elements 582 and 586 are activated, resulting in an offset voltage V generated between the output terminals of the voltage regulator 58._OSBecomes equal to a predetermined reference voltage + Vr. a_iWhen = 0, the switch elements 583 and 587 are activated and the offset voltage V_OSBecomes zero. a_i== + 1, the switch elements 584 and 588 are activated and the offset voltage V_OSIs equal to -Vr.
[0153]
Second and first input nodes I of stage 90₂And I₁The activation of the other two switch elements 581 and 585 connected to each of the voltage adjusting means 58 will be described below.
The control means 61 is substantially similar to the control means 60 'of FIG._1MAnd φ_2MAs well as each master control signal SAM_MAnd CON_MAlso generate. Master control signal φ_1M, Φ_2MAnd SAM_MIs applied to the bootstrap switch driving means 4 and 5 of each deformation voltage memory circuit. The bootstrap switch driving means of each deformed voltage storage circuit has a master control signal φ_1M, Φ_2MAnd SAM_MThe bootstrap control signal φ applied to the switch element of the deformed voltage storage circuit corresponding to₁, Φ₂And SAMPLE. The potential of the bootstrap control signal follows the output terminal potential of the amplifier element 3 of the modified voltage storage circuit. The control signal CONVERT used to activate the feedback switch element 48 associated with the modified voltage storage circuit is the master control signal CON_MMay be a bootstrap control signal derived from the master control signal CON since it is not fundamental as a signal applied to the feedback switch element 48 to be bootstrapped._MCan also be given directly.
[0154]
When the conversion operation by the voltage conversion stage 90 in FIG. 11 is started, the analog input voltage converted into an equivalent digital signal is the first and second input nodes I of the voltage conversion stage 90.₁And I₂Applied between In order to facilitate the sampling of the applied analog voltage, the control means 61 includes an input node I in each modified voltage storage circuit.₁And I₂Is activated via the switch elements 1 and 46 to the respective inputs of the amplifying element 3 of the deformed voltage storage circuit, the master control signal SAM for activating the bootstrap control signal SAMPLE._MIs generated. At this time, the CONVERT control signal is deactivated and the feedback switch element 48 is in the OFF state.
[0155]
The switch elements 581 and 585 of the voltage adjusting means 58 are also activated by the control signal SAMPLE, and the output terminal potential of the voltage adjusting means is the second and first input nodes I, respectively.₂And I₁Is equal to the potential. At this time, the other switch elements 582 to 584 and 586 to 588 are held in the OFF state.
Control signal φ during input voltage sampling₁Is active, the switch elements 91, 95, 101 and 105 are in the on state, and the first modified voltage storage circuit VSC₁Capacitor C in ′₁The upper plate is the first input node I₁And the lower plate is connected to the second input node I₂Connected to. Similarly, the second deformed voltage storage circuit VSC₂′ Indicates that the upper plate is connected to the second input node I₂And the lower plate is connected to the first input node I₁Connected to. Therefore, each capacitor C₁And C₂Stores the applied analog input voltage so as to sample the applied analog input voltage.
[0156]
Control signal φ₁Switch element 94, 98, 100 and 104 are in the on state while capacitor C is active._ThreeAnd C_FourAre alternately connected in parallel between the output terminals of the amplifier element 3. Since the amplifier element has a single gain, the sampled analog input voltage is φ₁Each capacitor C during_ThreeAnd C_FourIs also remembered.
[0157]
Next, the SAMPLE control signal is deactivated to finish sampling the input voltage, and the control signal φ₁Remains activated.
After the SAMPLE control signal is deactivated, the CONVERT control signal is activated for the remainder of the conversion operation. Since the input and output terminal potentials of the unity gain amplifier element 3 are always equal, the input side and output side terminals of the input switch element 1 are held at the same potential, and the element 1 is associated with the associated input node I.₁Or I₂Regardless of the accompanying change in the potential, the off state is stably maintained.
[0158]
Condenser C_ThreeAnd C_FourThe sampled input voltage held by the comparator means 70 is compared with a predetermined comparison potential V by the comparator means 70 in the same manner as in the ADC of FIG._rCompared with / 4. First bit a of 3-state logical digital data (+1, 0, -1)₁ Is generated based on the comparison result by the comparator means 70 (see Table 1).
[0159]
First data bit a₁Is obtained, each pair of switch elements 582 to 584 and 586 to 588 of the voltage adjusting means 58 is connected to the first data bit a.₁Activated according to In this way, the voltage adjusting means 58 is connected to the predetermined offset voltage V between the output terminals._OS(Digital data bit a₁-V corresponding to_r, 0, + V_r). Control signal φ₁Is still activated, switch elements 91, 95, 101, and 105 are all kept in the on state, and there is a first column connection between each input terminal of switch element 3. Become. This first row is the capacitor C₁, Voltage adjusting means 58 and capacitor C₂Configure. Thus, the voltage between each input terminal of the amplifier element 3 is the capacitor C₁And C₂To the sampled analog input voltage stored in the first data bit a₁Offset voltage V selected by_OSThe first conversion voltage V equal to twice the sum of_C1It is. Thus, the voltage conversion operation is performed according to Table 2.
[0160]
The input terminal potential of the amplifier element 3 is buffered by the amplifier element 3 and the first conversion voltage V_C1Is regenerated between each output terminal of the amplifier element 3.
The switch elements 94, 98, 100 and 104 all remain in the on state and the capacitor C_ThreeAnd C_FourAre connected in parallel to each other between the output terminals of the amplifier element 3, each of which is connected to a first conversion voltage V_C1Remember.
[0161]
First conversion voltage V_C1The reference potential V is_r/ 4 and the second data bit a₂Is generated according to the comparison result.
Next, the control means controls the control signal φ₁Is deactivated and the control signal φ₂Activate. At the same time, the second data bit a₂Is applied to the voltage adjusting means, and this data bit a₂Depending on the new offset voltage V_OSIs selected. Control signal φ₂Is activated, the switch elements 93, 97, 99 and 103 are turned on. As a result, capacitor C_ThreeAnd C_FourAre connected in series to the voltage regulating means 58, and between each input terminal of the amplifier element 3, a second column connection (C_Three -V_OS-C_Four) And the first column connection (C₁ -V_OS-C₂). Thus, the resulting new conversion voltage V generated between each output terminal of the amplifier element 3_C2Is the first conversion voltage V_C1Newly selected offset voltage V_OSIs equal to twice the value plus Control signal φ₂, The switch elements 92, 96, 102 and 106 are turned on, and this new conversion voltage V_C2Is a capacitor C connected in parallel between the output terminals of the amplifier element 3₁And C₂Is remembered.
[0162]
New conversion voltage V_C2Is the reference potential V by the comparator means 70._R/ 4 and the next data bit a_ThreeIs generated. Next, the control signal φ₂Is deactivated and the control signal φ₁Is activated, and data bit a_ThreeIs applied to the voltage adjusting means, and a new offset voltage V_OSIs selected. Control signal φ₁Is activated so that the first column connection (C₁ -V_OS-C₂) Is the second column connection (C_Three -V_OS-C_Four), Capacitor C_ThreeAnd C_FourIs the resulting new conversion voltage V_C3Remember.
[0163]
After that, the control signal φ₁And φ₂Are activated alternately and a new data bit a_iAnd a new conversion voltage is generated during each successive control signal phase.
As described with reference to FIG. 10, the data bit a_iAre applied to ADC data processing means 80 (not shown) and processed to produce a digital output word representing the originally applied analog voltage. It can be seen that the voltage conversion stage of FIG. 11 requires N clock phases to generate a digital output word based on N 3-state bits.
[0164]
In each amplifier element 3, since the input terminal potential is equal to the output terminal potential, the control signal φ₁Or φ₂Is activated, the first modified voltage storage circuit VSC₁'Switch elements 1, 48, 91, 92, 93 and 94, and a second modified voltage storage circuit VSC₂It is understood that each switch element of the corresponding switch element 1, 48, 103, 104, 105 and 106 'has no voltage across the two terminals.
[0165]
The switch elements 91 to 94 and 103 to 106 connected to the upper plate of the capacitor can be switched without overlap (ie, switched without delay after switch off. For example, before the switch element 92 is turned on. The switch element 92 is turned off.) This is because the four nodes to which these switch elements are connected (the input terminal of the amplifier element, the output terminal of the amplifier element, and the upper plate of each of the two capacitors) are before and after switching (ie, each control Signal phase is φ₁To φ₂This is because they have the same voltage. Since the switches 91 to 94 and 103 to 106 related to the upper plate are switched without overlapping, the generation of the control signal is simplified.
[0166]
Here, the switches 95 to 102 connected to the lower plate of the capacitor are predetermined after switching of the switch elements 91 to 94 and 103 to 106 connected to the upper plate of the capacitor in order to avoid the charge injection effect. It is important to be able to switch in a short time. This predetermined short time is minimized in view of the fact that the input terminal of each amplifier element 3 is effectively combined with the output terminal of the other amplifier element 3 during this time, resulting in positive feedback. The effect of this positive feedback is less important when the amplifier element has unity gain, but avoids voltage conversion stage 90 being in this state for longer than absolutely necessary to be in this state. Is desirable. Thereby, the switch elements 91 to 94 and 103 to 106 connected to the upper plate are set, and at the same time, the switch elements 95 to 102 connected to the lower plate are switched.
[0167]
First deformed voltage storage circuit VSC₁Is preferably formed in one or more wells of conductivity opposite to that of the material covering the substrate, the potential of that well or each well being the output of the amplifier element 3 of the first modified voltage storage circuit. Fixed with respect to terminal potential. The same is true for the VSC of the second modified voltage memory circuit.₂This also applies to the switch elements 1 and 103 to 106 '. This arrangement of switch elements makes it possible to bootstrap the parasitic capacitance of the modified voltage storage circuit in the same basic manner as already described in connection with the voltage storage circuit of FIGS. Become.
[0168]
In the voltage conversion stage of FIG. 12, the first voltage conversion operation samples the analog input voltage during the first clock phase, and this sampling ends immediately. This speeds up the conversion operation, but during sampling the capacitor C₁And C₂It is necessary to provide another switch element (elements 581 and 585 shown integrally with the voltage regulating means 58) for charging the lower plate of the lower plate to the input node potential. With the exception of these switch elements 581 and 585, at the first clock phase (a₁It is also possible to perform a comparison operation, and the first voltage conversion operation is performed at the next clock phase.
[0169]
The voltage conversion stage already described with reference to FIG. 10 or 11 can be applied to other analog-to-digital converters requiring double voltage and offset operation, with appropriate modifications.
In order to minimize power consumption in an ADC having a series of voltage conversion stages already described with reference to FIG. 10, it is advantageous to have a “scaled” continuous stage. This point will be described in more detail with reference to FIG.
[0170]
FIG. 12 schematically depicts the first three stages of the ADC illustrated in FIG. The first stage storage capacitors 2 each have a capacitance C, the transistors of the amplifier element 3 each have a channel width W, and the current flowing through each of these transistors of the amplifier element 3 is I.
In the second stage, each of the storage capacitors 2 has a capacitance of KC, where 1 / k is a preset scaling factor (k <1), and the transistors of the amplifier element 3 each have a width. kW, and the current flowing through each transistor is kI. Similarly, in the third stage, the capacitance is k²C, transistor channel width is k²W, transistor current is k²I.
[0171]
Thus, each next stage is scaled as long as at least these three parameters are related by a scaling factor 1 / k. As a result, the total current consumed in the device, expressed in terms of the current consumed in the first stage, is 1 + k + k²+ K^Three+ ...
Each stage has 1 / k noise power at its input, but for the ADC input terminal, this is reduced by the gain product of the previous stage. For example, the noise power of the second stage = 1 / k, the voltage gain of the previous stage (in this case, the voltage gain of the first stage) = 2, so the noise power is 1 / k with respect to the input noise power. .
[0172]
Therefore, the total noise power of the inputs of all stages is 1 + 1 / 4k + 1 / 16k²+ 1 / 64k^Three+. For example, when k = 1/2, the total noise = 1 + 1/2 + 1/4 + 1/8 +.
Similarly, if k = 1/2 is substituted into the above-described total current equation, the total current = 1 + 1/2 + 1/4 + 1/8 +.
[0173]
If the total power is constant, all sizes must be divided according to the result of the power addition, ie, the input noise is multiplied by the same factor and is expressed as:
[0174]
[Expression 1]

[0175]
Input noise is minimized when m = 1, ie, k = 1/2.
From the above analysis, it is clear that the optimal scaling factor for the minimum total power consumption of the ADC is 2. This provides a minimum noise level to a given power consumption or a minimum power consumption level to a given noise level. Thus, each stage is substantially half the size of the previous stage. In this case, the total power consumption is equal to twice the power consumption of the first stage, and the total noise power is equal to twice the noise power of the first stage.
[0176]
FIG. 13 shows how the total current and noise have a scaling factor 1 / k in the case of a 16-stage ADC. As shown in FIG. 13, the minimum noise for a given power consumption and the minimum power consumption for a given noise level each appear when the scaling factor 1 / k = 2.
The above analysis shows that the conversion stage scaling applies to all stages of the ADC, but in fact, if the stage scaling is a 16 stage sequence (17 bit ADC), this is the last stage Is 1/2 the size of the first stage¹⁶This means that it was 1/65536 times, so we cannot continue to the final stage.
[0177]
In a particular stage of the series, when the stage size is reasonably small, all the next stages are made the same size, i.e. this makes the noise a little bit but does not require a wide range of sizes It means that.
For example, if scaling stops after 6 stages, the minimum stage size (used for the 6th and all subsequent stages) will be 1/32 of the size of the first stage. In this case, the total power = 1 + 1/2 + 1/4 + 1/8 + 1/16 + 1/32 + 1/32 + 1/32 +...
[0178]
Once the minimum stage size is selected, the stage of that size is designed as a “unit” stage that can be paralleled (or “stretched” in the layout) to form the maximum stage. Can do. For example, when the unit stage has a size of 1/32 with respect to the first stage, the first stage = 32 parallel units, the second stage = 16 parallel units, and the third stage = 8 parallel units.
[0179]
One possible layout for an ADC chip using a 1/32 size unit stage is illustrated in FIG.
Table 3 is a table showing the optimal scaling factor 1 / k for a given minimum size stage, with the optimal scaling factor for the different minimum stages in the 15-stage ADC (16 bit) case. As is apparent from Table 3, the optimal scaling factor is very close to 2.
[0180]
[Table 3]

[0181]
Compared to the optimal noise power value of 4.0 when scaling is not stopped, the minimum stage size of 1/32 results in an overall power increase or noise increase of about 10% or 0.46 dB. A minimum stage size of 16 results in increasing power or noise by about 25% or 0.99 dB. These two minimum stage sizes appear to be a preferred measure.
[0182]
Scaling as described above can be effectively applied to any suitable type of analog to digital converter having a string of voltage conversion stages in another aspect of the invention. For example, it may be possible to apply scaling to the voltage conversion circuit described in the above-mentioned EP-B-0214831, in the case where a plurality of stages described in the document are connected in series.
[0183]
The current consumed by the ADC of FIG. 10 is directly proportional to the capacitance of the storage capacitor 2 and inversely proportional to the conversion rate. This means that the power is increased even for high resolution and high conversion rate. However, it is estimated that the 16-bit 10Ms / s converter consumes less than 0.5W. This suggests that when the conversion rate is lowered to 1 Ms / s, the power is reduced to 5 mW at 50 mW or 100 ks / s.
[0184]
For low resolution (eg, 12 bits), power and area decrease sharply because the capacitance is very small. A 12-bit 50 Ms / s converter is estimated to consume 200 mW, including the power consumption of the digital logic required to process the digital data provided by the different conversion stages.
This shows a well-balanced power / speed balance compared to conventional converters. One main reason is that each stage in the series can be half the size and power of the previous stage, giving a total converter power that is approximately twice that of the first stage. This provides a significant reduction in chip size, and the 16-bit Ms / s converter is 10mm with proper processing.²It is estimated that it occupies a smaller area.
[0185]
In addition to the voltage doubler circuit and the comparison means, the ADC digital logic circuit of the N-bit output word is (N-1)²D-type flip-flops and (N-1) full adders are installed, and all clocks are clocked at the conversion rate. For 16-bit resolution, this gives a base cell count of about 2000 and about 25% of the estimated analog power consumption at 16-bit resolution at 5V and 10 MHz (for 15-bit resolution, the analog power consumption is 4 will be reduced by a factor of 4).
[0186]
As described above, the gain of each amplifier element 3 of the voltage conversion stage of the ADC is completely a unit value. Otherwise, apart from directing the gain error to the propagation function, further gain error results because the parasitic capacitance is not completely bootstrapped. Non-linearity caused by these errors is caused by the reference voltage V used in each stage._rIt can be corrected by adjusting a little with the stage of the row. For example, to correct for a 0.1% gain error, V_rMay be reduced by 0.1% for each subsequent stage.
[0187]
Alternatively or additionally, the digital data processing means 80 that receives the digital data from each stage can arbitrarily correct the voltage conversion error of the analog circuit by functionally adjusting the digital data of the next stage. Can be implemented.
In order to generate an ADC capable of high speed operation, it is a basic condition that the operation of the switch element and the amplifier element of the stage is sufficiently high speed. The unity gain amplifier element 3 can be designed much faster than a normal operational amplifier, and the SPICE simulation has a stable time of 50 ns (corresponding to a conversion rate of 10 Ms / s) with appropriate processing. It was shown that it specifically corresponds to the precision of 16 bits. Using a depletion mode NMOS buffer and at the expense of some resolution, a 10 ns stabilization time is possible for 12-bit accuracy. This suggests that an ADC based on the design of FIG. 10 can be used for applications such as HDTV.
[0188]
Circuit noise is not a significant problem in the ADC of FIG. 10, because the noise due to the amplifier element is effectively reduced by the analog input voltage double before it reaches the amplifier element. Because. It is contemplated that amplifier elements can be designed so that they are associated with less noise than kT / C noise. This kT / C noise is caused by thermal noise that limits the accuracy of the voltage samples provided and stored in the arbitrarily switched capacitor circuit, and prevents the use of very small capacitors. For a 16-bit signal to noise ratio, it is estimated that a storage capacitor of at least 10 pF is required for the next stage and is reduced in half in each subsequent stage.
[0189]
For best performance, the ADC of FIG. 10 is advantageously produced by a p-well (n-substrate) CMOS process, preferably using a depletion mode device.
Obtaining a sufficiently large voltage swing is difficult even with a single 5V power supply (small voltage swing means that low noise levels are required for circuits forming different stages), and this The problem becomes more difficult with low supply voltages such as 3.3V.
[0190]
However, ADC devices are not fully applied to the supply voltage because they are connected in series. That is, only the source / drain diode is applied to the high voltage, but even this is not as large as the supply voltage. The maximum voltage (5V) is generated at the junction of the well substrate. From this point of view, ± 3V (or ± 3.3V) positive and negative power supplies are used with digital circuits (minimum geometry) operating in the range of 0V to + 3V and analog circuits using ± 3V It seems desirable. This positive and negative power supply approach also has the great advantage that it can be DC coupled because the input signal can swing to either side of 0V. Digital power consumption is also reduced as the effective digital logic supply voltage is reduced, and this is likely to provide a sufficient reduction in total power consumption.
[0191]
Smaller geometry can allow an increase in the maximum clock frequency even when this is not limited by analog power consumption. The main advantage of the split power supply is therefore the increased digital speed and the reduced power consumption, which would increase the maximum speed of operation of the ADC.
[0192]
【The invention's effect】
According to the present invention, since the current between the capacitor and the amplifier element generated due to the stray capacitance of the amplifier element is reduced, the voltage fluctuation caused by the electric charge accumulated in the capacitor is reduced, and the accuracy of the voltage storage circuit is improved. To do.
[Brief description of the drawings]
FIG. 1 shows a circuit diagram of a voltage storage circuit that specifically implements the present invention.
FIG. 2 shows an example design of an amplifier element mounted on the circuit of FIG.
FIG. 3 shows another example design of an amplifier element used in the circuit of FIG.
4 shows in more detail the input switch element mounted on the circuit of FIG.
FIG. 5 shows another design of the amplifier element with the case of switch drive means used in the circuit of FIG.
6A and 6B are diagrams showing one possible layout of the circuit of FIG. 1 on an integrated circuit substrate, where FIG. 6A is a plan view and FIG. 6B is a cross-sectional view.
7A and 7B are diagrams showing another example of a possible layout of the circuit of FIG. 1 on an integrated circuit substrate, where FIG. 7A is a plan view and FIG. 7B is a cross-sectional view.
FIG. 8 shows a circuit diagram of a voltage adder circuit using the voltage storage circuit shown in FIG.
FIG. 9 shows a circuit diagram of a voltage doubler circuit using the two voltage storage circuits shown in FIG.
FIG. 10 shows a circuit diagram of a part of an analog-to-digital converter comprising a plurality of conversion stages, each based on the voltage doubler circuit of FIG.
FIG. 11 is a partial circuit diagram of the analog-to-digital converter of the second aspect of the present invention described above having a single conversion stage.
12 is a schematic diagram of the components of the converter of FIG. 10 showing the advantages of scaling the stage from one value to the next in the converter of FIG. 10 according to a scaling factor.
FIG. 13 shows the relationship between the total power consumption of the converter and the scaling factor, and the total noise amount of the converter and the scaling factor in the case of the converter shown in FIG. 10 with 16 stages. It is a graph which shows a relationship.
14 is a schematic diagram illustrating one example of the layout of the converter of FIG. 10 with respect to a chip.
FIG. 15 shows a circuit diagram of a conventional voltage storage circuit.
16 shows in more detail an amplifier element mounted on the conventional circuit of FIG.
[Explanation of symbols]
1 ... Switch element
2. Memory capacitor
3 ... Amplifier element
4 ... Potential generation circuit (switch drive means)
5 ... Selector circuit (switch drive means)
31… Cascade source follower
32 ... Current source
33 ... Input transistor
34 Cascade transistor
35 ... Bias generator
44… Bootstrap capacitor

Claims (42)

A voltage storage circuit formed on one substrate,
  A first plate connected to an input terminal of the voltage storage circuit via an input switch element; and a second plate connected to a common terminal of the voltage storage circuit, and when the voltage storage circuit is in operation A storage capacitor for storing a voltage between the input terminal and the common terminal;
  An input connected to the first plate; and an amplifier element having an output connected to an output terminal of the voltage storage circuit and outputting an output signal based on a voltage stored in the storage capacitor;
  The amplifier element includes a FET input transistor having a gate electrode connected to the first plate;
  A current source connected to the source electrode of the FET input transistor;
  A cascade FET transistor connected in series to the drain electrode of the FET input transistor;
  A bias generator connected between a source electrode of the FET input transistor and a gate electrode of the cascade FET transistor and maintaining a potential difference between the electrodes substantially constant;
  The input switch element and the FET input transistor are disposed in a well having a conductivity type opposite to the conductivity type around the substrate, and the well is maintained at a potential that follows the potential of the first plate during circuit operation. Memory circuit. 2. The voltage storage circuit according to claim 1, further comprising switch drive means for changing a potential of a switching electrode of the input switch element to output a signal for switching between an on state and an off state.   Inserted between the input terminal and the input side of the input switch element, the potential of the input side of the input switch element is changed to the OFF state of the first plate of the storage capacitor after the input switch element is turned off. The voltage storage circuit according to claim 2, further comprising input potential holding means for holding the potential substantially fixed. A voltage memory circuit,
  A first plate connected to an input terminal of the voltage storage circuit via an input switch element; and a second plate connected to a common terminal of the voltage storage circuit, and when the voltage storage circuit is in operation A storage capacitor for storing a voltage between the input terminal and the common terminal;
  Switch driving means for changing a potential of the switching electrode of the input switch element and outputting a signal for switching between an on state and an off state;
  Inserted between the input terminal and the input side of the input switch element, the potential of the input side of the input switch element is changed to the OFF state of the first plate of the storage capacitor after the input switch element is turned off. Input potential holding means for holding substantially fixed with respect to the potential;
  An input connected to the first plate; and an amplifier element having an output connected to an output terminal of the voltage storage circuit and outputting an output signal based on a voltage stored in the storage capacitor;
  The amplifier element includes a FET input transistor having a gate electrode connected to the first plate;
  A current source connected to the source electrode of the FET input transistor;
  A cascade FET transistor connected in series to the drain electrode of the FET input transistor;
  A voltage storage circuit including a bias generator connected between a source electrode of the FET input transistor and a gate electrode of the cascade FET transistor and maintaining a potential difference between the electrodes substantially constant. The input switch element and the input element of the amplifier element are formed on one substrate, and the substrate is disposed in one or more wells having a conductivity type opposite to the surrounding conductivity type. The voltage storage circuit according to claim 4, further comprising means for causing the potential of the well to follow the potential of the first plate.   The voltage storage circuit according to claim 2, wherein the switching electrode potential is derived from the output signal. Said switch driving means, which is connected to the output terminal, based on the switching signal received, the ON potential is to hold the input switch element to the ON state, or off the input switch element off potential to hold the state, the work to add to the switching electrodes, wherein at the on and off potential is substantially fixed respectively relative to the potential of the output terminal is set in advance to each other values The voltage storage circuit according to claim 6, which differs only by. The first being connected to said output terminal to a potential which is fixed respectively relative to the potential of said output terminal comprising a second bias line, the potential of the second bias line potential of the on and off one and equally and the potential difference between the first and second bias lines is greater or equal than the value set before Ki予 Me,
It said switch drive means comprises a bootstrap capacitor, one plate of the bootstrap capacitor is pre SL be connected to the switching electrode to provide a switching electrode potential, and plates of both of said bootstrap capacitor And connecting means connected to the bias line,
The connecting means connects the one plate of the bootstrap capacitor to the second bias line when the switching electrode potential is changed from one of on and off potentials to another of these potentials, and From a charging configuration that operates to connect the other plate of the bootstrap capacitor to the second bias line, the one plate is separated from the second bias line, and the other plate is connected to the second bias line. 8. The floating configuration as described above, wherein the potential of the one plate can be changed from the potential of the second bias line to a potential different by the preset value. Voltage storage circuit. With the output terminals respectively fixed potential and the first that is connected to the output terminal to the second and the third bias line relative to the potential of the potential of the third bias lines the ON And the potential difference between the first and second bias lines is greater than or equal to the preset value,
Said switch drive means comprises a bootstrap capacitor, said one plate of said bootstrap capacitor is connected to the switching electrode to provide the switching electrode potential, and plates of both of said bootstrap capacitor And connecting means connected to the bias line,
The connecting means connects the one plate of the bootstrap capacitor to the third bias line when the switching electrode potential is changed from one of the on-state potential and the off-state potential to another of these potentials. Separating the one plate of the bootstrap capacitor from a third bias line from a charging configuration that operates to connect the other plate of the bootstrap capacitor to the first bias line; It is possible to switch to a floating configuration that operates to connect to the second bias line, whereby the potential of the one plate is changed from the potential of the third bias line to a different potential by the preset value. The voltage storage circuit according to claim 7, which is possible.   10. A voltage as claimed in any one of claims 7, 8 or 9, wherein the electrical input switch element is a MOSFET transistor and one of the on and off potentials is substantially the same as the potential of the output terminal. Memory circuit.   The one or more conductive shields are extended to the wells or portions of each well, and further comprise means for causing the potential of the shields or shields to follow the potential of the first plate. The voltage storage circuit according to 2, 3, or 5. The amplifier element comprises a first circuit portion and a second circuit portion that are substantially the same,
  The first circuit unit includes the FET input transistor and the cascade FET transistor,
  The voltage storage circuit according to claim 1, wherein the second circuit unit includes the current source. The amplifier element comprises a first circuit portion and a second circuit portion that are substantially the same,
  The first circuit unit includes the FET input transistor and the cascade FET transistor,
  The second circuit unit includes the current source,
  The first circuit portion is disposed in the well, the second circuit portion is formed in a further well having a conductivity type opposite to the conductivity type around the substrate, and the potential of the well is a power source of the circuit 13. The voltage storage circuit according to claim 1, wherein the voltage storage circuit is substantially fixed with respect to the potential of the line.   The input potential holding means is connected in series with the input switch element, and is operable to separate the input side of the element from the input terminal after the input switch element is changed to an off state. The voltage storage circuit according to claim 3, further comprising a switch element.   15. The voltage storage circuit according to claim 14, wherein the input potential holding means further includes an auxiliary capacitor connected between an input side of the input switch element and the second plate of the storage capacitor. The input potential holding means further includes a feedback switch element connected between the amplifier element and the input side of the input switch element, the feedback switch element being separated while the input side of the input switch element is separated. a voltage storage circuit according to claim 14 or 15 further comprises a hydraulic Sulf I over-back switch element to apply a potential derived from the potential of the first plate of the storage capacitor.   17. A voltage storage circuit according to any one of the preceding claims, wherein the amplifier element has a substantially unity gain. First, second and third input nodes to which first, second and third potentials are applied during operation;
A voltage storage circuit,
An output node connected to the output terminal of the voltage storage circuit;
Be connected to the voltage storage circuit and said input node, after the input switch element of the voltage storage circuit is changed to the off state, voltage addition circuit and a switching means that can be switched to the output consists input configuration There,
The voltage storage circuit is
A storage capacitor having a first plate connected to an input terminal of the voltage storage circuit via an input switch element; and a second plate connected to a common terminal of the voltage storage circuit;
An input connected to the first plate and an output connected to the output terminal of the voltage storage circuit, and during the differential of the voltage storage circuit, the potential of the output terminal is substantially equal to the potential of the one plate. And a single-gain amplifier element,
The amplifier element includes a FET input transistor having a gate electrode connected to the first plate;
A current source connected to the source electrode of the FET input transistor;
Cascade FET tiger Njisuta connected in series to the drain electrode of the FET input transistors,
A bias generator connected between a source electrode of the FET input transistor and a gate electrode of the cascade FET transistor and maintaining a potential difference between the electrodes substantially constant;
The input configuration of the switching means is configured such that the first and second input nodes are connected to respective input terminals and a common terminal of the voltage storage circuit, and the first and second potentials of the storage capacitor of the voltage storage circuit. The output configuration connects the common terminal of the voltage storage circuit to the third input node, and the third potential and the first and second at the output node. A voltage summing circuit that generates an output potential that is substantially equal to the sum of the stored differences between the two potentials. In operation, first and second input nodes to which a first pair of input voltages are applied, third and fourth input nodes to which a second pair of input voltages are applied, and a third pair of input voltages 5th and 6th input nodes to which
First and second voltage storage circuits;
First and second output nodes connected to respective output terminals of the first and second voltage storage circuits;
The input node is connected to the first voltage storage circuit and the first and second voltage storage circuits, and each input switch element of the first and second voltage storage circuits is changed to an off state, and then the input configuration is switched to the output configuration. it a voltage addition circuit and a switching means is Ru can,
The first and second voltage storage circuits are
A storage capacitor having a first plate connected to an input terminal of the voltage storage circuit via an input switch element; and a second plate connected to a common terminal of the voltage storage circuit;
An input connected to the first plate and an output connected to the output terminal of the voltage storage circuit, and during the differential of the voltage storage circuit, the potential of the output terminal is substantially equal to the potential of the one plate. And a single-gain amplifier element,
The amplifier element includes a FET input transistor having a gate electrode connected to the first plate;
A current source connected to the source electrode of the FET input transistor;
A cascade FET transistor connected in series to the drain electrode of the FET input transistor;
A bias generator connected between a source electrode of the FET input transistor and a gate electrode of the cascade FET transistor and maintaining a potential difference between the electrodes substantially constant;
The input configuration of the switching means includes connecting the first and second input nodes to each input terminal and a common terminal of the first voltage storage circuit and connecting the third and fourth input nodes to the second terminal. Connected to each input terminal and common terminal of the voltage storage circuit, the storage capacitor of the first voltage storage circuit can store the first potential difference between the two input voltages of the first pair. And allowing the storage capacitor of the second voltage storage circuit to store a second potential difference between the two input voltages of the second pair, and the output configuration includes first and second output configurations. A common terminal of each of the voltage storage circuits is connected to the fifth and sixth input nodes, respectively, to generate a pair of output voltages between the first and second output nodes, and a potential difference therebetween is the third pair. Two of Substantially equal to the voltage addition circuit to the sum of the difference between the first and the second potential difference is stored as the potential difference between the power voltage. First and second input nodes during which an input voltage that is doubled is applied during operation;
First and second voltage storage circuits;
First and second output nodes respectively connected to the output terminals of the first and second voltage storage circuits;
The input node is connected to the first voltage storage circuit and the first and second voltage storage circuits, and each input switch element of the first and second voltage storage circuits is changed to an off state, and then the input configuration is switched to the output configuration. it a voltage doubler circuit and a switching means is Ru can,
The first and second voltage storage circuits are
A storage capacitor having a first plate connected to an input terminal of the voltage storage circuit via an input switch element; and a second plate connected to a common terminal of the voltage storage circuit;
An input connected to the first plate and an output connected to the output terminal of the voltage storage circuit, and during the differential of the voltage storage circuit, the potential of the output terminal is substantially equal to the potential of the one plate. And a single-gain amplifier element,
The amplifier element includes a FET input transistor having a gate electrode connected to the first plate;
A current source connected to the source electrode of the FET input transistor;
A cascade FET transistor connected in series to the drain electrode of the FET input transistor;
A bias generator connected between a source electrode of the FET input transistor and a gate electrode of the cascade FET transistor and maintaining a potential difference between the electrodes substantially constant;
The input configuration of the switching means connects the first input node to both the input terminal of the first voltage storage circuit and the common terminal of the second voltage storage circuit and connects the second input node to the first input node. Connected to both the input terminal of the two voltage storage circuit and the common terminal of the first voltage storage circuit, each storage capacitor of the voltage storage circuit can be charged to the input voltage, respectively, and the output configuration Each of the common terminals of the first and second voltage storage circuits are connected to each other, and the storage capacitor is connected in series between the first and second output nodes, and between the output nodes, the storage capacitors are connected to each other. A voltage doubler circuit that generates an output voltage that is substantially twice the input voltage. A voltage doubler circuit according to claim 20;
Digital data connected to receive an operating voltage equal to or derived from the input voltage and connected to receive a comparison potential, and comparing the operation voltage with the comparison potential to indicate a comparison result; Comparator means for outputting;
Connected between the common terminals of the first and second voltage storage circuits, and after the switching means has been switched from the input configuration to the output configuration, between these terminals, Applying an offset voltage having a value selected from a plurality of preset values depending on the digital data, and an analog conversion different between the output nodes by an offset voltage selected from twice the input voltage A voltage conversion stage comprising voltage adjusting means for generating a voltage.   The voltage conversion stage according to claim 21, wherein the comparator means performs the comparison while the switching means of the voltage storage circuit is in the input configuration. The comparator means is connected to the first and second input nodes, and the input voltage becomes the operating voltage;
When the input voltage is smaller than the comparison potential × (−1), first digital data is given,
Providing second digital data when the input voltage is greater than or equal to the comparison potential;
Providing third digital data when the input voltage is smaller than the comparison potential and greater than or equal to the comparison potential × (−1);
Here, the offset voltage selected by the first digital data is + Vref,
The offset voltage selected by the second digital data is −Vref,
The offset voltage selected by the third digital data is zero;
The voltage conversion stage according to claim 21 or 22, wherein the comparison potential is substantially Vref / 4 . Each I Oh voltage conversion stage according to any one of claims 21 23, the analog voltage being digitized is applied between said first and second input nodes of the first stage of the column The first and second input nodes of each subsequent stage are connected in rows to the first and second output nodes of the immediately preceding stage, respectively,
Each switching means of consecutive said stage operated from the entering force configured to switch on the output configuration, the switching, at each stage, except the first stage, the switching means of the preceding stage Since it is in an output configuration, before the switching, the stage receives the analog conversion voltage generated by the immediately preceding stage as its input voltage and controls to generate the analog conversion voltage based on the analog conversion voltage after switching When,
Data processing connected to receive the digital data provided by the N stages and operative to derive an N + 1 bit digital output word representing the applied analog voltage therefrom Analog-to-digital converter with means. Alternately operating at the first and second clock phases, the control means retains the switching means of the odd stage of the column in the input configuration at the first clock phase, and the switching means of the even stage. But in the second clock phase, the switching means of the even stage is held in the input configuration, and the switching means of the odd stage is operated to be held in the output configuration. Item 25. The analog-digital converter according to item 24.   For at least one pair of adjacent stages in a column, each storage capacitor of the first and second voltage storage circuits of the second stage of the pair is more capacitive than an equivalent storage capacitor of the first stage of the pair 26. An analog-to-digital converter according to claim 24 or 25, wherein:   27. The analog to digital converter of claim 26, wherein the ratio of the capacitance of the storage capacitors of a pair or two stages of each pair is about 2: 1. For at least one pair of adjacent stages in the column, the input transistor of each amplifier element of the first and second voltage storage circuits of the second stage of the pair is more than the equivalent input transistor of the first stage of the pair. 28. An analog to digital converter according to any one of claims 25 or 27, wherein the width is narrow. 29. The analog to digital converter of claim 28, wherein the ratio of the width of the input transistors of the two stages of a pair or each pair is about 2: 1. For at least one pair of adjacent stages of the column, each current in the controllable current path of the input transistor of the amplifier element of the first and second voltage storage circuit of the second stage of the pair is the first of the pair 30. The analog to digital converter of any one of claims 24 to 29, wherein the analog to digital converter is less than an equivalent current of the stage.   31. The analog to digital converter of claim 30, wherein the current ratio of the two stages of a pair or each pair is about 2: 1.   In each of the second to nth stages of the converter, each storage capacitor of the first and second voltage storage circuits of the stage is respectively compared with the capacitance of the equivalent storage capacitor of the immediately preceding stage. 26. An analog to digital converter as claimed in claim 24 or 25, which is reduced by a first scaling factor which is constant from the second to the nth stage.   The analog-to-digital converter of claim 32, wherein the first scaling factor is approximately two.   In each of the second to nth stages, the input device of the amplifier element of each voltage storage circuit of the stage is from these second to the channel width of the input device of the equivalent amplifier element of the previous stage. 34. An analog to digital converter according to any one of claims 24, 25, 32 or 33, wherein the channel width is reduced by a second scaling factor which is constant over the nth stage.   35. The analog to digital converter of claim 34, wherein the second scaling factor is approximately two.   In each of the second to nth stages of the converter, where 2 ≦ n ≦ N, the current in each of the controllable current paths of the input device of the stage amplifier element is the current of the previous stage. 33. Controlled to be reduced by a third scaling factor that is constant over these second to nth stages for equivalent controllable current path currents. 36. The analog-digital converter according to any one of 33, 34, or 35.   38. The analog to digital converter of claim 36, wherein the third scaling factor is approximately two.   For at least one pair of adjacent stages of the column, at least one of the preset values of the offset voltage in the second stage of the pair is set to a corresponding preset of the offset voltage of the first stage of the pair. 38. The analog-to-digital converter according to any one of claims 24 to 37, wherein the analog-to-digital converter is partially adjusted in comparison with the measured value.   The data processing means adjusts in part the digital data provided by each comparator means in the subsequent stages of the series to facilitate correction of voltage conversion errors in these subsequent stages. 39. An analog-to-digital converter according to any of claims 24 to 38, which operates in the following manner. 24. Each of the voltage conversion stages according to claim 21, wherein the first and second output nodes of the first stage are connected to the first and second input nodes of the second stage, respectively. The first and second output nodes of the second stage are connected to each other so as to be connected to respective first and second input nodes of the first stage and are digitized. First and second stages applied between the first and second input nodes of the first stage at the beginning of the iterative conversion operation of the converter;
The switching means of the first and second stages start from the first stage and operate so as to be switched alternately from the input configuration to the output configuration, and the switching is switched to the output configuration by the switching means of the other stages. Since it is controlled to be performed at a certain stage at a certain time, a certain stage switched before this switching receives an analog conversion voltage generated by another stage as its input voltage and the analog conversion voltage Control means based on this to generate after this switching;
A digital output word connected to receive the digital data applied alternately by the first and second stages in the course of the iterative conversion operation and indicating an analog voltage applied therefrom; An analog-to-digital converter with data processing means operating to guide. An analog-to-digital converter operating alternately with first and second clock phases,
First and second input nodes to which an analog input voltage that is digitized during operation of the converter is applied;
First and second voltage storage circuits each including first and second storage capacitors and unity gain amplifier elements having input and output terminals;
Input sampling operative to connect an input terminal of the first voltage storage circuit to a first input node and connect an input terminal of the second voltage storage circuit to a second input node during a first phase of a clock. Means,
First and second output nodes respectively connected to the amplifier element output terminals of the first and second voltage storage circuits;
A digital signal connected to the first and second output nodes and connected to receive a comparison potential, and compares the potential difference between the first and second output nodes with the comparison potential at each clock phase, and shows the comparison result. A comparator means for providing data;
An offset voltage having a value selected from a plurality of predetermined values according to the digital data provided by the comparator means at the immediately preceding clock phase, each having a set of connection terminals; Voltage adjusting means operating to apply between these terminals;
In the first phase of the clock, two first storage capacitors and connection terminals are connected in series between the input terminals of the amplifier element, and the second storage capacitors are parallel to each other between the first and second output nodes. In the second phase of the clock, two second storage capacitors and a connection terminal are connected in series between each input terminal of the amplifier element, and the first storage capacitor is connected to the first and second storage capacitors. Switching means operating to connect the two output nodes in parallel with each other;
Data processing means connected to receive the digital data provided by said comparator means over a plurality of phases of the clock and operative to derive a digital output word representing an analog input voltage applied therefrom equipped with a door,
The first and second voltage storage circuits are
A storage capacitor having a first plate connected to an input terminal of the voltage storage circuit via an input switch element; and a second plate connected to a common terminal of the voltage storage circuit;
An input connected to the first plate and an output connected to the output terminal of the voltage storage circuit, and during the differential of the voltage storage circuit, the potential of the output terminal is substantially equal to the potential of the one plate. And a single-gain amplifier element,
The amplifier element includes a FET input transistor having a gate electrode connected to the first plate;
A current source connected to the source electrode of the FET input transistor;
A cascade FET transistor connected in series to the drain electrode of the FET input transistor;
An analog-to-digital converter comprising a bias generator connected between the source electrode of the FET input transistor and the gate electrode of the cascade FET transistor and maintaining the potential difference between the electrodes substantially constant . The output of one stage comprises a plurality of mutually similar voltage conversion stages connected in series so that it becomes the input of the next stage, each stage having a stage input voltage for storing the stage input voltage. A storage capacitor connected to the input or selectively connected and an amplifier element selectively connected between the storage capacitor and the output of the stage to provide a stage output voltage dependent on the stored input voltage In at least one stage except the first stage of the row, the storage capacitor capacitance is less than the storage capacitor capacitance of the previous stage, or the width of the input transistor of the amplifier element is It is characterized by being smaller than the width of the input transistor of the stage amplifier element or both. Analog-to-digital converter.

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