JPH08223016A - Driver circuit - Google Patents

Abstract

PURPOSE: To provide a driver circuit which can extremely reduce its power consumption for driving the capacity load and also can control the through rate without using a through current. CONSTITUTION: This driver circuit includes a power supply for target charging potential Vcc and also a power supply for potential 1/2 Vcc lower than the potential Vcc, and the supply lines of these power voltage and an output node n12, i.e., the PMOS transistors TR P11 and P12 and the NMOS TR N11 and N12 which secure the active connection of load capacity CL in response to the input levels of control signals ϕ1 to ϕ4. In a charging mode, the connection and non-connection states are successively switched to the TR P12 from P11 which are connected to a power supply for lower potential (1/2) Vcc. In a discharging mode, the connection and non-connection states are successively switched to the TR N12 from N11 which are connected to a power supply for potential (1/2) Vcc higher than the ground level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit for charging / discharging load capacitance.

[0002]

2. Description of the Related Art FIG. 15 is a circuit diagram showing a configuration example of a driver circuit formed of a general CMOS inverter. The driver circuit 1 includes a p-channel MOS (hereinafter referred to as PMOS) transistor P1 and a n-channel MOS (hereinafter referred to as NMOS) transistor N1 whose drains and gates are connected to each other, and the source of the PMOS transistor P1 is a power supply voltage. It is connected to the supply line of V _CC , and the source of the NMOS transistor N1 is connected to the ground line. The connection node side between the gates of both transistors is the input node n1, and the connection point between the drains is the output node n2.

In such a structure, as shown in FIG.
As described above, the voltage V _CCAnd two of 0V
A rectangular wave signal that takes a level is input. For example, input
When the signal SIN is input at 0V (low level), PMO
The S transistor P1 becomes conductive, and the NMOS transistor
The transistor N1 is held in a non-conductive state. As a result, the output
Node n2 is power supply voltage V_CCFigure connected to the supply line
15 As indicated by the middle arrow,
Capacitive load C_LIs charged.

When the input signal SIN is switched from the 0V level to the V _CC level, the PMOS transistor P1 switches to the non-conductive state and the NMOS transistor N1 switches to the conductive state. As a result, the output node n2 is connected to the ground line, and the capacitive load C _L is discharged as indicated by the arrow in FIG.

FIG. 17 is a diagram showing a driver circuit realizing so-called slew rate control in order to reduce output noise (radiation). Specifically, in order to prevent unwanted output radiation, a PMOS
A resistance element R1 is connected between a connection point n3 between the gates of the transistor P1 and the NMOS transistor N1 and the input node n1.

In such a configuration, the resistance element R1
By arranging on the input side, as shown in FIG.
By increasing the rise / fall time of the input signal, the high frequency component of the output signal is reduced.

[0007]

In the driver circuit shown in FIG. 15 described above, for example, the frequency f
When the charging and discharging are repeated at, the power of {(1/2) C _L · V _CC ² · f} is consumed by the PMOS transistor P1 and the NMOS transistor N1, respectively, and the driver circuit 1 as a whole has {C _L · V _CC ² · _f f} power is consumed.

This power consumption will be examined in more detail by taking the case where the output node n2 is charged from 0V to V _CC as an example. Here, in order to simplify the explanation, assuming that the current flowing through the PMOS transistor P1 is a constant current I ₀ , the potential of the output node n2 and the power consumption at the PMOS transistor P1 are (a) and (b) in FIG. As shown in.

In this case, the constant current I ₀ is {(V _CC · C _L ).
/ T ₀ }. Then, the PMOS transistor P
The power consumption at 1 is given by the product of the source-drain voltage V _SD of the PMOS transistor P1 and the constant current I ₀ ,
The total power consumption is {(1 / 2t ₀ ) _CL · V _CC ² }. FIG.
(B) The shaded area is the cumulative power consumption consumed by the PMOS transistor P1 when the output node n2 is charged from 0V to V _CC . As can be seen from FIG. 19B, in the circuit of FIG.
Since the source-drain voltage V _{SD of 1} is as large as V _CC ,
Charge from 0 V to (1/2) V _CC , and
Consume 4.

Therefore, for example, 64 with a large number of pins is used.
For bit MPU, etc., 1/3 of the power consumption of the entire chip
Half of the power is consumed by the driver circuit that constitutes the output buffer, but in the future, the wiring capacity will increase due to the proximity of adjacent wiring due to the miniaturization of the LSI design rule, and the output will increase as the LSI becomes larger and the number of pins increases. An increase in power consumption due to charge / discharge of the bus and output pin capacitance, such as an increase in pin capacitance, becomes a major issue.

In the driver circuit shown in FIG. 17, the output noise can be reduced, but the through current in the driver circuit forming the output buffer increases, resulting in an increase in power consumption.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a driver circuit capable of significantly reducing power consumption when driving a capacitive load and realizing slew rate control without through current. To provide.

[0013]

To achieve the above object, a driver circuit according to the present invention is a driver circuit for charging a capacitor, and includes at least a charging target potential power source and a potential power source lower than the charging target potential. Switch means having one and operably connecting the power supply for charging target potential and the power supply for low potential and the capacity to be charged, respectively.
A switch means connected to a lower power source, and means for sequentially switching between connected and disconnected states for charging.

Further, the driver circuit of the present invention is a driver circuit for discharging a capacitor, and has at least one power supply for charging target potential and a power supply for potential lower than the charging target potential.
And a switch means for operatively connecting the power source for charging target potential and the power source for low potential and the capacity to be charged, respectively, and a switch means connected to a power source having a high potential for connection and disconnection. And a means for performing discharge by sequentially switching.

The driver circuit of the present invention is a driver circuit for charging / discharging a capacity, and has at least one power supply for charging target potential and a power supply for potential lower than the charging target potential, and for the charging target potential. Switching means for operably connecting the power source and the power source for low potential and the capacity to be charged, and switch means connected to the power source with low potential are connected and disconnected to sequentially perform charging. A switching means connected to a high power source for sequentially discharging and connecting the connected and disconnected states.

[0016]

According to the driver circuit of the present invention, when the capacitor is charged, the switch means connected to the power source for the potential lower than the charging target potential is switched to the connected state, and the charge based on the low power source potential and the capacitance is charged. Flows against the capacity. Then, the switch means connected to the low potential power source is switched to the non-connection state, and at the same time, the switch means connected to the charging target potential power source is switched to the connected state. As a result, the capacitance is charged to the target potential. That is, the connection or non-connection state is sequentially switched from the switch means connected to the power source having a low potential, and the charging is performed stepwise.

Further, according to the driver circuit of the present invention, when discharging the capacitance, the switch means connected to the power source for low potential closer to the charge target potential is switched to the connected state, and the low power source potential is reduced. Electric charge flows. Then, at the same time as the switch means connected to the low potential power source is switched to the non-connection state, the switch means connected to the lower potential power source is switched to the connected state, and the electric charge is applied to this low power source potential. Flowing.
That is, the connection and non-connection states are sequentially switched from the switch means connected to the power source having a high potential, and the discharge is performed stepwise.

[0018]

1 is a circuit diagram showing a first embodiment of a driver circuit according to the present invention. As shown in FIG. 1, the driver circuit 10 includes PMOS transistors P11, P12 and NMOS transistors N1 whose drains are connected to each other.
1, N12 and each transistor P11, P12, N
The timing generating circuit 11 generates timing for switching the conduction state and the non-conduction state of 11 and N12.

The source of the PMOS transistor P11 and the source of the NMOS transistor N11 are the power supply voltage V _CC.
Connected to the supply line of a power supply circuit (not shown) for supplying a voltage (1/2) V _CC
The source of 2 is connected to the supply line of the power supply voltage V _CC , and N
The source of the MOS transistor N11 is connected to the ground line. Then, the transistors P11, P12,
The gates of N11 and N12 are connected to the control signal output line of the timing generation circuit 11. Specifically, P
The gate of the MOS transistor P11 is on the output line of the control signal φ1, the gate of the PMOS transistor P12 is on the output line of the control signal φ2, and the NMOS transistor N1 is
The gate of 1 is connected to the output line of the control signal φ3, and the gate of the NMOS transistor N12 is connected to the output line of the control signal φ4.

As shown in FIG. 2, the timing generation circuit 11 is connected to the supply line of the power supply voltage (1/2) V _{CC having} a low potential at the time of charging when the input signal SIN is input at 0V (low level). In order to make the PMOS transistor P11 conductive for a predetermined time, the control signal φ1 is input signal SIN.
There switched to 0V level from off unusual point at V _CC level to 0V, when the predetermined time has elapsed, the conductive state PMOS transistor P12 connected to the supply line of the power supply voltage V _CC of high potential is charged target potential In order to
At the same time that the control signal φ1 is switched from the 0V level to the V _CC level, the control signal φ2 is switched from the V _CC level to the 0V level. At this time, the control signals φ3 and φ4 are 0V.
Hold at the level, NMOS transistors N11, N1
2 is kept in a non-conducting state. When the input signal SIN is input at the power supply voltage V _CC level (high level), the voltage (1/2) V _CC having a high potential (with respect to the ground level) is discharged.
NMOS transistor N11 connected to the supply line of
Switching from 0V to V _CC level at the time when the input signal SIN a control signal φ3 is switched to V _CC level to the conducting state for a predetermined time, which is connected to the ground line of the lower potential at the time when a predetermined time has elapsed NMOS transistor N1
In order to make 2 conductive, the control signal φ3 is switched from the V _CC level to the 0 V level, and at the same time, the control signal φ4 is switched from the 0 V level to the V _CC level. At this time, the control signal φ1 is kept at the V _CC level and the control signal φ1
2 is V when the input signal SIN switches to V _CC level
Switching to _CC level, PMOS transistor P11,
P12 is held in a non-conducting state.

FIG. 3 is a circuit diagram showing a configuration example of the power supply circuit 20 for supplying the voltage (1/2) V _CC . This power circuit 20
Is a capacitor C2 connected between the sources of the PMOS transistor P11 and the NMOS transistor N11 of the driver circuit 10 and the ground line, as shown in FIG.
1 and a resistance element R21 connected to the connection electrode side of the capacitor C21 with the source of the transistor.

The power supply circuit 20 has a capacitor C2 when discharging.
The electric charge accumulated in 1 is supplied to the output node n12 through the PMOS transistor P11, and the electric charge is accumulated in the capacitor C21 through the NMOS transistor N11 at the time of discharging to stably hold and supply the voltage (1/2) V _CC .

Next, the operation during charging and discharging according to the above configuration will be described. At the time of discharging, the input signal SIN is 0V (low level) and is input to the timing generation circuit 11 via the input node n11. In the timing generation circuit 11,
When the input signal level is switched to 0V, the control signals φ1 and φ4 are switched from the V _CC level to the 0V level, and the gate of the PMOS transistor P11 and the N
It is output to the gate of the MOS transistor N12. At this time, the control signal φ2 is held at the V _CC level and the control signal φ3 is held at 0V, so that the PMOS transistor P12
Are output to the gate of the gate and the gate of the NMOS transistor N11. As a result, the PMOS transistor P11 becomes conductive and the PMOS transistor P1
2. The NMOS transistors N11 and N12 are held in the non-conducting state. As a result, from the power supply circuit 20 to the output node n12, {(1/2)
A charge of V _CC · C _L } flows.

Then, the input signal SIN changes from V _CC level to 0.
At the same time when the control signal φ1 is switched from the 0V level to the V _CC level after a lapse of a predetermined time after switching to V,
Control signal φ2 is switched from the V _CC level to the 0 V level. At this time, the control signals φ3 and φ4 are held at 0V level. As a result, the PMOS transistor P1
1 switches from the conductive state to the non-conductive state, the PMOS transistor P12 switches from the non-conductive state to the conductive state, and the NMOS transistors N11 and N12 are held in the non-conductive state. As a result, from the supply line of the power supply voltage V _CC (power supply for the charging target potential) to the output node n12, as indicated by the arrow in FIG. 1, {(1/2) V _CC · C _L }.
Charge flows. As described above, the so-called load capacitance C _{L is} adiabatically charged by sequentially connecting the power source for charging target potential power source and the power source for the charging target potential in order from the power source side with a low potential to the output node n12.

During this charging, the PMOS transistor P11
And the current flowing through P12 is I ₁₁ and I ₁₂ , I ₁₁
= I ₁₂ = I ₀ , the potential of the output node n12 shows the characteristic of the conventional circuit shown in FIG.
Similarly, as shown in FIG. However, in the case of this embodiment, the PMOS transistors P11 and P1 are
Since the maximum value of the source-drain voltage V _SD of 2 is (1/2) V _CC for both transistors P11 and P12, the cumulative power consumption consumed by the PMOS transistors P11 and P12 is shown in FIG. b) As indicated by the diagonally shaded lines. Therefore, the total power consumption _{{(1 / 4t 0) C} L ·
V _CC ² }, which is ½ of the conventional value. That is, FIG.
As can be seen from (b), in the circuit of FIG.
/ 2) When charging to V _CC, the source-drain voltage V _{SD of the} PMOS transistor P11 is as small as (1/2) V _CC , so charging from 0 V to (1/2) V _CC ,
While 3/4 of the cumulative power consumption was consumed, this circuit only consumes 1/4 of the cumulative power consumption, and the power consumption is significantly reduced.

Next, after charging for a predetermined time, the input signal SIN is switched from the 0V level to the V _CC level,
Discharge is performed. When the input signal SIN is switched from the 0V level to the V _CC level, in the timing generation circuit 11, the control signal φ2 is switched from the 0V level to the V _CC level, and at the same time, the control signal φ3 is switched from the 0V level to the V _CC.
Switch to level. At this time, the control signal φ1 is V
_The control signal φ4 is held at the _CC level and the 0V level.
As a result, the PMOS transistor P12 switches from the conductive state to the non-conductive state, and the NMOS transistor N1
1 is switched from the non-conducting state to the conducting state, and the PMOS transistor P11 and the NMOS transistor N12 are held in the non-conducting state. As a result, the output node n12
From (load capacitance C _L ) to (1/2) V _CC power supply circuit 20, as indicated by the arrow in FIG. 1, {(1/2) V _CC · C _L }
Charge flows.

[0027] Then, the input signal SIN at the same time the control signal φ3 after a predetermined time has elapsed since switched from 0V to V _CC level is switched from V _CC level to 0V level,
Control signal φ4 is switched from 0V level to V _CC level. At this time, control signals φ1 and φ2 are held at the V _CC level. As a result, the NMOS transistor N1
1 switches from the conductive state to the non-conductive state, the NMOS transistor N12 switches from the non-conductive state to the conductive state, and the PMOS transistors P11 and P12 are held in the non-conductive state. As a result, from the output node n12 (load capacitance C _L ) to the ground (power supply for 0 V), as shown by the arrow in FIG. 1, a charge of {(1/2) V _CC · C _L } flows.
As described above, with respect to the output node n12, the power supply is connected in order from the power supply side with the higher potential to the power supply with the lower potential,
The so-called load capacitance C _{L is} discharged.

One cycle of the above charging and discharging [~
], The flow of charge during charging and the flow of charge during discharging are canceled out, resulting in V _CC
{(1/2) V _CC・
The charge of _CL } will flow. That is, the power consumption Pc is 1/2 of that in the conventional case, as shown in the following equation. Pc = {((1/2) V _CC・ C _L ) / (1 / f)] ・ V _CC = (1/2) C _L・ V _CC ²・ f (1)

This reduction in power consumption will be described from another point of view. Each power P consumed by the four transistors P11, P12, N11, N12 forming the driver circuit 10 is explained.
Since ct is equivalent to the operation of the inverter when the power supply is (1/2) V _CC , it is expressed by the following formula. _{Pct = (1/2) C L ·} (V CC / 2) 2 · f = (1/8) C L · V CC 2 · f ... (2) Therefore, four transistors P11, P12, N1
The total power consumed by 1 and N12 is {(1/2) C _L · V _CC ² · f}, which is ½ of the conventional power, similarly to the power shown in the equation (1).

As described above, according to the first embodiment, in addition to the power source for the charge target potential V _CC , the power source for the potential (1/2) V _CC lower than the charge target potential V _CC is provided. ,
A PMOS transistor P11 for operatively connecting the supply line of the power supply voltage and the output node n12, that is, the load capacitance C _L according to the input levels of the control signals φ1 to φ4.
P12 and NMOS transistors N11 and N12 are provided to connect the PMOS transistors P11 to P12 connected to the (1/2) V _CC power supply, which has a low electric potential during charging, to sequentially switch the non-connection state to perform charging, and during discharging. Is connected to the NMOS transistors N11 to N12 connected to the (1/2) V _CC power supply whose potential is higher than ground, and sequentially switches the non-connection state to perform discharge. The power consumption when charging / discharging the load capacity of the bus etc. can be reduced to half of the conventional one, and the power consumption of the LSI can be reduced, and the cost reduction of the LSI can be realized by an inexpensive plastic package. is there.

FIG. 5 shows a second driver circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG. The second embodiment differs from the first embodiment described above in that the PMOS transistor 1
1, P12, NMOS transistors N11 and N12, and the output node n12 between PMOS transistors P13 and P14 and NMOS transistors N13 and N1, respectively.
4 is connected in series. Further, the timing generation circuit 11a includes four inverters 11 connected in series.
1, 112, 113, 114.

In this circuit, the input node n11 is a PMOS
The gates of the transistors P11 and P12 and the NMOS transistors N11 and N12 are respectively connected, and the input signal SIN is supplied as the control signal φ11. The output of the inverter 113 is the PMOS transistors P13 and NM.
Respectively connected to the gate of the OS transistor N13,
Inverters 111 whose input signal SIN and the opposite phase signal are three,
The signals 112 and 113 are supplied as the control signal φ12 at a time delayed by a predetermined time. In addition, the inverter 114
Is connected to the gates of the PMOS transistor P14 and the NMOS transistor N14, and a signal in phase with the input signal SIN is supplied as the control signal φ13 at a time delayed from the control signal φ12 by the inverter 114 for a predetermined time.

Next, the operation at the time of charging and discharging according to the above configuration will be described with reference to the timing chart of FIG. At the time of discharging, the input signal SIN is input to the timing generation circuit 11a at 0V (low level) via the input node n11, and is supplied as the control signal φ11 to the gates of the PMOS transistors P11 and P12 and the NMOS transistors N11 and N12, respectively. To be done. As a result, the PMOS transistors P11 and P12 are rendered conductive, and the NMOS transistors N11 and N12 are rendered non-conductive. At this time, the timing generation circuit 11a outputs the control signal φ12 at the 0V level and the control signal φ13 at the V _CC level. Therefore, P
The MOS transistor P13 and the NMOS transistor N14 are held in the conductive state, and the PMOS transistor P14 and the NMOS transistor N13 are held in the non-conductive state. As a result, from the (1/2) V _CC power supply to the output node n12, as shown by the arrow in FIG.
Through the OS transistors P11 and P13, {(1/2) V _CC
・ C _L } flows.

After the input signal SIN is input to the timing generation circuit 11a at 0V level, the input signal SIN
Is delayed by a predetermined time due to the level inversion action of the three inverters 111, 112, 113, and the control signal φ12 becomes 0.
The V level is switched to the V _CC level. This gives P
The MOS transistor P13 switches from the conductive state to the non-conductive state, and the NMOS transistor N13 switches from the non-conductive state to the conductive state. Furthermore, the inverter 113
The signal output from the inverter 114 is delayed by the inverter 114 for a predetermined period of time so that the control signal φ13 becomes V _CC.
The level switches to 0V level. By this, PM
The OS transistor P14 switches from the non-conductive state to the conductive state, and the NMOS transistor N14 switches from the conductive state to the non-conductive state. As a result, from the supply line of the power source voltage V _CC (power source for charging target potential) to the output node n12.
On the other hand, as shown by the arrow in FIG. 5, electric charges of {(1/2) V _CC · C _L } flow through the PMOS transistors P12 and P14. As described above, also in the second embodiment, the power source for charging target potential and the power source are sequentially connected to the output node n12 from the power source side having a lower potential, and the power source is connected step by step to the so-called load capacitance C _L. Adiabatic charging is performed.

Next, after charging for a predetermined time, the input signal SIN is switched from 0V level to V _CC level,
Discharge is performed. That is, when the input signal SIN is switched from the 0V level to the V _CC level, the control signal φ11 is also switched from the 0V level to the V _CC level.
The OS transistors P11 and P12 switch from the conductive state to the non-conductive state, and the NMOS transistors N11 and N1
2 switches from the non-conducting state to the conducting state. At this time,
The control signal φ12 is output from the timing generation circuit 11a to V _CC.
The control signal .phi.13 is output at a 0V level. Therefore, the PMOS transistor P1
3 and the NMOS transistor N14 are held in the non-conducting state, and the PMOS transistor P14 and the NMOS transistor N14
The transistor N13 is kept conductive. As a result, from the output node n12 (load capacitance C _L ) to (1/2) V _CC
As shown by the arrow in FIG. 5, for the power supply for power supply, through the NMOS transistors N13 and N11, {(1/2) V _CC
A charge of C _L } flows.

After the input signal SIN is input to the timing generation circuit 11a at the V _CC level, the input signal SIN
Is delayed by a predetermined time due to the level inversion effect by the three inverters 111, 112, 113, and the control signal φ12 becomes V
_It switches from _CC level to 0V level. This gives P
The MOS transistor P13 switches from the non-conductive state to the conductive state, and the NMOS transistor N13 switches from the conductive state to the non-conductive state. Furthermore, the inverter 113
The signal output from is subjected to the level inversion action in the inverter 114 and delayed for a predetermined time, and the control signal φ13 becomes 0V.
The level switches to the V _CC level. By this, PM
The OS transistor P14 switches from the conductive state to the non-conductive state, and the NMOS transistor N14 switches from the non-conductive state to the conductive state. As a result, the output node n12
From (load capacity C _L ) to ground (0V power supply),
As indicated by the middle arrow, the NMOS transistor N14,
A charge of {(1/2) V _CC C _L } flows through N12. As described above, the so-called load capacitance C _{L is} discharged by sequentially connecting to the output node n12 a power source having a high potential and a power source having a low potential in order.

According to the second embodiment, as in the first embodiment described above, the flow of charges during charging and the flow of charges during discharging are canceled out in FIG. 5, resulting in to, with respect to ground from the power supply V _CC, in one cycle {(1
/ 2) The electric charge of V _CC · C _L } will flow, and the power consumption Pc will be {(1/2) C _L · V _CC ² · f}, which is 1/2 of the conventional value.

FIG. 6 shows a third driver circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG. The third embodiment differs from the second embodiment described above in that the PMOS transistor 1
This is because the drains of P1 and P12 and the drains of NMOS transistors N11 and N12 are connected to each other, and the PMOS transistor P13 and the NMOS transistor N13 are connected in series between these connection points and the output node n12. Further, the timing generation circuit 11b according to the third embodiment receives the input signal SIN and delays it with a time constant τ set according to the load capacitance C _L so that the slew rate is optimized.
An inverter 116 for inverting the level of the output signal of the adjusting circuit 115 and outputting it as a control signal φ15; and a buffer 117 for receiving the output signal of the adjusting circuit 115 and outputting it as a control signal φ16.

In this circuit, the input node n11 is a PMOS
Transistor P13 and NMOS transistor N13
, And the input signal SIN is supplied as the control signal φ14. The output of the inverter 116 is P
It is connected to the gates of the MOS transistor P11 and the NMOS transistor N11, and is supplied as the control signal φ15 at the time when a signal having a phase opposite to that of the input signal SIN is delayed by a predetermined time. The output of the buffer 117 is PMOS
Transistor P12 and NMOS transistor N12
Of the input signal SIN is supplied as the control signal φ16 at a time delayed by a predetermined time.

Next, the operation during charging and discharging according to the above configuration will be described. At the time of discharging, the input signal SIN is at 0V level, and the timing generation circuit 11 passes through the input node n11.
It is input to b and PMO is used as the control signal φ14.
S transistor P13 and NMOS transistor N1
It is supplied to each of the three gates. This allows the PMO
The S transistor P13 becomes conductive and the NMOS transistor N13 becomes non-conductive. At this time, the timing generation circuit 11b outputs the control signal φ15 at the 0V level and the control signal φ16 at the V _CC level. Therefore, the PMOS transistor P11 and the NMOS transistor N12 are held in the conductive state,
The PMOS transistor P12 and the NMOS transistor N11 are held in the non-conducting state. As a result, (1/2)
From the power source for V _CC to the output node n12 via the PMOS transistors P11 and P13, {(1/2) V _CC
A charge of C _L } flows.

Then, 0V is applied to the timing generation circuit 11b.
The signal SIN input at the level is delayed for a predetermined time by the adjustment circuit 115 in which the time constant τ is set, and the signal SIN is delayed by the inverter 116.
And is input to the buffer 117. As a result, the inverter 116 outputs the control signal φ15 having the V _CC level in the opposite phase to the input signal SIN, and the buffer 117 outputs the control signal φ16 having the 0 V level in phase with the input signal SIN. Accordingly, PMOS transistors P11 and N
The MOS transistor N12 switches from the conductive state to the non-conductive state, and the PMOS transistors P12 and NMO are turned on.
The S transistor N11 switches from the non-conducting state to the conducting state. As a result, from the supply line of the power supply voltage V _CC (power supply for charging target potential) to the output node n12, the PMO
Via S-transistors P12 and P13, {(1/2) V _CC
A charge of C _L } flows. As described above, also in the third embodiment, the power source for charging target potential and the power source are sequentially connected in order from the power source side having a lower potential to the output node n12, and the so-called load capacitance C _L is connected. Adiabatic charging is performed.

Next, after charging for a predetermined time, the input signal SIN is switched from 0V level to V _CC level,
Discharge is performed. That is, when the input signal SIN is switched from 0V level to V _CC level, the control signal φ14 is also switched from 0V level to V _CC level.
The OS transistor P13 switches from the conducting state to the non-conducting state, and the NMOS transistor N13 switches from the non-conducting state to the conducting state. At this time, the timing generation circuit 11b outputs the control signal φ15 at the V _CC level and the control signal φ16 at the 0 V level. Therefore, the PMOS transistor P12 and the NMO
The S-transistor N11 is kept conductive and the PMOS
Transistor P11 and NMOS transistor N12
Are held in a non-conducting state. As a result, the output node n1
From 2 (load capacitance C _L ) to (1/2) V _CC power supply, NM
Via the OS transistors N13 and N11, {(1/2) V _CC
・ C _L } flows.

Then, the timing generation circuit 11b outputs V _CC
The signal SIN input at the level is delayed for a predetermined time by the adjustment circuit 115 in which the time constant τ is set, and the signal SIN is delayed by the inverter 116.
And is input to the buffer 117. Thus, the control signal φ15 of the input signal SIN and the reverse phase of 0V level from the inverter 116 is output, the control signal φ16 of V _CC level of the input signal SIN and the phase from the buffer 117 is output. Accordingly, PMOS transistors P11 and N
The MOS transistor N12 switches from the non-conducting state to the conducting state, and the PMOS transistors P12 and NMO are turned on.
S-transistor N11 switches from the conductive state to the non-conductive state. At this time, the PMOS transistor P13 is held in the non-conductive state and the NMOS transistor N13 is held in the conductive state. As a result, the electric charge of {(1/2) V _CC · C _L } flows from the output node n12 (load capacitance C _L ) to the ground (power supply for 0 V) via the NMOS transistors N13 and N12. As described above, the so-called load capacitance C _{L is} discharged by sequentially connecting to the output node n12 a power source having a high potential and a power source having a low potential in order.

According to the third embodiment, similarly to the first embodiment described above, {(1/2) V _CC · C _L } is _supplied from the V _CC power source to the ground in one cycle. Since electric charges flow, the power consumption Pc is {(1/2) C _L · V _CC ² · f}, which is half that of the conventional one, and there is an advantage that the circuit configuration is simplified.

Further, in FIG. 8, the driver circuit 11b of FIG. 7 is provided in parallel with the input node n11, the signals of the opposite phase are input to each circuit, and the NMOS transistors N31 to N35 are output by the output of each driver circuit 11b. , An example of application as a drive circuit of a charge pump circuit 30 of a high voltage generation circuit such as a flash memory composed of capacitors C31 to C34. Since such a charge pump circuit 30 has a large capacitive load, it has a great effect of reducing power consumption.

FIG. 9 shows a fourth driver circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG. The fourth embodiment is different from the above-mentioned first embodiment in that a power source lower than the charging target potential V _CC is (2/3) V instead of the (1/2) V _CC power source.
_{Using CC} power supply, PMOS transistors P11 and N
The source of the MOS transistor N11 is connected to the supply line of the voltage (2/3) V _CC . Other configurations and operational effects are similar to those of the first embodiment. In this example,
When the V _CC power supply and the (2/3) V _CC power supply are used as the LSI power supply, the power consumption can be reduced without making (1/2) V _CC .

FIG. 10 is a circuit diagram showing a fifth embodiment of the driver circuit according to the present invention. The fifth embodiment differs from the fourth embodiment described above in that, in addition to the (2/3) V _CC power supply, a (1/3) V power supply is used as a power supply lower than the charging target potential V _{CC.
This is because the CC} power supply was used, that is, three power supplies were used.

In the fifth embodiment, the sources of the PMOS transistor P11 and the NMOS transistor N11 are connected to the supply line of the voltage (1/3) V _CC , and the PMO
S transistor P12 and NMOS transistor N1
2 source is connected to the supply line of voltage (2/3) V _CC ,
The sources of the PMOS transistor P13 and the NMOS transistor N13 are connected to the supply line of the voltage V _CC . Then, the PMOS transistors P11, P12,
P13 and NMOS transistors N11, N12, N
Control signals .phi.1c, .phi.2c, .phi.3c, .phi.4c, .phi.5 output from the timing generation circuit 11c are supplied to the respective gates of the line 13.
c and φ6c are supplied respectively.

Next, the operation at the time of charging and discharging according to the above configuration will be described with reference to the timing chart of FIG. Input signal SIN is 0V (low level) during discharge
At the timing generation circuit 11c via the input node n11
Is input to In the timing generation circuit 11c, at the time when the input signal level is switched to 0V, the control signal φ1c
And φ6c are switched from the V _CC level to the 0 V level, and the gate of the PMOS transistor P11 and NM
It is output to the gate of the OS transistor N13. At this time, control signals φ2c and φ3c are held at V _CC level, and control signals φ4c and φ5c are held at 0V, and are output to the gates of PMOS transistors P12 and P13 and NMOS transistors N11 and N12, respectively. As a result, the PMOS transistor P
11 becomes conductive, and the PMOS transistor P12,
P13, NMOS transistors N11, N12, N13
Are held in a non-conducting state. As a result, the electric charge of {(1/3) V _CC · _CL } flows from the (1/3) V _CC power supply to the output node n12 as shown by the arrow in FIG.

Then, the input signal SIN changes from the V _CC level to 0.
Control signal φ1c after a lapse of a predetermined time after switching to V
Is switched from the 0V level to the V _CC level, and at the same time, the control signal φ2c is switched from the V _CC level to the 0V level. At this time, control signal φ3c is held at the V _CC level and control signals φ4c, φ5c, and φ6c are held at the 0V level. As a result, the PMOS transistor P11 switches from the conductive state to the non-conductive state, and the PMOS transistor P12 switches from the non-conductive state to the conductive state.
The PMOS transistor P13 and the NMOS transistors N11, N12, N13 are held in the non-conducting state.
As a result, from the (1/3) V _CC power supply to the output node n12, as indicated by the arrow in FIG. 10, {(1/3) V _CC C
_The charge of _L } flows.

Then, after a lapse of a predetermined time after the control signal φ2c is switched from the V _CC level to 0 V, the control signal φ2
At the same time as c is switched from the 0V level to the V _CC level, the control signal φ3c is switched from the V _CC level to the 0V level. At this time, control signals φ4c, φ5c, φ6
c is held at 0V level. As a result, the PMOS transistor P12 switches from the conductive state to the non-conductive state, the PMOS transistor P13 switches from the non-conductive state to the conductive state, and the PMOS transistor P11 and the NMOS transistors N11, N12, N13 are held in the non-conductive state. . As a result, the output node n12 from the supply line of the power supply voltage V _CC (power for charging target potential), as shown in FIG. 10 arrow, {(1/3) V _CC ·
A charge of C _L } flows. As described above, the output node n
With respect to 12, the power source for charging target potential and the power source for the charging target potential are sequentially connected in sequence from the power source side having a lower potential, so that the so-called load capacitance C _{L is} adiabatically charged.

Next, after charging for a predetermined time, the input signal SIN is switched from the 0V level to the V _CC level,
Discharge is performed. When the input signal SIN is switched from the 0V level to the V _CC level, in the timing generation circuit 11c, the control signal φ3c is switched from the 0V level to the V _CC level, and at the same time, the control signal φ5c is switched from the 0V level to the V _CC level. . At this time, the control signal φ1
c and φ2c are held at the V _CC level, and control signals φ4c and φ6c are held at the 0 V level. This allows the PMO
The S transistor P13 switches from the conductive state to the non-conductive state, the NMOS transistor N12 switches from the non-conductive state to the conductive state, and the PMOS transistor P11,
P12 and the NMOS transistors N11 and N13 are held in the non-conducting state. As a result, the output node n12
From (load capacitance C _L ) to (2/3) V _CC power supply,
As indicated by the middle arrow, a charge of {(1/3) V _CC · C _L } flows.

Then, after a lapse of a predetermined time after the control signal φ5c is switched from 0V to the V _CC level, the control signal φ5c
At the same time as c is switched from the V _CC level to the 0 V level, the control signal φ4c is switched from the 0 V level to the V _CC level. At this time, control signals φ1c, φ2c, φ3
c is held at the V _CC level, and control signal φ6c is held at the 0 V level. As a result, the NMOS transistor N
12 switches from conducting state to non-conducting state, and
The transistor N11 switches from the non-conducting state to the conducting state, and the PMOS transistors P11, P12, P13 are held in the non-conducting state. As a result, the output node n12
From (load capacitance C _L ) to (1/3) V _CC power supply,
As indicated by the middle arrow, a charge of {(1/3) V _CC · C _L } flows.

Then, after a lapse of a predetermined time after the control signal φ4c is switched from 0V to the V _CC level, the control signal φ4c
At the same time that c is switched from the V _CC level to the 0 V level, the control signal φ6c is switched from the 0 V level to the V _CC level. At this time, control signals φ1c, φ2c, φ3
c is held at the V _CC level, and control signal φ5c is held at the 0 V level. As a result, the NMOS transistor N
11 switches from the conducting state to the non-conducting state, and
The transistor N13 switches from the non-conducting state to the conducting state, and the PMOS transistors P11, P12, P13,
And the NMOS transistor N12 is held in a non-conductive state. As a result, the output node n12 (load capacitance C _L )
A charge of {(1/3) V _CC · C _L } flows from the ground to the ground (power supply for 0 V) as shown by the arrow in FIG. As described above, the so-called load capacitance C _{L is} discharged by sequentially connecting to the output node n12 a power source having a high potential and a power source having a low potential in order.

The above charging and discharging are repeated for one cycle [~
], The flow of charges at the time of charging and the flow of charges at the time of discharging, and the flow of charges at the time of charging and the flow of charges at the time of discharging are canceled, and as a result, from the power supply for V _CC . The electric charge of {(1/3) V _CC · C _L } flows in one cycle with respect to the ground.
That is, the power consumption Pc is {(1/3) C _L · V _CC ² · f}
Becomes 1/3 of the conventional value.

In the above-mentioned first to fifth embodiments, the case of two power sources or three power sources has been described as an example, but the present invention is not limited to this, and n power sources (n + 1 when ground is added to this). Power consumption by using
/ N. 12 and 13 show a conceptual circuit configuration when this n power supply is used. FIG. 12 shows an example of the output of the control signal of the timing generation circuit 11d, and FIG. 13 shows an example of the conceptual configuration of the output buffer stage. Shown respectively.

The power supply for each voltage (V _CC / n) including the ground (0) to the power supply for the voltage V _CC are connected in parallel to the output node n12 via the resistance elements R0 to Rn and the switch circuits SW0 to SWn. To be done. Then, each switch circuit SW0
ON to OFF of SWn are controlled by control signals φ0 to φn generated in the timing generation circuit 11d. Note that FIG. 14 shows the waveforms of the main parts in FIGS. 12 and 13.

As described above, the switch circuits SW0 to SWn, which use the n power supply and are connected to the power supply having a low potential during charging, are used.
From the connected to the non-connected state in order to charge
Switch means SW connected to a power supply with high potential during discharge
It is possible to reduce the power consumption to 1 / n as compared with the conventional circuit by sequentially switching the connected state and the unconnected state from n-1 to SW0 to perform the discharge.

[0059]

As described above, according to the driver circuit of the present invention, it is possible to significantly reduce power consumption when driving a capacitive load and to realize slew rate control without through current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a driver circuit according to the present invention.

FIG. 2 is a timing chart showing waveforms of main parts of the circuit of FIG.

FIG. 3 is a circuit diagram showing a configuration example of a (1/2) V _CC power supply circuit according to the present invention.

FIG. 4 is a diagram for explaining a power consumption reduction effect during charging of the circuit of FIG.

FIG. 5 is a circuit diagram showing a second embodiment of the driver circuit according to the present invention.

6 is a timing chart showing waveforms of a main part of the circuit of FIG.

FIG. 7 is a circuit diagram showing a third embodiment of the driver circuit according to the present invention.

8 is a circuit diagram showing an example in which the driver circuit of FIG. 7 is applied to a charge pump circuit.

FIG. 9 is a circuit diagram showing a fourth embodiment of the driver circuit according to the present invention.

FIG. 10 is a circuit diagram showing a fifth embodiment of the driver circuit according to the present invention.

11 is a timing chart showing main waveforms of the circuit of FIG.

FIG. 12 is a diagram for explaining a conceptual circuit configuration when using n power supplies, and is a diagram showing an output example of a control signal of the timing generation circuit.

FIG. 13 is a diagram for explaining a conceptual circuit configuration when using n power supplies, and is a diagram illustrating a conceptual configuration example of an output buffer stage.

FIG. 14 is a timing chart showing waveforms of main parts in FIGS. 12 and 13.

FIG. 15 is a circuit diagram showing a configuration example of a conventional driver circuit.

16 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 17 is a circuit diagram showing a driver circuit realizing slew rate control.

FIG. 18 is a timing chart showing waveforms of a main part of the circuit of FIG.

FIG. 19 is a diagram for explaining power consumption during charging of the circuit in FIG.

[Explanation of symbols]

10, 10a, 10b, 10c, 10d ... Driver circuits P11 to P14 ... PMOS transistors N11 to N14 ... NMOS transistors 11, 11a, 11b, 11c, 11d ... Timing generation circuit 20 ... Power supply circuit C21 ... Capacitor R21 ... Resistor element 30 ... Charge pump circuit _CL … Load capacity

Claims (3)

[Claims] 1. A driver circuit for charging a capacitor, comprising at least one charge target potential power source and a potential power source lower than the charge target potential, and the charge target potential power source and the low potential power source. A driver circuit having switch means for operatively connecting a capacity to be charged and means for charging by sequentially switching connection / disconnection states from a switch means connected to a power source having a low potential. 2. A driver circuit for discharging a capacity, comprising at least one of a charging target potential power source and a potential power source lower than the charging target potential, and the charging target potential power source and the low potential power source. A driver circuit having switch means for operatively connecting a capacity to be charged and means for discharging by sequentially switching between connected and disconnected states from a switch means connected to a power source having a high potential. 3. A driver circuit for charging / discharging a capacity, comprising at least one charge target potential power source and a potential power source lower than the charge target potential, the charge target potential power source and the low potential power source. And a capacity to be charged are respectively connected to a switch means and a switch means connected to a power source having a low electric potential, which is sequentially connected and disconnected to perform charging, and connected to a power source having a high electric potential. A driver circuit having means for sequentially switching the connected and disconnected states from the switch means to perform discharge.