JP2011147247A - Bootstrap circuit and integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bootstrap circuit capable of preventing an excessive voltage from being applied between a gate electrode and a source/drain electrode of a field-effect transistor or between a back gate and a source/drain electrode. <P>SOLUTION: A bootstrap circuit 10 includes a bootstrap capacitive element C3, switching elements M11 and M9 which perform a switching operation in synchronism with a first clock signal CLK1, a switching element M9 which causes conduction or non-conduction between the other end of the bootstrap capacitive element C3 and a control terminal of a switch circuit, a field-effect transistor M3 that performs a switching operation according to a first switching control voltage, and a field-effect transistor M4 which is connected to a signal transmission path between the field-effect transistor M3 and the other end of the bootstrap capacitive element C3 to perform the switching operation according to a second switching control voltage. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a bootstrap circuit that generates a voltage higher than a power supply voltage by using capacitive coupling, and an integrated circuit including the bootstrap circuit.

  In recent years, with the miniaturization of elements and wirings constituting an integrated circuit and a reduction in power supply voltage, field effect transistors (FETs) such as MOSFETs (Metal-Oxide-Field-Effect Transistors) in analog integrated circuits have been developed. On-resistance tends to increase. The dependence of the on-resistance of the FET on the input voltage can cause distortion of the output voltage waveform. Also, variations in transistor characteristics such as the threshold voltage of the FET are likely to increase due to variations in manufacturing processes and temperature changes. In such a case, the integrated circuit may not operate normally and stably. Therefore, in order to realize a stable operation of the integrated circuit against a low power supply voltage and a temperature change, a bootstrap circuit that lowers the input voltage dependency of the ON resistance of the FET is required.

FIG. 1 is a schematic diagram showing a basic configuration of a bootstrap circuit 100 connected between a control terminal (gate electrode) and a source electrode of a switch circuit 101 made of an FET. The source electrode of the switch circuit 101 is connected to the input terminal 102, and the drain electrode of the switch circuit 101 is connected to the output terminal 103. The bootstrap circuit 100 is connected between the source electrode of the switch circuit 101 and the control terminal. The bootstrap circuit 100 includes a capacitive element C _B (bootstrap capacitive element) and switching elements SWa, SWb, SWc. In recent years, in analog integrated circuits, FETs such as MOSFETs are used as the switching elements SWa, SWb, and SWc.

The switching elements SWa, SWb, SWc operate in synchronization with the clock signal CLK. That is, when the voltage of the clock signal CLK is at high level, the switching element SWa is a power supply voltage VDD is applied to the one end 200a connected to one end 200a of the capacitor _{C B} to the terminal 201a, the switching element SWb, the capacitive element connect the other end 200b of the C _B to terminal 201b applies the ground potential to the other end 200b. At the same time, the switching element SWc connects the node 200c connected to the control terminal of the switch circuit 101 to the terminal 202c and applies a ground potential to the control terminal. At this time, both ends 200a of the capacitor _{C B,} a potential difference is given between 200b. On the other hand, when the voltage of the clock signal CLK is low, the switching element SWa is connected to one end 200a of the capacitor _{C B} to the terminal 202a, the switching element SWb, the switch circuit and the other end 200b of the capacitor _{C B} 101 The switching element SWc connects the node 200c to the terminal 201c. Thus, both ends 200a of the capacitor _{C B,} 200b are respectively connected to the control terminal and the input terminal 102 of the switch circuit 101.

The operation of the bootstrap circuit 100 is as follows. First, the high level of the clock signal CLK ends 200a of the capacitor _{C B} is supplied and the capacitor _{C B} by applying a potential difference between 200b are precharged (initial charging) to the switching element SWa～SWc. The charging voltage of the capacitor C _B at this time is Vp. By supplying the low-level clock signal CLK after the precharge is completed, both ends 200a of the capacitor _{C B,} 200b are respectively connected to the control terminal and the input terminal 102 of the switch circuit 101. When the input voltage V _IN is supplied to the input terminal 102 at this time, the voltage of the higher charge voltage Vp to the control terminal of the switch circuit 101 is applied through capacitive coupling by the capacitive element C _B. By repeating the above operation, the bootstrap circuit 100 raises the control potential of the switch circuit 101 to a potential higher than the power supply voltage VDD (= VDD + V _IN ), thereby making the input voltage dependence of the on-resistance of the switch circuit 101 higher. Can be lowered.

  The bootstrap circuit having the basic configuration as described above is disclosed in, for example, Japanese translations of PCT publication No. 2007-501383 (Patent Document 1). The bootstrap circuit disclosed in Patent Document 1 is applied to a track / hold circuit.

JP-T-2007-501383 (FIG. 4, paragraph 0017)

  In the bootstrap circuit, when the switching elements connected to both ends of the bootstrap capacitive element are composed of FETs, these FETs transition from one of an on state (conductive state) and an off state (non-conductive state) to the other. In this case, there is a problem that an operation failure occurs in the bootstrap circuit. One cause of this problem is the occurrence of clock feedthrough in the FET that transitions from the on state to the off state. Clock feedthrough is caused by a sudden change in the gate voltage of the FET due to electrostatic coupling of the FET parasitic capacitance (for example, the gate-source parasitic capacitance or the gate-drain parasitic capacitance). This is a phenomenon in which the potential of the source electrode changes following. When clock feedthrough occurs in the FET connected to both ends of the bootstrap capacitive element, the potential at both ends of the bootstrap capacitive element changes temporarily and rapidly. Due to this potential change, the voltage between the gate electrode and the source / drain electrode of another FET connected to both ends of the voltage or the voltage between the back gate and the source / drain electrode of the FET exceeds the withstand voltage level. Therefore, it is considered that a malfunction occurs in the other FET.

  In view of the above, one of the objects of the present invention is that an excessive voltage is applied between the gate electrode and the source / drain electrode of the FET connected to the bootstrap capacitor element or between the back gate and the source / drain electrode. To provide a bootstrap circuit that can be prevented from being applied and an integrated circuit having the bootstrap circuit.

  A bootstrap circuit according to the present invention is a bootstrap circuit that controls the operation of a switch circuit, and is one of a pair of controlled terminals of the switch circuit in synchronization with a bootstrap capacitive element and a first clock signal. A first switching element for conducting or non-conducting between the controlled terminal of the bootstrap capacitor and one end of the bootstrap capacitor, the other end of the bootstrap capacitor and the switch in synchronization with the first clock signal Electrical connection between a second switching element for conducting or non-conducting with a control terminal of the circuit, a first power supply terminal for supplying a first power supply voltage, and the other end of the bootstrap capacitive element A first field effect transistor that performs a switching operation in accordance with a first switching control voltage; and Is connected to the signal transmission path between the other end of the bootstrap capacitor element, characterized in that it comprises a second field effect transistor for switching operation in response to a second switching control voltage.

  Another bootstrap circuit according to the present invention is a bootstrap circuit that controls the operation of the switch circuit, and is one of a pair of controlled terminals of the switch circuit in synchronization with the bootstrap capacitive element and the first clock signal. A first switching element for conducting or non-conducting between one controlled terminal of the bootstrap capacitor element and one end of the bootstrap capacitor element, and the other end of the bootstrap capacitor element in synchronization with the first clock signal. Electrically connected between a second switching element for conducting or non-conducting with the control terminal of the switch circuit, a first power supply terminal for supplying a first power supply voltage, and the other end of the bootstrap capacitive element. And a first field effect transistor that performs switching operation in accordance with a first switching control voltage, and boosts the first power supply voltage before A booster circuit for generating a first switching control voltage; and a clock generator for generating a first clock signal and a second clock signal having a phase different from that of the first clock signal based on a reference clock signal And the booster circuit is interposed in a path between the first capacitive element for level shift having one end to which the second clock signal is applied, and the other end of the first capacitive element and the first power supply terminal. And the first switching control voltage is supplied from the other end of the first capacitive element, and the clock generator is configured to start the operation when the first capacitive element is activated. Generating a first clock signal and a second clock signal after charging the first capacitive element by applying a voltage that gives a potential difference to both ends of the first capacitive element to charge the first capacitive element. And features.

  An integrated circuit according to the present invention includes the bootstrap circuit.

  According to the present invention, an excessive increase in the gate-source voltage of a field effect transistor can be prevented.

It is the schematic which shows the basic composition of the conventional bootstrap circuit. 1 is a diagram showing a schematic configuration of a bootstrap type switch circuit according to a first embodiment of the present invention. 3 is a timing chart schematically showing various waveforms during the operation of the bootstrap circuit of the first embodiment. 6 is a timing chart schematically showing various waveforms during other operations of the bootstrap circuit of the first embodiment. It is a figure which shows schematic structure of the bootstrap type | mold switch circuit of a comparative example. It is a timing chart which shows roughly various waveforms at the time of operation of the bootstrap circuit of a comparative example. It is a timing chart which shows roughly the various waveforms at the time of other operations of the bootstrap circuit of a comparative example. FIG. 3 is a schematic diagram illustrating an example of an integrated circuit in which the bootstrap type switch circuit according to the first embodiment is incorporated. It is a figure which shows schematic structure of the bootstrap type | mold switch circuit of Embodiment 2 which concerns on this invention. FIG. 6 is a schematic diagram illustrating an example of an integrated circuit in which the bootstrap switch circuit according to the second embodiment is incorporated. It is a figure which shows schematic structure of the bootstrap type | mold switch circuit which is a modification of Embodiment 2 which concerns on this invention.

  Hereinafter, various embodiments according to the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 2 is a diagram showing a schematic configuration of the bootstrap type switch circuit 1 according to the first embodiment of the present invention. The bootstrap type switch circuit 1 includes a bootstrap circuit 10, a switch circuit 20, and a control unit 30. The bootstrap circuit 10 and the switch circuit 20 are incorporated in an integrated circuit.

The switch circuit 20 includes an n-channel type MOS field effect transistor M0, and an input voltage _VIN is supplied to the source electrode (one controlled terminal) of the n-channel type MOS field effect transistor M0, and the drain electrode (the other side). The output voltage V _OUT is output from the controlled terminal. The bootstrap circuit 10 is connected to the gate electrode (control terminal) and source electrode of the MOS field effect transistor M0. Hereinafter, for convenience of description, the MOS field effect transistor is simply referred to as a “MOS transistor”.

  The control unit 30 generates two types of control signals PD and PDB for controlling the operation of the bootstrap type switch circuit 1 and supplies them to the bootstrap circuit 10. The control signal PDB is an inverted signal obtained by inverting the phase of the control signal PD. The control signal PD is supplied to the gate electrode of the MOS transistor M13 constituting the bootstrap circuit 10, and the control signal PDB is supplied to the clock generation unit 17. The control unit 30 operates the bootstrap circuit 10 normally by setting the logic level of the control signal PD low, and stops the operation of the bootstrap circuit 10 by setting the logic level of the control signal PD high ( Power down).

  Bootstrap circuit 10 includes MOS transistors M 1 to M 14, capacitive elements C 1 to C 3, and a clock generation unit 17. The bootstrap circuit 10 includes a power supply voltage VDD supplied from a power supply terminal 5 (hereinafter referred to as “VDD terminal 5”) and a power supply voltage VSS supplied from a power supply terminal 6 (hereinafter referred to as “VSS terminal 6”). (VSS <VDD; VSS is a ground potential, for example). The n-channel MOS transistors M1 and M2 and the capacitive elements C1 and C2 constitute a booster circuit 13, and the p-channel MOS transistor M7 and the n-channel MOS transistor M8 constitute an inverter element 14. The source electrodes of the MOS transistors M1 and M2 constituting the booster circuit 13 are both connected to the VDD terminal 5 that supplies the power supply voltage VDD. The back gates of these MOS transistors M1 and M2 are both connected to the VDD terminal 5.

  The clock generation unit 17 is a logic circuit including NAND gates I1 and I2 and inverter elements I3 and I4. The clock generator 17 is supplied with reference clock signals CLK and CLKB having opposite phases from a clock generator (not shown), and is supplied with a control signal PDB from the controller 30. The NAND gate I1 performs a negative product operation on the control signal PDB and the reference clock signal CLK, and outputs the operation result to the inverter element I3. Inverter element I3 inverts the logic level of the signal that is the operation result of NAND gate I1 (switching from a high level to a low level, or switching from a low level to a high level) to generate clock signal CLK1. On the other hand, the NAND gate I2 performs a NAND operation on the control signal PDB and the reference clock signal CLKB, and outputs the calculation result to the inverter element I4. The inverter element I4 generates the clock signal CLKB1 by performing inversion (switching from a high level to a low level, or switching from a low level to a high level) of a signal that is a calculation result of the NAND gate I2. . Therefore, when the logic level of the control signal PD is high, that is, when the logic level of the control signal PDB is low, the logic levels of the clock signals CLK1 and CLKB1 are both low. When the logic level of the control signal PD is low, the logic circuits I1 to I4 output clock signals CLK1 and CLKB1 having opposite phases. The configuration of the logic circuit of the clock generator 17 is not limited to that shown in FIG.

The capacitive element C3 (hereinafter referred to as “bootstrap capacitive element C3”) is a capacitive element for setting a control voltage to be supplied to the gate electrode of the MOS transistor M0 to a voltage (= VDD + V _IN ) higher than the power supply voltage VDD. is there. The MOS transistor M3 is electrically connected between the high-voltage side one end (node n3) of the bootstrap capacitive element C3 and the VDD terminal 5, and operates using the output of the booster circuit 13 as a switching control voltage. The drain electrode and the back gate of the MOS transistor M3 are both connected to the VDD terminal 5. A source electrode and a drain electrode of an n-channel MOS transistor M4 (hereinafter referred to as a dummy transistor M4) are connected to the source electrode of the MOS transistor M3 and the node n3. The back gate of the dummy transistor M4 is connected to the VDD terminal 5 similarly to the MOS transistor M3. As shown in FIG. 2, since the drain electrode and the source electrode of the dummy transistor M4 are both connected to the node n3, the MOS transistor M3 and the node n3 are electrically short-circuited with each other.

  A switching control voltage having a phase opposite to that of the switching control voltage applied to the gate electrode of the MOS transistor M3 is applied to the gate electrode of the dummy transistor M4. This is to compensate for clock feedthrough occurring in the MOS transistor M3. When the MOS transistor M3 transitions from the on state to the off state, a negative charge is generated at the source electrode of the MOS transistor M3 due to electrostatic coupling between the gate electrode and the source electrode. When the dummy transistor M4 transitions from the off state to the on state, the negative charge generated at the source electrode of the MOS transistor M3 is caused by electrostatic coupling between the gate electrode and the drain electrode and between the gate electrode and the source electrode. Generates a positive charge of opposite polarity. For this reason, the electric charge generated at the source electrode of the MOS transistor M3 and the electric charge generated at the source electrode and the drain electrode of the dummy transistor M4 are canceled each other, so that the potential change at the node n3 due to clock feedthrough is suppressed. be able to.

  In the booster circuit 13, the clock signal CLKB1 is applied to one end (node n10) of the capacitive element C1, and the gate electrode of the MOS transistor M2 and the source electrode of the MOS transistor M1 are connected to the other end (node n1) of the capacitive element C1. Is connected. The clock signal CLK1 is applied to one end (node n11) of the capacitive element C2, and the gate electrode of the MOS transistor M1 and the source electrode of the MOS transistor M2 are connected to the other end (node n2) of the capacitive element C2. The MOS transistor M1 is electrically connected between the VDD terminal 5 and the node n1, and the MOS transistor M2 is electrically connected between the VDD terminal 5 and the node n2. Further, the node n1 supplies a switching control voltage to the gate electrode of the MOS transistor M3, and the node n2 supplies a switching control voltage to the gate electrode of the dummy transistor M4.

  A p-channel MOS transistor M9 is electrically connected between one end on the high voltage side (node n3) of the bootstrap capacitive element C3 and the gate electrode of the MOS transistor M0 of the switch circuit 20. The back gate of the MOS transistor M9 is connected to the node n3. Inverter element 14 generates an inverted signal obtained by inverting the signal level of clock signal CLK1, and applies this inverted signal to the gate electrode of MOS transistor M9 via node n5. Since the MOS transistor M9 performs a switching operation using the inverted signal as a switching control voltage, the MOS transistor M9 performs a switching operation in synchronization with the clock signal CLK1. In the inverter element 14, the back gate of the p-channel MOS transistor M 7 is connected to the VDD terminal 5. Although the back gate of the n-channel MOS transistor M8 is connected to the VSS terminal 6, the back gate of the MOS transistor M8 may be connected to the node n4 instead.

  N-channel MOS transistors M12 and M14 are connected to the node n6. The MOS transistor M12 is always on because the power supply voltage VDD is applied to its gate electrode. The MOS transistor M14 is connected to the node n6 via the source electrode and the drain electrode of the n-channel MOS transistor M12. The MOS transistor M14 operates using the clock signal CLKB1 applied to its gate electrode as a switching control voltage. When the signal level of the clock signal CLKB1 is high, the MOS transistor M14 is turned on, and the signal level of the clock signal CLKB1 is low. When it is off. The MOS transistor M14 in the on state makes the node n6 conductive to the VSS terminal 6. The back gate of the MOS transistor M14 is connected to the VSS terminal 6.

  An n-channel MOS transistor M13 is connected to the source electrode and drain electrode of the MOS transistor M14. The MOS transistor M13 is turned off when the signal level of the control signal PD is low. When the signal level of the control signal PD is high, the MOS transistor M13 conducts the VSS terminal 6 to the node n6 via the MOS transistor M12, so that a low level voltage is applied to the gate electrode of the MOS transistor M0 of the switch circuit 20. As a result, the switch circuit 20 is turned off.

  The MOS transistor M6 is electrically connected between the low-voltage side one end (node n4) of the bootstrap capacitive element C3 and the VSS terminal 6, and operates using the clock signal CLKB1 as a switching control voltage. The source electrode and the back gate of the MOS transistor M6 are both connected to the VSS terminal 6. Further, the source electrode and drain electrode of an n-channel MOS transistor M5 (hereinafter referred to as a dummy transistor M5) are connected to the drain electrode of the MOS transistor M6 and the node n4. The back gate of the dummy transistor M5 is connected to the VSS terminal 6 like the MOS transistor M6. The drain electrode and the source electrode of the dummy transistor M5 are both connected to the node n4, and the MOS transistor M6 and the node n4 are electrically short-circuited with each other.

  A switching control voltage (clock signal CLK1) having a phase opposite to that of the switching control voltage (clock signal CLKB1) applied to the gate electrode of the MOS transistor M6 is applied to the gate electrode of the dummy transistor M5. This is to compensate for clock feedthrough occurring in the MOS transistor M6. When the MOS transistor M6 transitions from the on state to the off state, electric charges are generated at the drain electrode of the MOS transistor M6 due to electrostatic coupling between the gate electrode and the drain electrode. When the dummy transistor M5 transitions from the off state to the on state, the negative charge generated at the drain electrode of the MOS transistor M6 is caused by electrostatic coupling between the gate electrode and the drain electrode and between the gate electrode and the source electrode. Generates a positive charge of opposite polarity. For this reason, the electric charge generated at the drain electrode of the MOS transistor M6 and the electric charge generated at the source electrode and the drain electrode of the dummy transistor M5 are canceled each other, so that the potential change of the node n4 due to clock feedthrough is suppressed. be able to.

  An n-channel MOS transistor M11 is electrically connected between one end (node n4) on the low voltage side of the bootstrap capacitive element C3 and the source electrode of the MOS transistor M0 of the switch circuit 20. The back gate of the MOS transistor M11 is connected to the node n4. The MOS transistor M10 is a clamp circuit for preventing the gate-source voltage of the n-channel MOS transistor M11 from exceeding the power supply voltage VDD. In the MOS transistor M10, the gate electrode is connected to the node n6, the source electrode and the drain electrode are connected between the nodes n5 and n4, and the back gate is connected to the node n4.

  Since the inverter element 14 supplies an inverted signal obtained by inverting the voltage level of the clock signal CLK1 to the gate electrode of the MOS transistor M9, the MOS transistor M11 performs a switching operation in synchronization with the clock signal CLK1. When the signal level of the control signal PD is low and the MOS transistor M9 is on, the MOS transistor M3 is also on, so that a high level voltage is applied to the gate electrode of the MOS transistor M11, and the MOS transistor M11. Is also turned on. When the signal level of the control signal PD is low and the MOS transistor M9 is off, a low level voltage is supplied to the gate electrode of the MOS transistor M11, and the MOS transistor M11 is turned off.

The operation of the bootstrap type switch circuit 1 having the above configuration will be described below with reference to FIGS. 3 (A) to (H) and FIGS. 4 (A) to (I). 3A to 3H are timing charts schematically showing various waveforms during the operation of the bootstrap circuit 10. 3, (A) shows the waveform of the control signal PD, (B) shows the waveform of the clock signal CLK1, (C) shows the waveform of the clock signal CLKB1, and (D) shows the input voltage at a constant voltage level Vi. An example of the waveform of _VIN , (E) is the waveform of the potential at the node n1, (F) is the waveform of the potential at the node n2, and (G) is the gate-drain voltage V _GD (M1) of the MOS transistor M1. (H) shows the waveform of the node n6, that is, the gate voltage of the MOS transistor M0. In FIGS. 3E, 3F, and 3G, pVDD = 2 × VDD and mVDD = −VDD.

Before the operation of the bootstrap type switch circuit 1 (before time t ₁ ), as shown in FIG. 3A, the logic level of the control signal PD is maintained at a high level, and FIGS. As shown in C), the signal levels of the clock signals CLK1 and CLKB1 are both maintained at the low power supply voltage VSS. As a result, a potential difference is generated between both ends of the capacitive elements C1 and C2, and the capacitive elements C1 and C2 are both charged (precharged). Therefore, as shown in FIGS. 3E and 3F, the nodes n1 and n2 The potential is larger than the power supply voltage VSS.

At the start of the operation of the bootstrap type switch circuit 1 (time t ₁ ), as shown in FIG. 3A, the control unit 30 switches the logic level of the control signal PD from the high level to the low level to boot. The power-down state of the strap type switch circuit 1 is canceled. As a result, the clock generation unit 17 outputs clock signals CLK1 and CLKB1 having opposite phases.

As illustrated in FIGS. 3B and 3C, when the power-down state is released, the clock signal CLK1 of the high level voltage VDD and the clock signal CLKB1 of the low level voltage VSS are supplied. At this time, since the clock signal CLKB1 is supplied to one end (node n11) of the capacitor C2, the potential of the node n2 is increased by electrostatic coupling as illustrated in FIG. As a result, the gate-drain voltage V _GD of the MOS transistor M1 increases as shown in FIG.

After that, when the clock signal CLK1 of the low level voltage VSS and the clock signal CLKB1 of the high level voltage VDD are supplied (time t ₂ ), the clock signal of the low level voltage VSS is applied to the gate electrode of the p-channel MOS transistor M9. Since a high-level switching control voltage having a phase opposite to that of CLK1 is applied, the MOS transistor M9 is turned off. Further, the clock signal CLKB1 of the high level voltage VDD is applied to the gate electrode of the n-channel MOS transistor M14, and the MOS transistor M14 is turned on. For this reason, the potential of the node n6 is fixed to the reference voltage VSS as shown in FIG. Therefore, the MOS transistor M11 is turned off. Therefore, the bootstrap capacitive element C3 is electrically disconnected from the switch circuit 20. On the other hand, in the booster circuit 13, the clock signal CLKB1 is supplied to one end (node n10) of the capacitive element C1, and the clock signal CLK1 is supplied to one end (node n11) of the capacitive element C2. 3 (E) and (F), the potential of the node n1 rises and the potential of the node n2 falls. At this time, the MOS transistor M3 transitions from the off state to the on state according to the potential change of the node n1, and the dummy transistor M4 transitions from the on state to the off state according to the potential change of the node n2. In addition, the MOS transistor M6 transitions from the off state to the on state in response to the voltage change of the clock signal CLKB1, and the dummy transistor M5 transitions from the on state to the off state in response to the voltage change of the clock signal CLK1. Therefore, a potential difference is generated between both end nodes n3 and n4 of the bootstrap capacitive element C3, and the bootstrap capacitive element C3 is charged.

Thereafter, when the clock signal CLK1 having the high level voltage VDD and the clock signal CLKB1 having the low level voltage VSS are supplied (time t ₃ ), as shown in FIGS. 3E and 3F due to electrostatic coupling. The potential of the node n1 decreases and the potential of the node n2 increases. At this time, the MOS transistor M3 transitions from the on state to the off state according to the potential change of the node n1, and the MOS transistor M6 transitions from the on state to the off state according to the voltage change of the clock signal CLKB1. At this time, the MOS transistors M9 and M11 are turned on. Therefore, both end nodes n3 and n4 of the bootstrap capacitive element C3 are electrically disconnected from the power supply terminals 5 and 6, respectively. However, both end nodes n3 and n4 of the bootstrap capacitive element C3 are respectively connected to the gate electrode of the MOS transistor M0. Conducts to the source electrode. When the input voltage _{VIN in} FIG. 3D is supplied to the source electrode of the MOS transistor M0, the potential of the node n3 rises through electrostatic coupling, and as shown in FIG. A voltage (= VDD + V _IN ) is applied to the node n6, that is, the gate electrode of the MOS transistor M0. Therefore, the on-resistance of the MOS transistor M0 can be reduced and the dependence of the on-resistance on the input voltage can be reduced. Note that the waveforms in FIGS. 3A to 3H are obtained by simulation. In this simulation, the ratio of the voltage level Vi to the power supply voltage VDD (= Vi / VDD) was set to about 0.12.

Next, FIGS. 4A to 4I are timing charts schematically showing various waveforms during other operations of the bootstrap circuit 10 after the power-on state is released. 4, (A) shows the waveform of the clock signal CLK1, (B) shows the waveform of the clock signal CLKB1, that is, the waveform of the potential at the node n10, and (C) shows the input voltage V changing from the voltage level Vj to the voltage level Vk. An example of the waveform of _IN , (D) shows the waveform of the potential at node n1, (E) shows the waveform of the potential at node n3, (F) shows the waveform of the potential at node n4, and (G) shows the waveform of the potential at node n5. (H) shows the waveform of the gate-source voltage V _GS (M7) of the MOS transistor M7, and (I) shows the waveform of the gate-source voltage V _GS (M8) of the MOS transistor M8. ing. In FIG. 4D, pVDD = 2 × VDD.

As shown in FIGS. 4A and 4B, at time t ₄ , t ₆ , t ₈ , the clock signal CLK1 rises from the low level voltage VSS to the high level voltage VDD, and the clock signal CLKB1 is at the high level. When the voltage VDD falls to the low level voltage VSS, the MOS transistor M3 transitions from the on state to the off state in accordance with the potential change of the node n1 (FIG. 4D), and the dummy transistor M4 has the potential of the node n1. The MOS transistor M6 transitions from the off state to the on state in response to a change in the potential of the node n2 in the opposite phase to the MOS transistor M6 in response to the voltage change in the clock signal CLKB1, that is, the potential change in the node n10 (FIG. The dummy transistor M5 changes from the on state to the off state, and the dummy transistor M5 changes in the potential of the node n11 in the opposite phase to the potential of the node n10. Flip transitions to the ON state from the OFF state. At this time, the MOS transistors M9 and M11 are turned on. Therefore, both end nodes n3 and n4 of the bootstrap capacitive element C3 are electrically disconnected from the power supply terminals 5 and 6, respectively. Conducts to the source electrode. For this reason, the potential of the node n4 rapidly decreases as shown in FIG. 4F and then rises to the potential _VIN, and the potential of the node n3 sharply changes as shown in FIG. 4E. After decreasing, it rises to the potential VDD + _VIN . Here, the reason why the potentials of the nodes n3 and n4 have sharply decreased is that clock feedthrough has occurred in the MOS transistors M3 and M6 that have transitioned from the on state to the off state. The negative charges generated in the MOS transistors M3 and M6 due to clock feedthrough are canceled by the positive charges generated at the source and drain electrodes of the dummy transistors M4 and M5. On the other hand, the MOS transistor M7 changes from the on state to the off state in accordance with the voltage change of the clock signal CLK1, that is, the potential change of the node n11 (FIG. 4A), and the MOS transistor M8 changes from the off state to the on state. Therefore, the potential of the node n5 rapidly decreases following the potential of the node n4, and then rises to the potential _VIN (FIG. 4G). Accordingly, the gate-source voltages V _GS (M7) and V _GS (M8) of the MOS transistors M7 and M8 are steep as shown by the waveform portions 40 and 41 in FIGS. To rise.

At time _{t 5, t 7, t 9} , falling clock signal CLK1 from the high level voltage VDD to the low-level voltage VSS, the clock signal CLKB1 rises from the low level voltage VSS to the high-level voltage VDD, MOS transistors M3 Changes from the OFF state to the ON state in response to the potential change of the node n1 (FIG. 4D), and the MOS transistor M6 changes the voltage change of the clock signal CLKB1, that is, the potential change of the node n10 (FIG. 4B). In response to the transition from the off state to the on state. At this time, the MOS transistors M9 and M11 are turned off. Therefore, both end nodes n3 and n4 of the bootstrap capacitive element C3 are connected to the power supply terminals 5 and 6, respectively. For this reason, the potential of the node n4 decreases to the power supply voltage VSS as shown in FIG. 4F, and the potential of the node n3 decreases to the power supply voltage VDD as shown in FIG. 4E. On the other hand, the MOS transistor M7 changes from the off state to the on state in accordance with the voltage change of the clock signal CLK1, that is, the potential change of the node n11 (FIG. 4A), and the MOS transistor M8 changes from the on state to the off state. Therefore, the potential of the node n5 rises to the power supply voltage VDD (FIG. 4G). In response to this, the gate-source voltages V _GS (M7) and V _GS (M8) of the MOS transistors M7 and M8 both decrease.

In the bootstrap circuit 10 of the present embodiment, when the MOS transistors M3, M6 is changed from the ON state to the OFF state (at time _t 4 in FIG. 4 (A) ~ (I) , t 6, t 8), the MOS Although clock feedthrough occurs in the transistors M3 and M6, the dummy transistors M4 and M5 generate positive charges that cancel the negative charges generated in the MOS transistors M3 and M6, respectively. Therefore, the gate-source of the MOS transistors M7 and M8 It is possible to suppress the inter-voltages V _GS (M7) and V _GS (M8) from rising excessively and to prevent the breakdown voltage level from being exceeded. In addition, an excessive increase in voltage between the back gate and the source / drain electrodes of the MOS transistors M7 and M8 is suppressed. Even when only one of the dummy transistors M4 and M5 is provided, an excessive increase in the gate-source voltages V _GS (M7) and V _GS (M8) can be suppressed.

  FIG. 5 is a diagram showing a schematic configuration of a bootstrap type switch circuit 1M of a comparative example that does not have the dummy transistors M4 and M5. The bootstrap type switch circuit 1M includes a bootstrap circuit 10M, a switch circuit 20, and a clock generation unit 17M. The configuration of the bootstrap circuit 10M is the same as that shown in FIG. 2 except that it does not include the dummy transistors M4 and M5 and the MOS transistor M13, and the configuration of the clock generation unit 17M is different from the configuration of the clock generation unit 17 in FIG. The configuration of the second bootstrap circuit 10 is the same. The clock generation unit 17M is a logic circuit including inverter elements I9 and I10 that generate clock signals CLK1 and CLKB1.

The operation of the bootstrap type switch circuit 1M will be described below with reference to FIGS. 6 (A) to (E) and FIGS. 7 (A) to (I). 6A to 6E are timing charts schematically showing various waveforms during the operation of the bootstrap circuit 10M of the comparative example. 6A shows the waveform of the clock signal CLK1, that is, the potential waveform of the node n11, FIG. 6B shows the waveform of the clock signal CLKB1, that is, the potential waveform of the node n10, and FIG. 6C shows the waveform of the potential of the node n1. (D) shows the waveform of the potential of the node n2, and (E) shows the waveform of the gate-drain voltage V _GD (M1) of the MOS transistor M1. 6C, 6D, and 6E, pVDD = 2 × VDD and mVDD = −VDD.

When the operation of the bootstrap type switch circuit 1M is started, as shown in FIGS. 6A and 6B, the clock generation unit 17M outputs clock signals CLK1 and CLKB1 having opposite phases to each other. Prior to time _{t 10,} the clock signal CLK1 of a low-level voltage VSS and the clock signal CLKB1 high level voltage VDD is supplied. Further, the potential of the node n1 is substantially the high level voltage VDD as shown in FIG. Therefore, since the potential difference hardly occurs between the both-end nodes n1 and n10 of the capacitive element C1, the capacitive element C1 is hardly charged. Thereafter, when the signal level of the clock signal CLK1 changes from the high level voltage VDD to the low level voltage VSS and the signal level of the clock signal CLKB1 changes from the low level voltage VSS to the high level VDD (time t ₁₀ ), the capacitance element C1 Due to the sharp drop in the potential at one end (node n10), the potential at the node n1 also drops significantly as shown in FIG. 6C. As a result, as shown in the waveform portion 50 of FIG. 6E, the gate-drain voltage V _GD of the MOS transistor M1 rises and exceeds the breakdown voltage level.

In contrast, in the bootstrap circuit 10 of the first embodiment, prior to release of the power-down state of the bootstrap type switch circuit 1 (FIG. 3 (A) before the time t ₁ of ~ (H)), the capacitive element C1 , C2 is given a potential difference, and the capacitive elements C1 and C2 are both charged (precharged), so that the potential at the other end (node n1) of the capacitive element C1 is steep as shown in FIG. It is avoided that the voltage drops. Therefore, it is possible to prevent the gate-drain voltage V _{GD of} the MOS transistor M1 from exceeding the withstand voltage level.

Next, FIGS. 7A to 7I are timing charts schematically showing various waveforms during other operations of the bootstrap circuit 10M of the comparative example. 7A shows the waveform of the clock signal CLK1, FIG. 7B shows the waveform of the clock signal CLKB1, that is, the waveform of the potential of the node n10, and FIG. 7C shows the input voltage V changing from the voltage level Vj to the voltage level Vk. An example of the waveform of _IN , (D) shows the waveform of the potential at node n1, (E) shows the waveform of the potential at node n3, (F) shows the waveform of the potential at node n4, and (G) shows the waveform of the potential at node n5. (H) shows the waveform of the gate-source voltage V _GS (M7) of the MOS transistor M7, and (I) shows the waveform of the gate-source voltage V _GS (M8) of the MOS transistor M8. ing. In FIG. 7D, pVDD = 2 × VDD.

As shown in FIGS. 7A and 7B, at time t ₁₃ , t ₁₄ , t ₁₅ , the clock signal CLK1 rises from the low level voltage VSS to the high level voltage VDD, and the clock signal CLKB1 is at the high level. When the voltage VDD falls to the low level voltage VSS, the MOS transistor M3 changes from the on state to the off state in accordance with the potential change of the node n1 (FIG. 7D), and the MOS transistor M6 receives the clock signal CLKB1. In response to a voltage change, that is, a potential change of the node n10 (FIG. 7B), the on state is changed to the off state. At this time, clock feedthrough occurs in the MOS transistors M3 and M6. However, since the negative charges generated in the MOS transistors M3 and M6 cannot be canceled, the potentials of the nodes n3 and n4 are temporarily greatly reduced (FIGS. 7E and 7F), and the nodes The potential of n5 is also greatly reduced (FIG. 7G). As a result, as shown in the waveform portions 51 and 52 of FIGS. 7H and 7I, the gate-source voltages V _GS (M7) and V _GS (M8) of the MOS transistors M7 and M8 have the breakdown voltage level. The phenomenon of exceeding can occur.

On the other hand, since the bootstrap circuit 10 of the first embodiment includes the dummy transistors M4 and M5 as described above, the gate-source voltages V _GS (M7) and V _GS (M8) of the MOS transistors M7 and M8. Can be prevented from exceeding the breakdown voltage level. MOS transistor M3, even when the clock feedthrough occurs in M6 (time _t 4 in FIG. 4 (A) ~ (I) , t 6, t 8), as shown in FIG. 4 (E), (F) The decrease in the potentials of the nodes n3 and n4 is suppressed, and as shown in the waveform portions 40 and 41 in FIGS. 4H and 4I, the waveform portions 51 and 52 in FIGS. 7H and 7I. It can be seen that the peak values of the gate-source voltages V _GS (M7) and V _GS (M8) of the MOS transistors M7 and M8 are suppressed to low values.

  As described above, the bootstrap type switch circuit 1 of the first embodiment has the dummy transistors M4 and M5, and the dummy transistor M4 is between the MOS transistor M3 and one end (node n3) of the bootstrap capacitive element C3. The dummy transistor M5 is connected to a signal transmission path (short-circuit path) between the MOS transistor M6 and the other end (node n4) of the bootstrap capacitive element C3. Compensating clock feedthrough generated in the MOS transistors M3 and M6 by supplying a control voltage having a phase opposite to that applied to the gate electrodes of the MOS transistors M3 and M6 to the gate electrodes of the dummy transistors M4 and M5. Can do. Therefore, the gate-source voltages of the MOS transistors M7 and M8 connected to the nodes n3 and n4 can be prevented from exceeding the withstand voltage level.

  In addition, since the capacitive elements C1 and C2 of the booster circuit 13 are precharged before the operation of the bootstrap type switch circuit 1, the capacitive element C1 does not need to be charged up at the start of the operation, and the gate− It is possible to prevent the source-to-source voltage from exceeding the withstand voltage level.

  By providing such a bootstrap type switch circuit 1 in an integrated circuit such as an A / D converter or a sample and hold circuit, an integrated circuit that can operate stably even with a low power supply voltage or a temperature change is provided. Can do. For example, FIG. 8 is a schematic diagram showing an example of an integrated circuit 7 in which the bootstrap type switch circuit 1 is incorporated. The integrated circuit 7 includes an operational amplifier 64 and capacitive elements C10 to C13, and further includes bootstrap switch circuits 1A to 1H having the same structure as the bootstrap switch circuit 1.

Embodiment 2. FIG.
Next, a second embodiment according to the present invention will be described. As shown in FIG. 2, in the bootstrap type switch circuit 1, the bootstrap circuit 10 is connected to the input terminal and the control terminal (gate electrode) of the switch circuit 20, but is connected to the output terminal of the switch circuit 20. In this case, an unbalanced load is applied between the input side and the output side. For example, referring to FIG. 8, in the bootstrap type switch circuit 1H, the bootstrap circuit 10 is connected to one output terminal of the operational amplifier 64, but is not connected to the other output terminal. In the bootstrap type switch circuit 1E, the bootstrap circuit 10 is connected to the capacitive element C12, but not connected to the capacitive element C11. Such load imbalance may affect the performance of the integrated circuit 7.

  FIG. 9 is a diagram showing a schematic configuration of the bootstrap type switch circuit 2 according to the second embodiment for eliminating the load imbalance. The bootstrap type switch circuit 2 includes a bootstrap circuit 11, a switch circuit 20, and a control unit 30. The configuration of the bootstrap circuit 11 is the same as the configuration of the bootstrap circuit 10 of FIG. 2 except for the MOS transistor M11b connected to the drain electrode of the MOS transistor M0. As shown in FIG. 9, since the bootstrap circuit 11 is connected to the input terminal, the control terminal (gate electrode), and the output terminal of the switch circuit 20, the load unloading between the input side and the output side is performed. Balance can be eliminated.

  FIG. 10 is a schematic diagram illustrating an example of the integrated circuit 8 in which the bootstrap type switch circuit 2 according to the second embodiment is incorporated. The integrated circuit 8 includes an operational amplifier 64 and capacitive elements C10 to C13, and further includes a bootstrap switch circuit 2A having the same structure as the bootstrap switch circuit 1A to 1D, 1F, and 1G. , 2B.

  Note that the connection form of the MOS transistor M11b is not limited to that shown in FIG. For example, as shown in FIG. 11, a bootstrap switch circuit 3 having a bootstrap circuit 11M to which one of the controlled electrodes of the MOS transistor M11b is not connected may be employed.

  Although various embodiments according to the present invention have been described above with reference to the drawings, these are examples of the present invention, and various embodiments other than those described above can be adopted. For example, the bootstrap circuit 10 is configured by using field effect transistors M1 to M14 having a MOS (Metal-Oxide-Semiconductor) structure, but is not limited thereto. For example, instead of the field effect transistors M1 to M14 having a MOS structure, a field effect transistor having a MIS (Metal-Insulator-Semiconductor) structure may be used.

  1, 2, 3 Bootstrap type switch circuit, 10, 10M, 11 Bootstrap circuit, 20 switch circuit, M1-M14, M11b MOS field effect transistors.

Claims (12)

A bootstrap circuit for controlling the operation of the switch circuit,
A bootstrap capacitive element;
A first switching element that establishes conduction or non-conduction between one controlled terminal of the pair of controlled terminals of the switch circuit and one end of the bootstrap capacitive element in synchronization with the first clock signal; ,
In synchronization with the first clock signal, a second switching element that makes conduction or non-conduction between the other end of the bootstrap capacitive element and the control terminal of the switch circuit;
A first field effect transistor electrically connected between a first power supply terminal for supplying a first power supply voltage and the other end of the bootstrap capacitive element, and performing a switching operation in accordance with a first switching control voltage; ,
A second field effect transistor connected to a signal transmission path between the first field effect transistor and the other end of the bootstrap capacitive element and performing a switching operation according to a second switching control voltage. Features a bootstrap circuit. The bootstrap circuit according to claim 1,
The pair of controlled electrodes of the second field effect transistor are electrically short-circuited with each other,
At least one of the pair of controlled electrodes of the second field effect transistor is connected to the controlled electrode on the bootstrap capacitor element side of the pair of controlled electrodes of the first field effect transistor. A bootstrap circuit characterized by that.   3. The bootstrap circuit according to claim 1, further comprising a circuit unit that supplies signals having mutually inverted voltage levels as the first and second switching control voltages. circuit. A bootstrap circuit according to any one of claims 1 to 3,
A second power supply terminal that supplies a second power supply voltage lower than the first power supply voltage is electrically connected between one end of the bootstrap capacitive element, and a switching operation is performed according to a third switching control voltage. A third field effect transistor that
And a fourth field effect transistor connected to a signal transmission path between the third field effect transistor and one end of the bootstrap capacitive element and operating according to a fourth switching control voltage. A bootstrap circuit. The bootstrap circuit according to claim 4,
The pair of controlled electrodes of the fourth field effect transistor are electrically short-circuited to each other,
At least one of the pair of controlled electrodes of the fourth field effect transistor is connected to the controlled electrode on the bootstrap capacitive element side of the pair of controlled electrodes of the third field effect transistor. A bootstrap circuit characterized by that.   6. The bootstrap circuit according to claim 4, further comprising a circuit unit that supplies signals having mutually inverted voltage levels as the third and fourth switching control voltages, respectively. circuit. The bootstrap circuit according to any one of claims 1 to 6,
A bootstrap circuit further comprising a fifth field effect transistor having a controlled electrode connected to at least one of both end nodes of the bootstrap capacitor. A bootstrap circuit according to any one of claims 1 to 7,
A booster circuit that boosts the first power supply voltage to generate the first switching control voltage;
A clock generation unit that generates a first clock signal and a second clock signal having a phase different from that of the first clock signal based on a reference clock signal;
The booster circuit includes:
A first capacitive element for level shift having one end to which the second clock signal is applied;
A first step-up field effect transistor interposed in a path between the other end of the first capacitive element and the first power supply terminal;
The first switching control voltage is supplied from the other end of the first capacitive element;
The clock generation unit generates the first clock signal and the second clock signal after charging the first capacitive element by applying a potential difference to both ends of the first capacitive element at the start of operation. Bootstrap circuit. A bootstrap circuit for controlling the operation of the switch circuit,
A bootstrap capacitive element;
A first switching element that establishes conduction or non-conduction between one controlled terminal of the pair of controlled terminals of the switch circuit and one end of the bootstrap capacitive element in synchronization with the first clock signal; ,
In synchronization with the first clock signal, a second switching element that makes conduction or non-conduction between the other end of the bootstrap capacitive element and the control terminal of the switch circuit;
A first field effect transistor electrically connected between a first power supply terminal for supplying a first power supply voltage and the other end of the bootstrap capacitive element, and performing a switching operation in accordance with a first switching control voltage; ,
A booster circuit that boosts the first power supply voltage to generate the first switching control voltage;
A clock generation unit that generates a first clock signal and a second clock signal having a phase different from that of the first clock signal based on a reference clock signal;
The booster circuit includes:
A first capacitive element for level shift having one end to which the second clock signal is applied;
A first step-up field effect transistor interposed in a path between the other end of the first capacitive element and the first power supply terminal;
The first switching control voltage is supplied from the other end of the first capacitive element;
The clock generation unit applies a voltage that gives a potential difference to both ends of the first capacitive element at the start of operation to charge the first capacitive element after charging the first capacitive element. A bootstrap circuit for generating the second clock signal. A bootstrap circuit according to claim 8 or 9,
The booster circuit includes:
A second capacitive element for level shift having one end to which the first clock signal is applied;
A second boosting electric field interposed in a path between the other end of the second capacitive element and the first power supply terminal and performing a switching operation according to a switching control voltage supplied from the other end of the first capacitive element. An effect transistor,
The first step-up field effect transistor performs a switching operation according to a switching control voltage supplied from the other end of the second capacitor element,
The clock generation unit generates the first clock signal and the second clock signal after charging the second capacitive element by applying a potential difference to both ends of the second capacitive element at the start of the operation. To bootstrap circuit.   11. The bootstrap circuit according to claim 1, further comprising a third switching element connected to the other controlled terminal of the pair of controlled terminals of the switch circuit. A bootstrap circuit characterized by that.   An integrated circuit comprising the bootstrap circuit according to claim 1.

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