JP5467134B1 - Flash memory device and method of operating memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flash memory device and a memory device operating method capable of avoiding a delay.
The timing of a logic read operation in a flash memory device can be improved by a pad serial output circuit that pre-decodes command signals and pre-fetched logic before the last command clock. Data is received and high speed analysis is performed on the command of the pad serial output circuit at the last clock of the command input array. In another embodiment, the first command predecode and data prefetch are performed on the fourth clock of the command input, and the second command predecode is performed on the seventh clock of the command input.
[Selection] FIG.

Description

  The present invention relates to a flash memory, and more particularly, to reading logic data of a flash memory.

  Single bit serial and multiple bit serial flash memories have become popular due to LPC (low pin count) and a simple interface. The simplest interface is a one-bit Serial Peripheral Interface (SPI). The 1-bit SPI protocol allows the user to send 8-bit commands, address bytes, and optional dummy bytes to the SPI flash memory device, and in response, the SPI flash memory device returns data to the user. To do. A single 8-bit command can identify a read, delete / program, or other suitable operation. For high-performance system applications that require high-speed reading performance, for example, SPI-Dual, SPI-Quad, Quad Peripheral Interface (QPI), etc. -The interface has evolved. SPI-quad provides 8-bit commands serially, one bit at a time, but all subsequent fields (eg, address, optional dummy byte, and data) are 4 bits (quad) Completing on a serial basis improves read volume. In QPI, all fields (eg, 8-bit command, address, optional dummy byte, and data) are all completed in 4-bit serial. Thus, since QPI provides 8-bit commands in two clock periods, the SPI-quad requires eight clock periods. For example, various multi-bit serial flash interface protocols are disclosed in US Pat. No. 7,558,900 issued July 7, 2009 by Jigour et al.

  The types of read operations performed by the flash memory generally include memory array read and logic read. FIG. 1 is a schematic block diagram of a circuit for reading logic in a typical flash memory. The logic 12 receives logic data such as status data, JEDEC (Joint Electron Device Engineering Council) manufacturer, and partial authentication data from various registers (eg, register 4 in FIG. 2). The logic 12 also receives a serial input SI including a plurality of commands and various input data. The logic 12 completely decodes each command of the eighth clock, and when the command is the signal JEDEC, RDSR1, or RDSR2, selects the data JEDECID, SR1, or SR2, respectively, and selects the selected command as the logic. The data register 14 is provided as data LOGICDATA. When the command is a memory read command, the data register 14 also receives array data ARRAYDATA from the memory cell array. Based on input signals of the logic 12, for example, signals JEDEC, RDSR1, and RDSR2, the data register 14 selects logic data LOGICDATA or array data ARRAYDATA, and outputs the selected data as a serial data output signal SDOUT /. Pad serial output circuit 16 includes an output driver. When serial data output signal SDOUT / is logic data and pad serial output circuit 16 is enabled by signal RDLD, or serial data output signal SDOUT / is memory array data. When the pad serial output circuit 16 is enabled by the signal OEIN at the time, the above-described output driver outputs the serial data output signal SDOUT / to the contact surface of the mounted flash memory device such as lead, pad, and pin. To do. The pad serial output circuit 16 is controlled by the system clock SCK, while the logic 12 and the data register 14 are controlled by the clock signal CLK, that is, the system clock SCK buffered by the input pad circuit 10.

  FIG. 2 shows the logic 12 in more detail. The logic 12 decodes the command of the serial input SI, reads the logic read command, the explanatory signal JEDEC for reading the data JEDECID, the signal RDSR1 for reading the first status register, and the signal RDSR2 for reading the second status register Provides a signal that can be uniquely identified. These signals are combined in the combinational logic 24 to obtain a signal RDLD indicating a logic data read command. Signal RDLD is applied to the select input of multiplexer 26, and when signal RDLD is activated, multiplexer 26 selects logic data LOGICDATA from one of the plurality of data inputs, otherwise it selects data from register 25. . Register 25 stores memory array data received from main array sense amplifier 2.

  FIG. 3 shows the pad serial output circuit 16 in more detail. The output driver 34 is controlled by the clock signal CLK and the output enable signal OE from the D-type flip-flop 32. The D-type flip-flop 32 generates an output enable signal OE based on the signal RDLD applied to the input terminal SET and the signal OEIN applied to the input terminal D. The input signal OEIN is used for array reading. Both the D-type flip-flop 32 and the output driver 34 are controlled by the clock signal CLK.

  Flash memory can be widely applied to digital electronic devices and systems. However, high performance devices and systems typically require frequent operation of flash memory. For example, in the memory read operation, using a dummy clock after the command allows more frequent operations, but the speed of the logic read operation still causes a bottleneck. there is a possibility. This problem is caused by too much delay in command decode and logic circuits, data register circuits, and interconnect internal signal lines.

  In one embodiment of the present invention, logic data can be output in response to a set of logic read commands, an external signal input terminal, an addressable flash memory cell array, a data register, a plurality of registers, And a flash memory device including a command and control logic circuit. The data register is connected to the addressable flash memory cell array and is used to receive and store array data from the addressable flash memory cell array. Multiple registers are used to store logic data. The command and control logic circuit includes pre-fetch logic and output control logic. The prefetch logic is connected to the external signal input terminal, and when the first partial array of the most significant bits of the command received by the external signal input terminal is the predicted specific logic data read command, the plurality of logic read Used to prefetch logic data from one of the plurality of logic data registers based on a particular one of the commands. The output control logic is connected to the external signal input terminal, and the second partial array of the most significant bits of the command received by the external signal input terminal is one of the predicted logic data read commands. Is used to generate a predicted logic read command signal. The flash memory device is further connected to a data register, a prefetch logic, an output control logic, and an external signal input terminal, and a predicted logic read command signal and a command of a portion other than the first partial array and the second partial array are It includes a pad output circuit used to select and output logic data from the prefetch logic when analyzing any one of the received plurality of logic data read commands.

  In another embodiment of the present invention, there is provided a method of operating a memory device having a flash memory cell array and providing logic data to an application program in response to a logic read command having a predetermined number of command bits. To do. The method receives a bit arrangement of a command having a number of bits smaller than a predetermined number of command bits, the plurality of received bit arrangements being a plurality of most significant bits of the command, and the memory device Pre-decode the received bit arrangement in the logic circuit of the first and second to determine whether the received bit arrangement matches the bit arrangement of the corresponding logic read command; and in the pad output circuit Complete decoding of the remaining bits of the command to determine whether conformance of the predecode step correctly predicted the logic read command and output logic data based on the logic read command Including.

In another embodiment of the present invention, there is provided a method of operating a memory device having a flash memory cell array and providing logic data to an application program in response to a logic read command having a predetermined number of command bits. To do. The method receives a first bit arrangement of a command having a bit number smaller than a predetermined number of command bits, and the plurality of received first bit arrangements are a plurality of most significant bits of the command. Predecoding the received first bit array in the logic circuit of the memory device to determine whether the received first bit array matches a bit array of a corresponding logic read command; Prefetching logic data based on the logic read command adapted in the decoding step; and a second bit array of commands having a number of bits less than a predetermined number of command bits but greater than the first bit array And the received plurality of second bit arrangements are a plurality of final commands of the command. And the pre-decoding of the received second bit array in the logic circuit of the memory device to determine whether the received second bit array matches the bit array of the corresponding logic read command. And completing the decoding of the remaining bits of the command in the pad output circuit to determine whether the adaptation of the pre-decoding step of the second bit array correctly predicted the logic read command; And outputting the logic data prefetched in the prefetching step. In one variation, before the most significant bit Symbol second bit sequence is 7 bits. In another variation, the first partial array of most significant bits is 4 bits and the second partial array of most significant bits is 7 bits.

  The timing of the logic read operation can be improved by the pad serial output circuit, receiving the predecoded command signal and prefetched logic data before the last command clock, and the command input array of the pad serial output circuit By performing a fast resolution on the last clock command, serial logic circuit delay, data register delay, and internal signal line delay can be avoided.

1 is a block schematic diagram of pad, logic and data register circuits of a known flash memory device. FIG. FIG. 2 is a detailed block schematic diagram of the logic circuit in FIG. 1. FIG. 2 is a detailed block schematic diagram of the pad output circuit of FIG. 1. FIG. 2 is a timing diagram illustrating a defective state of the flash memory device of FIG. 1. FIG. 5 is a timing diagram showing a part of the timing diagram of FIG. 4 in detail. 1 is a schematic circuit diagram of a flash memory structure including command predecode and data prefetch. FIG. FIG. 6 is a table showing digital representations of various logic read commands. FIG. FIG. 7 is a timing diagram showing various signals included in the operation of the flash memory of FIG. 6. FIG. 7 is a block schematic diagram of a pad, logic and data register circuit of the flash memory device of FIG. 6. FIG. 10 is a detailed block schematic diagram of the logic circuit of FIG. 9. FIG. 10 is a detailed block schematic diagram of the pad output circuit of FIG. 9. FIG. 3 is a schematic circuit diagram of a part of a flash memory structure including command predecode and data prefetch used for the QPI mode. 7 is a flowchart schematically showing logic data reading using command predecode and logic data prefetch during operation of the flash memory device of FIG. 6. 5 is a flowchart schematically showing logic data reading using only 7-bit command predecode and logic data prefetch during operation of the flash memory device.

  Flash memory can be widely applied to digital electronic devices and systems. However, high performance devices and systems typically require frequent operation of flash memory. As an example, memory read operations can be performed more frequently by using a dummy clock after the command, but the speed of logic read operations may still be a bottleneck. is there. This problem is caused by too much delay in command decode and logic circuits, data register circuits, and interconnect internal signal lines.

  For example, the signal JEDEC read command (9Fh), the first status register read command (signal RDSR1 05h), and the second status register read command (signal RDSR2 35h) are all examples of logic read commands. The signal JEDEC read command outputs the manufacturer and device ID byte from the device to determine the device ID. The read commands for signals RDSR1 and RDSR2 output the contents of the first status register and the second status register, respectively.

  FIG. 4 shows an operation situation when the signals JEDEC, RDSR1 and RDSR2 are operated with extremely high frequency, and it is assumed that the flash memory device has no other bottleneck. The serial input SI includes 8 clocks and controls 8 command bits at the rising edges, and then connects multiple other clocks to control the data at the falling edges. In this flash memory, not only the eighth clock can control the least significant bit (LSB) at the rising edge of the command, but also the first at the falling edge, as indicated by the leftmost down arrow. Designed to control data bits. Thus, the command decode and fetch, and the timing margin for completing the output data is a fairly short half-cycle.

  Unfortunately, if there is no other bottleneck in the flash memory, as shown in FIG. 5, if the frequency of operation increases to a certain point, the half-cycle timing margin becomes insufficient. When many delays occur, relatively significant delays are indicated by arrows A1, B1, C1, D1 and E1. Arrow A1 indicates a delay due to buffering of the system clock SCK and can provide the internal clock signal CLK. Arrow B1 indicates the delay until the signal JEDEC, RDSR1 or RDSR2 is generated by decoding the command after the eighth bit has arrived. An arrow C1 indicates a delay when appropriate logic data is selected after the signal JEDEC, RDSR1, or RDSR2 is generated in the logic 12. An arrow D1 indicates that the combinational logic 24 in the data register 14 and the clock signal CLK of the multiplexer 26 (shown in FIG. 2) when the serial data output signal SDOUT / is output by selecting between the array data ARRAYDATA and the logic data LOGICDATA. Shows the delay associated with the rising edge. An arrow E1 indicates a delay for generating the output enable signal OE extending on the RDLR signal path and at the rising edge of the clock signal CLK of the D-type flip-flop 32. The output enable signal OE enables the output driver 34. The arrow F1 indicates the overall delay, which in this example is almost the full cycle and greatly exceeds the timing margin of the half cycle.

  In general, the operation frequency of the flash memory is ideally higher. In a flash memory array read operation, when the timing is improved and the bottleneck disappears, the timing delay during the logic read operation exceeds the half-cycle timing margin and becomes the next bottleneck in more frequent operations there is a possibility. Advantageously, the embodiments described herein can improve the timing of logic read operations using various methods.

  The timing of the logic read operation can be improved by the pad serial output circuit, receiving the predecoded command signal and prefetched logic data before the last command clock, and the command input array of the pad serial output circuit By performing a fast resolution on the last clock command, serial logic circuit delay, data register delay, and internal signal line delay can be avoided. In the SPI embodiment, command predecode is used to generate a pre-command signal that is completed in the seventh clock of the command input and provided to the pad serial output circuit in advance. The predecoded command is also used to prefetch logic data provided to the pad serial output circuit in advance. In another SPI embodiment, command predecode is completed in the fourth clock of the command input and is used to generate a precommand signal that is previously provided to the pad serial output circuit. Another command predecode is completed in the seventh clock of the command input, and is used to prefetch logic data provided in advance to the pad serial output circuit. In the QPI embodiment, the command predecode is completed in the first clock of the 4-bit command input, and is used to generate a precommand signal that is provided in advance to each of the four pad serial output circuits. The pre-command signal can prefetch logic data provided to each of the four pad serial output circuits in advance. The high-speed command analysis is completed at the second clock of the command input array of each circuit of the four pad serial output circuits, and each of the four pad serial output circuits receives four LSBs of commands. Command predecode, logic data prefetch, and high-speed command analysis techniques in the pad serial output circuit can be used alone or in any combination to improve logic read timing. .

  FIG. 6 is a block schematic diagram of a flash memory device structure including logic read command predecode, logic data prefetch, and high speed command analysis in a pad serial output circuit. The flash memory cell array 66 can be read and written by different address, read and write circuits, and the circuit described above includes a row decode circuit 64 and a column decode circuit 68. The column decode circuit 68 includes 32 sense amplifier blocks 681 for reading the flash memory cell array 66 and a 256-byte page buffer 682 for writing the flash memory cell array 66. The write protect logic 641 responds to the status register 42 to prevent writing to the flash memory cell array 66 in a specific situation. Command and control logic 50 controls high voltage generator 56 and page address latch and counter 58, and high voltage generator 56 and page address latch and counter 58 in turn control row decode circuit 64. The command and control logic 50 also controls the byte address latch and counter 60 and controls the column decode circuit 68 in turn. Command and control logic 50 includes four input / output signal lines IO0-IO3, a buffered clock input pin CLK1, and a chip select input pin CS. SPI and QPI are supported, including standard SPI commands, dual SPI commands, quad SPI commands and QPI commands. QPI operation is supported when the device is switched from standard / dual / quad SPI mode to QPI mode using the “Enable QPI (38h)” command. The “disable QPI (FFh)” command can be used to return the device to standard / dual / quad SPI mode.

  The command predecode embodiment can be described using three commands: signals RDSR1 (05h), RDSR2 (35h), and JEDEC (9Fh). For example, another logic data such as a third status register and a logic read command may be added, but the principle described here can be applied. Since the command bit is detected at the rising edge of the clock, any command can be clearly determined at the rising edge of the eighth clock. However, as shown in FIG. 7, the LSBs of the signals JEDEC, RDSR1, and RDSR2 commands are the same, that is, all of them are 1. Therefore, in these commands, a clear determination can be made at the rising edge of the seventh clock. Even though the 8 command bits are still unknown to the command decoder, the command can be obtained by analyzing the command bits in one fast clock period, ie, based on only 7 command bits. Also, as shown in FIG. 7, these commands differ in the four most significant bits (Most Significant Bits, MSB). Therefore, in these commands, it is possible to make a clear determination for prefetching the data JEDEC, SR1, and SR2 from the status register 42 at the rising edge of the fourth clock. Although the decode operation after the four command bits is not as clear as the other commands, such ambiguities are due to the seven bit predecode and / or pad serial output circuit 46 (shown in FIG. 6). ) Can be solved based on the command analysis executed in step (1).

  FIG. 8 is a timing diagram of signals JEDEC, RDSR1 and RDSR2 commands with 4-bit command predecode and data prefetch, 7-bit command predecode, and pad serial output circuit command analysis. FIG. 9 is a detailed block schematic diagram for realizing the above operation in the flash memory circuit of FIG. 10 shows details of the logic 54, and FIG. 11 shows details of the pad serial output circuit 46.

  As shown in FIG. 9, the system clock SCK is applied to the pad serial output circuit 46 and simultaneously to the input pad circuit 48. The system clock SCK is buffered by the input pad circuit 48 and supplied as the clock signal CLK. Clock signal CLK is applied to logic 54 and data register 52, which is located in command and control logic 50 (shown in FIG. 6). The logic 54 also receives logic data, eg, signal JEDEC, and status data SR1 and SR2 from the status register. The logic 54 receives the serial input SI separately.

  As shown in FIG. 10, the logic 54 includes a 4-bit predecoder 100, which decodes the 4 MSBs of the serial input SI, and when the 4 MSBs indicate a signal RDSR1, RDSR2 or JEDEC, respectively, The predecoder 100 activates the signal PD4_RDSR1, PD4_RDSR2, or PD4_JEDEC. Signals PD4_RDSR1, PD4_RDSR2, and PD4_JEDEC are applied to combinational logic 102 to generate select signals SELECT <1: 0> for controlling multiplexer 104. The manufacturer and part of the indicator signal JEDECID and the status data SR1 and SR2 from the status register are identified as data inputs and applied to the multiplexer 104, and the selection of these signals is applied to the selection signal SELECT <1: 0>. In addition, the prefetched data signal is identified as logic data LOGICDATA and applied to the pad serial output circuit 46 (shown in FIG. 9). Therefore, as shown in FIG. 8, at time A2, logic data LOGICDATA is provided to the pad serial output circuit 46 immediately after the rising edge of the fourth clock.

  FIG. 10 also includes a 7-bit predecoder when logic 54 includes a 7-bit predecoder 106 that decodes the 7 MSBs of the serial input SI and each of the 7 MSBs indicates a signal RDSR1, RDSR2 or JEDEC. 106 illustrates activation of signal PD7_RDSR1, PD7_RDSR2 or PD7_JEDEC. Signals PD7_RDSR1, PD7_RDSR2 and PD7_JEDEC are applied to combinational logic 108 to generate pre-command signal PRECMD <1: 0>. The pre-command signal PRECMD <1: 0> is provided to the pad serial output circuit 46 at time B2 (shown in FIG. 8), that is, at the rising edge of the seventh clock of the buffered clock signal CLK. As shown in FIG. 8, the values of the pre-command signal PRECMD <1: 0> are 0 and 1, as shown.

  As shown in FIG. 11, the pad serial output circuit 46 receives the pre-command signal PRECMD <1: 0> and the serial input SI, and performs combinational logic for executing high-speed command analysis in the last opcode period. 110 is included. The pre-command signal PRECMD <1: 0> indicates whether the command is an expected signal RDSR1, RDSR2, JEDEC, or a command other than these commands. The combinational logic 110 combines the pre-command signal PRECMD <1: 0> and the LSB of the command to analyze whether or not the command is the signal RDSR1, RDSR2 or JEDEC, and the result is output to the D-type flip-flop 112. Applied to the input terminal D, at time C2 (shown in FIG. 8), that is, at the rising edge after the eighth clock signal CLK, an output is generated and transmitted to the input terminal SET1 ′. Therefore, when the command is the expected signal RDSR1, RDSR2 or JEDEC, and the LSB of the command is 1 (shown in FIG. 7), the signal SET1 is activated. Otherwise, the signal SET1 is not activated.

  Pad serial output circuit 46 also includes another D-type flip-flop 114 that provides output enable signal OE to output driver 118 at output terminal Q. D-type flip-flop 114 receives signal OEIN at its input terminal D and enables array reading. D-type flip-flop 114 also includes input terminals SET1 'and SET and receives signals SET1 and RDLD, respectively. When both the signals SET1 and RDLD are 0, the state of the D flip-flop 114 and the enable state of the output driver 118 are determined by the signal OEIN that performs array reading. However, when the signal SET1 is 1, that is, when execution of logic reading is confirmed, the output enable signal OE is generated at time D2 (shown in FIG. 8), that is, at the falling edge of the eighth command clock. . This timing ensures that data from the output driver 118 is available on the falling edge of the clock of the eighth command and can anticipate proper operation of the flash memory device.

  The serial data output signal SDOUT / and the logic data LOGICDATA are applied to the input terminal of the multiplexer 116 and are applied to the input terminal of the output driver 118 in one of the following ways. The signal ARRAY_READ is related to reading of the flash memory cell array 66 and does not start until the array read command is decoded. Therefore, when the signal ARRAY_READ is initialized so as not to be activated, the multiplexer 116 is initialized to select the logic data LOGICDATA.

  With these command sets, it is not possible to make a clear determination of a command based on the seven MSBs of the command. For example, the signal JEDEC (9Fh or 10011111) cannot be distinguished from 9Eh (10011110) based on 7 MSBs. Similarly, the signal RDSR1 (05h or 00000101) cannot be distinguished from 04h (00000100) based on the seven MSBs. If a clear decision cannot be made based on the seven MSBs, there are two possible outcomes.

  The first situation is a command 9Eh as an example. It is practical to infer the signal JEDEC from the invalid 9Eh, since 9Eh is an invalid command at this time and does not affect the flash memory due to the output signal JEDEC data and may be overlooked by the device or system. is not a problem. Also, a carefully designed system or device will not issue such invalid commands. Therefore, this problem can be ignored when ambiguity arises due to invalid commands. However, for a flash memory control system, it is ideal to avoid misunderstanding of invalid commands and to make valid commands.

  The second situation is a command 04h as an example. Currently, in some flash memories, 04h is a write disable command issued to reset the write enable latch (WEL) bit of the status register from 1 to 0. Therefore, from the viewpoint of the computer program, 04h is a valid command. However, if such a command misinterprets the flash memory control circuit as the signal RDSR1 05h, a failure occurs in the computer program. For a flash memory that receives a valid command that cannot be clearly determined based on these seven MSBs, it is ideal that the flash memory control system can detect a potential erroneous command and properly process its decoding.

  The combinational logic 110 in the pad serial output circuit 46 performs ambiguity resolution on the 7-bit predecode in the following method. The LSBs of the invalid command 9Eh and the write enable latch command 04h both include one zero. In this situation, since the output terminal of the combinational logic 110 transmits 0 to the input terminal D of the flip-flop 112, the D-type flip-flop 112 stores 0 and the output terminal Q does not include the logic value of the input terminal D. 0 can be transmitted to the input terminal SET1 ′ of the D-type flip-flop 114. Therefore, any activation of the output enable signal OE is controlled by the input terminal D.

  The techniques described here can be applied to SPI or QPI interfaces. The memory device structure shown in FIG. 6 may be modified as shown in FIG. 12 and used to support 1-bit and multi-bit SPI as well as QPI.

  In 1-bit and multi-bit SPI interfaces, 8-bit commands are provided by 1-bit serial. That is, one bit is provided for each of the eight clocks. This input is provided by the serial input SI. For the multi-bit SPI, the memory device structure shown in FIG. 6 may be modified to include a plurality of pad serial output circuits equal in number to a plurality of output bits controlled in one time, and High speed command analysis may be performed in the pad serial output circuit. The pre-command signal PRECMD <1: 0> can have a value of 0 or 1 so that each pad serial output circuit can be enabled and output.

  In the QPI interface, 8-bit commands are provided in 4-bit serial. That is, four bits are transmitted using two clocks. For the QPI interface, the memory structure shown in FIG. 6 may be changed as shown in FIG. Command and control logic 120 includes a data register 122 and logic 124. Pad serial output circuits 130, 131, 132 and 133 may be used in combination with input / output signal lines IO0, IO1, IO2 and IO3 connected thereto, respectively. The bits <4,0>, <5,1>, <6,2> and <7,3> of the logic data LOGICDATA are transmitted to the pad serial output circuits 130, 131, 132 and 133 by the logic 124, respectively. The pre-command signal PRECMD <1: 0> is transmitted to the pad serial output circuits 130, 131, 132 and 133 by the logic 124. Bits <4,0>, <5,1>, <6,2>, and <7,3> of serial data output signal SDOUT / are sent to pad serial output circuits 130, 131, 132, and 133 by data register 122, respectively. Is transmitted. System clock SCK is transmitted to pad serial output circuits 130, 131, 132 and 133. The high-speed command analysis used for QPI can be performed by the following method. That is, when IO3 to IO0 of signals RDSR1, RDSR2 and JEDEC are 0101, 0101 and 1111 (FIG. 7), respectively, 0 and 1 value of the pre-command signal PRECMD <1: 0> are set to the pad serial output circuit 130, It can be used to enable the outputs of 131, 132 and 133.

  FIG. 13 is a flowchart 140 schematically illustrating a logic data read operation using 4-bit and 7-bit command predecode. System clock SCK is buffered by input pad circuit 48 and provides buffered clock signal CLK to logic 54 and data register 52 (step 141). After the four clock signals CLK control the four MSBs of the incoming command and these four MSBs are predecoded into logic 54 (step 142), the logic 54 predecoded in these four bits. Based on the read command (for example, the signal JEDEC or the status data SR1 or SR2 in the status register), the logic data is prefetched (step 143). The prefetched logic data is provided to the pad serial output circuit 46 before the eighth system clock SCK (step 144). The seven clock signals CLK control the seven MSBs of the incoming command and are predecoded by the logic 54 to generate a precommand signal (step 145). (Step 146). The pre-command signal is combined with the LSB (the rising edge of the eighth system clock SCK) used for the high-speed command analysis in the pad serial output circuit 46 to resolve the ambiguity of the pre-decode command (step 147). If the command is not a logic read command (No in step 148), the memory operation is continued without reading the logic data (step 150). If the command is a logic read command (Yes in step 148), the prefetched logic data is selected at the falling edge of the eighth system clock SCK, and the pad serial output circuit 46 controlled by the system clock SCK. (Step 149).

  Advantageously, one of the logic data, SR1 data, and SR2 data is prefetched at the fourth clock, so that even if multiplexing is performed in logic 54, the selected data is still long enough. And the multiplexer 116 of the pad serial output circuit 46 is processed to be usable. Advantageously, the logic data is multiplexed in the multiplexer 116 of the pad serial output circuit 46, and the multiplexer 116 is provided directly to the output driver 118, thus avoiding signal lines and other transmission and gate delays. Can do. Advantageously, since the multiplexer 116 and the pad serial output circuit 46 of the output driver 118 are controlled by the system clock SCK, delay of the clock buffer can be avoided. Advantageously, the decoding ambiguity is resolved at the rising edge of the system clock SCK of the combinational logic 110 in the pad serial output circuit 46, so that it is prefetched in the logic read command unless the command is parsed as a logic read command. No data is selected as input to the output driver 118.

  FIG. 14 is a flowchart 160 schematically showing a logic data reading operation using 7-bit command predecoding. The system clock SCK is buffered by the pad serial output circuit 46, and the buffered clock signal CLK is provided to the logic 54 and the data register 52 (step 161). The seven MSBs of the incoming command are controlled by the seven clock signals CLK, and these seven MSBs are predecoded by the logic 54 to generate a precommand signal (step 162), and then the precommand signal is sent to the pad serial output circuit 46. (Step 163). In addition, logic data (for example, signal JEDEC or status register status data SR1 or SR2) is prefetched in logic 54 based on which logic read command among the seven bits is predecoded (step 164). The logic data is provided to the pad serial output circuit 46 (step 165). The pre-command signal is combined with the LSB (the rising edge of the eighth system clock SCK) used for the high-speed command analysis in the pad serial output circuit 46 to resolve the ambiguity of the pre-decode command (step 166). If the command is not a logic read command (No in step 167), the memory operation is continued without reading logic data (step 169). If the command is a logic read command (Yes in step 167), the prefetched logic data is selected at the falling edge of the eighth system clock SCK, and the pad serial output circuit 46 controlled by the system clock SCK. (Step 168).

  The advantages included in the description of the invention and its applications are for illustrative purposes only and do not limit the invention, so the protection scope of the invention is based on the limitations of the claims. The embodiments disclosed herein can be changed and modified. If the person has ordinary knowledge in the technical field to which the present invention belongs, after reading this specification and the like, each component of these embodiments will be described. The actual substitution and equivalent effects can be clearly understood. Unless specifically limited, the specific numerical values shown here are only used for explanation, and can be changed as necessary. Each time submitted in the present invention is not an exact time unless specifically stated otherwise, and may vary depending on circuit placement, signal line impedance, and other actual design factors known in the art. is there. Each numerical value in a range referred to includes all numerical values within that range. Within the scope of the present invention, the embodiments disclosed herein are capable of these and other changes and modifications, including the replacement of each component of these embodiments and equivalent effects.

2, 109 Main array sense amplifier 4, 25, 107 Register 10, 48, 134 Input pad circuit 12, 54, 124 Logic 14, 52, 122 Data register 16, 46, 130, 131, 132, 133 Pad serial output circuit 24 , 102, 108, 110 Combination logic 26, 104, 116 Multiplexer 32, 112, 114 D-type flip-flop 34, 118 Output driver 40 Write control logic 42 Status register 50, 120 Command and control logic 56 High voltage generator 58 Page address latch And counter 60 byte address latch and counter 62 safety register 64 row decode circuit 641 write protect logic 66 flash memory cell array 68 column decode circuit 81 32 sense amplifier blocks 682 256-byte page buffer 100 4-bit predecoder 106 7-bit predecoder 140, 160 Flowchart CLK Clock signal CLK1, CLK ′ Buffered clock input pin CS Chip select input pin D, SET, SET1 'input terminal IO0, IO1, IO2, IO3 Input / output signal line OE Output enable signal PRECMD <1: 0> Pre-command signal Q Output terminal SI Serial input SDOUT / Serial data output signal SCK System clock SCK' System clock input pin SELECT <1: 0> selection signal

Claims (12)

A flash memory device capable of outputting logic data in response to a set of logic read commands,
An external signal input terminal,
An addressable flash memory cell array;
A data register connected to the addressable flash memory cell array for receiving and storing array data from the addressable flash memory cell array;
Multiple registers for storing logic data;
When the first partial arrangement of the most significant bits of the command connected to the external signal input terminal and received by the external signal input terminal is the predicted specific logic data read command, the plurality of logic data read commands Pre-fetch logic for prefetching logic data from one of the plurality of registers based on a particular one of the plurality of registers;
When the second partial arrangement of the most significant bits of the command connected to the external signal input terminal and received by the external signal input terminal is any one of the predicted logic data read commands Command and control logic circuitry, including output control logic to generate a predicted logic read command signal;
Connected to the data register, the prefetch logic, the output control logic, and the external signal input terminal, and receives the predicted logic read command signal and a command of a portion other than the first partial array and the second partial array And a pad output circuit for selecting and outputting logic data from the prefetch logic when an arbitrary one of the plurality of logic data read commands is analyzed. The external signal input terminal is disposed in a serial peripheral interface (SPI) protocol and includes a serial input signal line,
The flash memory device according to claim 1, wherein the pad output circuit is disposed in the serial peripheral interface protocol and includes a serial data output line. The external signal input terminals are arranged in a Quad Peripheral Interface (QPI) protocol, and include a first serial input / output signal line, a second serial input / output signal line, and a third serial input / output. Including a signal line and a fourth serial input / output signal line;
The pad output circuit is disposed in the quad peripheral interface protocol, and the first and first bit pad output circuits connected to the first serial input / output signal line, the second serial input / output signal A second and 1-bit pad output circuit connected to the line, a third and 1-bit pad output circuit connected to the third serial input / output signal line, and a second connected to the fourth serial input / output signal line 2. The flash memory device according to claim 1, further comprising a 4.1 bit pad output circuit.   The flash memory device according to claim 1, wherein the most significant bit of the first and second partial arrays is 7 bits. The external signal input terminal is disposed in a serial peripheral interface protocol and includes a serial input signal line,
5. The flash memory device according to claim 4, wherein the pad output circuit is disposed in the serial peripheral interface protocol and includes a serial data output line. The first partial array of most significant bits is 4 bits;
The flash memory device according to claim 1, wherein the second partial array of the most significant bits is 7 bits. The external signal input terminal is arranged in the quad peripheral interface protocol, and the first serial input / output signal line, the second serial input / output signal line, the third serial input / output signal line, and the fourth serial Including input / output signal lines,
The pad output circuit is disposed in the quad peripheral interface protocol, and the first and first bit pad output circuits connected to the first serial input / output signal line, the second serial input / output signal A second and 1-bit pad output circuit connected to the line, a third and 1-bit pad output circuit connected to the third serial input / output signal line, and a second connected to the fourth serial input / output signal line 7. The flash memory device according to claim 6, further comprising a 4.1 bit pad output circuit. A system clock input signal line connected to the pad output circuit;
The flash memory device of claim 1, further comprising: an input pad circuit connected to the system clock input signal line for providing a buffered clock signal to the prefetch logic, the output control logic, and the data register. . A method of operating a memory device for providing logic data to an application program in response to a logic read command having a flash memory cell array and having a predetermined number of command bits,
Receiving a bit array of commands having a number of bits less than a predetermined number of command bits, wherein the received plurality of bit arrays are a plurality of most significant bits of the command;
Pre-decoding the received bit sequence in the logic circuit of the memory device to determine whether the received bit sequence matches the bit sequence of the corresponding logic read command;
Completing the decoding of the remaining bits of the command in a pad output circuit to determine if the adaptation of the predecoding step correctly predicted the logic read command;
Outputting logic data based on the logic read command. A method of operating a memory device. A method of operating a memory device for providing logic data to an application program in response to a logic read command having a flash memory cell array and having a predetermined number of command bits,
Receiving a first bit arrangement of a command having a number of bits less than a predetermined number of command bits, wherein the plurality of received first bit arrangements are a plurality of most significant bits of the command;
Predecoding the received first bit array in a logic circuit of the memory device to determine whether the received first bit array is compatible with a corresponding logic read command bit array;
Prefetching logic data based on the logic read command adapted in the predecoding step;
A second bit array of commands having a number of bits less than a predetermined number of command bits but greater than the first bit array is received, and the plurality of received second bit arrays includes a plurality of second bits of the command. The upper bit,
Predecoding the received second bit array in the logic circuit of the memory device to determine whether the received second bit array is compatible with a corresponding logic read command bit array;
Completing the decoding of the remaining bits of the command in a pad output circuit to determine whether the adaptation of the pre-decoding step of the second array correctly predicted the logic read command;
Outputting the prefetched logic data in the prefetching step. Operation of the memory device according to prior Symbol second bit sequence, according to claim 10 which is 7 most significant bits of the command. The first bit array is the four most significant bits of the command;
The method of claim 10, wherein the second bit array is the seven most significant bits of the command.

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