KR20090055199A - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided to extract information required for parity bit generation in response to a continuous decision signal or data masking information, thereby preventing a writing error during continuous writing actions. A memory cell array(201) stores data and parity data. A continuous writing decider(280) decides on identity of a column address in case of a continuous inputting action of a writing command, and generates a continuous decision signal. A parity generator(270) controls generation and output of the current parity data by using previous data and change data in response to the continuous decision signal. The parity generator controls generation and output of the current parity data in response to the continuous decision signal and data masking information.

Description

Semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of preventing a write error when successive write operations are performed at the same column address.

A memory device is a device that stores data by using memory cells including one transistor and one capacitor.

The memory device refers to a memory cell array device, and includes a memory device and includes all peripheral devices that are provided to read and write data stored in the memory device. Is referred to as a semiconductor device.

In a semiconductor device using an ECC scheme (Error Correcting Code scheme), the memory cell array device includes normal data storage cells and parity data storage cells. Normal data storage cells store general data, and parity data storage cells store parity data having information on whether an error of normal data occurs.

In the semiconductor device described above, data masking is used to change data stored in some memory cells and maintain data of the remaining memory cells. Data masking refers to an operation of masking a part of memory cells to prevent rewriting of new data (preserving existing data), and rewriting new data in the remaining part so that the existing data is changed.

In this data masking operation, it is important to change the existing parity data by newly storing changed data and generating parity data reflecting the changed data. If some normal data change, parity data generation, and rewrite of the generated parity data cannot be performed smoothly, a data storage error occurs. Occurrence of such a data storage error may cause a problem in that the user may not be able to store data that he / she wants and may not use in a later reading step.

Therefore, in the semiconductor device including the memory cell array device, it is of paramount importance to prevent data writing and reading errors.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device capable of preventing a write error when successive write operations are performed at the same column address.

A semiconductor device according to an embodiment of the present invention is a memory device that reads previous data and writes and stores current parity data including change data and parity information of the change data. And a parity generating unit.

The memory cell array stores data and parity data.

When the write command is continuously input, the continuous write determiner determines whether the column addresses are the same and generates a continuous decision signal.

The parity generator adjusts generation and output of current parity data using the previous data, the change data, and the previous parity data in response to the continuous determination signal.

Preferably, the parity generating unit receives data masking information, and controls generation of the current parity data and output of the current parity data to the memory cell array in response to the continuous determination signal and the data masking information.

Preferably, the parity generating unit extracts data necessary for generating the current parity data from the previous parity data and the normal data in response to the data masking information.

Preferably, when the continuous write command is input and the corresponding column addresses are the same, the continuous write determination unit outputs the continuous determination signal at an activation level. The parity generator operates when the continuous determination signal is output at the activation level.

Preferably, the parity generator includes a delay unit, a selector, and a parity bit generator. The delay unit receives the change data and delays the change data by a first delay time to output delay change data. The selection unit receives the delay change data, the change data, and the previous data stored in the memory cell array, and extracts information necessary for generating the current parity data in response to the continuous determination signal and the data masking information. The parity bit generator generates the current parity data using the information output from the selector.

The semiconductor device may further include a compensation delay unit configured to receive the change data, delay the predetermined time, and output the change data to the memory cell array. The compensation delay unit has a delay time as long as the time required to generate the current parity data of the parity generator.

Preferably, the continuous write determination unit includes a write command delay unit and a comparison unit. The write command delay unit receives a write command and delays the write command by a command input period to output the write command. The comparator receives the output signal of the write command delay unit and the write command, and outputs the continuous determination signal at the activation level when the input signals are all at the activation level.

Preferably, the first comparator consists of an exclusive logic sum gate.

Preferably, the second comparator consists of a logic sum gate.

The semiconductor device according to an exemplary embodiment of the present invention can prevent write errors and increase write performance accordingly by determining whether the address is the same as successive write command receptions and controlling parity accordingly.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a diagram for describing a data masking operation of a memory cell array to which an ECC scheme is applied.

Referring to FIG. 1, a portion of a memory cell array 100 that performs data masking operations in units of bytes using 8 bits as 1 byte is illustrated.

In the data using an ECC scheme (Error Correcting Code scheme), some data (normal data) is the data information that the user wants to store, and some data (parity data) is information on whether or not an error of the normal data described above occurs. .

The ECC scheme uses a hamming code and stores data in code units of (m, n). Here, m is the sum of the number of bits of normal data and the number of bits of parity data, and n is normal data minus the number of bits of parity data. In general, Hamming codes have units of (12, 8), (38, 32), (71, 64), and the like.

The above-described general Hamming code and ECC scheme are obvious to those of ordinary skill in the art, and thus detailed descriptions thereof will be omitted.

Referring to FIG. 1, a portion of a memory cell array that stores data according to a Hamming code having units of (38, 32) is shown by way of example.

Part 110 is a part in which normal data is stored, and part 120 is a part in which parity data is stored. Normal data has 8 bits stored in units of 1 byte. As described above, the normal data 110 indicates data to be stored by the user, and the parity data 120 indicates data having an error occurrence information and error related information of the normal data 110.

In the data according to the (38, 32) hamming code, (masking is performed in units of 1 byte. For example, if data masking is performed from LSB to 1 byte, 107 parts of data are masked. The data of parts 103, 105 are changed, and part 107 is maintained, and the parity data part 120 should be newly generated and stored to reflect the changed data parts 101, 103, 105.

First, data to be newly stored is read in portions 101, 103, and 105 to be changed, and changed parity data is generated using data to be newly stored and existing data (masked portions) to be retained. Then, the newly stored data and the changed parity data are rewritten. This operation is called Read-Modify-Write (RMW).

Hereinafter, the configuration and operation of the semiconductor device according to an embodiment of the present invention and the above-described data masking operation will be described.

2 is a view showing a semiconductor device according to the present invention.

2, the semiconductor device 200 according to the present invention includes a memory cell array 201, a parity generator 270, and a continuous write determiner 280.

The memory cell array 201 stores normal data (hereinafter referred to as 'data') and parity data.

The memory cell array 201 includes a plurality of memory cells including 1T 1C (one transistor one capacitor), a bit line sense amplifier (BLSA) for sensing bit lines, a global input / output line (GI, GO) of data, Global input / output lines GIP and GOp of parity data, local input / output lines LI and LO of data, and local input / output lines LIp and LOp of parity data are provided.

Data read from an activated memory cell in response to a row address and a column address is output through a local output line LO. Then, the data is transferred to the outside of the memory cell array 201 through the output buffer 231 through the global output line GO.

The continuous write determination unit 280 generates a continuous determination signal cons depending on whether the write command CMD_WR is continuously input and the column address Addr_col is the same. Specifically, when the write command is continuously input and the column addresses are the same, the continuous determination signal cons is output at the activation level. Here, the activation level is a level of a signal that causes the parity generation unit to perform the parity generation operation to be described below. The illustrated D_cons signal is a signal output at the activation level when the column addresses are the same. The CMDs signal may be various commands. The continuous write determiner 280 generates a signal output at an activation level when the write commands CMD_WR are continuously input to the input commands.

A detailed description of the continuous write determination unit 280 will be described with reference to FIG. 4 below.

The parity generator 270 adjusts generation and output of current parity data by using previous data and change data in response to the continuous determination signal cons.

Here, the previous data means data stored in the memory cell array. In FIG. 2, the previous data is an FDIOA signal stored through the global output line GO. The change data refers to data to be newly written except for the masked portion (107 in FIG. 1). The change data is shown as WD (n) and is input to the compensation delay unit 260 and the parity generator 270.

In addition, the parity generator 270 receives the data masking information DM and operates accordingly. Here, the data masking information DM is a signal having information regarding which part of data is to be masked (held). The parity generator 270 receives the data masking information DM, and thus extracts data necessary for parity generation from previous data and change data.

The parity generating unit 270 extracts the parity data D_parity by extracting a portion necessary for parity generation from the previous data and change data which have been received in response to the continuous determination signal cons and the data masking information DM as described above. )

The newly generated parity data D_parity is stored in the parity data storage cells 205 through the global input line GIP of the parity data and the local input line LIp of the parity data.

In addition, the memory device 200 may further include a compensation delay unit 260 or an address storage and distribution unit 290.

The compensation delay unit 260 receives the change data WD (n) and delays the change data WD (n) for a predetermined time and outputs the change data WD (n) to the memory cell array 201. The 'scheduled time' is equal to the time required for the parity generator to generate the changed parity data in generating the parity data. That is, the 'scheduled time' refers to the new parity data reflecting the change data from the time when all the signals (cons, DM, WD (n), and FDIO) necessary for parity generation are applied to the parity generator 270. D_parity) is the time until the output point.

The compensation delay unit 260 outputs data to be newly stored in the portion 203 in which normal data of the memory cell array 201 is stored, so as to match an output time point with the newly generated parity data D_parity. It is provided.

The address store and compare unit < RTI ID = 0.0 > (290) < / RTI > The column decoder (Col. DEC: Column Decoder) 253 and the row decoder (Row DEC: Row Decoder) 251 serves to activate the designated cell in response to the column address (Addr_col) and the row address (Addr_row). . Configuration and role operations of the address storage and distribution unit 290, the column decoder 253, and the row decoder 251 are obvious in the art, and thus detailed descriptions thereof will be omitted.

3 is a diagram illustrating in detail the parity generator of FIG. 1.

Referring to FIG. 3, the parity generator 270 includes a delay unit 310, a selector 315, and a parity bit generator 320.

The delay unit 310 receives the change data WD (n) and delays the change data WD (n) by a first delay time to output the delay change data WD (n-1). Here, 'n' represents the current state, and 'n-1' represents one cycle before the state.

The selector 315 operates in response to the continuous determination signal cons and the data masking information DM. The selector 315 receives delay change data WD (n-1), the change data WD (n), or the previous data FDIOA stored in the memory cell array, and receives the continuous determination signal cons. And information necessary for generating the current parity data in response to the data masking information DM, where the DM (n-1) signal is data masking information according to the previous write command signal, and DM (n) is present. It becomes data masking information according to the write command signal.

The parity bit generator 320 generates and outputs current parity data D_parity using the information output from the selector 315. Parity bit generation occurs according to the code operation method in hamming code generation.

First, when the write command CMD_WR is input for the first time, the write command is not input continuously. Consecutive input means a case where the write command is continuously applied two or more times. Therefore, even when the column addresses are the same, when the write command CMD_WR is input for the first time, the continuous determination signal cons is output at an inactive level. Then, only the previous data FDIO and change data WD (n) are needed, and the delay change data WD (n-1) is not needed. Only data masking information DM (n) is also required. The selector 315 extracts data held in the previous data FDIO and data of the unmasked portion of the change data WD (n) using the data masking information DM. The extracted data is output to the parity bit generator 320.

When the write command CMD_WR is input continuously and has the same column address, the continuous determination signal cons is output at the activation level. If there is no part to be masked by the data masking information DM, the selector 315 selects and extracts only the change data WD (n) and outputs the parity bit generator 320 to the parity bit generator 320. Since the parity bit generator 320 is not masked, the parity bit generator 320 performs the parity bit generation operation using only the change data WD (n).

When the write command CMD_WR is input continuously and has the same column address, the continuous determination signal cons is output at the activation level. The case where there is a part currently masked by the current data masking information DM (n) is as follows. The masked portion (the retained portion) is extracted from the previous change data WD (n-1), and the non-masked portion is extracted from the current change data WD (n).

Regardless of the data masking information DM, the change data WD (n) should be selected in any case. In addition, whether the WD (n-1) and FDIOA signals are selected depends on a combination of logic states of the above-described control signals cons, DM (n-1), and DM (n). Can be controlled programmatically.

For example, whether the WD (n-1), FDIOA, or WD (n) signals are selected is determined by Equation 1, which is the following logical operation expression.

[Equation 1]

Here, the '*' symbol represents an AND operation, the '+' symbol represents an OR operation, and the 'XOR' symbol represents an exclusive logical sum operation. 'always' indicates that it is always selected and entered. The FDIO signal and the FDIOA signal will be the same.

As described above, the parity generation unit 270 of the present application extracts information necessary for generating the current parity bit in response to the continuous determination signal cons or data masking information DM, thereby having a write command having the same column address. It is possible to prevent writing errors that occur when inputted continuously.

4 is a diagram illustrating in detail the continuous write determining unit of FIG. 1.

Referring to FIG. 4, the write determination unit 280 includes a write command delay unit 405, a first comparison unit 401, and a second comparison unit 411.

The write command delay unit 405 receives a write command CMD_WR, delays it by a command input period, and outputs a delayed write command signal CMD_WR (n-1). Here, the command input period means a time interval between the input of one write command and the input of the next write command.

The first comparator 401 receives the delayed write command signal CMD_WR (n-1) and the current write command signal CMD_WR (n), and outputs the activated level if both input signals have an activation level. Here, the activation level refers to the logic level output when the write command is continuously input.

The first comparator 401 may be formed of an exclusive logical sum gate (XOR). The activation level at this time is a logic high level.

If the output signal of the first comparator 401 is input at the activation level and the consecutive column addresses are the same column address signal SC_addr, the second comparator 411 outputs the continuous determination signal cons at the activation level. do. Preferably, the second comparator 411 may be an AND gate. In addition, the activation level at this time is a logic high level.

5 is a timing diagram illustrating signals input to and output from the semiconductor device of FIG. 1.

Referring to FIG. 5, the clock signal CLK is continuously applied. Signal 501 represents a clock signal CLK, and signal 502 represents an inverted signal of the clock signal CLK. Signals input and output to the semiconductor device 200 are input or output in synchronization with the clock signal CLK.

The write commands CMD_WRs 505 and 506 are sequentially input.

'NOP' stands for 'no operation', meaning that no operation is taking place.

The column addresses Addr corresponding to the write command CMD_WR are the same column addresses CA0 511 and CA0 512.

Since new data must be written, change data (WD) 521, 522, 523, 524 to be written is output. In addition, masking information (DM) 526, 527, 528, and 529 necessary for data masking are output.

The read column selection line RCSL is enabled at time t3. The read column selection line RCSL is enabled from a time point t3 to a time point t4.

Here, when the read column select line RCSL is enabled, previous data stored in the memory cell array 201 starts to be output.

The LO signal 530 refers to a signal output to the LO signal lines (FIGS. 2 and 211) and becomes previous data stored in the memory cell array 201. Data output through the LO signal line 211 is transmitted again through the GO signal lines (FIGS. 2 and 221), and this signal is referred to as FDIO.

The FDIOA signal 540 is a data signal stored in the memory cell array 201, which is a core of the semiconductor device, and refers to data output through the output buffers (FIGS. 2 and 231).

DINB refers to change data WD input to the parity generator 270.

The DMP becomes data masking information DM input to the parity generator 270.

M_p means parity data 561 and 562 newly generated by reflecting the change data.

The parity generator 270 generates parity data 561 and 562 reflecting the change data by using the FDIOA, DINB, or DMP signal.

The write column select line WCSL is activated again. The write column select line WCSL is activated from time t7 to time t8.

When the write column select line WCSL is activated, the parity data and the change data 563 and 564 output from the parity generator 270 are input to the memory cell array 201 through the local signal input line LI. Writing starts from t13.

The first parity data 561 is generated by properly reflecting the previous data and the changed data. That is, error-free parity data 561 is generated.

M_p (old) and LI (old) represent new parity data reflecting the changed data and a signal input to the local input signal line LI in the conventional semiconductor device (not shown), respectively.

The parity data 572 according to the second write command output from the conventional semiconductor device (not shown) becomes invalid data. In parity data generation, parity data is generated by reading data stored in a previous memory cell array. However, before the first generated parity data 571 is rewritten, data stored in the previous memory cell array is read. That is, the parity data 572 according to the second inputted write command 506 is generated without reflecting the first generated parity data 571 and the changed data.

Therefore, parity data generated after the first generated parity data becomes invalid parity data, and data (change data and parity data) stored in the memory cell array also become error data. will be.

In contrast, in the present application, since the parity generation is controlled according to the continuous determination signal cons output to the continuous writing determination unit 280, generation of the invalid parity data described above is prevented.

Therefore, in the semiconductor device 200 according to the present invention, the parity data 562 outputted later becomes valid parity data, and the data 564 transmitted on the LI line is also valid data.

That is, the semiconductor device 200 according to the present invention has an effect of preventing generation and writing errors of parity data.

 As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, these terms are only used for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a diagram for describing a data masking operation of a memory cell array to which an ECC scheme is applied.

2 is a view showing a semiconductor device according to the present invention.

3 is a diagram illustrating in detail the parity generator of FIG. 1.

4 is a diagram illustrating in detail the continuous write determining unit of FIG. 1.

5 is a timing diagram illustrating signals input to and output from the semiconductor device of FIG. 1.

Claims (9)

A memory device for reading previous data and writing and storing change data and current parity data reflecting the change data, the memory device comprising: A memory cell array for storing data and parity data; A continuous write determination unit for determining whether the column addresses are the same and generating a continuous determination signal when the write commands are continuously input; And And a parity generator configured to adjust generation and output of current parity data using the previous data and the change data in response to the continuous determination signal. The apparatus of claim 1, wherein the parity generator And receiving data masking information and controlling generation of the current parity data and outputting of the current parity data to the memory cell array in response to the continuous determination signal and the data masking information. The apparatus of claim 2, wherein the parity generator And in response to the data masking information, data necessary for generating the current parity data from the previous data and the change data. The method of claim 1, The continuous write determination unit If a continuous write command is input and corresponding column addresses are the same, the continuous determination signal is output at an activation level, The parity generator And operate when the continuous determination signal is output at an activation level. The apparatus of claim 3, wherein the parity generator A delay unit receiving the change data and delaying the change data by a first delay time to output delay change data; A selection unit configured to receive the delay change data, the change data, or the previous data, and extract information necessary for generating the current parity data in response to the continuous determination signal and the data masking information; And And a parity bit generator for generating the current parity data by using the information output from the selector. The method of claim 5, The semiconductor device And a compensation delay unit configured to receive the change data, delay the predetermined time, and output the delayed data to the memory cell array. The compensation delay unit And a delay time as long as the time required to generate the current parity data. The method of claim 4, wherein the continuous write determination unit A write command delay unit which receives the write command and outputs the delayed command by a command input period; A first comparing unit receiving the output signal of the write command delay unit and the write command and outputting the continuous determination signal at an activation level when the input signals are all at an activation level; And And a second comparator for outputting a continuous determination signal at an activation level when the first comparator output signal is applied at an activation level and the same column address is applied. The method of claim 7, wherein the first comparison unit A semiconductor device comprising an exclusive logic sum gate. The method of claim 7, wherein the second comparison unit A semiconductor device comprising a logic sum gate.

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