KR20170128057A - Memory device comprising parity error detect circuit - Google Patents

Abstract

A memory device according to an embodiment of the present invention includes a parity check unit and a mask unit. The parity check unit performs a parity check of sampled data according to a strobe signal. The mask unit generates a parity error signal outputted during a time determined according to the burst length of the data based on a parity check result. The strobe signal does not include a post-amble. Accordingly, the present invention can output a parity output signal even if the data strobe signal without the post-amble is received.

Description

A MEMORY DEVICE COMPRISING PARITY ERROR DETECT CIRCUIT,

The present invention relates to semiconductor memory devices, and more particularly to a memory device including a parity error detection circuit.

The memory device can be used as a storage medium for storing information such as a voice of an information device such as a computer, a mobile phone, a smart phone, a PDA, a digital camera, a camcorder, a voice recorder, an MP3 player, a personal digital assistant (PDA), a handheld PC, a game machine, a fax machine, And image data storage media. BACKGROUND OF THE INVENTION As memory devices are used as storage media for various devices, consumer needs for memory devices have diversified.

Therefore, large capacity, high speed, and low power consumption technologies of memory devices are actively researched. As the processing data of devices that support various functions increase, the capacity and speed of memory devices are accelerating. However, as the operation of the memory device becomes faster, the probability of error occurrence in the reception operation of the signals may increase. That is, there is a problem that the stable operation of the memory device is not guaranteed.

To ensure stable operation of a memory device operating at high speed, the memory device may exchange data with the memory controller using a parity scheme. The memory device uses a parity error detection circuit to check whether the data transmitted by the parity method is received without distortion.

It is an object of the present invention to provide a memory device including a parity error detection circuit for performing a parity check in a memory system using a data strobe signal that does not include a post-amble.

A memory device according to an embodiment of the present invention may include a parity check unit and a mask unit. The parity check unit may perform a parity check of the sampled data according to a strobe signal. The mask unit may generate a parity error signal output during a time determined according to a burst length of data based on a parity check result. The strobe signal may not include a post-amble.

A memory device according to another embodiment of the present invention may include an aligner and a parity error detection circuit. The sorter can sample data by a data strobe signal that does not include a post amble. The parity error detection circuit performs a parity check on the data sampled by the aligner and outputs a parity error signal indicating whether a parity error has occurred in the data for a time determined according to the burst length of the data based on the parity check result Lt; / RTI >

The memory device including the parity error detection circuit according to the embodiment of the present invention can output the parity output signal for a time determined according to the burst length even when the data strobe signal without the postamble is provided.

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.
2 is a block diagram illustrating the memory device shown in FIG.
3 is a block diagram illustrating the first DQS aligner shown in FIG.
4 is a block diagram illustrating the first clock arranger shown in FIG.
FIG. 5 is a block diagram showing the parity error detection unit shown in FIG. 2. FIG.
6 is a circuit diagram showing the parity check unit shown in FIG.
7 is a block diagram illustrating the second parity latency unit shown in FIG.
8 is a block diagram showing the mask signal generator shown in FIG.
9 is a block diagram showing the error signal generator shown in FIG.
10 is a timing diagram showing signals generated according to the operation of the memory system of FIG.
11 is a timing chart showing a signal generated when the parity error detection unit shown in FIG. 1 operates.
12 is a block diagram showing a user system to which a memory device according to an embodiment of the present invention is applied.

In the following, embodiments of the present invention will be described in detail and in detail so that those skilled in the art can easily carry out the present invention.

1 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention. Referring to FIG. 1, a memory system 1000 may include a host 1100 and a memory device 1200. For example, the memory system 1000 may be a single system that includes both the host 1100 and the memory device 1200. Alternatively, the host 1100 and memory device 1200 of the memory system 1000 may be implemented as separate devices.

Host 1100 may be a general purpose processor or a processor circuit or system that includes an application processor. Alternatively, the host 1100 may be a computing device (e.g., a personal computer, a peripheral device, a digital camera, a PDA, a portable media player (PMP), a smartphone, A tablet, a wearable device, or the like).

Host 1100 may perform booting or training for memory device 1200 in certain situations. Through training, the host 1100 can increase the reliability of data and signal exchange with the memory device 1200. For example, the host 1100 can write or read training data (TD) on the memory device 1200 under various conditions to determine an optimum clock timing or a reference level.

The memory device 1200 may store data provided from the host 1100 or data to be provided to the host 1100. The memory device 1200 may be implemented in any storage medium including volatile memory or non-volatile memory. For example, when the memory device 1200 includes volatile memory, the memory device 1200 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor RAM (TRAM) capacitor RAM), or Twin transistor RAM (TTRAM), MRAM, and the like. The present invention can be applied to any storage medium including volatile memory. For example, the memory device 1200 includes an Unbuffered Dual In-Line Memory Module (UDIMM), a Registered DIMM (RDIMM), a Load Reduced DIMM (LRDIMM), a Non Volatile DIMM (NVDIMM) can do.

For example, when the memory device 1200 includes a non-volatile memory, the memory device 1200 may include an EPROM (Electrically Erasable Programmable Read-Only Memory), a Flash memory, a MRAM (MRAM), a conductive bridging RAM (CBRAM), a FeRAM (Ferroelectric RAM), a PRAM (Phase change RAM), a Resistive RAM (RRAM), a Nanotube RRAM, a Polymer RAM RAM: PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory device, or an insulator resistance change memory can do. One or more bits may be stored in the unit cell of the non-volatile memory. The above-mentioned examples are not intended to limit the present invention.

Hereinafter, for convenience of explanation, it is assumed that the memory device 1200 includes a single memory device. However, as described above, it will be easily understood that the present invention can be applied to various storage devices.

The memory device 1200 may communicate with the host 1100. For example, the memory device 1200 may be a universal serial bus (USB), a small computer system interface (SCSI), a PCIe, an M-PCIe (Mobile PCIe), an ATA (Advanced Technology Attachment), a PATA A variety of wire communication protocols such as Serial ATA, Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), Transmission Control Protocol / Internet Protocol (TCP / IP) (Evolution), WiMax, Global System for Mobile communication (GSM), Code Division Multiple Access (CDMA), High Speed Packet Access (HSPA), Bluetooth, Near Field Communication And may communicate with the host 1100 based on one or more of a variety of wireless communication protocols. The above-mentioned examples are not intended to limit the present invention.

The memory device 1200 receives the command / address signals CMD / ADDR synchronized with the clock signal CLK from the host 1100 and reads data (DATA) synchronized with the data strobe signal DQS. An operation and a write operation can be performed. The read operation and the write operation of the memory device 1200 are as follows.

In the case of a read operation, the memory device 1200 receives active command and row address information from the host 1100 along with the clock signal CLK. After the reference time, the memory device 1200 is provided with a column address from the host 1100. Thereafter, after the reference time, the memory device 1200 provides the requested data (DATA) to the host 1100.

In the case of a write operation, first, the memory device 1200 receives an active command and a row address from the host 1100 along with a clock signal (CLK). After the reference time, the memory device 1200 is provided with write command and column address information from the host 1100. Thereafter, the memory device 1200 receives the data (DATA) to be written from the host 1100. The memory device 1200 writes the provided data (DATA) in the memory area of the predetermined address.

The memory device 1200 of the present invention may be provided with data (DATA) and data strobe signal (DQS) from the host 1100. The data strobe signal DQS is a kind of clock signal. The data (DATA) received by the memory device 1200 is synchronized by the data strobe signal DQS. The data strobe signal DQS is provided from the memory device 1200 to the host 1100 when the memory device 1200 provides data (DATA) to the host 1100. The data strobe signal DQS is also provided from the host 1100 to the memory device 1200 when the host 1100 provides the data (DATA) to the memory device 1200.

The data strobe signal DQS may include a preamble and a postamble. The preamble and postamble may be used to indicate whether the memory device 1200 has received an input buffer (not shown), a clock (not shown), or the like of the memory device 1200 before or after the memory device 1200 receives data DATA from the host 1100. [ And a buffer (not shown) to the data strobe signal DQS. It is assumed that the data strobe signal DQS of the present invention does not include a postamble but includes only a preamble.

The memory device 1200 of the present invention may include a parity error detection unit 1220. The parity error detection unit 1220 performs a parity check on the data (DATA) to be written to the memory device 1200 by the write operation. Hereinafter, data (DATA) to be written into the memory device 1200 by a write operation will be referred to as write data (DATA). Write data DATA may be synchronized by the data strobe signal DQS provided from the host 1100 within the memory device 1200. [

The parity error detection unit 1220 receives the parity signal PRT from the host 1100 and can perform an additional parity check on the write data DATA using the parity signal PRT. An additional parity check of the data DATA using the parity signal PRT will be described with reference to FIG. The parity error detection unit 1220 provides the parity check result to the host 1100 as a parity output signal P_out.

The parity error detection unit 1220 performs a parity check on the data (DATA) arranged on the basis of the data strobe signal DQS and outputs the parity check result as a parity output signal P_out. When the data strobe signal DQS includes a postamble, the parity error detection unit 1220 includes a parity check result on the last bit of the data (DATA) because the parity error detection unit 1220 operates synchronously with the data strobe signal DQS The parity output signal P_out may be reset by the postamble of the data strobe signal DQS.

However, as described above, the data strobe signal DQS of the present invention does not include a postamble. Therefore, the parity output signal P_out including the parity check result for the last bit of the data (DATA) is not reset by the data strobe signal DQS. Therefore, the parity output signal P_out including the parity check result of the last bit of the data (DATA) is held without being reset. That is, the parity output signal P_out is not reset at the edge of the data strobe signal DQS. For this reason, the memory device 1200 may not comply with the communication protocol of the memory system 1000 defined by Joint Electron Device Engineering Council (JEDEC) standards.

The parity error detection unit 1220 of the present invention adjusts the output time of the parity output signal P_out according to the burst length (BL) based on the data strobe signal DQS not including the postamble. Here, the burst length means the number of bits of data (DATA) continuously exchanged between the memory device 1200 and the host 1100.

The parity error detection unit 1220 that adjusts the output time of the parity output signal P_out according to the burst length and the configuration of the memory device 1200 including the parity error detection unit 1220 have been briefly described above. With this configuration, the memory device 1200 can output the parity output signal P_out for a time determined by the burst length BL even when the data strobe signal DQS without the postamble is provided. As a result, the memory device 1200 can comply with the communication protocol of the memory system 1000 defined by Joint Electron Device Engineering Council (JEDEC) standards.

2 is a block diagram illustrating the memory device shown in FIG. The block diagram of Fig. 2 will be described with reference to Fig. 2, memory device 1200 includes a data input driver 1210, first and second DQS aligners 1211 and 1213, first and second clock aligners 1212 and 1214, a parity error detection Unit 1220, a mode register 1230, a clock buffer 1240, a memory cell array 1250, a command / address latch 1260, a command decoder 1270, and a data output driver 1280 .

 When the memory device 1200 performs a write command, the data input driver 1210 receives the write data (DATA) and the data strobe signal (DQS) from the host 1100 through the DQS pad (DQS_p) and the DQ pad (DQ_p) . As described above, the data strobe signal DQS does not include a postamble. The data input driver 1210 outputs the received data DATA and the data strobe signal DQS as internal data DQ_i and internal DQS signal DQS_i, respectively.

The first DQS sorter 1211 arranges the internal data DQ_i into an internal DQS signal DQS_i. That is, the first DQS sorter 1211 samples the internal data DQ_i at the rising and falling edges of the internal DQS signal DQS_i and outputs the internal data DQ_i to the internal DQS And outputs odd data and even data sorted by the signal DQS_i. The odd data means the odd data of the internal data DQ_i and the even data means the even data of the internal data DQ_i.

The first clock aligner 1212 samples and arranges the odd data and even data of the internal data DQ_i by the internal clock signal CLK_i. The first clock aligner 1212 outputs the data sorted by the internal clock signal CLK_i as the auto alignment data D_od and the even alignment data D_ev, respectively. The auto alignment data D_od and the even alignment data D_ev are provided to the parity error detection unit 1220 and the sense amplifier 1251, respectively.

The second DQS aligner 1213 samples and aligns the parity signal PRT provided from the host 1100 via the parity pad PRT_p by the internal DQS signal DQS_i. Although not shown, the memory device 1200 may further include an input driver for receiving the parity signal PRT. The second clock aligner 1214 samples and aligns the parity signal PRT sampled by the internal DQS signal DQS_i by the internal clock signal CLK_i. The second clock aligner 1214 outputs the parity signal PRT aligned by the internal clock signal CLK_i as the internal parity signal PRTi.

The parity error detection unit 1220 performs parity check on the chord alignment data D_od and the even alignment data D_ev using the internal clock signal CLK_i. The parity error detection unit 1220 receives the internal parity signal PRTi and performs an additional parity check on the data DATA using the parity signal PRT.

The parity error detection unit 1220 receives the pulse write command PWY, the parity latency PL and the burst length BL from the command decoder 1270 and the mode register 1230, respectively. The parity error detection unit 1220 generates a mask signal (not shown) for adjusting the time at which the parity output signal P_out is output based on the pulse write command PWY and the burst length BL of the data. By the mask signal (not shown), the output time of the parity output signal P_out is adjusted. The parity error detection unit 1220 adjusts the output timing of the parity output signal P_out according to the parity latency PL.

The mode register 1230 may store information provided from the command decoder 1270. [ For example, the mode register 1230 may receive and store the parity latency PL and the burst length BL from the command decoder 1270. The mode register 1230 may also provide the stored parity latency PL and burst length BL to the parity error detection unit 1220.

The clock buffer 1240 is supplied with the clock signal CLK and the clock bar signal CLKb from the host 1100 through the clock pad CLK_p and the clock bar pad CLKb_p. For example, the clock buffer 1240 may be configured as a differential input buffer. The clock buffer 1240 generates an internal clock signal CLK_i based on the provided clock signal CLK and the clock bar signal CLKb. The generated internal clock signal CLK_i is provided to the parity error detection unit 1220, the first and second clock aligners 1212 and 1214, and the command decoder 1270.

The memory cell array 1250 can provide the stored data to the data output driver 1280 through the sense amplifier 1251. [ Or, in the memory cell array 1250, the od alignment data D_od and the even alignment data D_ev may be stored by the sense amplifier 1251. [ The address of the memory cell in which the data provided from the host 1100 is to be stored may be provided to the memory cell array 1250 through the command / address latch 1260, the row decoder 1252, and the column decoder 1253.

The command / address latch 1260 receives the command CMD and the address ADDR from the host 1100. The command / address latch 1260 provides the received command CMD to the command decoder 1270. In addition, the command / address latch 1260 provides the address of the received memory cell to the row decoder 1252 and the column decoder 1253. The command decoder 1270 is provided with various commands through a command / address latch 1260. The command decoder 1270 provides decoded instructions to components such as a parity error detection unit 1220, a mode register 1230, a row decoder 1252, and a column decoder 1253.

The data output driver 1280 can output the data stored in the memory cell array 1250 to the host 1100 through the DQ pad DQ_p. At this time, the row decoder 1252 and the column decoder 1253 can provide the memory cell array 1250 with the address of the memory cell storing the data to be output. In addition, when the data output driver 1280 outputs data to the host 1100, the data output driver 1280 can provide the data strobe signal DQS to the host 1100 via the DQS pad (DQS_p) .

3 is a block diagram illustrating the first DQS aligner shown in FIG. The block diagram of Fig. 3 will be described with reference to Fig. Referring to FIG. 3, the first DQS aligner 1211 may include first and second flip-flops FF1 and FF2.

The first flip-flop FF1 receives internal data DQ_i as a data input D and receives a data strobe signal DQS as a clock input CK. The first flip-flop FF1 samples the internal data DQ_i by the rising edge of the data strobe signal DQS. The odd-numbered data of the internal data DQ_i is sampled by the rising edge of the data strobe signal DQS, and the first flip-flop FF1 outputs the sampled data as the odd data DD_od.

The second flip-flop FF2 receives the internal data DQ_i as a data input D and the bar signal of the data strobe signal DQS as a clock input CK. The second flip-flop FF2 samples the internal data DQ_i by the polling edge of the data strobe signal DQS. The even-numbered data of the internal data DQ_i is sampled by the polling edge of the data strobe signal DQS and the second flip-flop FF2 outputs the sampled data as the even data DD_ev.

As a result, the first and second flip-flops FF1 and FF2 sample and align the internal data DQ_i by the rising edge and the falling edge of the data strobe signal DQS, respectively. The first and second flip-flops FF1 and FF2 separate the sampled data into odd data DD_od and odd data DD_ev, respectively, and output the separated data.

The second DQS aligner 1213 shown in FIG. 2 may have the same configuration as the first DQS aligner 1211. The second DQS aligner 1213 receives the parity signal PRT from the host 1100 through the parity pad PRT_p and receives the parity signal PRT by the rising edge and the polling edge of the data strobe signal DQS Can be sampled. The second DQS aligner 1213 outputs the sampled signals as odd parity signals (not shown) and even parity signals (not shown), respectively.

4 is a block diagram illustrating the first clock arranger shown in FIG. The block diagram of Fig. 4 will be described with reference to Fig. Referring to FIG. 4, the first clock aligner 1212 may include first and second flip-flops FF1 and FF2.

The first flip-flop FF1 receives the odd data DD_od as a data input D and receives the internal clock signal CLK_i as a clock input CK. The first flip-flop FF1 samples the odd data DD_od by the rising edge of the internal clock signal CLK_i. The first flip-flop FF1 outputs the sampled data as the odd alignment data D_od.

The second flip-flop FF2 receives the even data DD_ev as a data input D and receives the internal clock signal CLK_i as a clock input CK. The second flip-flop FF2 samples the even data DD_ev by the rising edge of the internal clock signal CLK_i. The second flip-flop FF2 outputs the sampled data as even alignment data D_ev.

As a result, the first and second flip-flops FF1 and FF2 sample and arrange the odd data DD_od and even data DD_ev by the rising edge of the internal clock signal CLK_i, respectively, And outputs it as odd alignment data D_od and even alignment data D_ev.

The second clock aligner 1214 shown in FIG. 2 may include the same configuration as the first clock aligner 1212. The second clock aligner 1214 receives the odd parity signal (not shown) and the even parity signal (not shown) from the second DQS aligner 1213 and receives the odd parity A signal (not shown) and an even parity signal (not shown). The second clock aligner 1214 outputs the sampled signals as an ord alignment parity signal (not shown) and an even aligned parity signal (not shown), respectively.

FIG. 5 is a block diagram showing the parity error detection unit shown in FIG. 2. FIG. The block diagram of Fig. 5 will be described with reference to Figs. 1 and 2. Fig. 5, the parity error detection unit 1220 may include a parity check unit 1221, first and second parity latency units 1222 and 1223, and a mask unit 1224. [

The parity check unit 1221 receives the odd alignment data D_od [N: 0] and the even alignment data D_ev [N: 0] from the first clock aligner 1212. Here, the number of bits 'N' depends on the size of the data bus of the memory device 1200. That is, if the memory device 1200 includes a data bus comprised of M DQ pads (DQ_p), the number of bits may be 'M'.

Hereinafter, it is assumed that the number of bits 'N' is 3. Thus, the memory device 1200 includes first through fourth DQ pads DQ_p [3: 0]. The data provided via the first DQ pad DQ_p [0] is supplied to the internal DQS signal DQS_i and the internal clock signal CLK_i via the internal DQS signal D_od [0] and the even alignment data D_ev [0] It is sorted data. Similarly, the odd alignment data D_od [3: 1] and the even alignment data D_ev [3: 1] have the data provided through the second through fourth DQ pads DQ_p [3: The data DQS_i and the internal clock signal CLK_i.

The parity check unit 1221 performs a parity check on the provided data. The parity check unit 1221 outputs the parity check result as the first odd error signal ERR1_od and the first even error signal ERR1_ev, respectively. The configuration of the parity check unit 1221 will be described with reference to FIG.

The first parity latency unit 1222 receives the internal clock signal CLK_i from the clock buffer 1240. The first parity latency unit 1222 delays the first odd error signal ERR1_od and the first even error signal ERR1_ev by a multiple of the period of the internal clock signal CLK_i according to the parity latency PL. The first parity latency unit 1222 outputs the delayed signals as the delayed odd error signal ERRd_od and the delayed one-bit error signal ERRd_ev.

The second parity latency unit 1223 receives the internal clock signal CLK_i from the clock buffer 1240. The second parity latency unit 1223 is also supplied with a decoded pulse write command PWY from the command decoder 1270. [ The second parity latency unit 1223 delays the pulse write command PWY by a multiple of the period of the internal clock signal CLK_i according to the parity latency PL. The second parity latency unit 1223 outputs the delayed command as a delay pulse write command PWYd. The configuration of the second parity latency unit 1223 will be described with reference to Fig.

The mask unit 1224 is provided with a delayed odd error signal ERRd_od, a delayed one-time error signal ERRd_ev, a delayed pulse write command PWYd, an internal clock signal CLK_i, and a burst length BL. The mask unit 1224 generates a parity output signal P_out indicating whether a parity error has occurred in the data based on the provided signals. The mask unit 1224 outputs the parity output signal P_out for a time determined according to the burst length BL.

The mask unit 1224 may include a mask signal generator 1225 and an error signal generator 1226. The mask signal generator 1225 is provided with a delay pulse write command PWYd and a burst length BL. The mask signal generator 1225 adjusts the pulse of the delay pulse write command PWYd according to the burst length BL to generate a mask signal (MASK) signal. The configuration of the mask signal generator 1225 will be described with reference to Fig.

The error signal generator 1226 is provided with a delayed odd error signal ERRd_od, a delayed one-time error signal ERRd_ev, and a mask signal MASK. In addition, the error signal generator 1226 may be further provided with an internal parity signal PRTi. The internal parity signal PRTi may include an odd parity signal PRTi_od and an even parity signal PRTi_ev. The error signal generator 1226 can analyze whether the parity error of the write data DATA is the parity error of the odd data or the parity error of the even data based on the odd parity signal PRTi_od and the even parity signal PRTi_ev .

The error signal generator 1226 performs a parity check on the write data DATA based on the delayed odd error signal ERRd_od, the delayed one error signal ERRd_ev, and the internal parity signal PRTi. The error signal generator 1226 outputs the parity check result as the parity output signal P_out during the active period of the mask signal MASK. The configuration of the error signal generator 1226 will be described with reference to FIG.

6 is a circuit diagram showing the parity check unit shown in FIG. The circuit diagram of Fig. 6 will be described with reference to Figs. 1 and 5. Fig. 6, the parity check unit 1221 may include first through sixth exclusive logic sum logic XOR1 through XOR6.

As described above, the parity check unit 1221 checks the parity of the od alignment data D_od [3: 0] and the even alignment data D_ev [3: 0]. For example, the memory device 1200 may receive data from the host 1100 in an even parity manner. In this case, the auto alignment data D_od [3: 0] will be provided from the host 1100 such that the bits at the same position (hereinafter, referred to as bit strings) include an even number of logic '1'. In addition, the even alignment data D_ev [3: 0] will be provided from the host 1100 such that each bit string includes an even number of logic '1's.

For example, when data is provided from the host 1100 in the even parity method, '1011' is provided to the even alignment data D_ev [0] and '1001' is added to the even alignment data D_ev [ '1100' is provided to the even alignment data D_ev [2], and '1111' is provided to the even alignment data D_ev [3]. In this case, the data of the first bit string of the even alignment data D_ev [3: 0] is '1111'. Since the number of logic '1' is an even number, no parity error occurs. The data of the second and third bit strings of the even alignment data D_ev [3: 0] are '0011' and '1001', respectively. Since the number of logic '1's in the data of the second and third bit strings is an even number, no parity error occurs. However, the data of the fourth bit string of the even alignment data D_ev [3: 0] is' 1101 'and a parity error occurs because the number of logic' 1's in the data in the bit string is odd.

The above-described example describes a case where the memory device 1200 receives data (DATA) from the host 1100 in an even parity manner. The memory device 1200 may receive data (DATA) from the host 1100 in an odd parity manner. In this case, the od alignment data D_od [3: 0] and the even alignment data D_ev [3: 0] will be provided such that bit strings in the same position each include an odd logic '1'. Hereinafter, it is assumed that the memory system 1000 of FIG. 1 exchanges data (DATA) in an even parity manner.

The first, second and fifth excluded logic sum logic XOR1, XOR2, XOR5 checks the parity of the odordinated data D_od [3: 0]. The checked parity result is output as the first odd error signal ERR1_od. The third, fourth and sixth excluded logic sum logic XOR3, XOR4 and XOR6 checks the parity of the even alignment data D_ev [3: 0]. The checked parity result is output as the first even error signal ERR1_ev.

For example, if there is a parity error in the odordination data D_od [3: 0], the first odd error signal ERR1_od will be a logic '1'. Also, if there is a parity error in the even alignment data D_ev [3: 0], the first even error signal ERR1_ev will be a logic '1' output.

On the other hand, when a parity error occurs in the memory array system 1000 using the odd parity method in the od alignment data D_od [3: 0] or in the even alignment data D_ev [3: 0] The signal ERR1_od or the first even error signal ERR1_ev will output an opposite value (for example, 0) when using the even parity method.

7 is a block diagram illustrating the second parity latency unit shown in FIG. The block diagram of Fig. 7 will be described with reference to Fig. Referring to FIG. 7, the second parity latency unit 1223 may include first through fourth multiplexers MUX1 through MUX4 and first through fourth flip-flops FF1 through FF4.

The first multiplexer MUX1 selects one of the output signals of the pulse write command PWY or the second flip-flop FF2 according to the parity latency PL [0]. The output signal of the first multiplexer MUX1 is provided to the first flip-flop FF1. The first flip-flop FF1 samples the output signal of the first multiplexer MUX1 by the internal clock signal CLK_i and outputs the sampled signal as a signal of one period of the internal clock signal CLK_i . The output signal is supplied to the mask signal generator 1225 with a delay pulse write command PWYd.

Similarly, the second multiplexer MUX2 selects one of the output signals of the pulse write command PWY or the third flip-flop FF3 according to the parity latency PL [1] MUX3 selects one of the output signals of the pulse write command PWY or the third flip-flop FF3 according to the parity latency PL [2] and outputs it. The output signal of the second multiplexer MUX2 is provided to the second flip-flop FF2 and the output signal of the third multiplexer MUX3 is provided to the third flip-flop FF3. The second and third flip-flops FF2 and FF3 sample the output signals of the second and third multiplexers MUX2 and MUX3 by the internal clock signal CLK_i and output the sampled signal to the internal clock signal CLK_i ) As a signal having a length of one cycle.

The fourth multiplexer MUX4 selects either the pulse write command PWY or the ground voltage GND according to the parity latency PL [3] and provides it to the fourth flip-flop FF4. The fourth flip-flop FF4 samples the output signal of the fourth multiplexer MUX4 by the internal clock signal CLK_i and outputs the sampled signal as a signal having a length of one cycle of the internal clock signal CLK_i .

When the parity latency PL [0] is activated, the pulse write command PWY is supplied to the first flip-flop FF1 through the first multiplexer MUX1 without passing through the second to fourth flip- ). Thus, the pulse write command PWY is not delayed, but is sampled by the first rising edge of the internal clock signal CLK_i. The sampled pulse write command PWY is converted into a pulse signal having a length of one period of the internal clock signal CLK_i without delay, and the converted signal is output as a delay pulse write command PWYd.

When the parity latency PL [1] is activated, the pulse write command PWY is selected by the second multiplexer MUX2 and provided to the second flip-flop FF2. The pulse write command PWY is converted into a pulse signal having a length of one cycle of the internal clock signal CLK_i by the second flip-flop FF2 and output. The output signal is output as a delay pulse write command PWYd through the first multiplexer MUX1 and the first flip-flop FF1. That is, since the pulse write command PWY passes through the first and second flip-flops FF1 and FF2, it is delayed by one period of the internal clock signal CLK_i and output as the delay pulse write command PWYd.

Similarly, when the parity latency PL [2] is activated, the pulse write command PWY is selected by the third multiplexer MUX3 and provided to the third flip-flop FF3. The pulse signal sampled by the third flip-flop FF3 passes through the second multiplexer MUX2, the second flip-flop FF2, the first multiplexer MUX1, and the first flip- The write command (PWYd) is output. Therefore, since the pulse write command PWY passes through the first to third flip-flops FF1 to FF3, the pulse write command PWY is delayed by two periods of the internal clock signal CLK_i and output as the delay pulse write command PWYd.

Further, when the parity latency PL [3] is activated, the pulse write command PWY is selected by the fourth multiplexer MUX4 and provided to the fourth flip-flop FF4. The pulse signal sampled by the fourth flip-flop FF4 is input to the third multiplexer MUX3, the third flip-flop FF3, the second multiplexer MUX2, the second flip-flop FF2, (MUX1), and the first flip-flop (FF1), as a delay pulse write command PWYd. Therefore, since the pulse write command PWY passes through the first to fourth flip-flops FF1 to FF4, the pulse write command PWY is delayed by three cycles of the internal clock signal CLK_i and output as the delay pulse write command PWYd.

The configuration of the first parity latency unit 1222 is similar to that of the second parity latency unit 1223. The first parity latency unit 1222 receives the first odd error signal ERR1_od and the first even error signal ERR1_ev and outputs the first odd error signal ERR1_od and the first odd error signal ERR1_ev according to the parity latency PL, And delays the error signal ERR1_ev by a multiple of the period of the internal clock signal CLK_i. The first parity latency unit 1222 outputs the delayed signals as the delayed odd error signal ERRd_od and the delayed one-bit error signal ERRd_ev. Those skilled in the art will understand that the first parity latency unit 1222 can be configured with reference to the configuration of the second parity latency unit 1223 shown in FIG.

8 is a block diagram showing the mask signal generator shown in FIG. The block diagram of Fig. 8 will be described with reference to Figs. 2 and 5. Fig. Referring to FIG. 8, the mask signal generator 1225 may include a divider 1225_1, and a multiplexer (MUX).

The divider 1225_1 is supplied with a delay pulse write command PWYd and an internal clock signal CLK_i. The divider 1225_1 converts the delay pulse write command PWYd into a pulse signal having a length twice the cycle of the internal clock signal CLK_i based on the internal clock signal CLK_i and the delay pulse write command PWYd do.

In accordance with the burst length BL, the multiplexer MUX outputs a delay pulse write command PWYd having a pulse of one period of the internal clock signal CLK_i and an internal clock signal CLK_i converted by the divider 1225_1 And outputs one of signals having pulses of two cycles as a mask signal (MASK). For example, when the burst length BL is '2', the multiplexer MUX outputs a delay pulse write command PWYd having a pulse of one period of the internal clock signal CLK_i as a mask signal MASK can do. When the burst length BL is '4', the multiplexer MUX outputs a signal having two pulses of the internal clock signal CLK_i converted by the divider 1225_1 as a mask signal MASK can do.

9 is a block diagram showing the error signal generator shown in FIG. The block diagram of Fig. 9 will be described with reference to Figs. 2 and 5. Fig. Referring to FIG. 9, the error signal generator 1226 may include first and second exclusive logic sum logic (XOR1, XOR2), negative logic sum logic (NOR), and negation logic logic (ND).

The first exclusive logical sum logic XOR1 performs an exclusive logical sum of the delayed odd error signal ERRd_od and the odd parity signal PRTi_od. The second exclusive logical sum logic XOR2 performs an exclusive logical sum of the delayed-on-error signal ERRd_ev and the even parity signal PRTi_ev. As described above, the error signal generator 1226 generates a parity error of the odd data of the data based on the odd parity signal PRTi_od and the even parity signal PRTi_ev, Can be analyzed.

For example, when a parity error of the odd data of the write data (DATA) occurs, the delayed odd error signal ERRd_od can output a logic '1'. The parity output signal P_out outputs a logic '1' by the delayed odd error signal ERRd_od of the logic '1'. However, the host 1100 can not know which of the delayed odd error signal ERRd_od and the delayed one-time error signal ERRd_ev has output logic '1'. In this case, the host 1100 can sequentially provide the odd parity signal PRTi_od of the logic '1' and the even parity signal PRTi_ev of the logic '1' to the error signal generator 1226. The parity output signal P_out will output logic '0' by the odd parity signal PRTi_od of logic '1'. As a result, the host 1100 can recognize that a parity error of the odd data of the write data (DATA) has occurred.

The negative logic sum logic (NOR) performs a negative logic sum of the first and second exclusive logic sum logic (XOR1, XOR2). That is, the negative logic sum logic (NOR) outputs the result of the logical sum of the delayed odd error signal ERRd_od, the odd parity signal PRTi_od, the delayed one-way error signal ERRd_ev and the even parity signal PRTi_ev. As a result, the negative logic sum logic (NOR) outputs a parity check result obtained by additionally performing the parity check result of the write data (DATA) using the parity signal (PRT).

The NAND logic ND performs a negative logical multiplication of the output signal of the negative logic sum logic (NOR) with the mask signal MASK. As a result, the NAND logic ND outputs the inverted signal of the output signal of the negative logic sum logic (NOR) by the pulse width of the mask signal MASK. As described above, the pulse width of the mask signal MASK is adjusted in accordance with the burst length BL. Thus, the NAND logic ND outputs the inverted signal of the output signal of the negative logic sum logic (NOR) by the time determined according to the burst length BL.

10 is a timing diagram showing signals generated according to the operation of the memory system of FIG. The timing chart of Fig. 10 will be described with reference to Figs. 1, 2, and 5. Fig. Referring to FIG. 10, the parity output signal P_out generated based on the data strobe signal DQS not including the postamble maintains the output even after the second data D2 is provided. Here, it is assumed that the burst length BL is '2' and the parity latency PL is '0'.

At time t1, the memory device 1200 receives the write command WR, the clock signals CLK and CLKb, and the preamble signal of the data strobe signal DQS from the host 1100. The command / address latch 1260 samples the write command WR by the clock signals CLK and CLKb. The memory device 1200 performs a write operation by a sampled write command WR. Since the write latency CWL is '1', the first data D1 is provided at time t2, which is a point after one cycle of the clock signal CLK from the time t1.

Then, at time t2, the memory device 1200 receives the first data D1 from the host 1100. [ The first DQS aligner 1211 of the memory device 1200 samples the first data D1 by the rising edge of the data strobe signal DQS and outputs it as the odd data DD_od. Next, at time t3, the memory device 1200 receives the second data D2 from the host 1100. [ The first DQS aligner 1211 of the memory device 1200 samples the second data D2 by the polling edge of the data strobe signal DQS and outputs it as the even data DD_ev.

At time t4, the first clock aligner 1212 of the memory device 1200 samples the odd data DD_od and even data DD_ev at the rising edge of the clock signal CLK, Data D_od and even alignment data D_ev. The parity error detection unit 1220 generates the parity output signal P_out based on the provided odd alignment data D_od and the even alignment data D_ev. In the example of FIG. 10, when the mask unit 1224 of the parity error detection unit does not operate, the parity output signal P_out maintains the same parity error result even after time t5 and outputs it.

11 is a timing chart showing a signal generated when the parity error detection unit shown in FIG. 1 operates. The timing chart of Fig. 11 will be described with reference to Figs. 1, 2, 5, and 10. Fig. 11, the memory device 1200 receives a data strobe signal DQS not including a postamble from the host 1100, as in the example of Fig. In the example of FIG. 11, it is assumed that the burst length BL is '2' and the parity latency PL is '0'.

11, the parity output signal P_out generated on the basis of the data strobe signal DQS not including the postamble in the example of FIG. 11 corresponds to the mask signal MASK generated by the mask unit 1224 ) During one period of the clock signal CLK. The operation of the memory device 1200 at time t1 to t3 is the same as that described with reference to FIG. 10, and a description thereof will be omitted.

At time t4, the parity error detection unit 1220 generates the delay error signal ERRd based on the auto-alignment data D_od and the even alignment data D_ev. As described above, the delay error signal ERRd may include a delayed odd error signal ERRd_od and a delayed one-bit error signal ERRd_ev. The pulse write command PWY is provided to the second parity latency unit 1223, delayed by the second parity latency unit 1223, and output as a delay pulse write command PWYd. However, in the example of FIG. 11, since the parity latency PL is '0', the delay pulse write command PWYd is output at the time t4 without delay.

Next, the mask signal generator 1225 generates the mask signal MASK based on the delay pulse write command PWYd and the burst length BL. In the example of FIG. 11, since the burst length BL is '2', the mask signal MASK includes a pulse having a length of one period of the clock signal CLK. The error signal generator 1226 generates a parity output signal P_out based on the delayed odd error signal ERRd_od and the delayed one error signal ERRd_ev and outputs the parity output signal P_out by the time of the pulse width of the mask signal MASK And outputs a signal P_out. After time t5, the error signal generator 1226 does not output the parity output signal P_out.

As a result, the memory device 1200 of the present invention can output the parity output signal P_out for a time determined by the burst length BL even when the data amble signal DQS without the postamble is provided.

12 is a block diagram showing a user system to which a memory device according to an embodiment of the present invention is applied. 12, the user system 10000 may include an application processor 11000, a memory module 12000, a network module 13000, a storage module 14000, and a user interface 15000. [

The application processor 11000 can drive components, an operating system (OS) included in the user system 10000. For example, the application processor 11000 may include controllers, interfaces, graphics engines, etc. that control the components included in the user system 10000. The application processor 11000 may be provided as a system-on-chip (SoC).

Memory module 12000 may operate as the main memory, operational memory, buffer memory, or cache memory of the user system 10000. The memory module 12000 may be a volatile random access memory such as a DRAM, an SDRAM, a DDR SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, an LPDDR SDARM, an LPDDR3 SDRAM, an LPDDR3 SDRAM, an HBM, or a nonvolatile random access memory such as a PRAM, a ReRAM, . ≪ / RTI >

For example, the controller and memory module 12000 included in the application processor 11000 may be configured with the memory system 1000 of the present invention described with reference to Figs. 1-11. That is, the controller included in the application processor 11000 may correspond to the host 1100 shown in FIG. 1, and the memory module 12000 may include the memory device 1200 shown in FIG. That is, the memory module 12000 includes the parity error detection unit 1220 shown in FIG. 1, and can perform the parity error detection operation by the parity error detection unit 1220. FIG.

The network module 13000 can communicate with external devices. For example, the network module 13000 may be a CDMA (Code Division Multiple Access), a GSM (Global System for Mobile communication), a WCDMA (Wideband CDMA), a CDMA-2000, a Time Division Multiple Access (TDMA) ), Wimax, WLAN, UWB, Bluetooth, WI-DI, and the like. Here, the network module 13000 may be included in the application processor 11000.

The storage module 14000 can store data. For example, the storage module 14000 may store data received from the application processor 11000. Alternatively, the storage module 14000 may send the data stored in the storage module 14000 to the application processor 11000. For example, the storage module 14000 may be a nonvolatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash, a NOR flash, Can be implemented.

The user interface 15000 may include interfaces for inputting data or instructions to the application processor 11000 or for outputting data to an external device. For example, the user interface 15000 may include user input interfaces such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, have. The user interface 15000 may include user output interfaces such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an AMOLED (Active Matrix OLED) display, an LED, a speaker,

The above description is a concrete example for carrying out the present invention. The present invention includes not only the above-described embodiments, but also embodiments that can be simply modified or easily changed. In addition, the present invention includes techniques that can be easily modified by using the above-described embodiments.

Claims (10)

A parity check unit for performing a parity check on the sampled data according to a data strobe signal; And
And a mask unit for generating a parity error signal output during a time determined according to a burst length of the data based on the result of the parity check,
Wherein the data strobe signal does not include a post-amble. The method of claim 1,
Wherein the mask unit comprises:
A mask signal generator for generating a mask signal to be activated for a time determined according to a burst length of the data based on a write command; And
And an error signal generator for generating the parity error signal based on the mask signal and the parity check result. The method of claim 1,
Wherein the mask unit receives a parity signal from a host and additionally performs a parity check on the parity check result based on the parity signal to generate the parity error signal. 4. The method of claim 3,
And a parity latency unit for delaying the parity check result according to the parity latency and providing the result to the mask unit. 4. The method of claim 3,
Wherein the mask unit comprises:
A mask signal generator for generating a mask signal based on the write command, the mask signal including a pulse signal activated for a time determined according to a burst length of the data; And
A parity check result of odd data and an odd parity signal of the parity signal are subjected to an exclusive-OR operation (XOR), a parity check result of even data, and an even parity signal of the parity signal are subjected to an exclusive- And generating an error signal generator for generating the parity error signal based on the mask signal and the output signal of each of the first and second exclusive logical sum logic (XOR) ≪ / RTI > The method of claim 1,
Wherein the mask unit comprises:
A mask signal generator for generating a mask signal to be activated for a time determined according to a burst length of the data based on a write command; And
And an error signal generator for receiving the parity signal from the host and generating the parity error signal based on the parity signal, the mask signal, and the parity check result. An aligner for sampling data by a data strobe signal; And
A parity error signal indicating whether or not a parity error has occurred in the data is output for a time determined according to the burst length of the data based on the parity check result, A parity error detection circuit for generating a parity error,
Wherein the data strobe signal does not include a postamble. 8. The method of claim 7,
Wherein the parity error detection circuit comprises:
A mask signal generator for generating a mask signal to be activated for a time determined according to a burst length of the data based on a write command; And
And an error signal generator for generating the parity error signal based on the mask signal and the parity check result. 9. The method of claim 8,
Wherein the error signal generator receives a parity signal from a host and additionally performs a parity check on the parity check result based on the parity signal to generate the parity error signal. The method according to claim 9,
Wherein the parity error detection circuit comprises:
A first parity latency unit for delaying the write command and providing the write command to the mask signal generator according to a parity latency; And
And a second latency unit for delaying the parity check result according to the parity latency and providing the delayed result to the mask unit,
Wherein the parity signal is delayed according to the parity latency and is provided to the error signal generator.

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