KR20140109206A - Semiconductor Memory Device and System Conducting Parity Check and Operating Method of Semiconductor Memory Device - Google Patents

Abstract

A semiconductor memory device carrying out parity check, a memory system, and a method for operating a semiconductor memory device are disclosed. According to an embodiment of the present invention, the semiconductor memory device comprises a parity check unit which carries out parity check by receiving a command and a parity signal; a command register which receives, delays and prints out the command; a command decoder which receives the command from the command register and prints out internal command according to an outcome of the parity check of the parity check unit; and an information generation unit which creates and prints out information which shows whether a parity error is found on the command according to the parity check result.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor memory device, a memory system, and a semiconductor memory device,

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device, a memory system, and a semiconductor memory device that perform a parity check.

Semiconductor memory devices, which are widely used in high performance electronic systems, are increasing in capacity and speed. As an example of a semiconductor memory device, a DRAM is a volatile memory, and is a memory that determines data by a charge stored in a capacitor.

The semiconductor memory device receives signals such as a command and an address from the memory controller to perform a memory operation. However, as the operation speed of the semiconductor memory device increases, the error occurrence probability increases in the reception operation of the signals, which may cause a problem that the stable operation of the semiconductor memory device is not guaranteed.

The present invention provides a semiconductor memory device, a memory system, and a method of operating a semiconductor memory device that performs a parity check that can operate at high speed and reduce a signal reception error, The purpose.

According to an aspect of the present invention, there is provided a semiconductor memory device including a parity check unit configured to receive a command and a parity signal to perform a parity check, a command receiving a command, A command decoder for receiving the command from the command register and outputting an internal command in accordance with the parity check result from the parity check unit and a parity check unit for determining whether or not a parity error has occurred in the command, And an information generating unit for generating and outputting error information.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a parity check unit for receiving a command and a parity signal to perform a parity check and outputting a parity check result; And a command decoder for decoding the command from the command storage unit and generating an internal command according to a result of the parity check from the delay unit And the delay unit delays the parity check result so that the parity check result is provided to the command decoder in synchronization with the command.

According to another aspect of the present invention, there is provided a semiconductor memory device including: a memory cell array including a plurality of memory cells; a row decoder for driving a row of the memory cell array in response to a row address; A column decoder for driving a column of the memory cell array and a command and chip select signal from the outside and performing a parity check operation on the command by detecting a bit value of the command and the parity signal, And a command control logic for selectively outputting an internal command corresponding to the command when a parity error is not generated according to the result.

According to another aspect of the present invention, there is provided a method of operating a semiconductor memory device including receiving a command and a parity signal, and generating a parity check result by performing a parity check on the command using the parity signal And outputting a result of the parity check to the command decoder; blocking an output of an internal command when a parity error occurs according to the parity check result; and generating a parity error And outputting the generated parity error information to the memory controller.

According to the semiconductor memory device, the memory system, and the operation method of the semiconductor memory device performing the parity check of the embodiment of the present invention, not only can the reception error of various signals be reduced even if the semiconductor memory device operates at high speed, It is possible to prevent the operation from being performed in advance, thereby improving the operational reliability.

1 is a block diagram showing a semiconductor memory device and a memory system according to an embodiment of the present invention.
2 is a block diagram showing an example of operation of the semiconductor memory device of FIG.
3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
4 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention.
5A and 5B are block diagrams showing a semiconductor memory device according to another embodiment of the present invention.
6 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention.
7 is a timing diagram illustrating a parity check operation according to an embodiment of the present invention.
8 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention.
9 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention.
10 and 11 are waveform diagrams showing an example of the internal operation of the semiconductor memory device according to the parity check result according to the embodiment of the present invention.
12 is a circuit diagram illustrating an example of a parity check unit included in a semiconductor memory device according to an embodiment of the present invention.
13A and 13B are diagrams showing examples of waveforms of various signals according to the operation of the parity check unit 2100 of FIG.
14 is a flowchart showing an operation method of a semiconductor memory device according to an embodiment of the present invention.
15 is a flowchart showing an operation method of a semiconductor memory device according to another embodiment of the present invention.
16 is a flowchart illustrating an operation method of a memory controller according to an embodiment of the present invention.
17 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention.
18A, 18B, 18C, and 18D are circuit diagrams showing an example of the configuration of the semiconductor memory device of FIG.
19 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention.
20A and 20B are circuit diagrams showing an embodiment of the structures of the semiconductor memory device shown in FIG.
21 is a circuit diagram showing another embodiment of the command control logic included in the semiconductor memory device.
22 is a block diagram illustrating a memory controller according to an embodiment of the present invention.
23 is a block diagram showing an embodiment of a memory system to which a semiconductor memory device according to an embodiment of the present invention is applied.
24 is a block diagram showing another embodiment of a memory system to which a semiconductor memory device according to an embodiment of the present invention is applied.
25A and 25B are block diagrams showing another embodiment of a memory system to which a semiconductor memory device according to an embodiment of the present invention is applied.
26 is a structural view showing a semiconductor memory device according to still another embodiment of the present invention.
27 is a block diagram showing another embodiment of a memory system to which a semiconductor memory device according to an embodiment of the present invention is applied.
28 is a block diagram illustrating a computing system incorporating a memory system in accordance with an embodiment of the present invention.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

As the operating speed of the semiconductor memory device increases, the error occurrence probability of signals transmitted and received in the memory system may increase. For example, a DRAM (Dynamic Random Access Memory) as a semiconductor memory device is a memory having a finite data retention characteristic and receives a command, an address and a chip selection signal from a memory controller, and performs command decoding and address control To perform the memory operation requested by the memory controller. Stable operation of the semiconductor memory device requires stable transmission and reception of the signals.

1 is a block diagram illustrating a memory system including a semiconductor memory device according to an embodiment of the present invention. 1, the memory system 1000 may include a memory controller 1010 and a semiconductor memory device 1100. The semiconductor memory device 1100 includes a cell array 1110, a parity check unit 1120 A command register 1130, an information generator 1140, and a command decoder 1150. [ In addition, the semiconductor memory device 1100 may further include a multiple purpose register (MPR) 1160. The structure of the semiconductor memory device 1100 shown in FIG. 1 is intended to illustrate the basic operation of a parity check according to an embodiment of the present invention. Other structures for a memory operation such as read / 1100).

The memory controller 1010 provides various signals to the semiconductor memory device 1100 to control the memory operation. For example, the memory controller 1010 provides the clock signal CLK, the chip select signal CS, the command CMD, and the address ADD to the semiconductor memory device 1100, (Data) is transmitted and received between the memory controller 1010 and the semiconductor memory device 1100.

For the parity check operation according to the embodiment of the present invention, the memory controller 1010 may provide a parity signal to the semiconductor memory device 1100. The parity signal may include one or more bits and may also have a bit value according to the logic state of the command CMD and the address ADD. Each of the command CMD and the address ADD may be implemented with a plurality of bits and the bit value of the parity signal parity may be determined according to the bit value of the command CMD and the address ADD. For example, when the number of bits having a logic high in the bit values of the command CMD, the address ADD and the parity signal parity is set to be provided in an even number, the bit constituting the command CMD and the address ADD The parity signal parity may have a logic high value when the number of bits having logic high is odd, whereas the parity signal parity may have a logic high value among the bits constituting the command CMD and the address ADD, The parity signal may have a logic low value. As another embodiment, in the case of performing the parity check only on the command CMD, the bit value of the parity signal parity may be determined according to the bit value of the bits constituting the command CMD, The bit value of the parity signal parity may be determined according to the bit value of the bits constituting the address ADD.

The parity check unit 1120 performs a parity check on at least one of the command CMD and the address ADD using the parity signal received from the memory controller 1010. [ The parity check unit 1120 receives the command CMD and the address ADD and the parity signal parity and outputs the command CMD ) And the address ADD and the parity signal parity to generate a parity check result. The information generating unit 1140 generates parity error information (Info_PEI) indicating the presence or absence of a parity error according to the parity check result, and outputs the parity error information (Info_PEI) to the memory controller 1010.

As a result of the parity check, if a parity error does not occur, an internal command is generated as the command CMD is normally supplied to the command decoder 1150, and a memory operation is performed in response to the internal command. The command CMD may be temporarily stored in the command register 1130 in consideration of the time required for the parity check operation and may be stored in the command register 1130 so as to be synchronized with the timing at which the parity check result is provided to the command decoder 1150 The stored command CMD may be provided to the command decoder 1150. [ The command register 1130 may be implemented by means of a shift register or the like and may store a chip select signal CS provided to the command decoder 1150 or an address ADD provided to a row / column decoder Other storage means for storing data may be further included in the semiconductor memory device 1100.

On the other hand, when a parity error occurs, the generation of an internal command is blocked, thereby preventing an erroneous memory operation from being performed. As the parity check result is provided to the command decoder 1150, the command decoder 1150 can be controlled not to output the internal command. Or the output of the command CMD from the command register 1130 is blocked as the result of the parity check is supplied to the command register 1130. [

The MPR 1160 may include registers for storing various types of information in the semiconductor memory device 1100. For example, the parity check result of the parity check performed according to the embodiment of the present invention may include a command CMD and an address (ADD), and the like. At least some information stored in the MPR 1160 may be provided to the memory controller 1010 in consultation with the memory controller 1010. The memory controller 1010 can receive the information of the command / address (CMD / ADD) in which the error has occurred by accessing the MPR 1160. The memory controller 1010 may perform operations such as detecting an error pattern of a command / address (CMD / ADD) received by the semiconductor memory device 1100 by analyzing the information stored in the MPR 1160 .

On the other hand, the memory controller 1010 can activate the chip select signal CS and output it together with the command CMD when requesting the execution of the actual memory operation. When the chip select signal CS is inactivated, Device 1100 may be in a non-operational state. Accordingly, the parity check unit 1120 can operate when the chip select signal CS is activated. For example, the chip select signal CS is a signal for controlling the enable of the parity check unit 1120 Can be used. Also, when the activated chip select signal CS is provided to the command decoder 1150, the command decoder 1150 can generate an appropriate internal command, thereby generating a chip select signal CS when a parity error occurs, It is possible to prevent an internal command from being generated by blocking the signal provided to the decoder 1150. According to the description, the chip select signal CS may be described as being included in the command CMD. Accordingly, even when the chip selection signal CS is not explicitly shown in the following description, it can be assumed that the chip selection signal CS is included or not included in the command CMD.

2 is a block diagram showing an example of operation of the semiconductor memory device of FIG. 1 and 2, a command / address CMD / ADD and a parity signal parity from the memory controller 1010 are provided to a parity check unit 1120. The parity check unit 1120 receives a command / CMD), an address ADD and a parity signal parity to generate a parity check result Res_CHK.

According to the parity check result (Res_CHK), the information generator 1140 generates parity error information (Info_PEI) and outputs it to the memory controller 1010. The semiconductor memory device 1100 may include a plurality of pins for communicating with the memory controller 1010 and the semiconductor memory device 1200 may include an information pin for outputting parity error information Info_PEI . For example, when no parity error is generated, the information generator 1140 may output inactive parity error information (Info_PEI). On the other hand, when a parity error occurs, the information generator 1140 generates It is possible to output parity error information (Info_PEI). The memory controller 1010 receives parity error information (Info_PEI) and can control the command output for subsequent memory operations according to parity error information (Info_PEI).

Also, the operation of generating the internal command (Int_CMD) of the semiconductor memory device 1100 can be controlled according to the parity check result (Res_CHK). If no parity error is generated, the command decoder 1150 can decode the command CMD to generate and output an internal command Int_CMD. The command CMD may be provided to the command decoder 1150 by a predetermined time delay through the command register 1130 in consideration of the time required for the parity check operation. On the other hand, when a parity error occurs, the command CMD is blocked from being supplied to the command decoder 1150, or the signal received from the command decoder 1150 is blocked so that the internal command Int_CMD Output can be prevented.

3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention. 3, the semiconductor memory device 1200 includes a parity check unit 1220, one or more registers 1231 and 1232, an information generator 1240, a command decoder 1250, a delay unit 1260, One or more buffers 1271, 1272, 1273, and one or more flip-flops 1281, 1282, 1283. One or more registers 1231 and 1232 correspond to a storage unit for storing a chip selection signal and a command, and may include a chip selection signal register 1231 and a command register 1232, for example. The one or more buffers 1271, 1272 and 1273 also include a first buffer 1271 for storing a chip select signal CS, a second buffer 1272 for storing a command CMD and a parity signal parity And a third buffer 1273 for storing the data. The one or more flip-flops 1281, 1282 and 1283 also include a first flip-flop 1281 for storing a chip select signal CS, a second flip-flop 1282 for storing a command CMD, And a third flip-flop 1283 for storing the third flip-flop 1283.

3, buffers, flip-flops, registers, and the like are shown as means for storing the chip select signal CS, the command CMD, and the parity signal. However, the embodiment of the present invention is not limited thereto. (Or a delay operation) using the means. Although the parity check unit 1220 and the delay unit 1260 are illustrated as separate functional blocks, the parity check unit 1220 and the delay unit 1260 may include one functional block (parity check and latency It can also be implemented as a part.

The first buffer 1271 receives and buffers the chip select signal CS and converts the chip select signal CS at the external TTL level into a chip select signal CS at the CMOS level. Similarly, the second and third buffers 1272 and 1273 also convert an external TTL level signal to a CMOS level signal, the second buffer 1272 receives and buffers the command CMD, The buffer 1273 receives and buffers a parity signal (parity).

Each of the first to third flip-flops 1281 to 1283 inputs and outputs a signal in synchronization with the clock signal in the semiconductor memory device 1200. The first flip-flop 1281 outputs the chip selection signal CS from the first buffer 1271 in synchronization with the internal clock signal. The second flip-flop 1282 outputs the command CMD from the second buffer 1272 in synchronization with the internal clock signal and the third flip-flop 1283 outputs the command CMD from the third buffer 1273 And outputs the signal parity in synchronization with the internal clock signal.

The parity check unit 1220 performs a parity check operation on the command CMD synchronized with the internal clock signal. For example, as described above, the bit value of the bits included in the command CMD and the bit of the parity signal parity Value to perform a parity check operation. The parity check unit 1220 may or may not perform the parity check operation in response to the chip select signal CS. The parity check result Res_CHK is provided to the information generating unit 1240. The information generating unit 1240 generates parity error information (Info_PEI) indicating whether a parity error has occurred using the parity check result (Res_CHK) .

On the other hand, the chip select signal CS and the command CMD from the first and second flip-flops 1281 and 1282 may be provided to the chip select signal register 1231 and the command register 1232, respectively. The chip select signal register 1231 and the command register 1232 temporarily store the chip select signal CS and the command CMD to compensate the time delay required for the parity check operation on the command CMD. The delay unit 1260 receives the parity check result Res_CHK from the parity check unit 1220 and outputs a signal ERRB delayed by the result to the command decoder 1250. Accordingly, the chip select signal CS and the command CMD can be provided to the command decoder 1250 in synchronization with the parity check result Res_CHK. The command decoder 1250 generates an internal command Int_CMD by decoding the chip select signal CS and the command CMD or blocks the output of the internal command Int_CMD when a parity error occurs. According to the above-described operation, even if an error occurs in the reception operation of the command CMD as the semiconductor memory device 1200 operates at a high speed, generation of an internal command Int_CMD in which an error exists can be prevented in advance .

4 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention. In the embodiment of FIG. 4, an example is shown in which a parity check operation is performed on the address ADD from the memory controller.

4, the semiconductor memory device 1300 includes a parity check unit 1320, an information generating unit 1340, a command decoder 1350, a delay unit 1360, at least one buffer 1371, 1372, 1373 , 1374), and one or more flip-flops (1381, 1282, 1383, 1384). The semiconductor memory device 1300 may further include an address register 1390 that receives an address ADD / BA / BG provided from the memory controller and outputs an internal address Int_ADD / BA / BG. The cell array (not shown) included in the semiconductor memory device 1300 may include a plurality of banks, and at least two banks may be defined as one bank group. As shown in Fig. 4, it is assumed that the address ADD / BA / BG further includes a bank address BA and a bank group address BG in addition to the address ADD shown in the above-described example.

One or more buffers 1371, 1372, 1373 and 1374 include a first buffer 1371 for storing a chip select signal CS, a second buffer 1372 for storing an address ADD / BA / BG, a parity signal a third buffer 1373 for storing parity and a fourth buffer 1374 for storing the command CMD. In addition, the one or more flip-flops 1381, 1382, and 1383 include a first flip-flop 1381 for storing a chip select signal CS, a second flip-flop 1382 for storing an address ADD / BA / BG, A third flip-flop 1383 for storing a parity signal, and a fourth flip-flop 1384 for storing a command CMD.

The address ADD / BA / BG may include one or more bits in performing a parity check operation on the address ADD / BA / BG, and the bit ADD / BA / The bit value of the parity signal (parity) can be determined according to the value. For example, if the number of bits having logic high among the bits constituting the address ADD / BA / BG is odd, the parity signal parity may have a logic high value and the number of bits having logic high In case of an even number, the parity signal may have a logic low value.

Similar to the above embodiment, the parity check unit 1220 performs a parity check operation on an address ADD / BA / BG synchronized with an internal clock signal, and outputs the address ADD / BA / BG) and a bit value of a parity signal (parity). The parity check result Res_CHK is provided to the information generator 1340. The information generator 1340 generates parity error information (Info_PEI) indicating whether a parity error is generated according to the parity check result (Res_CHK) Output. The parity check result Res_CHK is supplied to the delay unit 1360 and the signal EBBR from the delay unit 1360 is supplied to the command decoder 1350. [ The signal EBBR from the delay unit 1360 may be a signal that is a delayed signal of the parity check result Res_CHK and therefore the signal EBBR from the delay unit 1360 may be referred to as a parity check result EBBR Do. The command decoder 1350 decodes the command CMD according to the parity check result EBBR to generate the internal command Int_CMD or not to generate the internal command Int_CMD.

The internal command Int_CMD is prevented from being generated even if an error occurs in the reception operation of the address ADD / BA / BG as the semiconductor memory device 1300 operates at high speed in accordance with the operation described above, It is possible to prevent the memory operation by the address ADD in which the address exists.

5A and 5B are block diagrams showing a semiconductor memory device according to another embodiment of the present invention. In the embodiment of Figs. 5A and 5B, an example is shown in which a parity check operation is performed on the command CMD and the address ADD from the memory controller.

5A, the semiconductor memory device 1400 includes a parity check unit 1420, one or more registers 1431 and 1432, an information generating unit 1440, a command decoder 1450, a delay unit 1460, One or more buffers 1471, 1472, 1473, 1474, one or more flip-flops 1481, 1482, 1483, 1484 and an address register 1490. The one or more registers 1431 and 1432 may include a chip select signal register 1431 and a command register 1432.

The one or more buffers 1471, 1472, 1473 and 1474 further include a first buffer 1471 for storing a chip selection signal CS, a second buffer 1472 for storing a command CMD, A third buffer 1473 for storing a parity signal and a fourth buffer 1474 for storing a parity signal (parity). The one or more flip-flops 1481, 1482, 1483 and 1484 also include a first flip-flop 1481 for storing the chip select signal CS, a second flip-flop 1482 for storing the command CMD, A third flip-flop 1483 for storing a parity signal ADD and a fourth flip-flop 1484 for storing a parity signal (parity). Although a parity check operation is performed for the address ADD in FIG. 5A, when the semiconductor memory device 1400 has a plurality of banks and a bank group concept is applied as in the above-described embodiment, ADD) may further include a bank address and a bank group address.

The parity check unit 1420 performs a parity check operation on the command CMD and the address ADD synchronized with the internal clock signal and outputs the command CMD and the address ADD, And performs a parity check operation using the bit value of the bits included in the parity bit and the bit value of the parity signal (parity). The result of the parity check (Res_CHK) is provided to the information generator 1440. The information generator 1440 generates parity error information (Info_PEI) indicating whether a parity error has occurred according to the parity check result (Res_CHK) Output. The parity check result ERRB from the delay unit 1460 is also provided to the command decoder 1450. [

The chip select signal CS and the command CMD from the first and second flip-flops 1481 and 1482 may be provided to the chip select signal register 1431 and the command register 1432, respectively, The address ADD from the flip-flop 1483 may be provided to the address register 1490. The chip select signal CS and the command CMD are supplied from the chip select signal register 1431 and the command register 1432 in synchronization with the parity check result ERRB from the delay unit 1460 being supplied to the command decoder 1450. [ Is provided to the command decoder 1450. In accordance with the parity check result Res_CHK, the command decoder 1450 generates and outputs the internal command Int_CMD or blocks the output of the internal command Int_CMD.

Further, the address register 1490 receives the address ADD from the memory controller and generates and outputs the internal address Int_ADD. The address register 1490 can also delay and output the address ADD in order to output the internal address Int_ADD in synchronization with the output timing of the internal command Int_CMD. In addition, the address register 1490 can perform an output operation of the internal address Int_ADD in response to the chip select signal CS. It is possible to prevent the internal command Int_CMD from being generated in advance even if an error occurs in the reception operation of the command CMD and the address ADD as the semiconductor memory device 1400 operates at a high speed in accordance with the above- have.

5B shows an example in which the means for processing the command CMD and the address ADD in the parity check on the command CMD and the address ADD is implemented as one functional block. 5B, the semiconductor memory device 1400a includes a parity check unit 1420a, one or more registers 1431a and 1432a, an information generating unit 1440a, a command / address decoder 1450a, a delay unit 1460a ), One or more buffers 1471a, 1472a, 1473a, and one or more flip-flops 1481a, 1482a, 1483a. The one or more registers 1431a and 1432a may include a chip select signal register 1431a and a command / address register 1432a.

The command / address CMD / ADD from the memory controller is supplied to the parity check unit 1420a via the second buffer 1472a and the second flip-flop 1482a. In addition, the command / address CMD / ADD from the second flip-flop 1482a is provided to the command / address decoder 1450a via the command / address register 1432a. The parity check unit 1420a outputs a parity check result (Res_CHK) for the received command / address CMD / ADD and the parity check result ERRB delayed therefrom is provided to the command / address decoder 1450a In synchronism, the command / address CMD / ADD from the command / address register 1432a is provided to the command / address decoder 1450a.

6 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention. In the embodiment of FIG. 6, an example is shown in which a parity check operation is performed on the command CMD and the address ADD from the memory controller.

6, the semiconductor memory device 1500 includes first and second parity check units 1521 and 1522, an operation unit 1523, one or more registers 1531 and 1532, an information generation unit 1540, The first to fourth buffers 1571, 1572, 1573 and 1574 as one or more buffers, the first to fourth flip-flops 1581, 1582 and 1583 as one or more flip-flops, , 1584 and an address register 1590. [ 6, the same or similar configurations as those of the above-described embodiments are the same as or similar to those of the above-described embodiments, and thus detailed description thereof will be omitted.

The fourth buffer 1474 receives one or more parity signals from the memory controller and receives and stores, for example, a first parity signal parity1 and a second parity signal parity2. For example, the first parity signal parity1 may be a signal for a parity check for the command CMD, and the second parity signal parity2 may be a signal for a parity check for the address ADD. 6, a parity check operation is performed on the address ADD. However, when the semiconductor memory device 1500 includes a plurality of banks and a bank group concept is applied thereto as in the above-described embodiment, The address ADD may further include a bank address and a bank group address.

The command CMD from the second flip flop 1582 and the first parity signal parity1 from the fourth flip flop 1582 can be provided to the first parity check unit 1521. [ The first parity check unit 1521 generates the first parity check result using the command CMD and the first parity signal parity1. The first parity check result can be generated by determining the bit value of the bits constituting the command CMD and the bit value of the parity signal parity as in the above embodiment.

The address ADD from the third flip-flop 1583 and the second parity signal parity2 from the fourth flip-flop 1582 may be provided to the second parity check unit 1522. The second parity check unit 1522 generates a second parity check result using the address ADD and the second parity signal parity2. It is possible to generate the second parity check result by discriminating the bit value of the bits constituting the address ADD and the bit value of the parity signal parity as in the above embodiment.

The first and second parity check results may be provided to the operation unit 1523. The arithmetic operation unit 1523 outputs a parity check result (Res_CHK) indicating whether an error has occurred in at least one of the command CMD and the address ADD by calculating the first and second parity check results. If an error occurs in at least one of the command CMD and the address ADD, the generation of the internal command Int_CMD needs to be blocked, while if there is an error in both the command CMD and the address ADD The memory operation can be performed according to the internal command Int_CMD. Accordingly, when no parity error is generated in both the command CMD and the address ADD, the arithmetic unit 1523 outputs a parity check result (Res_CHK) indicating that no parity error has occurred, When a parity error occurs in at least one of the addresses ADD, the arithmetic unit 1523 outputs a parity check result (Res_CHK) indicating that a parity error has occurred. The parity error information (Info_PEI) is generated in accordance with the parity check result (Res_CHK) from the arithmetic unit 1523. The parity check result RES_CHK is provided to the delay unit 1560 and the parity check result ERRB from the delay unit 1560 is provided to the command decoder 1550.

According to the embodiment, it is possible to prevent the parity check result from appearing normally when two errors are generated in the command CMD and the address ADD. That is, since a separate parity signal is given to the command CMD and the address ADD, a separate parity check operation can be performed for the command CMD and the address ADD. In addition, when a parity error occurs in at least one of the command CMD and the address ADD, erroneous memory operation can be prevented from being performed.

7 is a timing diagram illustrating a parity check operation according to an embodiment of the present invention.

The clock signal CLK and the command / address CMD / ADD are outputted from the memory controller as shown in Fig. 7, and the semiconductor memory device outputs the command / address CMD / ADD in synchronization with the clock signal CLK . For example, the semiconductor memory device may receive the command / address CMD / ADD in synchronization with the rising edge of the clock signal CLK and may receive the received command / address CMD / ADD and the accompanying parity signal ) To perform a parity check operation.

A parity error may be generated in the fourth command / address CMD / ADD as a result of performing the parity check operation on the command / address CMD / ADD received in synchronization with the clock signal CLK. Parity error information (Info_PEI) indicating that a parity error has occurred may be provided to the memory controller after two clocks, taking into consideration the time period during which the parity check operation is performed. When a parity error occurs, the parity error information (Info_PEI) may have a level corresponding to a logic low, and the parity error information (Info_PEI) maintains a logic low level for a predetermined period. For example, as shown in FIG. 7, the logic low level may be maintained for three clocks.

The memory controller can receive parity error information (Info_PEI) and analyze it to detect the command / address (CMD / ADD) in which the error occurred. For example, it can be determined that a parity error has occurred in the command / address CMD / ADD output two clocks before the parity error information (Info_PEI) changes to low level. As a result, the memory controller can again supply the command / address (CMD / ADD) in which the parity error has occurred and the subsequent command / address to the semiconductor memory device.

8 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention. 8, the semiconductor memory device 1600 includes a parity check unit 1620, one or more registers 1631 and 1632, a command decoder 1650, a delay unit 1660, one or more buffers 1671 and 1672 , 1673, and one or more flip-flops 1681, 1682, 1683. For convenience of description, in this embodiment, an example is shown in which a parity check operation is performed on the command CMD.

The command CMD is provided to the parity check unit 1620 via the second buffer 1672 and the second flip-flop 1682. The parity signal is supplied to the parity check unit 1620 via the third buffer 1673 and the third flip-flop 1683. The parity check unit 1620 performs a parity check operation on the command CMD in response to the chip select signal CS provided through the first buffer 1671 and the first flip-flop 1681.

The chip select signal CS from the first flip flop 1681 is stored in the chip select signal register 1631 and the command CMD from the second flip flop 1682 is stored in the command register 1632 do. The parity check result (Res_CHK) from the parity check unit 1620 is provided to the command decoder 1650 via the delay unit 1660. [ The chip select signal CS and the command CMD are provided to the command decoder 1650 in synchronization with the parity check result Res_CHK being provided to the command decoder 1650. In addition, An internal command is output from the decoder 1650. [ On the other hand, when a parity error occurs, the internal command is not output from the command decoder 1650.

The parity check operation of the parity check unit 1620 and the signal delay operation of the delay unit 1660 can be performed in response to the chip select signal CS. For example, when the chip select signal CS is inactivated, the semiconductor memory device 1600 does not perform a normal memory operation, so that the parity check operation or the signal delay operation can be disabled. On the other hand, when the chip select signal CS is activated, the parity check unit 1620 performs a parity check operation using the command CMD and the parity signal parity, (Res_CHK) from the parity check result (1620), and delays and outputs the parity check result (Res_CHK).

In addition, when a parity error occurs, an internal command can be prevented from being generated by intercepting a signal provided to the command decoder 1650. For example, the parity check result (Res_CHK) may be provided to at least one of the chip select signal register 1631 and the command register 1632, and the chip select signal register 1631 and the command register 1632 may be provided with a parity check result Res_CHK The output operation of the signal can be controlled. In one embodiment, both the chip select signal CS and the command CMD may be blocked from being provided to the command decoder 1650. [ Alternatively, as another embodiment, the command decoder 1650 may be designed not to output an internal command if the chip select signal CS is not activated, in which case only the chip select signal register 1631 is supplied to the command decoder 1650, . ≪ / RTI >

8, the first flip-flop 1681 receives the chip select signal CS and outputs it in synchronization with an internal clock signal, and the signal output from the first flip-flop 1681 is a first chip select signal Signal SMP_CS0. ≪ / RTI > The chip select signal register 1631 receives and outputs the first chip select signal SMP_CS0 and the signal output from the first flip flop 1681 is referred to as a second chip select signal SMP_CS . The first chip select signal SMP_CS0 and the second chip select signal SMP_CS may be generated by delaying the chip select signal CS so that the first chip select signal SMP_CS0 or the second chip select signal SMP_CS, SMP_CS) may be referred to as a chip selection signal, respectively. In the following description, it is assumed that the terms can be used in combination. Similarly, the first command SMP_CMD0 and the second command SMP_CMD may also be referred to as commands, respectively.

9 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention. 9, the semiconductor memory device 1700 includes a parity check unit 1720, one or more registers 1731 and 1732, a command decoder 1750, a delay unit 1760, a control signal generation unit 1791, And a bypass selection unit 1792. [ For convenience of explanation, the buffer or flip-flops shown in the above-described embodiment are not shown, and in this embodiment, an example in which a parity check operation is performed on the command CMD is shown.

The parity check unit 1720 receives the command CMD and the parity signal parity and performs a parity check operation on the command CMD. Also, the parity check result (Res_CHK) is provided to the command decoder 1750 via the delay unit 1760. At the same time, the parity check result (Res_CHK) may be provided to at least one of the chip select signal register 1731 and the command register 1732, and the chip select signal register 1731 and the command register 1732 may be provided as a parity check result Res_CHK) to control the output operation of the signal.

The semiconductor memory device 1700 may selectively perform a parity check operation according to the set mode. For example, a mode register set (MRS) (not shown) may be provided in the semiconductor memory device 1700, and a mode signal (Mode ), Or may be set such that a parity check operation is not performed.

The control signal generator 1791 generates a control signal according to the mode signal Mode. For example, when the parity check operation is set to be performed, the control signal generating unit 1791 may enable or disable the parity check unit 1720 and the delay unit 1760 according to whether the chip select signal CS is activated or not . For example, when the chip select signal CS is activated, the parity check unit 1720 performs a parity check operation on the command CMD, and the delay unit 1760 delays and outputs the parity check result Res_CHK . On the other hand, when the chip select signal CS is inactivated, the parity check unit 1720 and the delay unit 1760 are disabled. When the parity check operation is set to be performed, the bypass selector 1792 provides the chip select signal CS and the command CMD to the chip select signal register 1731 and the command register 1732, respectively.

On the other hand, when the parity check operation is not performed, the parity check unit 1720 and the delay unit 1760 are disabled under the control of the control signal generation unit 1791. The bypass selection section 1792 provides the chip selection signal CS and the command CMD to the command decoder 1750 without going through the registers under the control of the control signal generation section 1791. [ When the parity check operation is set not to be performed, the chip select signal CS and the command CMD can be directly supplied to the command decoder 1750 without latency for the parity check according to the above-described operation. On the other hand, when a parity check operation is performed, a chip select signal SMP_CS and a command SMP_CMD, which are delayed by a predetermined clock, may be provided to the command decoder 1750.

10 and 11 are waveform diagrams showing an example of the internal operation of the semiconductor memory device according to the parity check result according to the embodiment of the present invention. As shown in Figs. 10 and 11, the command / address CMD / ADD is received in synchronization with the clock signal CLK, and the parity check operation is performed on the received command / address CMD / ADD.

Referring to FIG. 10, an error may occur in receiving the command / address CMD / ADD in synchronization with the clock signal CLK, and the parity error may be detected through the parity check operation. In consideration of the parity check and the delay operation on the parity result signal, it can be assumed that the command CMD is provided to the command decoder after four clocks after receiving the command.

As a parity error is detected, the parity check result (or the signal that delayed the parity check result, ERRB) may be changed to a logic low state. The logic low state of the parity check result ERRB may be maintained for a predetermined period and for a predetermined clock (e.g., three clocks) as in the above-described example. As the parity check result ERRB changes to a logic low, the internal command generating operation of the command decoder can be interrupted. For example, as the parity check result ERRB is supplied to the chip select signal register, the chip select signal SMP_CS provided from the chip select signal register can be blocked from being provided to the command decoder. The internal command generation operation may be interrupted during a period in which the parity check result ERRB is logic low. In this way, the internal command according to the error-generated command may not be included in the command decoder output CMDDEC_Output.

Although not shown in FIG. 10, the parity check result ERRB again changes to a logic high after a predetermined period, and the command / address CMD / ADD is again received from the memory controller. A parity check operation for the received command / address CMD / ADD will be performed, and a normal internal command will be generated if no parity error is generated.

11 is a modification of the waveform diagram of FIG. 10, in which the parity check result ERRB corresponds to a command in which a parity error has occurred so that only the command generated as a parity error is blocked from being provided to the command decoder as shown in FIG. It can only have a logic low value. That is, the semiconductor memory device performs the internal command generation operation in accordance with the command CMD from the memory controller, and does not generate the internal command for the command CMD in which the parity error is generated. In addition, an internal command generation operation is performed for subsequent normal commands (commands for which no parity error has occurred).

Parity error information (not shown) according to the parity check result ERRB as described above will be provided to the memory controller, and the memory controller can later provide the errored command to the semiconductor memory device. If no parity error is generated in the command, the semiconductor memory device performs an internal command generation operation for the command and a corresponding memory operation, and outputs the result to the memory controller. In this case, the order of the commands executed by the semiconductor memory device may be partially changed, and the memory controller can use the normal data by receiving the results of performing the memory operation and reordering the order of the commands.

12 is a circuit diagram illustrating an example of a parity check unit included in a semiconductor memory device according to an embodiment of the present invention. In FIG. 12, it is assumed that a parity check operation is performed on the command and the address.

12, the parity check unit 2100 may include a parity operation unit 2110, a delay unit 2120, and a parity check result output unit 2130. The operation unit 2110, the delay unit 2120, and the parity check result output unit 2130 may each include one or more logic elements. For example, in FIG. 12, the operation unit 2110 and the delay unit 2120 include a plurality of XOR operators, respectively, and the check result information output unit 2130 includes a NOR operator. However, the present invention is not limited to this, and the same calculation result may be generated using another computing unit.

The parity operation unit 2110 receives a command and an address, performs arithmetic operation through a plurality of XOR operators, and outputs the operation result. (ACT, RAS, CAS, WE) constituting the command are provided to the parity operation unit 2110 and a plurality of address bits A0 to A13 constituting the address are supplied to the parity operation unit 2110, . Further, the bank addresses BA0 and BA1 and the bank group addresses BG0 and BG1 may be further provided as a parity operation unit 2110. [ A parity signal parity is further provided to the parity operation unit 2110 and voltage signals VEXT and VSS may be further provided to the parity operation unit 2110 to provide a signal of a constant level as required.

For example, the command, the address, the bank address, and the bank group address are composed of 23 bits. The parity operation unit 2110 determines whether the number of bits having a logic high bit value among the 23 bits is even Can be output. The parity operation unit 2110 outputs a signal having a first state when the number of bits having a logic high bit number is an even number and outputs a signal having a second state when the number of bits having a bit value of logic high is odd. Can be output. The memory controller adjusts the level of the parity signal so that the number of bits having a logic high bit value among the 23 bits is an even number. When the parity error is not generated, the parity operation unit 2110 And outputs a signal having a first state. When a parity error occurs, the parity operation unit 2110 can output a signal having the second state.

The delay unit 2120 receives the chip selection signal CS and outputs the delayed signal. For example, the delay unit 2120 can delay and output the chip selection signal CS in consideration of the time required for the parity check of the parity operation unit 2110. For example, when the parity operation unit 2110 performs an XOR operation over five stages, the delay unit 2120 may include five cascaded XOR operators.

The parity check result output unit 2130 receives the operation result from the parity operation unit 2110 and the delayed chip select signal CS from the delay unit 2120 and performs a NOR operation on the result of the parity check on the parity check result Res_CHK, As shown in Fig. The parity check result output unit 2130 outputs the parity check result Res_CHK corresponding to the calculation result from the parity calculation unit 2110 when the chip selection signal CS is activated. On the other hand, when the chip select signal CS is inactivated, the parity check result output unit 2130 outputs a parity check result (Res_CHK) having a constant level regardless of the operation result from the parity operation unit 2110.

13A and 13B are diagrams showing examples of waveforms of various signals according to the operation of the parity check unit 2100 of FIG. FIG. 13A shows an example in which no parity error is generated, and FIG. 13B shows an example in which a parity error occurs. For convenience of explanation, it is assumed that address bits (A <0:13>, BG <0: 1>, BA <0: 1>) all have logic high values.

The command may be composed of a combination of various signals. For example, the command may include ACT_n, RAS_n, CAS_n, WE_n, and so on. 13A, the chip select signal CS_n is further shown, and the chip select signal CS_n may be described as being included in the command. The logic of the bits of the address bits A <0:13>, BG <0: 1>, BA <0: 1>, command bits CS_n, ACT_n, RAS_n, CAS_n, WE_n, It is assumed that the bit value of the parity signal parity is set so that the number of bits having a high level is an even number.

The address bits A <0:13>, BG <0: 1>, BA <0: 1> and the command bits CS_n, ACT_n, RAS_n, CAS_n and WE_n are normally As received, a parity error may not occur. For example, the command provided to the semiconductor memory device may have various types of signal combinations. For example, the MRS command MRS, the refresh command REF, the precharge command PRE, the write command WR, the read command RD ), And the like. As a parity error is not generated for the commands, the parity check result (Res_CHK) can maintain a first level (e.g., a logic high level).

On the other hand, as shown in FIG. 13B, a parity error may be generated as a signal is received incorrectly in a command receiving operation. For example, when receiving the write command WR, the semiconductor memory device erroneously receives the write enable signal WE_n and outputs the write enable signal WE_n (WE_n) even though the write enable signal WE_n of logic low is supplied from the memory controller to the memory controller. ) May have a logic high value.

At this time, of the bits constituting the write command WR, parity signal (parity) and address bits (A <0:13>, BG <0: 1>, BA <0: 1> May be an odd number, which can be detected as a parity error has occurred. Accordingly, the parity check result (Res_CHK) may be changed to a second level (e.g., logic low level), and the parity check result (Res_CHK) may be maintained at the second level for a predetermined period as in the above- have.

14 is a flowchart showing an operation method of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 14, the semiconductor memory device receives various signals for the memory operation from the memory controller, and can receive, for example, commands and addresses. In addition, a parity signal may be received from the memory controller for a parity check on the command and / or the address (S11). The parity signal is provided from the memory controller as a specific value according to the bit value of the command and / or address, for example, when a parity check is performed on the command and the address, the parity signal has a logic high of the bits constituting the command, The bit value of the parity signal may be determined such that the number of bits is an even number (or an odd number).

A parity check operation is performed on the command and / or the address using the received parity signal (S12). A parity check can be performed by detecting a bit value of bits constituting a command, an address, and a parity signal, and it is determined whether a parity error has occurred (S13). As a result of the determination, if the parity error is not generated, the memory operation is performed as the internal command is generated by decoding the command. The parity check result may be provided to the command decoder through a predetermined delay as a result of the parity check being performed and the command is supplied to the command decoder in synchronism with the parity check result being provided to the command decoder, The command can be delayed by a predetermined register and output to the command decoder.

On the other hand, when a parity error occurs, generation of an internal command is blocked (S15). In order to block the generation of the internal command, either the decoding operation of the command decoder is disabled as the parity check result is provided to the command decoder, or the command is provided to the command decoder as the parity check result is provided to the predetermined register Can be blocked. Although not shown in FIG. 14, a chip select signal may be provided to the command decoder together with a command, and a parity check result is provided to a register for storing a chip select signal, thereby preventing a chip select signal from being provided to the command decoder .

On the other hand, if a parity error occurs, it is necessary to output information indicating the parity error to the memory controller, and parity error information may be generated according to a result of the parity check and output to the memory controller (S16). In addition, the command and / or address in which the parity error is generated can be stored according to the result of the parity check (S17). For example, when a multipurpose register (MPR) is provided in the semiconductor memory device, Lt; RTI ID = 0.0 &gt; and / or &lt; / RTI &gt; The information stored in the MPR may be provided to a memory controller.

15 is a flowchart showing an operation method of a semiconductor memory device according to another embodiment of the present invention. For convenience of explanation, it is assumed in Fig. 15 that a parity check is performed on the command.

A chip selection signal and a command are received from the memory controller (S21), and a parity signal is received from the memory controller for a parity check on the command (S22). A parity check operation is performed using the received command and the parity signal, and a parity check result signal is output (S23).

If no parity error occurs, the parity check result signal may have a first state, whereas if a parity error occurs, the parity check result signal may have a second state. If it is determined that the check result signal is in the first state (S24) and the check result signal is in the first state due to no parity error, the parity check result signal is delayed by a predetermined clock to be provided to the command decoder (S27) . In addition, the chip select signal and the command are supplied to the command decoder by a predetermined clock delay as the chip select signal and the command are stored in the registers, respectively, so that the chip select signal and the command are supplied to the command decoder in synchronization with the parity check result signal being provided to the command decoder ). The command decoder performs a decoding operation using the received chip selection signal and command, generates an internal command, and outputs the internal command (S29).

On the other hand, when the check result signal is in the second state as a parity error occurs, the generation of the internal command is interrupted (S25). It is possible to prevent the internal command from being outputted by blocking the chip decoder and the command from being supplied to the command decoder as in the above-described embodiment, or by blocking the input of the signal in the command decoder . In addition, parity error information indicating that a parity error has occurred can be generated and output to the memory controller (S26).

16 is a flowchart illustrating an operation method of a memory controller according to an embodiment of the present invention.

As shown in FIG. 16, the memory controller outputs a chip selection signal and a command to the semiconductor memory device to request a memory operation (S31). In addition, the memory controller generates a parity signal for parity check and outputs it to the semiconductor memory device (S32). The parity signal may have a level corresponding to the bit value of the bits constituting the command. For example, the parity signal may have a bit value of the parity signal such that the number of bits corresponding to the logic high among the bits constituting the command and the parity signal is an odd number or an even number. Can be set.

A parity check operation is performed in the semiconductor memory device, and parity error information indicating a parity error is received at the memory controller (S33). In step S34, it is determined whether the error state is activated by detecting the state of the parity error information. If the parity error is not generated, the memory controller proceeds to a normal operation of outputting a subsequent command in step S35.

On the other hand, if a parity error occurs, the memory controller detects the timing of activation of the parity error information, and detects an error-generated command among the commands output to the semiconductor memory device (S36). For example, the memory controller can temporarily store commands output to the semiconductor memory device, and can detect an errored command in consideration of the time required for the parity check of the semiconductor memory device. For example, when parity error information for the command is received after two clocks after the memory controller outputs a command, the memory controller can detect that an error has occurred in the command output 2 clocks before receiving the parity error information have. The memory controller re-outputs the errored command and the subsequent command to the semiconductor memory device (S37). Accordingly, it is possible to prevent the memory operation from being performed in the semiconductor memory device by an error command, and the memory controller can request the semiconductor memory device to perform the memory operation again.

17 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention. 17 shows an example of a DRAM (dynamic random access memory) as a semiconductor memory device that performs a parity check operation in the above-described embodiment.

17, the DRAM 3000 as a semiconductor memory device includes a DRAM cell array 3100, a command control logic 3200, an address register 3300, a row decoder 3400, a column decoder 3500, and information And a generating unit 3600. The command control logic 3200 also includes a command register 3210, a parity check section 3220, a parity latency 3230 and a command decoder 3240. [

The command control logic 3200 may perform the parity check operation described in the above embodiments. Accordingly, the command control logic 3200 can receive the command CMD, the chip select signal CS and the clock signal CLK, and outputs the command CMD and the chip select signal &lt; RTI ID = 0.0 &gt; CS) is stored in the command register 3210. [ The command register 3210 may include buffers, flip-flops, and shift registers (not shown) shown in the above-described embodiments. In the above-described embodiments, It is also possible to explain that the command register 3210 stores the chip select signal CS and the command CMD as shown in Fig.

It is assumed that the first command SMP_CMD0 and the first chip select signal SMP_CS0 are output from the flip flops in the command register 3210 and the first command SMP_CMD0 and the first chip select signal SMP_CS0 are shifted Assuming that the signals delayed by the registers are the second command SMP_CMD and the second chip select signal SMP_CS, the parity check unit 3220 performs a parity check operation in response to the first chip select signal SMP_CS0 can do.

Assuming that the address outputted from the address register 3300 is the first address SMP_ADD0 / BA0 / BG0 and the parity signal is the first parity signal SMP_Parity0, the first command SMP_CMD0 and the first address The parity check unit 3220 receives the parity check result for the command CMD and the address ADD / BA / BG as the first parity check signal SMP_ADD0 / BA0 / BG0 and the first parity signal SMP_Parity0 are supplied to the parity check unit 3220. [ Perform a check. In the above-described embodiments, the parity signal Parity0 is stored in a separate register. However, the parity signal Parity0 may be transmitted through the address register 3300 as shown in FIG.

The parity check result Res_CHK is provided to the parity latency 3230 and the parity latency 3230 delays the received parity check result Res_CHK and provides the delayed parity check result ERRB to the command decoder 3240. [ The parity check result ERRB delayed in synchronization with the second command SMP_CMD and the second chip select signal SMP_CS is supplied to the command decoder 3240 is provided to the command decoder 3240. [ The command decoder 3240 generates and outputs an internal command Int_CMD through a decoding operation.

The internal command Int_CMD may be provided to the row decoder 3400 and the column decoder 3500 and a row address RAi and a column address CAi may be generated in accordance with the internal address SMP_ADD / BA / BG . For example, a memory operation such as data write / read with respect to the DRAM cell array 3100 can be performed in accordance with the internal command Int_CMD, and the DRAM cell array 3100 can be operated according to the row address RAi and the column address CAi. The area to be accessed of the &lt; / RTI &gt; The internal address SMP_ADD / BA / BG may be a signal for delaying and outputting the first address SMP_ADD0 / BA0 / BG0 by the address register 3300.

Also, the information generator 3600 receives the parity check result (Res_CHK), and can generate and output parity error information (Info_PEI) indicating whether or not a parity error has occurred.

18A, 18B, 18C, and 18D are circuit diagrams showing an example of the configuration of the semiconductor memory device of FIG.

18A, the command register 3210 may include a flip-flop 3211 and a shift register 3212. Although not shown in FIG. 18A, the external register TTL level signal is converted into a CMOS level signal (Not shown) may be additionally provided in the command register 3210. The flip-flop 3211 receives the command CMD in synchronization with the clock signal CLK and outputs the first command SMP_CMD0 in synchronization with the clock signal CLK.

Shift register 3212 may include one or more flip-flops and one or more inverters. The shift register 3212 receives the first command SMP_CMD0 and delays it for a predetermined clock to output the second command SMP_CMD. The number of flip-flops provided in the shift register 3212 can be adjusted according to the number of clocks to be delayed.

On the other hand, as shown in Fig. 18B, the command decoder 3240 performs logic operation on input commands and outputs the result of the operation as an internal command Int_CMD. For example, although one NAND operator and an inverter are shown in FIG. 18B, a larger number of NAND operators and inverters may be provided. The NAND operator outputs the delayed parity check result ERRB, the second command SMP_CMD and the second chip select signal SMP_CS by logical operation and outputs the result of the operation from the NAND operator through the at least one inverter to the internal command Int_CMD ). &Lt; / RTI &gt;

The internal command Int_CMD according to the state of the second command SMP_CMD and the second chip select signal SMP_CS is generated when the delayed parity check result ERRB has the first level (for example, when no parity error is generated) (SMP_CMD) and the second chip selection signal (ERRB) have a second level (for example, when a parity error has occurred), while the normal memory operation is performed as the parity check result ERRB is generated The generation of the internal command Int_CMD according to the instruction SMP_CS is blocked, thereby preventing the erroneous memory operation from being performed.

Meanwhile, as shown in FIG. 18C, the parity check unit 3220 may include an operation unit 3221 including XOR operators as a plurality of operators. The parity check unit 3220 further includes a flip flop 3222 operating in response to the first chip select signal SMP_CS0 so that the parity check result Res_CHK is provided only when the chip select signal CS is activated can do. The operation unit 3221 provides the operation result for the first command / address SMP_CMD0 / ADD0 and the first parity signal SMP_parity0 to the input terminal of the flip-flop 3222 and also outputs the result of the operation for the first chip select signal SMP_CS0 And provides the result of the operation to the output terminal of the flip-flop 3222. The result of the operation on the first chip select signal SMP_CS0 may be a signal delaying the simple first chip select signal SMP_CS0. The flip-flop 3222 provides its output as a parity check result (Res_CHK) in response to activation of the delayed first chip select signal (SMP_CS0).

18D shows an example of the parity latency 3230. The parity latency 3230 receives the parity check result Res_CHK from the parity check unit 3220 and generates a delayed parity check result ERRB by delaying the result. The parity latency 3230 may include one or more flip-flops 3231 and one or more delay units 3232 for delaying the internal clock Int_CLK in the semiconductor memory device, and the parity check result (Res_CHK) And output as a delayed parity check result (ERRB) through connected flip-flops.

19 is a block diagram illustrating a semiconductor memory device according to another embodiment of the present invention.

19, the DRAM 4000 as a semiconductor memory device includes a DRAM cell array 4100, a command control logic 4200, an address register 4300, a row decoder 4400, a column decoder 4500, And a generating unit 4600. The command control logic 4200 may also include a command register 4210, a parity checker 4220, a parity latency 4230 and a command decoder 4240. Since the same components as those shown in FIG. 17 are the same as or similar to those shown in FIG. 19, detailed description thereof will be omitted.

The command control logic 4200 can receive the command CMD, the chip select signal CS and the clock signal CLK and outputs the command CMD and the chip select signal CS in synchronization with the clock signal CLK And is stored in the command register 4210. The parity check unit 4220 may perform a parity check operation in response to the first chip select signal SMP_CS0. For example, the parity check unit 4220 may include a first command SMP_CMD0, a first address SMP_ADD0 / BA0 / BG0) and a first parity signal (SMP_Parity0) to perform a parity check operation and output a parity check result (Res_CHK). The parity latency 4230 receives the parity check result (Res_CHK) and delays the result to output a delayed parity check result ERRB. The second command SMP_CMD and the second chip select signal SMP_CS may be prevented from being provided to the command decoder 4240 in order to block the occurrence of an internal command (Int_CMD) in which an error exists when a parity error occurs. To this end, the delayed parity check result ERRB from the parity latency 4230 may be provided to the command register 4210. [ The command register 4210 blocks the second command SMP_CMD and the second chip select signal SMP_CS from being supplied to the command decoder 4240 in response to the parity check result ERRB.

20A and 20B are circuit diagrams showing an embodiment of the structures of the semiconductor memory device shown in FIG.

20A shows an embodiment of the chip select signal register 4211 provided in the command register 4210 of FIG. Although not shown in FIG. 20A, the command register 4210 may further include a register for storing a command.

The chip select signal register 4211 may include a flip flop 4211_1 and a shift register 4211_2 and the flip flop 4211_1 stores and outputs the chip select signal CS in response to the clock signal CLK . The output from the flip-flop 4211_1 may be defined as a first chip select signal SMP_CS0.

The first chip select signal SMP_CS0 may be provided as an input of the shift register 4211_2. The delay amount of the first chip select signal SMP_CS0 can be determined according to the number of flip-flops provided in the shift register 4211_2. In addition to the flip-flops for delaying the first chip select signal SMP_CS0, the shift register 4211_2 further includes logic elements for controlling the output of the second chip select signal SMP_CS in response to the delayed parity check result ERRB For example, the shift register 4211_2 may include a NAND gate and an inverter. A delayed parity check result ERRB is provided to one input terminal of the NAND gate and the output of the second chip select signal SMP_CS from the shift register 4211_2 is blocked when a parity error occurs.

20B shows a command decoder 4240, and FIG. 20B shows one NAND operator and an inverter. However, a larger number of NAND operators and inverters may be provided. The delayed parity check result ERRB is prevented from generating an error internal command Int_CMD according to a method provided to the registers provided in the command register 4210. Therefore, the NAND operator of the command decoder 4240 is a second The internal command Int_CMD can be generated by performing a logic operation on the command SMP_CMD and the second chip select signal SMP_CS.

21 is a circuit diagram showing another embodiment of the command control logic included in the semiconductor memory device.

As shown in FIG. 21, the command control logic 5000 may include a command register 5100, a parity check and latency portion 5200, and a command decoder 5300. 21 shows an example in which the parity check and latency unit 5200 performs the parity check operation and the delay operation on the check result in the above-described embodiment.

The command register 5100 provides the first command (SMP_CMD0) and the first chip select signal (SMP_CS0) to the parity check and latency unit 5200. The command decoder 5300 also receives the parity check result ERRB delayed from the parity check and latency unit 5200 and also receives the second command SMP_CMD and the second chip select signal SMP_CS from the command register 5100, . If no parity error is generated, the command register 5100 decodes the second command (SMP_CMD) and the second chip select signal (SMP_CS) and outputs an internal command.

The parity check and latency unit 5200 may perform a parity check operation in response to the first chip select signal SMP_CS0. The parity check and latency unit 5200 may include a first command SMP_CMD0, a first address SMP_ADD0, And can receive the parity signal SMP_parity0. The parity check and latency unit 5200 may also include one or more arithmetic operators (e.g., XOR arithmetic operators) for parity checking, similar to the above-described embodiment, and also for delaying the parity check result And may include a flip-flop as one or more delay elements.

22 is a block diagram illustrating a memory controller according to an embodiment of the present invention. 22, the memory controller 6100 includes a packet decoder 6110, a command queue 6120, a write data queue 6130, an arbiter 6140, a controller input / output unit 6150, and a packet generating unit 6170 . The memory controller 6100 may further include a parity signal generator 6160, an information receiver 6180, and an error command output controller 6180 according to an embodiment of the present invention.

The packet decoder 6110 receives and decodes a packet containing information for accessing the semiconductor memory device. As the packet is decoded, the command CMD and the address ADD corresponding thereto can be generated. For example, one command CMD and one address ADD may be generated per packet, or a plurality of commands CMD and ADD per packet may be generated.

The command queue 6120 includes a space for storing a plurality of commands CMD and ADD, and queues commands and addresses in the order in which they are received. The command queue 6120 can operate as a first-in first-out (FIFO) system in which the information first inserted in the list is deleted first.

The arbiter 6140 receives a plurality of commands CMD and corresponding addresses ADD stored in the command queue 6120 and controls the command CMD and the address ADD to be executed according to the priority order do. Execution of the command CMD and the address ADD may indicate an operation of outputting the command CMD and the address ADD to the semiconductor memory device in accordance with the priority order. On the other hand, the write data queue 6130 receives the write control signal Ctrl_WR from the arbiter 6140 and outputs the data transferred from the packet decoder 6110 to the controller input / output unit 6150 in response to the write control signal Ctrl_WR Output. The packet generation unit 6170 receives the data read from the semiconductor memory device and generates a packet, and the generated packet can be output to an external device such as a central processing unit (not shown).

Meanwhile, the controller input / output unit 6150 may be implemented as a physical layer area. Accordingly, the controller input / output unit 6150 defines interfaces between transmission media and provides mechanical, electrical, and functional procedural means for signal transmission between the data link layers. The controller input / output unit 6150 transfers the command CMD, address ADD, and data (DATA) generated in the memory controller 6100 to the semiconductor memory device.

In accordance with an embodiment of the present invention, the parity signal generator 6160 generates a parity signal parity based on the bit values of the command CMD and the address ADD output from the memory controller 6100. For example, it is possible to determine and output the bit value of the parity signal parity according to the number of bits having logic high (or logic low) among the bits constituting the command CMD and the address ADD.

The information receiving unit 6180 receives the parity error information (Info_PEI) output from the semiconductor memory device and outputs a command CMD and an address ADD to the semiconductor memory device based on the received parity error information (Info_PEI) . For example, when the parity error is generated in the command CMD and the address ADD output before the predetermined clock as the parity error information (Info_PEI) is activated, the command CMD and the address ADD ) Is output to the semiconductor memory device again.

The error command output control section 3180 controls the output of the command CMD and the address ADD in which a parity error has occurred in accordance with the state of the parity error information (Info_PEI) received by the information receiving section 6180. [ The error command output control section 3180 may include a predetermined storage means (for example, a register or the like) therein and may store information indicating the command CMD and the address ADD output to the semiconductor memory device, A flag indicating whether a parity error has occurred with respect to the address CMD and the address ADD may be stored in the storage means.

The error command output control section 3180 can control the arbiter 3140 to control the command CMD and the address ADD in which the parity error is generated to be provided to the semiconductor memory device again. The command CMD and the address ADD provided to the semiconductor memory device can be temporarily stored in the command queue 6120 or the arbiter 6140. [ When the activated parity error information (Info_PEI) is received, it can be determined that a parity error has occurred in the command (CMD) and the address (ADD) outputted before the predetermined number of clocks for receiving the parity error information (Info_PEI) Thus, the error-generated command CMD and address ADD stored in the command queue 6120 or the arbiter 6140 are provided again to the semiconductor memory device.

23 is a block diagram showing an embodiment of a memory system to which a semiconductor memory device according to an embodiment of the present invention is applied. 23, the memory system 7100 according to an embodiment of the present invention includes a memory module 7110 and a memory controller 7120. [ Also, the memory module 5110 includes one or more semiconductor memory devices 7111 mounted on a module board. For example, the semiconductor memory device 7111 may be a DRAM chip. Further, the semiconductor memory device 7111 may be a DRAM chip to which any one of the above-described various embodiments is applied.

The memory controller 7120 outputs various signals for controlling the semiconductor memory device 7111 included in the memory module 7110. For example, the memory controller 7120 outputs various commands (CMD), address (ADD) and data (Data) for the memory operation and outputs the command CMD provided to the semiconductor memory device 7111 according to the embodiment of the present invention. And a parity signal (parity) for a parity check on the address ADD.

A parity check unit for parity check on the command CMD and / or the address ADD may be employed in the semiconductor memory device 7111. The parity check unit for generating parity error information (Info_PEI) An information generating unit may be provided. In order to control the operation of the command decoder in accordance with the parity check result, the command CMD is supplied to the command decoder in synchronization with the timing at which the parity check result is provided to the command decoder, A command register may be provided.

24 is a block diagram showing another embodiment of a memory system to which a semiconductor memory device according to an embodiment of the present invention is applied.

As shown in FIG. 24, the memory system 7200 includes a memory module 7210 and a memory controller 7220, and the memory module 7210 includes one or more DRAM chips 7211 as a semiconductor memory device. 24 shows an example in which a registered dual in-line memory module (RDIMM) is applied as a module for a server, and a register 7212 and a PLL 7213 are connected to the module of the memory module 7210 Can be mounted on a board.

The memory module 7210 and the memory controller 7220 transmit and receive signals through various system buses. The register 7212 buffers the command CMD and the address ADD and provides the buffered command CMD and the address ADD to the DRAM chip 7211. [ Also, according to an embodiment of the present invention, the register 7212 further receives a parity signal (parity), buffers it, and provides it to the DRAM chip 7211. In addition, the PLL 7213 receives and adjusts the phase of the clock signal CLK and provides the phase adjusted clock signals CLKs to the DRAM chip 7211.

In the semiconductor memory device 7211, a parity check part for parity check on the command CMD and / or the address ADD may be employed as in the above embodiment, and parity error information according to the parity check result (Info_PEI). &Lt; / RTI &gt; In order to control the operation of the command decoder in accordance with the parity check result, the command CMD is supplied to the command decoder in synchronization with the timing at which the parity check result is provided to the command decoder, A command register may be provided.

25A and 25B are block diagrams showing another embodiment of a memory system to which a semiconductor memory device according to an embodiment of the present invention is applied. 25A and 25B shows an example in which a fully-buffered DIMM (FBDIMM) is applied.

25A, the memory system 7300 includes a memory module 7310 and a memory controller 7320. The memory module 7310 includes at least one DRAM chip 7311 and an AMB (Advanced Memory Buffer) 7312 ). The FBDIMM type memory module 7310 communicates with the memory controller 7320 and the memory controller 7320 and the AMB 7312 in the memory module 7310 are connected to each other in a point-to-point manner Serial communication. According to this, it is possible to increase the number of memory modules 7310 connected to the memory system 7300, thereby enabling a large capacity. Also, since the FBDIMM uses a packet protocol, high-speed operation is possible.

As in the above-described embodiment, the DRAM chip 7311 performs a parity check on the command CMD and / or the address ADD in addition to the general command / address (CMD / ADD) and the clock signal (CLKs) And a parity error information (Info_PEI) may be provided to the memory controller 7320. The memory controller 7320 may be provided with a parity error signal (Info_PEI). The DRAM chip 7311 has a parity check unit for parity checking, an information generating unit for outputting parity error information (Info_PEI), and a command CMD (synchronizing signal) in synchronization with the timing at which the parity check result is supplied to the command decoder And a command register for delaying and outputting the command CMD so as to be provided to the command decoder.

Although the embodiment of the present invention is applied to the RDIMM or the FBDIMM in the above-described embodiment, the embodiment of the present invention need not be limited to this. Embodiments of the present invention can be applied to various types of semiconductor memory devices, memory modules and systems, and the like, for example, other types of memory modules (SIMM (Single in-line memory module), dual in-line memory module (DIMM) -DIMM (Small-outline DIMM), UDIMM (Unbuffered DIMM), RBDIMM (Rank-buffered DIMMmini-DIMM and micro-DIMM).

26 is a structural view showing a semiconductor memory device according to still another embodiment of the present invention. 26 shows an example in which the semiconductor memory device is implemented by stacking a plurality of semiconductor layers.

As shown in FIG. 26, the semiconductor memory device 8100 may include a plurality of semiconductor layers LA1 to LAn. Each of the semiconductor layers LA1 to LAn may be a DRAM chip including a DRAM cell or some of the semiconductor layers LA1 to LAn may be a master chip for interfacing with an external memory controller, Slave chip. In the example of FIG. 26, it is assumed that the lowermost semiconductor layer LA1 is a master chip, and the remaining semiconductor layers LA2 to LAn are slave chips.

The plurality of semiconductor layers LA1 to LAn transmit and receive signals through the through silicon vias TSV and the master chip LA1 communicates with the memory controller through conductive means (not shown) formed on the outer surface. The configuration and operation of the semiconductor memory device 8100 with the first semiconductor layer LA1 as a master chip and the n-th semiconductor layer LAn as a slave chip will be described as follows.

The first semiconductor layer LA1 includes various circuits for driving the cell array 8121 provided in the slave chips. For example, the first semiconductor layer LA1 includes a row driver (X-Driver) 8111 for driving the word lines of the cell array 8121, a column driver (Y-Driver) 8112 for driving the bit lines, A command decoder 8114 for decoding the command CMD from the outside, an address controller 8115 for receiving an address from the outside and outputting row and column addresses, and the like are connected to the data input / output section 8113, .

Also, as in the above embodiment, the first semiconductor layer LA1 may include a parity check unit 8116 for receiving a parity signal and for parity checking on the command CMD and / or the address ADD . The first semiconductor layer LA1 includes an information generator 8117 for generating parity error information in accordance with a parity check result and a command decoder 8117 for synchronizing a command CMD with a command decoder in synchronization with a timing at which a parity check result is provided to a command decoder. And a command register 8118 for delaying and outputting the command CMD so that the command CMD is provided.

On the other hand, the n-th semiconductor layer LAn includes a row / column selection circuit 8121 for selecting the row and column of the cell array 8121 and other peripheral circuits for driving the cell array 8121, And a peripheral circuit region 8122 in which a bit line sense amplifier (not shown) is disposed.

27 is a block diagram showing another embodiment of a memory system to which a semiconductor memory device according to an embodiment of the present invention is applied. 27, the memory system 8200 includes optical connection devices 8230 and 8240, a memory controller 8220, and a semiconductor memory device 8210. [ A DRAM chip is exemplified as the semiconductor memory device 8210.

The optical connectors 8230 and 8240 interconnect the memory controller 8220 and the semiconductor memory device 8210. The memory controller 8220 includes a control unit 8221, a first transmitting unit 8222, and a first receiving unit 8223. [ The control unit 8221 transmits the first electric signal SN1 to the first transmitter 8222. [ The first electrical signal SN1 may include a command, a clock signal, an address, data, and the like transmitted to the semiconductor memory device 8210. [ Further, according to an embodiment of the present invention, the first electrical signal SN1 may include a buffer read command for accessing data stored in a data buffer (not shown) in the semiconductor memory device 8210. [

The first transmitter 8222 includes an optical modulator E / O and the optical modulator E / O converts the first electrical signal SN1 into a first optical transmission signal OTP1EC to form an optical connection device 8230 ). The first optical transmission signal OTP1EC is transmitted in serial communication through the optical connector 8230. The first demodulator O / E includes a second demodulator O / E that receives the second optical reception signal OPT2OC received from the optical connector 8240 as a second electrical signal SN2 And transmits it to the control unit 8221. [

The semiconductor memory device 8210 includes a second receiving portion 8211, a cell array 8212, and a second transmitting portion 8213. The second demodulator O / E includes a second demodulator O / E that receives the first optical signal OPT1OC from the optical coupler 8230 as a first electrical signal SN1 And transmits it to the cell array 8212. [

The cell array 8212 writes the write data to the memory cell in response to the first electrical signal SN1 or transfers the read data to the second transmitter 8213 as the second electrical signal SN2. The second electrical signal SN2 may include a clock signal, read data, and the like transmitted to the memory controller 8220. [ The second transmitter 8213 includes an optical modulator E / O and the optical modulator E / O converts the second electrical signal SN2 into a second optical transmission signal OPT2EC, ). The second optical transmission signal (OTP2EC) is transmitted in serial communication through the optical connector (8240).

Although not shown in FIG. 27, the semiconductor memory device 8210 includes a parity check unit for parity checking for the command CMD and / or the address ADD, and an information generating unit for generating parity error information according to the parity check result . In addition, the semiconductor memory device 8210 may further include a command register for delaying the output of the command CMD provided to the command decoder.

28 is a block diagram illustrating a computing system incorporating a memory system in accordance with an embodiment of the present invention. The semiconductor memory device of the present invention may be mounted as a RAM 8320 in a computing system 8300 such as a mobile device or a desktop computer. The semiconductor memory device mounted with the ram 8320 can be applied to any of the above-described embodiments. For example, the RAM 8320 may be a semiconductor memory device in the above embodiments, or may be applied in the form of a memory module. Further, the RAM 8320 in Fig. 28 may be a concept including a semiconductor memory device and a memory controller.

A computing system 8300 in accordance with an embodiment of the present invention includes a central processing unit 8310, a RAM 8320, a user interface 8330 and a non-volatile memory 8340, As shown in Fig. The nonvolatile memory 8340 may be a mass storage device such as an SSD or an HDD.

In the computing system 8300, as in the previous embodiments, the RAM 8320 includes a parity check unit for parity checking for the command CMD and / or the address ADD, parity error information And an information generating unit for generating the information. Further, the RAM 8320 may further include a command register for delaying the output of the command provided to the command decoder.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (20)

A parity check unit for receiving a command and a parity signal and performing a parity check;
A command register for receiving the command and outputting the command in a delayed manner;
A command decoder for receiving the command from the command register and outputting an internal command in accordance with a parity check result from the parity check unit; And
And an information generator for generating parity error information indicating whether or not a parity error has occurred in the command according to a result of the parity check, and outputting the generated parity error information. The method according to claim 1,
Further comprising a delay unit for receiving the parity check result and for delaying and outputting the parity check result such that the parity check result is provided to the command decoder in synchronization with the command being provided to the command decoder. The method according to claim 1,
Wherein the parity check unit further receives a chip select signal from a memory controller and performs the parity check in response to a state of the chip select signal. The method of claim 3,
And a chip selection signal register for storing the chip selection signal,
Wherein the chip selection signal register provides the chip selection signal to the command decoder in synchronization with the command being provided to the command decoder. The method according to claim 1,
Wherein the parity check unit further receives an address, and performs the parity check using the command, the address, and the parity signal. 6. The method of claim 5,
Further comprising an address register for storing the address,
And said address register outputs an internal address in synchronization with the output of said internal command. 6. The method of claim 5,
Wherein the address includes a bank address and a bank group address. The method according to claim 1,
Wherein when the parity error occurs, the output of the internal command is interrupted as the result of the parity check is provided to the command decoder. The method according to claim 1,
Wherein when a parity error occurs, a command from the command register is blocked from being provided to the command decoder as the result of the parity check is provided to the command register. The method according to claim 1,
Wherein a bit value of the parity signal is set so that the number of bit values of the logic high of the bits constituting the parity signal and the command is an odd number or an even number. A parity check unit for receiving a command and a parity signal to perform a parity check and outputting a parity check result;
A delay unit receiving the parity check result and outputting the delayed result;
A command storage unit for receiving the command and outputting the command in a delayed manner;
And a command decoder for decoding the command from the command storage unit and generating an internal command in accordance with the parity check result from the delay unit,
Wherein the delay unit delays the parity check result so that the parity check result is provided to the command decoder in synchronization with the command. 12. The method of claim 11,
And a chip selection signal storage unit for receiving a chip selection signal and for delaying and outputting the chip selection signal,
Wherein the parity check unit performs the parity check when the chip select signal is activated. 13. The method of claim 12,
Wherein the chip selection signal storage unit delays and outputs the chip selection signal so that the chip selection signal is provided to the command decoder in synchronization with the command and the parity check result. A memory cell array including a plurality of memory cells;
A row decoder for driving a row of the memory cell array in response to a row address;
A column decoder for driving a column of the memory cell array in response to a column address; And
A parity check operation for the command is performed by receiving a command and a chip select signal from the outside and detecting a bit value of the command and the parity signal, and when a parity error is not generated according to a result of the parity check, And a command control logic for outputting an internal command corresponding to the command. 15. The apparatus of claim 14, wherein the command control logic comprises:
A command register for storing the command and the chip select signal;
A parity check unit receiving the command and the parity signal and performing a parity check on the command in response to the chip selection signal;
A parity latency for receiving a parity check result from the parity check unit and outputting the result of the parity check; And
And a command decoder for decoding the command and outputting the internal command when a parity error is not generated in the command. 15. The method of claim 14,
Further comprising an address register for receiving an address from the outside and storing the received address,
And a parity check operation is performed on the command and the address as an address from the address register is provided to the command control logic. Receiving a command and a parity signal;
Generating a parity check result by performing a parity check on the command using the parity signal;
Delaying a result of the parity check and providing the result to the command decoder;
Blocking an output of an internal command when a parity error occurs according to the result of the parity check; And
And generating parity error information indicating whether or not a parity error has occurred according to a result of the parity check and outputting the generated parity error information to the memory controller. 18. The method of claim 17,
Further comprising delaying the command,
Wherein the command is provided to the command decoder in synchronism with the parity check result being provided to the command decoder. 18. The method of claim 17,
Further comprising receiving an address,
The step of generating the parity check result comprises:
And performing a parity check on the command and the address using the parity signal. 20. The method of claim 19,
Wherein the step of receiving the address receives the bank address and the bank group address.

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