CN109754841B

CN109754841B - Memory device including parity error detection circuit

Info

Publication number: CN109754841B
Application number: CN201711094426.8A
Authority: CN
Inventors: 柳慧承; 姜锡龙; 尹元柱; 李贤义; 郑载勋
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2017-11-08
Filing date: 2017-11-08
Publication date: 2023-03-24
Anticipated expiration: 2037-11-08
Also published as: CN109754841A

Abstract

A memory device including a parity check circuit and a mask circuit is provided. The parity check circuit may perform parity checking on data sampled in accordance with a data strobe signal, wherein the data strobe signal does not include a post-amble. The mask circuit may generate a parity error signal based on a result of parity and output the parity error signal during a time period determined according to a burst length of the data.

Description

Memory device including parity error detection circuit

Technical Field

Exemplary embodiments of the inventive concepts disclosed herein relate to semiconductor memory devices, and more particularly, to memory devices including parity error detection circuits.

Background

Storage devices are being used as voice and image data storage media for information devices such as computers, cellular phones, smart phones, personal Digital Assistants (PDAs), digital cameras, video recorders, audio recorders, MP3 players, hand-held PCs, game consoles, facsimile machines, scanners, and printers. As storage devices are used as storage media for various devices, consumer demand for the storage devices is being diversified.

Accordingly, techniques are being developed for large capacity, high speed, and/or low power storage devices. As data processing of devices supporting various functions increases, the capacity and speed of memory devices are increasing and accelerating. However, as the operating speed of the memory device becomes higher, the probability of generating an error in receiving a signal becomes higher. Therefore, ensuring stable operation of the memory device becomes a challenge.

To ensure stable operation of the high-speed memory device, the memory device may exchange data with the memory controller by using a parity scheme. For example, some memory devices use parity error detection circuitry to check whether data transmitted in a parity scheme is received without distortion.

Disclosure of Invention

Some exemplary embodiments of the inventive concepts provide a memory device including a parity error detection circuit that performs parity checking in a memory system using a data strobe signal without a postamble.

According to an exemplary embodiment, a memory device includes a parity check circuit and a mask unit. The parity check circuit performs parity checking on data sampled according to the data strobe signal. The masking unit generates a parity error signal based on a parity result, wherein the parity error signal is output during a time period determined according to a burst length of the data. The data strobe signal does not include a postamble.

According to one exemplary embodiment, a memory device includes an aligner and a parity error detection circuit. The aligner samples data by a data strobe signal. The parity error detection circuit performs parity checking on the data sampled by the aligner, generates a parity error signal output during a period determined according to a burst length of the data, and indicates whether a parity error is generated in the data. The data strobe signal does not include a postamble.

According to one exemplary embodiment, a memory device includes: a parity check circuit configured to perform parity checking on data sampled according to a data strobe signal, the data strobe signal not including a post-amble; and a mask circuit configured to generate a parity error signal based on a result of the parity and output the parity error signal during a time period determined according to a burst length of the data.

According to one exemplary embodiment, a memory device includes: an aligner configured to sample data by a data strobe signal, the data strobe signal not including a post-amble; and a parity error detection circuit configured to perform parity checking on the data sampled by the aligner to generate a parity error signal, the parity error signal being output during a time period determined according to a burst length of the data, the parity error signal indicating whether a parity error is generated in the data.

According to one exemplary embodiment, a memory device includes: a parity check circuit configured to perform a first parity check on data sampled according to a data strobe signal, the data strobe signal not including a post-amble; a mask signal generator configured to generate a mask signal based on a write command, wherein the mask signal is active during a time period determined according to a burst length of the data; and an error signal generator configured to receive a parity signal from the host, perform a second parity on a result of the first parity based on the parity signal, and generate a parity error signal based on the mask signal and the result of the second parity.

Drawings

Fig. 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept;

FIG. 2 is a block diagram illustrating the memory device shown in FIG. 1;

FIG. 3 is a block diagram illustrating the first DQS aligner shown in FIG. 2;

FIG. 4 is a block diagram illustrating the first clock Zhong Duiji device shown in FIG. 2;

FIG. 5 is a block diagram illustrating the parity error detection circuit shown in FIG. 2;

FIG. 6 is a circuit diagram showing the parity check circuit shown in FIG. 5;

FIG. 7 is a block diagram illustrating a second parity delay unit shown in FIG. 5;

fig. 8 is a block diagram illustrating a mask signal generator shown in fig. 5;

FIG. 9 is a block diagram illustrating the error signal generator shown in FIG. 5;

FIG. 10 is a timing diagram illustrating signals generated when the memory system shown in FIG. 1 is operating;

FIG. 11 is a timing diagram showing signals generated when the parity error detection circuit shown in FIG. 1 is operating; and

fig. 12 is a block diagram illustrating a user system to which a storage device according to an exemplary embodiment of the inventive concept is applied.

Detailed Description

Some exemplary embodiments of the inventive concept will be described in detail and clearly below to the extent that the inventive concept is easily implemented by those skilled in the art.

Fig. 1 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept. Referring to fig. 1, a memory system 1000 may include a host 1100 and a memory device 1200. For example, memory system 1000 may be a single system that includes both host 1100 and memory device 1200. In some example embodiments, the host 1100 and the storage device 1200 of the memory system 1000 may be implemented by separate devices, respectively.

Host 1100 may be a processor circuit or system that includes a general purpose processor or an application processor. In some example embodiments, host 1100 may be a computing device including one or more processors. For example, the computing device may be a personal computer, a peripheral device, a digital camera, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a smart phone, a tablet, or a wearable device.

Host 1100 may perform training on storage device 1200 at boot (booting) or in certain circumstances. Host 1100 may improve the reliability of data or signal exchanges with memory device 1200 by performing training. For example, host 1100 may write training data to memory device 1200 or read training data from memory device 1200 under various circumstances to determine an optimal clock timing or an optimal reference level.

The storage device 1200 may store data provided from the host 1100 or data to be provided to the host 1100. The storage device 1200 may be implemented as any storage medium including volatile memory or non-volatile memory. For example, where the memory device 1200 includes volatile memory, the volatile memory may include DRAM, static RAM (SRAM), thyristor RAM (TRAM), zero-capacitance RAM (Z-RAM), twin Transistor RAM (TTRAM), or Magnetoresistive RAM (MRAM). The storage device 1200 may be a storage medium including a volatile memory. For example, the memory device 1200 may include unbuffered dual in-line memory modules (UDIMMs), registered DIMMs (RDIMMs), reduced load DIMMs (LRDIMMs), non-volatile DIMMs (NVDIMMs), high Bandwidth Memory (HBM), and the like.

For example, where the memory device 1200 includes a non-volatile memory, the non-volatile memory may be an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, MRAM, spin transfer torque MRAM (STT-MRAM), conductive Bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM (RRAM), polymer RAM (popram), nano Floating Gate Memory (NFGM), holographic memory, molecular electronic memory device, or insulator resistance change memory. One or more bits may be stored in a unit cell of the non-volatile memory. The above examples do not limit the exemplary embodiments.

Hereinafter, for convenience of explanation, it is assumed that the memory device 1200 includes a single memory device. However, as described above, it can be easily understood that the exemplary embodiments are applied to various memory devices.

The storage device 1200 may communicate with a host 1100. For example, the storage device 1200 may communicate with the host 1100 based on one or more of various wired communication protocols (e.g., universal Serial Bus (USB), small Computer System Interface (SCSI), peripheral component interconnect express (PCIe), mobile PCIe (M-PCIe), advanced Technology Attachment (ATA), parallel ATA (PATA), serial ATA (SATA), serial Attached SCSI (SAS), integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), or transmission control protocol/internet protocol (TCP/IP)) or various wireless communication protocols (e.g., long Term Evolution (LTE), worldwide interoperability for microwave access (WiMax), global system for mobile communications (GSM), code Division Multiple Access (CDMA), high Speed Packet Access (HSPA), bluetooth Fi, near Field Communication (NFC), wi-Radio Frequency Identification (RFID)). The above examples do not limit the exemplary embodiments.

The memory device 1200 may perform a read or write operation on the DATA synchronized with the DATA strobe signal DQS in response to the command/address signals CMD/ADDR synchronized with the clock signal CLK from the host 1100. For example, write operations and read operations of the memory device 1200 may be as follows.

In the case of a read operation, an activation command and a row address CMD/ADDR are supplied from the host 1100 to the memory device 1200 together with a clock signal CLK. After the first reference time, a column address is provided from the host 1100 to the memory device 1200. Then, the memory device 1200 provides the requested DATA to the host 1100 after the second reference time.

In the case of a write operation, first, an active command and a row address are supplied from the host 1100 to the memory device 1200 together with the clock signal CLK. After the reference time, a write command and column addresses CMD/ADDR are provided from the host 1100 to the memory device 1200. After that, the DATA to be written is supplied from the host 1100 to the memory device 1200. The memory device 1200 writes the received data in a memory area defined by a column address and a row address.

According to an exemplary embodiment of the inventive concept, the DATA and the DATA strobe signal DQS may be provided from the host 1100 (or the memory device 1200) to the memory device 1200 (or the host 1100). The data strobe signal DQS may be a clock signal. The DATA received by the memory device 1200 is synchronized with the DATA strobe signal DQS. When the memory device 1200 provides DATA to the host 1100, a DATA strobe signal DQS is provided from the memory device 1200 to the host 1100. In addition, when the host 1100 supplies the DATA to the memory device 1200, the DATA strobe signal DQS is supplied from the host 1100 to the memory device 1200.

The data strobe signal DQS may include a preamble and a postamble. The preamble and postamble are signals that allow the memory device 1200 to synchronize, for example, its input buffer (not shown) and/or clock buffer (not shown) with the data strobe signal DQS before and after the memory device 1200 receives data from the host 1100, respectively. In the exemplary embodiments disclosed herein, it is assumed that the data strobe signal DQS does not include the postamble but includes only the preamble.

According to an exemplary embodiment of the inventive concept, the memory device 1200 may include a parity error detection circuit 1220. The parity error detection circuit 1220 may perform parity checking on data to be written to the memory device 1200 through a write operation. Hereinafter, data to be written to the memory device 1200 by a write operation is referred to as "write data". The write data may be synchronized within the memory device 1200 by a data strobe signal DQS provided from the host 1100.

The parity error detection circuit 1220 may be supplied with the parity signal PRT from the host 1100, and may perform additional parity on the write data using the parity signal PRT. Additional parity performed on write data using the parity signal PRT will be described with reference to fig. 9. The parity error detection circuit 1220 may provide the parity output signal P _ out as the parity result to the host 1100.

The parity error detection circuit 1220 may perform parity checking on data aligned based on the data strobe signal DQS and output a parity output signal P _ out as a parity result. In the case where the data strobe signal DQS includes the postamble, since the parity error detection circuit 1220 operates in synchronization with the data strobe signal DQS, the parity output signal P _ out including the result of parity checking the last bit of the write data may be reset by the postamble of the data strobe signal DQS.

However, as described above, according to an exemplary embodiment of the inventive concept, the data strobe signal DQS may not include the postamble. Accordingly, the parity output signal P _ out including the parity result for the last bit of the write data may not be reset by the data strobe signal DQS. Accordingly, the parity output signal P _ out including the parity result for the last bit of the write data may be maintained without being reset by the data strobe signal DQS. If the parity output signal P _ out is not reset at the edge of the data strobe signal DQS, the memory device 1200 does not conform to the communication protocol of the memory system 1000 defined by the Standard Specification of the Joint Electron Devices Engineering Committee (JEDEC).

According to an exemplary embodiment of the inventive concept, the parity error detection circuit 1220 may adjust a period of outputting the parity output signal P _ out according to the burst length BL based on the data strobe signal DQS not including the postamble. Herein, the burst length BL denotes the amount of serial data continuously exchanged between the memory device 1200 and the host 1100.

The configuration of the parity error detection circuit 1220 that adjusts the period of outputting the parity output signal P _ out based on the burst length BL and the memory device 1200 including the parity error detection circuit 1220 are described above. With the above-described configuration, even if the data strobe signal DQS without the postamble is supplied to the memory device 1200, the memory device 1200 may output the parity output signal P _ out during a period determined according to the burst length BL. Thus, the memory device 1200 can conform to the communication protocol of the memory system 1000 defined by the JEDEC standard specification.

Fig. 2 is a block diagram illustrating the memory device 1200 shown in fig. 1. Fig. 2 will be described with reference to fig. 1. Referring to fig. 2, the memory device 1200 may include: data input driver 1210, first and

second DQS aligners

1211 and 1213, first and second clocks Zhong Duiji and 1212 and 1214, parity error detection circuit 1220, mode register 1230, clock buffer 1240, memory cell array 1250, command/address latch 1260, command decoder 1270, and data output driver 1280.

When the memory device 1200 executes a write command, the DATA input driver 1210 receives write DATA and a DATA strobe signal DQs from the host 1100 through a DQ pad DQ _ p and a DQs pad DQs _ p, respectively. As described above, the data strobe signal DQS may not include the postamble. The data input driver 1210 may output the received write data and the received data strobe signal DQS as the internal data DQ _ i and the internal DQS signal DQS _ i, respectively.

The first DQS aligner 1211 may align the internal data DQ _ i with the internal DQS signal DQS _ i. For example, the first DQS aligner 1211 may sample the internal data DQ _ i on rising and falling edges of the internal DQS signal DQS _ i, respectively, and output the internal data DQ _ i to be divided into odd data and even data aligned with the internal DQS signal DQS _ i. The odd data represents odd-numbered data of the internal data DQ _ i, and the even data represents even-numbered data of the internal data DQ _ i.

The first clock Zhong Duiji device 1212 may sample and align odd data and even data of the internal data DQ _ i by the internal clock signal CLK _ i. The first time Zhong Duiji device 1212 may output the data aligned by the internal clock signal CLK _ i as odd aligned data D _ od and even aligned data D _ ev. The odd alignment data D _ od and the even alignment data D _ ev may be provided to each of the parity error detection circuit 1220 and the sense amplifier 1251.

The second DQS aligner 1213 may sample and align the parity signal PRT supplied from the host 1100 through the parity pad PRT _ p by the internal DQS signal DQS _ i. Although not shown in fig. 2, the memory device 1200 may further include an input driver for receiving the parity signal PRT. The second clock aligner 1214 may sample and align the parity signal PRT sampled by the internal DQS signal DQS _ i through the internal clock signal CLK _ i. The second clock aligner 1214 may output the parity signal PRT aligned by the internal clock signal CLK _ i as an internal parity signal PRT _ i.

The parity error detection circuit 1220 may perform parity checking on the odd alignment data D _ od and the even alignment data D _ ev by using the internal clock signal CLK _ i. The parity error detection circuit 1220 may be supplied with the inner parity signal PRT _ i and perform additional parity on data by using the inner parity signal PRT _ i.

In addition, the parity error detection circuit 1220 may be supplied with the decoded pulse write command PWY from the command decoder 1270 and the parity delay PL and the burst length BL from the mode register 1230. The parity error detection circuit 1220 may generate a mask signal (not shown) for adjusting a period of outputting the parity output signal P _ out based on the decoded pulse write command PWY and the burst length BL of the data. That is, the period of time for which the parity output signal P _ out is output may be adjusted by the mask signal. The parity error detecting circuit 1220 may adjust an output timing point of the parity output signal P _ out based on the parity delay PL. The parity output signal P _ out may be provided to the host 1100 through the parity output pad DERR.

Mode register 1230 may store information provided from command decoder 1270. For example, the mode register 1230 may store the parity delay PL and the burst length BL supplied from the command decoder 1270. In addition, the mode register 1230 may provide the parity error detection circuit 1220 with the parity delay PL and the burst length BL.

The clock signal CLK and the clock bar signal CLKb may be provided from the host 1100 to the clock buffer 1240 through the clock pad CLK _ p and the clock bar pad CLKb _ p. For example, clock buffer 1240 may be implemented with a differential input buffer. The clock buffer 1240 may generate the internal clock signal CLK _ i based on the clock signal CLK and the clock bar signal CLKb. The internal clock signal CLK _ i may be provided to the parity error detection circuit 1220, the first Zhong Duiji device 1212 and the second clock aligner 1214, and the command decoder 1270.

Data stored in the memory cell array 1250 may be provided to the data output driver 1280 through the sense amplifier 1251. In some example embodiments, the odd alignment data D _ od and the even alignment data D _ ev may be stored in the memory cell array 1250 by the sense amplifier 1251. An address of a memory cell to which data supplied from the host 1100 is to be stored may be supplied to the memory cell array 1250 through a command/address latch 1260, a row decoder 1252, and a column decoder 1253.

The command/address latch 1260 receives command signals CMD and address signals ADDR from the host 1100 through the command/address pad CA _ p. The command/address latch 1260 may provide the received command CMD to the command decoder 1270. In addition, a command/address latch 1260 may provide received addresses to a row decoder 1252 and a column decoder 1253. Various commands may be provided to the command decoder 1270 through the command/address latch 1260. The command decoder 1270 may provide decoded commands to elements such as the parity error detection circuit 1220, the mode register 1230, the row decoder 1252, and the column decoder 1253.

The data output driver 1280 may output data stored in the memory cell array 1250 to the host 1100 through the DQ pad DQ _ p. To this end, the row decoder 1252 and the column decoder 1253 may provide an address of a memory cell storing data to be output to the memory cell array 1250. In addition, when the data output driver 1280 outputs data to the host 1100, the data output driver 1280 may provide the data strobe signal DQS to the host 1100 through the DQS pad DQS _ p.

Fig. 3 is a block diagram illustrating the first DQS aligner 1211 shown in fig. 2. Fig. 3 will be described with reference to fig. 2. Referring to fig. 3, the first DQS aligner 1211 may include a first flip-flop FF1 and a second flip-flop FF2.

The first flip-flop FF1 may be provided with internal data DQ _ i as a data input D and an internal data strobe signal DQs _ i as a clock input CK. The first flip-flop FF1 may sample the internal data DQ _ i by a rising edge of the internal data strobe signal DQS _ i. Odd-numbered data of the internal data DQ _ i may be sampled by a rising edge of the internal data strobe signal DQS _ i, and the first flip-flop FF1 may output the sampled data as the odd data DD _ od.

The second flip-flop FF2 may be supplied with the internal data DQ _ i as a data input D and a bar signal (bar signal) of the internal data strobe signal DQs _ i as a clock input CK. The second flip-flop FF2 may sample the internal data DQ _ i through a falling edge of the internal data strobe signal DQS _ i. Even-numbered data of the internal data DQ _ i may be sampled by a falling edge of the internal data strobe signal DQS _ i, and the second flip-flop FF2 may output the sampled data as even data DD _ ev.

Accordingly, the first and second flip-flops FF1 and FF2 may sample and align the internal data DQ _ i by the rising and falling edges of the internal data strobe signal DQS _ i, respectively. The first and second flip-flops FF1 and FF2 may output odd data DD _ od and even data DD _ ev, respectively, based on the sampled data.

The second DQS aligner 1213 shown in fig. 2 may include the same configuration as the first DQS aligner 1211. The parity signal PRT may be provided from the host 1100 to the second DQS aligner 1213 through the parity pad PRT _ p, and the second DQS aligner 1213 may sample the parity signal PRT through the rising and falling edges of the internal data strobe signal DQS _ i. The second DQS aligner 1213 may output an odd check signal (not shown) and an even check signal (not shown) based on the sampled parity signal PRT, respectively.

FIG. 4 is a block diagram illustrating the first clock Zhong Duiji device shown in FIG. 2. Fig. 4 will be described with reference to fig. 2. Referring to fig. 4, the first time Zhong Duiji device 1212 may include a first flip-flop FF1 and a second flip-flop FF2.

The first flip-flop FF1 may be provided with the odd data DD _ od as the data input D and the internal clock signal CLK _ i as the clock input CK. The first flip-flop FF1 may sample the odd data DD _ od by a rising edge of the internal clock signal CLK _ i. The first flip-flop FF1 may output the sampled data as odd alignment data D _ od.

The second flip-flop FF2 may be provided with even data DD _ ev as a data input D and an internal clock signal CLK _ i as a clock input CK. The second flip-flop FF2 may sample the even data DD _ ev by a rising edge of the internal clock signal CLK _ i. The second flip-flop FF2 may output the sampled data as even alignment data D _ ev.

Accordingly, the first and second flip-flops FF1 and FF2 may sample and align the odd data DD _ od and the even data DD _ ev, respectively, by a rising edge of the internal clock signal CLK _ i and output the sampled data as the odd aligned data D _ od and the even aligned data D _ ev.

The second clock aligner 1214 shown in fig. 2 may include the same configuration as the first clock Zhong Duiji device 1212. Second clock aligner 1214 may be provided with odd and even check signals (not shown) from second DQS aligner 1213 and may sample the odd and even check signals by the rising edge of internal clock signal CLK-i. The second DQS aligner 1213 may output the sampled signals as an odd aligned parity signal (not shown) and an even pair Ji Jiou parity signal (not shown).

Fig. 5 is a block diagram illustrating the parity error detection circuit shown in fig. 2. The block diagram of fig. 5 will be described with reference to fig. 1 and 2. Referring to fig. 5, the parity error detection circuit 1220 may include a parity circuit 1221, first and second

parity delay circuits

1222 and 1223, and a mask circuit 1224.

The parity circuit 1221 may be supplied with odd alignment data D _ od [ N:0] and even alignment data D _ ev [ N:0]. Here, the number of bits "N" may depend on the width of a data bus of the memory device 1200. For example, in the case where the memory device 1200 includes a data bus connected to "M" DQ pads DQ _ p, the bit number "N" may be "M".

Hereinafter, the number of bits "N" is assumed to be "3". Accordingly, the memory device 1200 includes first to fourth DQ pads DQ _ p [3:0]. The odd alignment data D _ od [0] and the even alignment data D _ ev [0] are data generated by aligning data supplied through the first DQ pad DQ _ p [0] through the internal DQS signal DQS _ i and the internal clock signal CLK _ i. As described above, the odd alignment data D _ od [3:1] and even alignment data D _ ev [3:1] is a signal generated by transmitting a signal through fourth to second DQ pads DQ _ p [3:1] data generated by aligning the supplied data.

The parity circuit 1221 may perform parity checking on the supplied data. The parity circuit 1221 may output the parity result as the first odd error signal ERR1_ od and the first even error signal ERR1_ ev, respectively. The configuration of the first parity circuit 1221 will be described with reference to fig. 6.

The first parity delay circuit 1222 may be provided with the internal clock signal CLK _ i from the clock buffer 1240. The first parity delay circuit 1222 may delay each of the first odd error signal ERR1_ od and the first even error signal ERR1_ ev by a multiple of the period of the internal clock signal CLK _ i based on the parity delay PL. The first parity delay circuit 1222 may output the delayed signals as a delayed odd error signal ERRd _ od and a delayed even error signal ERRd _ ev.

The second parity delay circuit 1223 may be provided with the internal clock signal CLK _ i from the clock buffer 1240. In addition, the second parity delay circuit 1223 may be supplied with the decoded pulsed write command PWY from the command decoder 1270. The second parity delay circuit 1223 may delay the decoded pulsed write command PWY by a multiple of the period of the internal clock signal CLK _ i based on the parity delay PL. The second parity delay circuit 1223 may output the delayed command as a delayed decoded pulse write command PWYd. The configuration of the second parity delay circuit 1223 will be described with reference to fig. 7.

Masking circuitry 1224 may be provided with delayed odd error signal ERRd _ od, delayed even error signal ERRd _ ev, delayed decoded pulse write command PWYd, internal clock signal CLK _ i, and burst length BL. The mask circuit 1224 may generate a parity output signal P _ out indicating whether a parity error is generated in the data based on the provided signal. The mask circuit 1224 may output the parity output signal P _ out during a time period determined according to the burst length BL.

The mask circuit 1224 may include a mask signal generator 1225 and an error signal generator 1226. The mask signal generator 1225 may be supplied with the delayed decoding pulse write command PWYd and the burst length BL. The MASK signal generator 1225 may generate the MASK signal MASK by adjusting the pulse of the delayed decoding pulse write command PWYd based on the burst length BL. The configuration of the mask signal generator 1225 will be described with reference to fig. 8.

Error signal generator 1226 may be provided with delayed odd error signal ERRd _ odd, delayed even error signal ERRd _ ev, and MASK signal MASK. The error signal generator 1226 may also be provided with an inner parity signal PRT _ i. The inner parity signal PRT _ i may include an odd parity signal PRTi _ odd and an even parity signal PRTi _ ev. The error signal generator 1226 may determine whether the parity error of the write data is a parity error of odd data of the write data or a parity error of even data of the write data based on the odd check signal PRTi _ odd and the even check signal PRTi _ ev.

The error signal generator 1226 may perform parity checking on the write data based on the delayed odd error signal ERRd _ odd, the delayed even error signal ERRd _ ev, and the inner parity signal PRT _ i. The error signal generator 1226 may output the parity result as the parity output signal P _ out during activation of the MASK signal MASK. The configuration of the error signal generator 1226 will be described with reference to fig. 9.

Fig. 6 is a circuit diagram showing the parity check circuit shown in fig. 5. The circuit diagram of fig. 6 will be described with reference to fig. 1 and 5. Referring to fig. 6, the parity circuit 1221 may include first to sixth exclusive-or logics XOR1 to XOR6.

As described above, the parity circuit 1221 may check the odd alignment data D _ od [3:0] and even alignment data D _ ev [3: parity of 0]. For example, data may be provided from host 1100 to storage device 1200 in a parity scheme. In this case, odd alignment data D _ od [3:0] so that the same-position bits (hereinafter referred to as "bit string") have an even number of logical "1 s". Further, even alignment data D _ ev [3:0], such that the bit string comprises an even number of logical "1 s".

For example, in the case where data is provided from host 1100 in an even parity scheme, "1011" may be provided as even alignment data D _ ev [0], "1001" may be provided as even alignment data D _ ev [1], "1100" may be provided as even alignment data D _ ev [2], and "1111" may be provided as even alignment data D _ ev [3]. In this case, even alignment data D _ ev [3:0] is "1111". Since the number of logic "1" is an even number, no parity error is generated. Further, even alignment data D _ ev [3:0] and even alignment data D _ ev [3: data of the third bit string of 0] are "0011" and "1001", respectively. Since the number of logical "1" included in the data of each of the second bit string and the third bit string is an even number, no parity error is generated. Even alignment data D _ ev [3: data of the fourth bit string of 0] is "1101". Since the number of logical "1" contained in the data of the fourth bit string is an odd number, a parity error is generated.

The above example describes a case where data is provided from the host 1100 to the memory device 1200 in the even parity scheme. In some exemplary embodiments, data may be provided from the host 1100 to the storage device 1200 in an odd parity scheme. In this case, odd alignment data D _ od [3:0] and even alignment data D _ ev [3:0] such that the identically located bit string includes an odd number of logical "1 s". In the following, it is assumed that the memory system 1000 of fig. 1 exchanges data in an even parity scheme.

The first exclusive or logic XOR1, the second exclusive or logic XOR2, and the fifth exclusive or logic XOR5 may check the odd alignment data D _ od [3: parity of 0]. The parity result may be output as the first odd error signal ERR1_ od. The third, fourth and sixth exclusive-or logic XOR3, XOR4 and XOR6 may check the even alignment data D _ ev [3:0]. The parity result may be output as the first even error signal ERR1_ ev.

For example, when the odd alignment data D _ od [3:0], a first odd error signal ERR1_ od having logic '1' may be output. When even alignment data D _ ev [3: when the parity error is generated in 0], the first even error signal ERR1_ ev having logic "1" may be output.

In contrast, in the memory system 1000 using the odd parity scheme, when the parity data D _ od [3:0] or even alignment data D _ ev [3:0], a value (e.g., logic '0') of the first odd error signal ERR1_ od or the first even error signal ERR1_ ev may be opposite to a value in the case where the memory system 1000 uses the even parity scheme.

Fig. 7 is a block diagram illustrating a second parity delay circuit shown in fig. 5. Fig. 7 will be described with reference to fig. 5. Referring to fig. 7, the second parity delay circuit 1223 may include first to fourth multiplexers MUX1 to MUX4 and first to fourth flip-flops FF1 to FF4.

The first multiplexer MUX1 may select and output one of the decoded pulsed write command PWY or the output signal of the second flip-flop FF2 based on the parity delay PL [ 0]. The output signal of the first multiplexer MUX1 may be provided to a first flip-flop FF1. The first flip-flop FF1 may sample the output signal of the first multiplexer MUX1 by the internal clock signal CLK _ i and output the sampled signal as a signal having a length of one cycle of the internal clock signal CLK _ i. The output signal may be supplied to the mask signal generator 1225 as the delayed decoded pulse write command PWYd.

Similar to in the first multiplexer MUX1, the second multiplexer MUX2 may select and output one of the output signals of the decoded pulsed write command PWY or the third flip-flop FF3 based on the parity delay PL [1], and the third multiplexer MUX3 may select and output one of the output signals of the decoded pulsed write command PWY or the fourth flip-flop FF4 based on the parity delay PL [2 ]. The output signal of the second multiplexer MUX2 may be provided to a second flip-flop FF2. The output signal of the third multiplexer MUX3 may be provided to a third flip-flop FF3. The second and third flip-flops FF2 and FF3 may sample output signals of the second and third multiplexers MUX2 and MUX3 by the internal clock signal CLK _ i, respectively, and output the sampled signals as a signal having a length of one cycle of the internal clock signal CLK _ i.

The fourth multiplexer MUX4 may provide one of the decoded pulsed write command PWY or the ground voltage GND to the fourth flip-flop FF4 based on the parity delay PL [3]. The fourth flip-flop FF4 may sample the output signal of the fourth multiplexer MUX4 by the internal clock signal CLK _ i and output the sampled signal as a signal having a length of one cycle of the internal clock signal CLK _ i.

In the case where the parity delay PL [0] is activated, the decoded pulse write command PWY may be supplied to the first flip-flop FF1 through the first multiplexer MUX1 (and not through the second to fourth flip-flops FF2 to FF 4). Thus, the decoded pulsed write command PWY may be sampled by the first rising edge of the internal clock signal CLK _ i without delay. The sampled decoded pulse write command PWY may be converted without delay into a pulse signal of one cycle in length of the internal clock signal CLK _ i, and the converted signal may be output as the delayed decoded pulse write command PWYd.

With the parity delay PL [1] activated, the decoded pulsed write command PWY may be provided to the second flip-flop FF2 through the second multiplexer MUX 2. The decoded pulse write command PWY may be converted by the second flip-flop FF2 and output as a pulse signal of one cycle of the length of the internal clock signal CLK _ i. The output signal may be output as a delayed decoded pulse write command PWYd through the first multiplexer MUX1 and the first flip-flop FF1. That is, the decode pulse write command PWY may be output as the delayed decode pulse write command PWYd after being delayed by one cycle of the internal clock signal CLK _ i by the first and second flip-flops FF1 and FF2.

As described above, in the case where the parity delay PL [2] is activated, the decoded pulse write command PWY may be provided to the third flip-flop FF3 through the third multiplexer MUX 3. The pulse signal sampled by the third flip-flop FF3 may be output as a delayed decoded pulse write command PWYd through the second multiplexer MUX2, the second flip-flop FF2, the first multiplexer MUX1, and the first flip-flop FF1. Accordingly, the decode pulse write command PWY may be output as the delayed decode pulse write command PWYd after being delayed by two cycles of the internal clock signal CLK _ i by the first to third flip-flops FF1 to FF3.

With the parity delay PL [3] activated, the decode pulse write command PWY may be provided to the fourth flip-flop FF4 through the fourth multiplexer MUX 4. The pulse signal sampled by the fourth flip-flop FF4 may be output as a delayed decoded pulse write command PWYd through the third multiplexer MUX3, the third flip-flop FF3, the second multiplexer MUX2, the second flip-flop FF2, the first multiplexer MUX1, and the first flip-flop FF1. Accordingly, the decode pulse write command PWY may be output as the delayed decode pulse write command PWYd after being delayed by three cycles of the internal clock signal CLK _ i by the first to fourth flip-flops FF1 to FF4.

The configuration of the first parity delay circuit 1222 may be the same as or substantially similar to the configuration of the second parity delay circuit 1223. The first parity delay circuit 1222 may be supplied with each of the first odd error signal ERR1_ od and the first even error signal ERR1_ ev, and the first parity delay circuit 1222 may delay the first odd error signal ERR1_ od and the first even error signal ERR1_ ev by a multiple of a period of the internal clock signal CLK _ i based on the parity delay PL. The first parity delay circuit 1222 may output the delayed signals as a delayed odd error signal ERRd _ od and a delayed even error signal ERRd _ ev. As will be appreciated by those skilled in the art, the first parity delay circuit 1222 is configured with reference to the configuration of the second parity delay circuit 1223 shown in fig. 7.

Fig. 8 is a block diagram illustrating a mask signal generator shown in fig. 5. The block diagram of fig. 8 will be described with reference to fig. 2 and 5. Referring to fig. 8, the mask signal generator 1225 may include a frequency divider 12251 and a multiplexer MUX.

The delayed decoded pulse write command PWYd and the internal clock signal CLK _ i may be supplied to the frequency divider 12251. The frequency divider 12251 may convert the delayed decoded pulse write command PWYd into a pulse signal having a length twice the period of the internal clock signal CLK _ i based on the internal clock signal CLK _ i and the delayed decoded pulse write command PWYd.

Based on the burst length BL, the multiplexer MUX may output one of the following signals as a MASK signal MASK: a decoded pulse write command PWYd whose pulse is one cycle of the internal clock signal CLK _ i delayed, and a signal converted by the frequency divider 12251 and whose pulse is two cycles of the internal clock signal CLK _ i. For example, in the case where the burst length BL is "2", the multiplexer MUX may output the decoded pulse write command PWYd whose pulse is one cycle of the internal clock signal CLK _ i as the MASK signal MASK. As another example, in the case where the burst length BL is "4", the multiplexer MUX may output a signal converted by the frequency divider 12251 and having a pulse of two cycles of the internal clock signal CLK _ i as the MASK signal MASK.

Fig. 9 is a block diagram illustrating the error signal generator shown in fig. 5. The block diagram of fig. 9 will be described with reference to fig. 2 and 5. Referring to fig. 9, the error signal generator 1226 may include first and second exclusive-or logics XOR1 and XOR2, NOR logic NR, and NAND logic ND.

The first exclusive-or logic XOR1 may perform an exclusive-or operation on the delayed odd error signal ERRd _ od and the odd parity signal PRTi _ od. The second exclusive-or logic XOR2 may perform an exclusive-or operation on the delayed even error signal ERRd _ ev and the even check signal PRTi _ ev. As described above, the error signal generator 1226 may determine whether a parity error of write data is a parity error of odd data of the write data or a parity error of even data of the write data based on the odd check signal PRTi _ odd and the even check signal PRTi _ ev.

For example, when a parity error of odd data of write data is generated, the delayed odd error signal ERRd _ od having logic "1" may be output, thereby outputting the parity output signal P _ out having logic "1". The host 1100 may not recognize which of the odd check signal PRTi _ odd and the even check signal PRTi _ ev causes a logical "1" to be output. In some exemplary embodiments, the host 1100 may be configured to sequentially supply the odd parity signal PRTi _ odd of logic "1" and the even parity signal PRTi _ ev of logic "1" to the error signal generator 1226. If the odd check signal PRTi _ od has a logic "1", the parity output signal P _ out may have a logic "0". Thus, the host 1100 can determine that a parity error has occurred in odd data of the write data.

The NOR logic NR may perform a NOR operation on the output signals of the first exclusive or logic XOR1 and the second exclusive or logic XOR 2. That is, the NOR logic NR may output the result of performing an or operation on the delayed odd error signal ERRd _ od, the odd parity signal PRTi _ od, the delayed even error signal ERRd _ ev, and the even parity signal PRTi _ ev. Accordingly, the NOR logic NR can output a parity result obtained by performing additional parity on the parity result of the write data by using the parity signal PRT.

The NAND logic ND may perform a NAND operation on the output signals of the MASK signal MASK and the NOR logic NR. Through the above description, the NAND logic ND can output an inverted signal of the output signal of the NOR logic NR to the pulse width of the MASK signal MASK. As described above, the pulse width of the MASK signal MASK may be adjusted according to the burst length BL. This means that the NAND logic ND can output an inverted signal of the output signal of the NOR logic NR during a period of time determined according to the burst length BL.

Fig. 10 is a timing diagram illustrating signals generated when the memory system shown in fig. 1 operates. The timing diagram of fig. 10 will be described with reference to fig. 1, 2, and 5. Referring to fig. 10, after the second data D2 is supplied, the parity output signal P _ out generated based on the data strobe signal DQS not including the postamble is maintained. Here, it is assumed that the burst length BL is "2" and the parity delay time "PL" is "0".

At a time point t1, the memory device 1200 may receive a write command WR, clock signals CLK and CLKb, and a preamble of the data strobe signal DQS from the host 1100. The command/address latch 1260 may sample the write command WR by the clock signals CLK and CLKb. The memory device 1200 may perform a write operation by the sampled write command WR. Assuming that the write delay CWL is "1", the first data D1 may be provided at a time point t2 after one cycle of the clock signal CLK has elapsed from the time point t 1.

At a time point t2, the memory device 1200 may receive the first data D1 from the host 1100. The first DQS aligner 1211 of the memory device 1200 may sample the first data D1 by a rising edge of the data strobe signal DQS and output the sampled data as the odd data DD _ od. At a time point t3, the memory device 1200 may receive the second data D2 from the host 1100. The first DQS aligner 1211 of the memory device 1200 may sample the second data D2 through a falling edge of the data strobe signal DQS and output the sampled data as the even data DD _ ev.

At time point t4, the first time Zhong Duiji and 1212 of the memory device 1200 may sample odd data DD _ od and even data DD _ ev, respectively, by a rising edge of the clock signal CLK and output the sampled data as odd alignment data D _ od and even alignment data D _ ev, respectively. The parity error detection circuit 1220 may generate a parity output signal P _ out based on the odd alignment data D _ od and the even alignment data D _ ev. In the example of fig. 10, if the mask circuit 1224 of the parity error detection circuit 1220 does not operate, the parity output signal P _ out continuously maintains the same parity error result even after the time point t 5.

FIG. 11 is a timing diagram illustrating signals generated when the parity error detection circuit shown in FIG. 1 is operating. The timing diagram of fig. 11 will be described with reference to fig. 1, 2, 5, and 10. Similar to the example of FIG. 10, in the example of FIG. 11, a data strobe signal DQS that does not include a postamble may be provided from the host 1100 to the memory device 1200. In the example of fig. 11, it is assumed that the burst length BL is "2" and the parity delay time "PL" is "0".

In contrast to the example of fig. 10, in the example of fig. 11, the parity output signal P _ out may be generated based on the data strobe signal DQS not including the post-amble, and the parity output signal P _ out is output during one cycle of the clock signal CLK through the MASK signal MASK generated by the MASK circuit 1224. The operation of the memory device 1200 from t1 to t3 is the same as that described with reference to fig. 10, and thus a description thereof is omitted.

At time point t4, the parity error detection circuit 1220 may generate a delayed error signal ERRd based on the odd alignment data D _ od and the even alignment data D _ ev. As described above, the delayed error signal ERRd may include a delayed odd error signal ERRd _ od and a delayed even error signal ERRd _ ev. The decoded pulse write command PWY may be provided to the second parity delay unit 1223, and the second parity delay unit 1223 may delay the decoded pulse write command PWY, thereby outputting the delayed decoded pulse write command PWYd. However, in the example of fig. 11, since the parity delay PL is assumed to be "0", the delayed decoded pulse write command PWYd can be output without delay at a time point t 4.

Subsequently, the MASK signal generator 1225 may generate a MASK signal MASK based on the delayed decoding pulse write command PWYd and the burst length BL. In the example of fig. 11, since the burst length BL is assumed to be "2", the MASK signal MASK may include pulses having a length of one cycle of the clock signal CLK. The error signal generator 1226 may generate the parity output signal P _ out based on the delayed odd error signal ERRd _ od and the delayed even error signal ERRd _ ev and output the parity output signal P _ out during a time period corresponding to a pulse width of the MASK signal MASK. After the time point t5, the error signal generator 1226 may stop outputting the parity output signal P _ out.

Accordingly, even if the data strobe signal DQS without the postamble is supplied to the memory device 1200, the memory device 1200 may output the parity output signal P _ out during a period determined according to the burst length BL.

Fig. 12 is a block diagram illustrating a user system to which a storage device according to an exemplary embodiment of the inventive concept is applied. Referring to fig. 12, the user system 10000 may include an application processor 11000, a memory 12000, a network interface 13000, a storage device 14000, and a user interface 15000.

The application processor 11000 may drive elements included in the user system 10000 and an operating system. For example, the application processor 11000 may include a controller for controlling elements, interfaces, a graphic engine, etc. of the user system 10000. The application processor 11000 may be implemented using a system on chip (SoC).

The memory 12000 can be used as a main memory, a work memory, a buffer memory, or a cache memory of the user system 10000. The memory 12000 may be implemented with volatile random access memory (e.g., DRAM, SDRAM, double-rate (DDR) SDRAM, DDR2SDRAM, DDR3SDRAM, low-power DDR (LPDDR) SDRAM, LPDDR2SDRAM, LPDDR3SDRAM, or High Bandwidth Memory (HBM) or non-volatile random access memory (e.g., phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or Ferroelectric RAM (FRAM)).

For example, the controller and the memory 12000 included in the application processor 11000 may constitute the memory system 1000 described with reference to fig. 1 to 11. For example, a controller included in the application processor 11000 may correspond to the host 1100 of fig. 1, and the memory 12000 may correspond to the storage device 1200 of fig. 1. That is, the memory 12000 may include the parity error detection circuit 1220 shown in fig. 1 that performs a parity error detection operation.

The network interface 13000 can communicate with external devices. For example, network interface 13000 may support wireless communications (e.g., code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time Division Multiple Access (TDMA), long Term Evolution (LTE), wiMax, wireless Local Area Network (WLAN), ultra Wideband (UWB), bluetooth, and/or wireless display (WI-DI)). Here, the network interface 13000 may be included in the application processor 11000.

Storage device 14000 may store data. For example, the storage device 14000 may store data received from the application processor 11000. In some example embodiments, the storage device 14000 may transmit data stored therein to the application processor 11000. For example, the storage device 14000 may be implemented as a nonvolatile semiconductor memory device (e.g., PRAM, MRAM, RRAM, NAND flash, NOR flash, or three-dimensional NAND flash).

The user interface 15000 may include an interface to input data or commands to the application processor 11000 or output data to an external device. For example, the user interface 15000 may include a user input interface (e.g., a keyboard, a keypad, buttons, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, or a piezoelectric element). The user interface 15000 may also include a user output interface (e.g., a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display device, an Active Matrix OLED (AMOLED) display device, a Light Emitting Diode (LED), a speaker, or a motor).

According to an exemplary embodiment of the inventive concept, even if a memory device including a parity error detection circuit receives a data strobe signal without a postamble, a parity output signal may be output during a period of time determined according to a burst length.

Although the present inventive concept has been described with reference to some exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present inventive concept. Accordingly, it should be understood that the above-described exemplary embodiments are not restrictive, but illustrative.

Claims

1. A memory device, comprising:

a parity check circuit configured to perform parity checking on data sampled according to a data strobe signal, the data strobe signal not including a post-amble; and

a mask circuit configured to generate a parity error signal based on a result of parity and output the parity error signal during a time period determined according to a burst length of the data,

wherein the masking circuit comprises:

a mask signal generator configured to generate a mask signal based on a write command, the mask signal being active during a time period determined according to a burst length of the data; and

an error signal generator configured to generate the parity error signal based on the mask signal and a result of the parity.

2. The memory device of claim 1, wherein the parity circuit comprises exclusive-or logic configured to perform an exclusive-or operation on odd data and even data of the data.

3. The memory device of claim 1, further comprising:

a parity delay circuit configured to delay the write command based on a parity delay and provide the delayed write command to the mask signal generator.

4. The memory device of claim 1, wherein the mask circuit is configured to receive a parity signal from a host and to generate the parity error signal by performing an additional parity check on a result of the parity check based on the parity signal.

5. The memory device of claim 4, further comprising:

a parity delay circuit configured to delay a result of the parity based on a parity delay and provide the delayed result of the parity to the mask circuit.

6. The memory device of claim 4, wherein the masking circuit is configured to receive the parity signal and a result of the parity delayed according to a parity delay.

7. The memory device of claim 4,

the mask circuit includes:

a mask signal generator configured to generate a mask signal based on a write command, the mask signal including a pulse signal, the mask signal being active during a time period determined according to a burst length of the data, an

An error signal generator comprising:

a first exclusive OR logic configured to perform an exclusive OR operation on a result of parity of odd data among the data and an odd check signal of the parity signal; and

a second exclusive OR logic configured to perform an exclusive OR operation on a result of parity of even data among the data and an even signal of the parity signal; and

the error signal generator is configured to generate an error signal,

generating the parity error signal based on the mask signal, an

And outputting signals of the first exclusive-OR logic and the second exclusive-OR logic.

8. The memory device of claim 1, wherein the masking circuit comprises:

an error signal generator configured to receive a parity signal from a host and generate the parity error signal based on the parity signal, the mask signal, and a result of the parity.

9. A memory device, comprising:

an aligner configured to sample data by a data strobe signal, the data strobe signal not including a post-amble; and

a parity error detection circuit configured to detect a parity error in the data stream,

performing a parity check on the data sampled by the aligner to generate a parity error signal; and

outputting the parity error signal during a time period determined according to a burst length of the data, the parity error signal indicating whether a parity error is generated in the data,

wherein the parity error detection circuit comprises:

10. The memory device of claim 9, wherein the error signal generator is further configured to,

receiving a parity signal from a host; and

generating the parity error signal by performing an additional parity on a result of the parity based on the parity signal.

11. The memory device of claim 10, wherein the parity error detection circuit comprises:

a first parity delay unit configured to delay the write command based on a parity delay and provide the delayed write command to the mask signal generator, an

A second parity delay unit configured to delay a result of the parity based on the parity delay and provide the delayed result of the parity to the error signal generator,

wherein the error signal generator is configured to receive the parity signal and a result of the parity delayed according to the parity delay.

12. The memory device of claim 11, further comprising:

a mode register configured to store information of a parity latency from the host and to provide the stored information of the parity latency to the parity error detection circuitry.

13. The memory device of claim 9, further comprising:

a mode register configured to store information of a burst length from a host and to provide the stored information of the burst length to the parity error detection circuit.

14. A memory device, comprising:

a parity check circuit configured to perform a first parity check on data sampled according to a data strobe signal, the data strobe signal not including a post-amble;

an error signal generator configured to generate, based on the error signal,

a parity signal is received from the host and,

performing a second parity check on the result of the first parity check based on the parity check signal, an

A parity error signal is generated based on the mask signal and a result of the second parity.

15. The memory device of claim 14, further comprising:

an aligner configured to sample the data by the data strobe signal and to provide the sampled data to the parity circuit.

16. The memory device of claim 14, further comprising:

a first parity delay unit configured to delay the write command based on a parity delay and provide the delayed write command to the mask signal generator; and

a second parity delay unit configured to delay a result of the first parity based on the parity delay and provide the delayed result of the first parity to the error signal generator.

17. The memory device of claim 16, wherein the error signal generator is configured to receive a result of the first parity that has been delayed by the second parity delay unit according to the parity delay.

18. The memory device of claim 16,

an error signal generator comprising:

a first XOR logic configured to perform an XOR operation on a result of a first parity of odd data among the data and an odd check signal of the parity signal, an

A second exclusive OR logic configured to perform an exclusive OR operation on a result of a first parity of even data among the data and an even signal of the parity signals; and

an error signal generator configured to generate the parity error signal based on the mask signal and output signals of the first and second exclusive OR logics.