CN109754841A - Memory device including parity error detection circuit - Google Patents
Memory device including parity error detection circuit Download PDFInfo
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Abstract
Provide a kind of memory device including parity checker and mask circuit.Parity checker can execute even-odd check to the data sampled according to data strobe signal, wherein the data strobe signal does not include postamble.The mask circuit can generate parity errors error signal based on the result of even-odd check, and export the parity errors error signal during the period determined according to the burst-length of the data.
Description
Technical field
The exemplary embodiment of inventive concept disclosed herein is related to semiconductor storage unit, more particularly, to
Memory device including parity error detection circuit.
Background technique
Memory device is just being used as such as computer, cellular phone, smart phone, personal digital assistant (PDA), digital phase
The information equipments such as machine, video recorder, recorder, MP3 player, hand-held PC, game machine, facsimile machine, scanner and printer
Voice and image data storage media.As memory device is used as the storage medium of various equipment, consumer is to memory device
Demand it is diversified.
Therefore, the technology for large capacity, high speed and/or low power memory part is being developed.With the various function of support
The data processing of the equipment of energy increases, and the capacity and speed of memory device are increasing and accelerating.However, with memory device
The speed of service becomes higher and higher, and the probability that mistake is generated when receiving signal also becomes higher and higher.Thereby it is ensured that memory
The stable operation of part becomes a challenge.
In order to ensure the stable operation of high speed memory devices, memory device can be by using parity scheme and storage
Device controller exchanges data.It is not being lost for example, some memory devices are checked whether using parity error detection circuit
The data transmitted with parity scheme are received in genuine situation.
Summary of the invention
Some exemplary embodiments of present inventive concept provide the memory device including parity error detection circuit,
Wherein the parity error detection circuit is held in storage system using the data strobe signal without postamble
Row even-odd check.
According to an exemplary embodiment, memory device includes parity checker and masking unit (mask unit).It is odd
Even parity check circuit executes even-odd check to the data sampled according to data strobe signal.Masking unit is produced based on even-odd check result
Raw parity errors error signal, wherein the parity error signal is in the time determined according to the burst-length of the data
It is exported during section.The data strobe signal does not include postamble.
According to an exemplary embodiment, memory device includes aligner and parity error detection circuit.It is described right
Neat device samples data by data strobe signal.Parity error detection circuit holds the data sampled by aligner
Row even-odd check generates the parity error exported during the period determined according to the burst-length of the data and believes
Number, and indicate whether produce parity error in the data.The data strobe signal does not include postamble.
According to an exemplary embodiment, a kind of memory device includes: parity checker, is configured as to according to data
The data of gating signal sampling execute even-odd check, and the data strobe signal does not include postamble；And mask circuit, quilt
The result for being configured to even-odd check generates parity errors error signal, and according to the determination of the burst-length of the data
The parity errors error signal is exported during period.
According to an exemplary embodiment, a kind of memory device includes: aligner, is configured as passing through data strobe signal
Data are sampled, the data strobe signal does not include postamble；And parity error detection circuit, it is configured
To execute even-odd check to generate parity errors error signal, in the burst according to the data to the data sampled by aligner
The parity errors error signal is exported during the period that length determines, the parity error signal designation is in the number
Whether parity error is produced in.
According to an exemplary embodiment, a kind of memory device includes: parity checker, is configured as to according to data
The data of gating signal sampling execute the first even-odd check, and the data strobe signal does not include postamble；Mask signal hair
Raw device is configured as generating mask signal based on write order, wherein the mask signal is in the burst-length according to the data
It is activation during the determining period；And error signal generator, it is configured as receiving the even-odd check letter from host
Number, the second even-odd check is executed based on result of the parity signal to the first even-odd check, and be based on the mask
Signal and the result of the second even-odd check generate parity errors error signal.
Detailed description of the invention
Fig. 1 is to show the block diagram of the storage system for the exemplary embodiment conceived according to the present invention；
Fig. 2 is to show the block diagram of memory device shown in FIG. 1；
Fig. 3 is to show the block diagram of the first DQS aligner shown in Fig. 2；
Fig. 4 is to show the block diagram of the first clock alignment device shown in Fig. 2；
Fig. 5 is to show the block diagram of parity error detection circuit shown in Fig. 2；
Fig. 6 is to show the circuit diagram of parity checker shown in fig. 5；
Fig. 7 is to show the block diagram of the second even-odd check delay unit shown in fig. 5；
Fig. 8 is to show the block diagram of mask signal generator shown in fig. 5；
Fig. 9 is to show the block diagram of error signal generator shown in fig. 5；
Figure 10 is to show the timing diagram of the signal generated when storage system shown in FIG. 1 operation；
Figure 11 is to show the timing diagram of the signal generated when parity error detection circuit shown in FIG. 1 operation；
And
Figure 12 is to show the custom system for the memory device for applying the exemplary embodiment conceived according to the present invention
Block diagram.
Specific embodiment
Below so that those of ordinary skill in the art's present inventive concept easy to accomplish degree in detail and clearly illustrate
Some exemplary embodiments of present inventive concept.
Fig. 1 is to show the block diagram of the storage system for the exemplary embodiment conceived according to the present invention.With reference to figure
1, storage system 1000 may include host 1100 and memory device 1200.For example, storage system 1000 can be including
The individual system of 1200 the two of host 1100 and memory device.In some exemplary embodiments, the master of storage system 1000
Machine 1100 and memory device 1200 can be realized by individual equipment respectively.
Host 1100 can be processor circuit or system including general processor or application processor.In some examples
In property embodiment, host 1100 can be the calculating equipment including one or more processors.For example, calculating equipment can be
People's computer, peripheral equipment, digital camera, personal digital assistant (PDA), portable media player (PMP), smart phone,
Tablet computer or wearable device.
Host 1100 can execute training on memory device 1200 under guidance (booting) or specific condition.Host
1100 can improve the reliability that data or signal exchange are carried out with memory device 1200 by executing training.For example, host
Training data can be written memory device 1200 in all cases or read training data from memory device 1200 by 1100, with
Determine optimal clock timing or optimal reference level.
Memory device 1200 can store the data provided from host 1100 or the data that be supplied to host 1100.Storage
Device 1200 can be implemented as include volatile memory or nonvolatile memory any storage medium.For example, storing
In the case that device 1200 includes volatile memory, volatile memory may include DRAM, static state RAM (SRAM), brilliant lock
Pipe RAM (TRAM), zero capacitance RAM (Z-RAM), pair transistor RAM (TTRAM) or magnetic resistance RAM (MRAM).Memory device 1200 can
To be the storage medium for including volatile memory.For example, memory device 1200 may include without buffering dual inline type storage
Module (UDIMM), registered DIMM (RDIMM), the reduced DIMM (LRDIMM) of load, non-volatile DIMM (NVDIMM),
Big bandwidth memory (HBM) etc..
For example, nonvolatile memory can be electricity in the case where memory device 1200 includes nonvolatile memory
Erasable Programmable Read Only Memory EPROM (EEPROM), flash memory, MRAM, spin-transfer torque MRAM (STT-MRAM), conduction
It bridges RAM (CBRAM), ferroelectric RAM (FeRAM), phase transformation RAM (PRAM), resistance RAM (RRAM), nanotube RRAM (RRAM), gather
Close object RAM (PoRAM), nanometer floating gate memory (NFGM), holographic memory, molecular electronic memory device or insulator electricity
Resistive memory.One or more bits can store in the unit cell of nonvolatile memory.Above-mentioned example is unlimited
Exemplary embodiment processed.
Hereinafter, let it be assumed, for the purpose of illustration, that memory device 1200 includes single memory device.However, as set forth above, it is possible to
It will be readily understood that, exemplary embodiment is applied to various memory devices.
Memory device 1200 can be communicated with host 1100.For example, memory device 1200 can be based on various wire communications
Agreement is (for example, universal serial bus (USB), small computer system interface (SCSI), peripheral component interconnection express passway
(PCIe), mobile PC Ie (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), serial ATA (SATA), serial attached
Even SCSI (SAS), integrated driving electronic device (IDE), firewire, Common Flash Memory (UFS) or transmission control protocol/Internet protocol
(TCP/IP)) or various wireless communication protocols are (for example, long term evolution (LTE), World Interoperability for Microwave Access, WiMax (WiMax), complete
Ball mobile communication system (GSM), CDMA (CDMA), high-speed packet access (HSPA), bluetooth, near-field communication (NFC), Wi-
One or more of Fi or radio frequency identification (RFID)), it is communicated with host 1100.Above-mentioned example does not limit exemplary implementation
Example.
Memory device 1200 can be in response to the command/address signal synchronous with the clock signal clk from host 1100
CMD/ADDR executes read or write to the data DATA synchronous with data strobe signal DQS.For example, memory device 1200
Write operation and read operation can be as follows.
In the case of a read operation, from host 1100 by activation command and row address CMD/ADDR and clock signal clk one
It rises and is supplied to memory device 1200.After the first reference time, column address is provided from host 1100 to memory device 1200.So
Afterwards, memory device 1200 provides requested data DATA to host 1100 in the rear of the second reference time.
In the case of a write operation, firstly, being mentioned together with clock signal clk from host 1100 by activation command and row address
Supply memory device 1200.After the reference time, write order and column address are provided from host 1100 to memory device 1200
CMD/ADDR.Later, the data DATA to be written is provided from host 1100 to memory device 1200.Memory device 1200 will receive
To the memory area that is defined by column address and row address of data write-in in.
The exemplary embodiment conceived according to the present invention, can be from host 1100 (or memory device 1200) to storage
Device 1200 (or host 1100) provides data DATA and data strobe signal DQS.When data strobe signal DQS can be a kind of
Clock signal.The received data DATA of memory device 1200 is synchronous with data strobe signal DQS.When memory device 1200 is to host
When 1100 offer data DATA, data strobe signal DQS is provided from memory device 1200 to host 1100.In addition, working as host
1100 to memory device 1200 provide data DATA when, from host 1100 to memory device 1200 provide data strobe signal DQS.
Data strobe signal DQS may include preamble and postamble.Preamble and postamble are to allow to deposit
Memory device 1200 respectively will for example its input buffer be (before and after memory device 1200 receives data from host 1100
Show) and/or the signal that synchronizes of clock buffer (not shown) and data strobe signal DQS.In example disclosed herein
Property embodiment in, it is assumed that data strobe signal DQS does not include postamble and only includes preamble.
The exemplary embodiment conceived according to the present invention, memory device 1200 may include parity errors error detection
Circuit 1220.Parity error detection circuit 1220 can be executed by data of the write operation to memory device 1200 to be written
Even-odd check.Hereinafter, the data that memory device 1200 will be written by write operation are known as " writing data ".It can be in memory device
It is synchronized by the data strobe signal DQS provided from host 1100 to data are write in 1200.
Parity error detection circuit 1220 can be provided to the parity signal PRT from host 1100, and
Parity signal PRT can be used and execute additional parity to data are write.Parity signal will be used with reference to Fig. 9 description
PRT is to the additional parity for writing data execution.Parity error detection circuit 1220 can provide odd even to host 1100
Output signal P_out is verified as even-odd check result.
Parity error detection circuit 1220 can execute odd even school to the data being aligned based on data strobe signal DQS
It tests, and exports even-odd check output signal P_out as even-odd check result.It include postamble in data strobe signal DQS
In the case where, since parity error detection circuit 1220 and data strobe signal DQS are synchronously carried out operation, it is possible to
By the postamble reflex bit parity check output signal P_out of data strobe signal DQS, wherein the even-odd check exports
Signal P_out includes the result that even-odd check is carried out to the last position for writing data.
However, as described above, the exemplary embodiment conceived according to the present invention, data strobe signal DQS can not
Including postamble.Therefore, the even-odd check output signal including the even-odd check result for the last position for writing data
P_out can not be resetted by data strobe signal DQS.Therefore, including existing for the even-odd check result for the last position for writing data
Interior even-odd check output signal P_out can be kept, without being resetted by data strobe signal DQS.If even-odd check exports
Signal P_out is not reset in the edge of data strobe signal DQS, then memory device 1200 is not met by joint electronics device
The communication protocol of the storage system 1000 of the standard specification definition of the part engineering committee (JEDEC).
The exemplary embodiment conceived according to the present invention, parity error detection circuit 1220 can be based on not wrapping
Include the data strobe signal DQS of postamble adjust according to burst-length BL export even-odd check output signal P_out when
Between section.Herein, burst-length BL indicates the number of the serial data continuously exchanged between memory device 1200 and host 1100
Amount.
The foregoing describe the odd even schools for the period that output even-odd check output signal P_out is adjusted based on burst-length BL
The configuration of error checking erroneous detection slowdown monitoring circuit 1220 and the memory device 1200 including parity error detection circuit 1220.By above-mentioned
Configuration, even if providing the data strobe signal DQS of not no postamble to memory device 1200, memory device 1200 can also be
Even-odd check output signal P_out is exported during the period determined according to burst-length BL.Therefore, memory device 1200 can be with
Meet the communication protocol of the storage system 1000 defined by JEDEC standard specification.
Fig. 2 is to show the block diagram of memory device 1200 shown in FIG. 1.Fig. 2 will be described with reference to Figure 1.With reference to Fig. 2, deposit
Memory device 1200 may include: data input drivers 1210, the first DQS aligner 1211 and the 2nd DQS aligner 1213,
One clock aligner 1212 and second clock aligner 1214, parity error detection circuit 1220, mode register 1230,
Clock buffer 1240, memory cell array 1250, command/address latch 1260, command decoder 1270 and data are defeated
Driver 1280 out.
When memory device 1200 executes write order, data input drivers 1210 pass through DQ pad DQ_p and DQS respectively
Pad DQS_p writes data DATA and data strobe signal DQS from the reception of host 1100.As described above, data strobe signal DQS can
Not include postamble.Data input drivers 1210 can write data and received data strobe signal DQS for received
Output is internal data DQ_i and internal DQS signal DQS_i respectively.
Internal data DQ_i can be aligned by the first DQS aligner 1211 with internal DQS signal DQS_i.For example, first
DQS aligner 1211 can respectively adopt internal data DQ_i in the rising edge of internal DQS signal DQS_i and failing edge
Sample, and internal data DQ_i is exported to be classified as and the internal DQS signal DQS_i odd data being aligned and even data.Odd number
According to the data for the odd-numbered for indicating internal data DQ_i, even data indicates the data of the even-numbered of internal data DQ_i.
First clock alignment device 1212 can be by internal clock signal CLK_i to the odd data and idol of internal data DQ_i
Data are sampled and are aligned.First clock alignment device 1212 can be defeated by the data being aligned by internal clock signal CLK_i
It is out surprise align data D_od and even align data D_ev.Odd align data D_od and idol align data D_ev can be provided to
Each of parity error detection circuit 1220 and sense amplifier 1251.
2nd DQS aligner 1213 can by internal DQS signal DQS_i to by even-odd check pad PRT_p from master
The parity signal PRT that machine 1100 provides is sampled and is aligned.Although being not shown in Fig. 2, memory device 1200 can be with
Including the input driver for receiving parity signal PRT.Second clock aligner 1214 can be believed by internal clocking
Number CLK_i is sampled and is aligned to the parity signal PRT sampled by internal DQS signal DQS_i.Second clock alignment
Device 1214 can export the parity signal PRT being aligned by internal clock signal CLK_i for inner parity signal
PRT_i。
Parity error detection circuit 1220 can be come by using internal clock signal CLK_i to odd align data D_
Od and idol align data D_ev executes even-odd check.Parity error detection circuit 1220 can be provided inner parity
Signal PRT_i, and additional parity is executed to data by using inner parity signal PRT_i.
In addition, the decoding pulse that parity error detection circuit 1220 can be provided to from command decoder 1270 is write
Order PWY and the even-odd check delay PL and burst-length BL from mode register 1230.Parity error detection circuit
1220 can be generated based on the burst-length BL of decoding pulse write order PWY and data for adjusting output even-odd check output
The mask signal (not shown) of the period of signal P_out.That is, output odd even school can be adjusted by mask signal
Test the period of output signal P_out.Parity error detection circuit 1220 can be delayed PL based on even-odd check to adjust
The output time point of even-odd check output signal P_out.Even-odd check output signal P_out can be exported by even-odd check and be welded
Disk DERR is supplied to host 1100.
Mode register 1230 can store the information provided from command decoder 1270.For example, mode register 1230
The even-odd check delay PL and burst-length BL provided from command decoder 1270 is provided.In addition, mode register 1230
Even-odd check delay PL and burst-length BL can be provided to parity error detection circuit 1220.
It can be provided by clock pad CLK_p and clock pad CLKb_p from host 1100 to clock buffer 1240
Clock signal clk and clock bars CLKb.For example, clock buffer 1240 can be realized with differential input buffer.When
Clock buffer 1240 can generate internal clock signal CLK_i based on clock signal clk and clock bars CLKb.Internal clocking
Signal CLK_i can be provided to parity error detection circuit 1220, the first clock alignment device 1212 and second clock pair
Neat device 1214 and command decoder 1270.
It is defeated the data being stored in memory cell array 1250 can be supplied to data by sense amplifier 1251
Driver 1280 out.In some exemplary embodiments, odd align data D_od and idol align data D_ev can be put by reading
Big device 1251 is stored in memory cell array 1250.Command/address latch 1260,1252 and of row decoder can be passed through
The address for the memory cell that the data provided from host 1100 will store is supplied to memory cell by column decoder 1253
Array 1250.
Command/address latch 1260 receives command signal CMD and ground from host 1100 by command/address pad CA_p
Location signal ADDR.The order CMD received can be supplied to command decoder 1270 by command/address latch 1260.In addition,
The address received can be supplied to row decoder 1252 and column decoder 1253 by command/address latch 1260.It can lead to
It crosses command/address latch 1260 and provides various orders to command decoder 1270.Command decoder 1270 can be to such as surprise
The element of even parity check error detection circuit 1220, mode register 1230, row decoder 1252 and column decoder 1253 etc mentions
For decoded order.
Data output driver 1280 can be stored in memory cell battle array to the output of host 1100 by DQ pad DQ_p
Data in column 1250.For this purpose, row decoder 1252 and column decoder 1253 can be provided to memory cell array 1250 and be deposited
The address of the memory cell for the data to be exported is stored up.In addition, when data output driver 1280 exports number to host 1100
According to when, data output driver 1280 can by DQS pad DQS_p to host 1100 provide data strobe signal DQS.
Fig. 3 is to show the block diagram of the first DQS aligner 1211 shown in Fig. 2.Fig. 3 will be described with reference to Figure 2.With reference to figure
3, the first DQS aligner 1211 may include the first trigger FF1 and the second trigger FF2.
First trigger FF1 can be provided internal data DQ_i as data and input D and internal data strobe signal
DQS_i inputs CK as clock.First trigger FF1 can be by the rising edge of internal data strobe signal DQS_i to inside
Data DQ_i is sampled.The odd number of internal data DQ_i can be compiled by the rising edge of internal data strobe signal DQS_i
Number data sampled, and the first trigger FF1 can export the data of sampling as odd data DD_od.
Second trigger FF2 can be provided internal data DQ_i as data and input D and internal data strobe signal
The bars (bar signal) of DQS_i inputs CK as clock.Second trigger FF2 can pass through internal data strobe signal
The failing edge of DQS_i samples internal data DQ_i.It can be internal by the failing edge of internal data strobe signal DQS_i
The data of the even-numbered of portion data DQ_i are sampled, and it is even that the second trigger FF2, which can export the data of sampling,
Data DD_ev.
Therefore, the first trigger FF1 and the second trigger FF2 can pass through respectively internal data strobe signal DQS_i's
Rising edge and failing edge are sampled and are aligned to internal data DQ_i.First trigger FF1 and the second trigger FF2 can be with bases
Odd data DD_od and even data DD_ev are exported respectively in the data of sampling.
2nd DQS aligner 1213 shown in Fig. 2 may include configuration identical with the first DQS aligner 1211.It can be with
Parity signal PRT, and are provided from host 1100 to the 2nd DQS aligner 1213 by even-odd check pad PRT_p
Two DQS aligners 1213 can be by the rising edge and failing edge of internal data strobe signal DQS_i to parity signal PRT
It is sampled.2nd DQS aligner 1213 can export odd signal based on the parity signal PRT after sampling respectively
(not shown) and even parity check signal (not shown).
Fig. 4 is to show the block diagram of the first clock alignment device shown in Fig. 2.Fig. 4 will be described with reference to Figure 2.With reference to Fig. 4,
First clock alignment device 1212 may include the first trigger FF1 and the second trigger FF2.
First trigger FF1 can be provided odd data DD_od as data and input D and internal clock signal CLK_i
CK is inputted as clock.First trigger FF1 can by the rising edge of internal clock signal CLK_i to odd data DD_od into
Row sampling.First trigger FF1 can export the data of sampling as odd align data D_od.
Second trigger FF2 can be provided even data DD_ev as data and input D and internal clock signal CLK_i
CK is inputted as clock.Second trigger FF2 can by the rising edge antithesis data DD_ev of internal clock signal CLK_i into
Row sampling.Second trigger FF2 can export the data of sampling as even align data D_ev.
Therefore, the first trigger FF1 and the second trigger FF2 can pass through the rising edge of internal clock signal CLK_i point
It is other that odd data DD_od and even data DD_ev are sampled and be aligned, and be odd align data D_od by the output of the data of sampling
With even align data D_ev.
Second clock aligner 1214 shown in Fig. 2 may include configuration identical with the first clock alignment device 1212.The
Two clock alignment devices 1214 can be provided to believe from the odd signal (not shown) of the 2nd DQS aligner 1213 and even parity check
Number (not shown), and odd signal and even parity check signal can be carried out by the rising edge of internal clock signal CLK-i
Sampling.2nd DQS aligner 1213 can export the signal of sampling as odd alignment parity signal (not shown) and couple
Neat parity signal (not shown).
Fig. 5 is to show the block diagram of parity error detection circuit shown in Fig. 2.Fig. 5 will be described with reference to Fig. 1 and Fig. 2
Block diagram.With reference to Fig. 5, parity error detection circuit 1220 may include parity checker 1221, the first even-odd check
Delay circuit 1222 and the second even-odd check delay circuit 1223 and mask circuit 1224.
Parity checker 1221 can be provided to the odd align data D_od [N:0] from the first clock alignment device 1212
With even align data D_ev [N:0].Here, digit " N " can depend on the width of the data/address bus of memory device 1200.Example
Such as, in the case where memory device 1200 includes the data/address bus connecting with " M " a DQ pad DQ_p, digit " N " be can be
“M”。
Below, it is assumed that digit " N " is " 3 ".Therefore, memory device 1200 includes first to fourth DQ pad DQ_p [3:0].
Odd align data D_od [0] and idol align data D_ev [0] are by via internal DQS signal DQS_i and internal clock signal
The data provided by the first DQ pad DQ_p [0] are carried out being aligned the data generated by CLK_i.As described above, odd alignment number
It is by respectively via internal DQS signal DQS_i and internal clock signal according to D_od [3:1] and idol align data D_ev [3:1]
The data provided by the 4th to the 2nd DQ pad DQ_p [3:1] are carried out being aligned the data generated by CLK_i.
Parity checker 1221 can execute even-odd check to provided data.Parity checker 1221 can incite somebody to action
Even-odd check result is exported respectively as the even error signal ERR1_ev of the first surprise error signal ERR1_od and first.Fig. 6 will be referred to
The configuration of first parity checker 1221 is described.
First even-odd check delay circuit 1222 can be provided to the internal clock signal from clock buffer 1240
CLK_i.First even-odd check delay circuit 1222 can be based on even-odd check delay PL, by the first odd error signal ERR1_od
With the multiple in the period of each of the first even error signal ERR1_ev delayed internal clock signal CLK_i.First odd even school
The odd error signal ERRd_od for delay and the even error signal of delay can be exported for the signal of delay by testing delay circuit 1222
ERRd_ev。
Second even-odd check delay circuit 1223 can be provided to the internal clock signal from clock buffer 1240
CLK_i.In addition, the decoded pulse that the second even-odd check delay circuit 1223 can be provided to from command decoder 1270 is write
Order PWY.Second even-odd check delay circuit 1223 can be based on even-odd check delay PL, by decoded pulse write order PWY
The multiple in the period of delayed internal clock signal CLK_i.Second even-odd check delay circuit 1223 can be defeated by the order of delay
It is out the decoding pulse write order PWYd of delay.Reference Fig. 7 is described to the configuration of the second even-odd check delay circuit 1223.
Mask circuit 1224 can be provided the even error signal ERRd_ of the odd error signal ERRd_od of delay, delay
Ev, delay decoding pulse write order PWYd, internal clock signal CLK_i and burst-length BL.Mask circuit 1224 can be with base
Generate whether instruction produces the even-odd check output signal P_out of parity error in data in provided signal.
Mask circuit 1224 can export even-odd check output signal P_out during the period determined according to burst-length BL.
Mask circuit 1224 may include mask signal generator 1225 and error signal generator 1226.Mask signal hair
Raw device 1225 can be provided decoding the pulse write order PWYd and burst-length BL of delay.Mask signal generator 1225 can be with
By generating mask signal MASK based on the pulse of the decoding pulse write order PWYd of burst-length BL adjustment delay.It will refer to
Fig. 8 describes the configuration of mask signal generator 1225.
Error signal generator 1226 can be provided the even error signal of the odd error signal ERRd_odd of delay, delay
ERRd_ev and mask signal MASK.Error signal generator 1226 may be provided with inner parity signal PRT_i.It is interior
Portion parity signal PRT_i may include odd signal PRTi_odd and even parity check signal PRTi_ev.Error signal occurs
Device 1226 can determine the parity error for writing data based on odd signal PRTi_odd and even parity check signal PRTi_ev
It writes the parity error of the odd data of data or writes the parity error of the even data of data.
Error signal generator 1226 can odd error signal ERRd_odd based on delay, delay even error signal
ERRd_ev and inner parity signal PRT_i executes even-odd check to data are write.Error signal generator 1226 can be
Even-odd check result is exported as even-odd check output signal P_out during the activation of mask signal MASK.It will be described with reference to Fig. 9
The configuration of error signal generator 1226.
Fig. 6 is to show the circuit diagram of parity checker shown in fig. 5.Reference Fig. 1 and 5 are described to the circuit diagram of Fig. 6.
With reference to Fig. 6, parity checker 1221 may include the first XOR logic XOR1 to the 6th XOR logic XOR6.
As described above, parity checker 1221 can check odd align data D_od [3:0] and even align data D_ev
The even-odd check of [3:0].For example, data can be provided from host 1100 to memory device 1200 with even parity check scheme.This
In the case of, odd align data D_od [3:0] can be provided from host 1100, so that the position (hereinafter referred to as " bit string ") of same position
With even number logical one.Furthermore, it is possible to even align data D_ev [3:0] be provided from host 1100, so that bit string includes even number
A logical one.
For example, " 1011 " can be provided as couple in the case where providing data from host 1100 with even parity check scheme
" 1001 ", can be provided as even align data D_ev [1], " 1100 " can be provided as couple and counted together by neat data D_ev [0]
According to D_ev [2], and " 1111 " can be provided as to even align data D_ev [3].In this case, even align data D_ev
The data of first bit string of [3:0] are " 1111 ".Because the quantity of logical one is even number, parity error is not generated.
In addition, the data of the data of the second bit string of idol align data D_ev [3:0] and the third bit string of idol align data D_ev [3:0]
Respectively " 0011 " and " 1001 ".Because including the logical one in the data of each of the second bit string and third bit string
Quantity be even number, so not generating parity error.The data of 4th bit string of even align data D_ev [3:0] are
"1101".Due to include the 4th bit string data in the quantity of logical one be odd number, so generating parity error.
Above-mentioned example describes with even parity check scheme the case where data are provided from host 1100 to memory device 1200.One
In a little exemplary embodiments, data can be provided from host 1100 to memory device 1200 with odd scheme.In such case
Under, each of odd align data D_od [3:0] and idol align data D_ev [3:0] can be provided from host 1100, so that
The bit string of same position includes odd number logical one.Hereinafter it is assumed that the storage system 1000 of Fig. 1 is with the exchange of even parity check scheme
Data.
First XOR logic XOR1, the second XOR logic XOR2 and the 5th XOR logic XOR5 can check odd align data
The even-odd check of D_od [3:0].Even-odd check result can be exported as the first odd error signal ERR1_od.Third exclusive or is patrolled
The odd even school of even align data D_ev [3:0] can be checked by collecting XOR3, the 4th XOR logic XOR4 and the 6th XOR logic XOR6
It tests.Even-odd check result can be exported as the first even error signal ERR1_ev.
For example, mistaking when generating parity errors in surprise align data D_od [3:0], can export with logical one
First odd error signal ERR1_od.It mistakes when generating parity errors in even align data D_ev [3:0], can export has
The even error signal ERR1_ev of the first of logical one.
On the contrary, in the storage system 1000 using odd scheme, when in odd align data D_od [3:0] or couple
It generates parity errors in neat data D_ev [3:0] to mistake, the even error signal of the first surprise error signal ERR1_od or first
The value (for example, logical zero) of ERR1_ev can be with the value phase in the case where storage system 1000 is using even parity check scheme
Instead.
Fig. 7 is to show the block diagram of the second even-odd check delay circuit shown in fig. 5.Fig. 7 will be described with reference to Figure 5.Ginseng
Fig. 7 is examined, the second even-odd check delay circuit 1223 may include the first multiplexer MUX1 to the 4th multiplexer MUX4 and first
Trigger FF1 to the 4th trigger FF4.
First multiplexer MUX1 can be delayed PL [0] based on even-odd check to select and export decoded pulse write order
One of the output signal of PWY or the second trigger FF2.The output signal of first multiplexer MUX1 can be provided to the first triggering
Device FF1.First trigger FF1 can be adopted by output signal of the internal clock signal CLK_i to the first multiplexer MUX1
Sample, and the signal of sampling is exported as the signal for a cycle that length is internal clock signal CLK_i.The output can be believed
Number as delay decoding pulse write order PWYd be supplied to mask signal generator 1225.
Similar in the first multiplexer MUX1, the second multiplexer MUX2 can be based on even-odd check delay PL [1] selection
And one of the output signal of decoded pulse write order PWY or third trigger FF3 are exported, and third multiplexer MUX3 can be with
Based on even-odd check delay PL [2] select and export decoded pulse write order PWY or the 4th trigger FF4 output signal it
One.The output signal of second multiplexer MUX2 can be provided to the second trigger FF2.The output signal of third multiplexer MUX3
Third trigger FF3 can be provided to.Second trigger FF2 and third trigger FF3 can be believed by internal clocking respectively
Number CLK_i samples the output signal of the second multiplexer MUX2 and third multiplexer MUX3, and the signal of sampling is exported
For the signal for a cycle that length is internal clock signal CLK_i.
4th multiplexer MUX4 can provide decoded pulse to the 4th trigger FF4 based on even-odd check delay PL [3]
One of write order PWY or ground voltage GND.4th trigger FF4 can be by internal clock signal CLK_i to the 4th multiplexer
The output signal of MUX4 is sampled, and the signal of sampling is exported to a cycle for being internal clock signal CLK_i for length
Signal.
In the case where even-odd check delay PL [0] is activated, decoded pulse write order PWY can be answered by first
With device MUX1 (without being supplied to the first trigger FF1 by the second trigger FF2 to the 4th trigger FF4).Therefore, Ke Yiwu
Lingeringly decoded pulse write order PWY is sampled by the first rising edge of internal clock signal CLK_i.The solution of sampling
Code pulse write order PWY can be converted to the pulse letter for a cycle that length is internal clock signal CLK_i without delay
Number, and the signal after conversion can be outputted as the decoding pulse write order PWYd of delay.
In the case where even-odd check delay PL [1] is activated, decoded pulse write order PWY can pass through the second multiplexing
Device MUX2 is provided to the second trigger FF2.Decoded pulse write order PWY can be converted and be exported by the second trigger FF2
For the pulse signal for a cycle that length is internal clock signal CLK_i.The output signal can pass through the first multiplexer
MUX1 and the first trigger FF1 is outputted as the decoding pulse write order PWYd of delay.That is, decoding pulse write order
PWY can a cycle that internal clock signal CLK_i is delayed by the first trigger FF1 and the second trigger FF2 it
It is outputted as the decoding pulse write order PWYd of delay afterwards.
As described above, decoding pulse write order PWY can pass through in the case where even-odd check delay PL [2] is activated
Third multiplexer MUX3 is supplied to third trigger FF3.It can be answered by second by the pulse signal that third trigger FF3 is sampled
It is write with the decoding pulse that device MUX2, the second trigger FF2, the first multiplexer MUX1 and the first trigger FF1 are outputted as delay
Order PWYd.Therefore, decoding pulse write order PWY can be in being delayed by the first trigger FF1 to third trigger FF3
Portion's clock signal clk _ i is outputted as the decoding pulse write order PWYd of delay after two periods.
In the case where even-odd check delay PL [3] is activated, decoding pulse write order PWY can pass through the 4th multiplexer
MUX4 is supplied to the 4th trigger FF4.By the 4th trigger FF4 sampling pulse signal can by third multiplexer MUX3,
Third trigger FF3, the second multiplexer MUX2, the second trigger FF2, the first multiplexer MUX1 and the first trigger FF1 are defeated
It is out the decoding pulse write order PWYd of delay.Therefore, decoding pulse write order PWY can pass through the first trigger FF1 extremely
Life is write in the decoding pulse that delay is outputted as after three periods that 4th trigger FF4 delays internal clock signal CLK_i
Enable PWYd.
The configuration of first even-odd check delay circuit 1222 can be with the configuration phase of the second even-odd check delay circuit 1223
It is same or substantially similar.It is even that first even-odd check delay circuit 1222 can be provided the first surprise error signal ERR1_od and first
Each of error signal ERR1_ev, and the first even-odd check delay circuit 1222 can be based on even-odd check delay PL,
By times in the period of the even error signal ERR1_ev delayed internal clock signal CLK_i of the first surprise error signal ERR1_od and first
Number.The signal of delay can be exported the odd error signal ERRd_od for delay and prolonged by the first even-odd check delay circuit 1222
Slow even error signal ERRd_ev.It will be understood by those skilled in the art that it is electric to be delayed with reference to the second even-odd check shown in Fig. 7
The configuration on road 1223 configures the first even-odd check delay circuit 1222.
Fig. 8 is to show the block diagram of mask signal generator shown in fig. 5.Reference Fig. 2 and 5 are described to the block diagram of Fig. 8.Ginseng
Fig. 8 is examined, mask signal generator 1225 may include frequency divider 12251 and multiplexer MUX.
Decoding the pulse write order PWYd and internal clock signal CLK_i of delay can be provided to frequency divider 12251.Frequency dividing
Device 12251 can the decoding pulse write order PWYd based on internal clock signal CLK_i and delay, the decoding pulse of delay is write
Order PWYd is converted into twice of the pulse signal in the period that length is internal clock signal CLK_i.
Based on burst-length BL, multiplexer MUX can export one of following signals and be used as mask signal MASK: pulse is interior
It the decoding pulse write order PWYd of the delay of portion's clock signal clk _ i a cycle and is converted and arteries and veins by frequency divider 12251
Punching is the signal in two periods of internal clock signal CLK_i.For example, in the case where burst-length BL is " 2 ", multiplexer
Pulse can be that the decoding pulse write order PWYd output of the delay of a cycle of internal clock signal CLK_i is to cover by MUX
Code signal MASK.As another example, in the case where burst-length BL is " 4 ", multiplexer MUX can will be by frequency divider
12251 convert and pulse be internal clock signal CLK_i two periods signal export into mask signal MASK.
Fig. 9 is to show the block diagram of error signal generator shown in fig. 5.The block diagram of Fig. 9 will be described referring to figs. 2 and 5.
With reference to Fig. 9, error signal generator 1226 may include the first XOR logic XOR1 and the second XOR logic XOR2, NOR logic
NR and NAND logic ND.
First XOR logic XOR1 can execute the odd error signal ERRd_od and odd signal PRTi_od of delay
XOR operation.Second XOR logic XOR2 can execute the even error signal ERRd_ev and even parity check signal PRTi_ev of delay
XOR operation.As described above, error signal generator 1226 can be based on odd signal PRTi_odd and even parity check signal
PRTi_ev writes the parity error of the odd data of data determining the parity error for writing data or writes the idol of data
The parity error of data.
For example, the delay with logical one can be exported when the parity errors for generating the odd data for writing data are mistaken
Odd error signal ERRd_od, so that output has the even-odd check output signal P_out of logical one.Host 1100 is possibly can not
Identification which of odd signal PRTi_odd and even parity check signal PRTi_ev cause to export logical one.In some examples
In property embodiment, host 1100 be can be configured as the odd signal PRTi_odd of logical one and the even parity check of logical one
Signal PRTi_ev is sequentially supplied to error signal generator 1226.If odd signal PRTi_od has logical one,
Even-odd check output signal P_out can have logical zero.Therefore, host 1100 can determine in the odd data for writing data
Parity error has occurred.
NOR logic NR can execute NOR fortune to the output signal of the first XOR logic XOR1 and the second XOR logic XOR2
It calculates.That is, NOR logic NR can export the odd error signal ERRd_od to delay, odd signal PRTi_od, delay
Even error signal ERRd_ev and even parity check signal PRTi_ev execute inclusive-OR operation result.Therefore, NOR logic NR can lead to
It crosses using parity signal PRT to export and be obtained and executing additional parity to the even-odd check result for writing data
Even-odd check result.
NAND logic ND can execute NAND operation to the output signal of mask signal MASK and NOR logic NR.By with
Upper description, NAND logic ND can be wide by the pulse of the inversion signal output masking signal MASK of the output signal of NOR logic NR
Degree.As set forth above, it is possible to adjust the pulse width of mask signal MASK according to burst-length BL.This means that NAND logic ND
The inversion signal of the output signal of NOR logic NR can be exported during the period determined according to burst-length BL.
Figure 10 is to show the timing diagram of the signal generated when storage system shown in FIG. 1 operation.Will with reference to Fig. 1,
Fig. 2 and Fig. 5 describes the timing diagram of Figure 10.With reference to Figure 10, after providing the second data D2, based on not including postamble
The even-odd check output signal P_out that data strobe signal DQS is generated is kept.Here, suppose that burst-length BL is " 2 ", and odd
Even parity check delay " PL " is " 0 ".
In time point t1, memory device 1200 can be received from host 1100 write order WR, clock signal clk and CLKb with
And the preamble of data strobe signal DQS.Command/address latch 1260 can pass through clock signal clk and CLKb pairs
Write order WR is sampled.Memory device 1200 can execute write operation by the write order WR of sampling.Assuming that write delay CWL be
" 1 " can then provide the first data at the time point t2 after a cycle from time point t1 by clock signal clk
D1。
In time point t2, memory device 1200 can receive the first data D1 from host 1100.The of memory device 1200
One DQS aligner 1211 can sample the first data D1 by the rising edge of data strobe signal DQS, and by sampling
Data output is odd data DD_od.In time point t3, memory device 1200 can receive the second data D2 from host 1100.It deposits
First DQS aligner 1211 of memory device 1200 can carry out the second data D2 by the failing edge of data strobe signal DQS
Sampling, and the data of sampling are exported as even data DD_ev.
The rising of clock signal clk can be passed through in the first clock alignment device 1212 of time point t4, memory device 1200
Edge respectively samples odd data DD_od and even data DD_ev, and the data of sampling are exported respectively as odd align data D_
Od and even align data D_ev.Parity error detection circuit 1220 can be based on surprise align data D_od and even align data
D_ev generates even-odd check output signal P_out.In the example in Figure 10, if parity error detection circuit 1220
Mask circuit 1224 does not work, even if even-odd check output signal P_out is also continuously kept identical then after time point t5
Parity error result.
Figure 11 is to show the timing diagram of the signal generated when parity error detection circuit shown in FIG. 1 operation.
Reference Fig. 1, Fig. 2, Fig. 5 and Figure 10 are described to the timing diagram of Figure 11.It, in the example of fig. 11, can be with similar to the example of Figure 10
From host 1100 to memory device 1200, offer does not include the data strobe signal DQS of postamble.In the example of fig. 11, false
If burst-length BL is " 2 ", and even-odd check delay " PL " is " 0 ".
It, in the example of fig. 11, can be based on the data strobe signal for not including postamble compared with the example of Figure 10
DQS generates even-odd check output signal P_out, and the even-odd check output signal P_out is generated by mask circuit 1224
Mask signal MASK exported during a cycle of clock signal clk.Operation and ginseng of the memory device 1200 from t1 to t3
The operation for examining Figure 10 description is identical, and therefore descriptions thereof is omitted.
In time point t4, parity error detection circuit 1220 can be based on surprise align data D_od and even align data
D_ev generates the error signal ERRd of delay.As described above, the error signal ERRd of delay may include the surprise mistake letter of delay
The even error signal ERRd_ev of number ERRd_od and delay.Decoding pulse write order PWY can be provided to the second even-odd check
Delay unit 1223, and the second even-odd check delay unit 1223 can be by decoding pulse write order PWY delay, to export
The decoding pulse write order PWYd of delay.However, in the example of fig. 11, since even-odd check delay PL is assumed to be " 0 ", institute
It can be exported without delay in time point t4 with the decoding pulse write order PWYd of delay.
Then, mask signal generator 1225 can the decoding pulse write order PWYd and burst-length BL based on delay come
Generate mask signal MASK.In the example of fig. 11, since burst-length BL is assumed to be " 2 ", mask signal MASK can
To include length as the pulse of a cycle of clock signal clk.Error signal generator 1226 can be based on the surprise mistake of delay
Error signal ERRd_od and the even error signal ERRd_ev of delay generate even-odd check output signal P_out, and with mask
Even-odd check output signal P_out is exported during the pulse width of the signal MASK corresponding period.After time point t5,
Error signal generator 1226 can stop exporting even-odd check output signal P_out.
Therefore, even if providing the data strobe signal DQS of not postamble, memory device 1200 to memory device 1200
Even-odd check output signal P_out can also be exported during the period determined according to burst-length BL.
Figure 12 is to show the custom system for the memory device for applying the exemplary embodiment conceived according to the present invention
Block diagram.With reference to Figure 12, custom system 10000 may include application processor 11000, memory 12000, network interface 13000,
Store equipment 14000 and user interface 15000.
Application processor 11000 can drive including the element and operating system in custom system 10000.For example, answering
With the controller of the element, interface, graphics engine that processor 11000 may include for controlling custom system 10000 etc..Using
System on chip (SoC) Lai Shixian can be used in processor 11000.
Memory 12000 may be used as main memory, working storage, buffer storage or the height of custom system 10000
Fast buffer storage.Memory 12000 can be with volatile random access memory (for example, DRAM, SDRAM, Double Data Rate
(DDR) SDRAM, DDR2SDRAM, DDR3SDRAM, low-power DDR (LPDDR) SDRAM, LPDDR2SDRAM, LPDDR3SDRAM
Or big bandwidth memory (HBM) or nonvolatile RAM (for example, phase transformation RAM (PRAM), magnetic ram (MRAM),
Resistance RAM (RRAM) or ferroelectric RAM (FRAM)) Lai Shixian.
E.g., including controller and memory 12000 in application processor 11000 may be constructed referring to figs. 1 to 11
The storage system 1000 of description.E.g., including the controller in application processor 11000 can be with the host 1100 of Fig. 1
It is corresponding, and memory 12000 can be corresponding with the memory device 1200 of Fig. 1.That is, memory 12000 can wrap
Include the parity error detection circuit 1220 of execution parity errors error detection operation shown in FIG. 1.
Network interface 13000 can be communicated with external equipment.For example, network interface 13000 can support channel radio
Letter is (for example, CDMA (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time-division are more
Location (TDMA), long term evolution (LTE), WiMax, WLAN (WLAN), ultra wide band (UWB), bluetooth and/or radio display
(WI-DI)).Here, network interface 13000 may include in application processor 11000.
Storage equipment 14000 can store data.For example, storage equipment 14000 can store from application processor 11000
Received data.In some exemplary embodiments, the data being stored therein can be sent to application by storage equipment 14000
Processor 11000.For example, storage equipment 14000 can be implemented as non-volatile memory semiconductor device (for example, PRAM,
MRAM, RRAM, nand flash memory, NOR flash memory or three dimensional NAND flash memory).
User interface 15000 may include to 11000 input data of application processor or order or outputting data to outer
The interface of portion's equipment.For example, user interface 15000 may include user input interface (for example, keyboard, keypad, button, touch
Panel, touch tablet, touches ball, camera, microphone, gyro sensor, vibrating sensor or piezoelectric element at touch screen).User
Interface 15000 can also include user's output interface (for example, liquid crystal display (LCD), Organic Light Emitting Diode (OLED) are shown
Equipment, Activematric OLED (AMOLED) show equipment, light emitting diode (LED), loudspeaker or motor).
The exemplary embodiment conceived according to the present invention, even if including the memory of parity error detection circuit
Part receives the data strobe signal of not postamble, can also export during the period determined according to burst-length odd
Even parity check output signal.
Although describing present inventive concept referring to some exemplary embodiments, those skilled in the art are come
It says it is readily apparent that can be made various changes and modifications in the case where not departing from the spirit and scope of present inventive concept.
It will thus be appreciated that the above exemplary embodiments are not limiting, and it is exemplary.
Claims (20)
1. a kind of memory device, comprising:
Parity checker is configured as executing the data sampled according to data strobe signal even-odd check, the data choosing
Messenger does not include postamble；And
Mask circuit is configured as the result based on even-odd check and generates parity errors error signal, and according to the data
Burst-length determine period during export the parity errors error signal.
2. memory device according to claim 1, wherein the parity checker includes XOR logic, the exclusive or is patrolled
It collects and is configured as executing xor operation to the odd data and even data of the data.
3. memory device according to claim 1, wherein the mask circuit includes:
Mask signal generator is configured as generating mask signal based on write order, and the mask signal is according to the data
Burst-length determine period during be activation；And
Error signal generator is configured as generating the odd even school based on the mask signal and the result of the even-odd check
Error checking error signal.
4. memory device according to claim 3, further includes:
Even-odd check delay circuit is configured as being delayed based on even-odd check to postpone the write order, and life is write in delay
Order is supplied to the mask signal generator.
5. memory device according to claim 1, wherein the mask circuit is configured as receiving even-odd check from host
Signal, and by executing additional parity based on result of the parity signal to the even-odd check to generate
State parity errors error signal.
6. memory device according to claim 5, further includes:
Even-odd check delay circuit, be configured as postponing based on even-odd check delay the even-odd check as a result, and will prolong
The result of slow even-odd check is supplied to the mask circuit.
7. memory device according to claim 5, wherein the mask circuit is configured as receiving the even-odd check letter
Number and be delayed the result of postponed even-odd check according to even-odd check.
8. memory device according to claim 5, wherein
The mask circuit includes:
Mask signal generator is configured as generating mask signal based on write order, and the mask signal includes pulse signal, institute
Stating mask signal is activation during the period determined according to the burst-length of the data, and
Error signal generator, comprising:
First XOR logic is configured as the result and even-odd check letter of the even-odd check to the odd data in the data
Number odd signal execute XOR operation；And
Second XOR logic is configured as the result and even-odd check letter of the even-odd check to the even data in the data
Number even parity check signal execute XOR operation；And
The error signal generator is configured as,
The parity errors error signal is generated based on the mask signal, and
Export the signal of the first XOR logic and the second XOR logic.
9. memory device according to claim 1, wherein the mask circuit includes:
Mask signal generator is configured as generating mask signal based on write order, and the mask signal is according to the data
Burst-length determine period during be activation；And
Error signal generator is configured as receiving parity signal from host, and based on the parity signal, described
Mask signal and the result of the even-odd check generate the parity errors error signal.
10. a kind of memory device, comprising:
Aligner is configured as sampling data by data strobe signal, and the data strobe signal is same after not including
Walk code；And
Parity error detection circuit, is configured as,
Even-odd check is executed to the data sampled by the aligner, to generate parity errors error signal；And
The parity errors error signal, the odd even are exported during the period determined according to the burst-length of the data
Whether check errors signal designation produces parity error in the data.
11. memory device according to claim 10, wherein the parity error detection circuit includes:
Mask signal generator is configured as generating mask signal based on write order, and the mask signal is according to the data
Burst-length determine period during be activation；And
Error signal generator is configured as generating the odd even school based on the mask signal and the result of the even-odd check
Error checking error signal.
12. memory according to claim 11, wherein the error signal generator is additionally configured to,
Parity signal is received from host；And
By executing additional parity based on result of the parity signal to the even-odd check, to generate the surprise
Even parity check error signal.
13. memory device according to claim 12, wherein the parity error detection circuit includes:
First even-odd check delay unit is configured as being delayed based on even-odd check to postpone the write order, and by delay
Write order is supplied to the mask signal generator, and
Second even-odd check delay unit is configured as being delayed based on the even-odd check to postpone the knot of the even-odd check
Fruit, and the result of the even-odd check of delay is supplied to the error signal generator,
Wherein the error signal generator is configured as receiving the parity signal and be prolonged according to the even-odd check
When the result of even-odd check that is postponed.
14. memory device according to claim 13, further includes:
Mode register is configured as storing the information of the even-odd check delay from the host, and the odd even that will be stored
The information of verification delay is supplied to the parity error detection circuit.
15. memory device according to claim 10, further includes:
Mode register, is configured as storing the information of the burst-length from host, and by the letter of the burst-length stored
Breath is supplied to the parity error detection circuit.
16. a kind of memory device, comprising:
Parity checker is configured as executing the first even-odd check, the number to the data sampled according to data strobe signal
It does not include postamble according to gating signal；
Mask signal generator is configured as generating mask signal based on write order, and the mask signal is according to the data
Burst-length determine period during be activation；And
Error signal generator is configured as,
Parity signal is received from host,
The second even-odd check is executed based on result of the parity signal to the first even-odd check, and
Parity errors error signal is generated based on the mask signal and the result of the second even-odd check.
17. memory device according to claim 16, further includes:
Aligner is configured as sampling the data by the data strobe signal, and the data of sampling is provided
To the parity checker.
18. memory device according to claim 16, further includes:
First even-odd check delay unit is configured as being delayed based on even-odd check to postpone the write order, and by delay
Write order is supplied to the mask signal generator；And
Second even-odd check delay unit is configured as being delayed based on the even-odd check to postpone the knot of the first even-odd check
Fruit, and the result of the first even-odd check of delay is supplied to the error signal generator.
19. memory device according to claim 18, wherein the error signal generator be configured as receiving via
Second even-odd check delay unit is delayed the result of postponed the first even-odd check according to the even-odd check.
20. memory device according to claim 18, wherein
Error signal generator, comprising:
First XOR logic, be configured as the first even-odd check to the odd data in the data result and the odd even school
The odd signal for testing signal executes XOR operation, and
Second XOR logic, be configured as the first even-odd check to the even data in the data result and the odd even school
The even parity check signal for testing signal executes XOR operation；And
Error signal generator is configured as defeated based on the mask signal and the first XOR logic and the second XOR logic
Signal out generates the parity errors error signal.
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| CN116844605B (en) * | 2022-03-23 | 2024-05-03 | 长鑫存储技术有限公司 | Signal sampling circuit and semiconductor memory |
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