TWI501240B - Flash memory and method for operating memory device - Google Patents

Flash memory and method for operating memory device Download PDF

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Publication number
TWI501240B
TWI501240B TW101121363A TW101121363A TWI501240B TW I501240 B TWI501240 B TW I501240B TW 101121363 A TW101121363 A TW 101121363A TW 101121363 A TW101121363 A TW 101121363A TW I501240 B TWI501240 B TW I501240B
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instruction
logic
output
bit
data
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TW101121363A
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Chinese (zh)
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TW201351414A (en
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Johnny Chan
Teng Su
Michael Chi Li
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Winbond Electronics Corp
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Description

Flash memory and method of operating memory device

The present invention relates to a flash memory, and more particularly to a logical data reading on a flash memory.

Unitary string and multi-bit serial flash memory have become commonplace due to fewer pin counts and simple interfaces. The simplest interface is a Serial Peripheral Interface (SPI). A meta-string peripheral interface protocol includes a user sending an 8-bit instruction, an address byte, and a selective dummy byte to the serial peripheral flash device, and the string The column peripheral interface flash memory device will respond to the user by returning the data. A single 8-bit instruction can identify read, erase/stylize, or another suitable operation. For high-performance system applications that require fast read performance, for example, a dual serial peripheral interface (SPI-Dual), a four-string peripheral interface (SPI-Quad), and a Quad Peripheral Interface (QPI) have been developed. The multi-bit serial interface. In the four-column peripheral interface, 8-bit instructions are provided in tandem in a one-bit manner, but all subsequent fields (such as address, selective virtual byte, and data) are in 4 bits. Yuan (4) is completed on a serial basis to improve the reading amount. In the quaternary interface, all fields (such as 8-bit instructions, addresses, selective virtual bytes, and data) are all done in 4-bit serials. In this way, the quaternary peripheral interface provides 8-bit instructions in two clock cycles, while the four-string peripheral interface requires eight clock cycles. each A multi-bit serial flash interface protocol is described, for example, in U.S. Patent No. 7,558,900, filed on Jan. 7, 2009.

The types of read operations performed by flash memory typically include memory array reads and logical reads. 1 is a block diagram of a circuit for performing a logic read in a typical flash memory. Logic 12 receives logic data from different registers (e.g., register 4 in Figure 2), such as status data, Joint Electron Device Engineering Council (JEDEC) manufacturers, and partial certification materials. Logic 12 also receives a serial input SI that includes a plurality of instructions and different input data. The logic 12 completely decodes each instruction on the eighth clock. If the instruction is the signal JEDEC, RDSR1 or RDSR2, respectively selects the data JEDECID, SR1 or SR2, and selects the selected instruction as the logical data LOGICDATA. The identity is provided to the data register 14. When the instruction is a memory read instruction, the data register 14 also receives the array data ARRAYDATA from the memory cell array. Based on the input signals from the logic 12, such as the signals JEDEC, RDSR1, and RDSR2, the data register 14 selects the logical data LOGICDATA or the array data ARRAYDATA, and outputs the selected data as a serial data output signal SDOUT/output. The pad serial output circuit 16 includes an output driver. When the pad serial output circuit 16 is enabled by the signal RDLD when the serial data output signal SDOUT/ is logic data, or the serial data output signal SDOUT/ is memory When the body array data is enabled by the signal OEIN, the output driver is the output string Output signal SDOUT/ to the contact surface of the packaged flash memory device, such as lead, pad or pin. The pad serial output circuit 16 is controlled by the system clock SCK, while the logic 12 and data register 14 are controlled by the clock signal CLK, that is, the system clock SCK buffered by the input pad circuit 10.

More detailed details of the logic 12 are shown in FIG. The logic 12 decodes the instructions in the serial input SI and provides a signal that uniquely identifies the logical read instruction, the illustrative signal JEDEC for reading the data JEDECID, and the signal for reading the first state register RDSR1 and signal RDSR2 for reading the second status register. These signals are combined in combination logic 24 to obtain a signal RDLD that symbolizes a logical data read instruction. The signal RDLD is applied to the selected input of the multiplexer 26. When the trigger signal RDLD, the multiplexer 26 selects the logic data LOGICDATA from one of its plurality of data inputs, otherwise selects the data from the register 25, The register 25 stores the memory array data received by the main array sense amplifier 2.

More detailed details of the pad serial output circuit 16 are shown in FIG. The output driver 34 is controlled by a clock signal CLK and an output enable signal OE from the D-type flip-flop 32. The D-type flip-flop 32 generates an output enable signal OE based on the signal RDLD applied to the input terminal SET and the signal OEIN applied to the input terminal D. The input signal OEIN is used for array reading. Both the D-type flip-flop 32 and the output driver 34 are controlled by the clock signal CLK.

An embodiment of the present invention provides a flash memory having the capability of outputting logic data in response to a set of logical read commands, including an external signal input terminal, an addressable flash memory cell array, a data register, Most of the scratchpads as well as the instruction and control logic. The data register is coupled to the addressable flash memory cell array for receiving and storing array data from the addressable flash memory cell array. Most registers are used to store logical data. Instruction and control logic, including pre-fetch logic and output control logic. Prefetching logic is coupled to the external signal input terminal, when the first signal sequence of the most significant bit of the instruction received by the external signal input terminal is a predicted specific logic data read instruction, according to the multiple logic Reading one of the specific ones of the instructions, prefetching the logical data from one of the plurality of logical data registers. The output control logic is coupled to the external signal input terminal, and the second partial sequence of the most significant bit of the command received by the external signal input terminal is any one of the predicted plurality of logical data read commands. In one of the cases, a predicted logical read command signal is generated. The flash memory further includes an output pad circuit coupled to the data register, the prefetch logic, the output control logic, and the external signal receiving end for reading the command signal and the And when the part of the first partial sequence and the second partial sequence parse the received one of the plurality of logical data read instructions, the logical data from the prefetch logic is selected and outputted.

Another embodiment of the present invention provides a method of operating a memory device having a flash memory cell array for responding to a logical read instruction having a predetermined number of instruction bits to provide logic data to application. The method includes receiving a sequence of bits of instructions having fewer than a predetermined number of instruction bits, the plurality of received bit sequences being a plurality of most significant bits of the instruction. The received bit sequence is pre-decoded in a logic circuit of the memory device to determine whether the received bit sequence matches a bit sequence of a corresponding logical read instruction. Decoding of the remaining bits of the instruction is done in the pad output circuit to determine if the match in the pre-decoding step correctly predicts the logical read instruction. The logic data is output according to the logic read instruction.

Another embodiment of the present invention provides a method of operating a memory device having a flash memory cell array for responding to a logical read instruction having a predetermined number of instruction bits to provide logic data to an application The program includes: receiving a first bit sequence of instructions having a number of bits less than a predetermined number of instruction bits, the plurality of received first bit sequences being a plurality of most significant bits of the instruction. The received first bit sequence is pre-decoded in a logic circuit of the memory device to determine whether the received first bit sequence matches a bit sequence of a corresponding logical read instruction. The logical data is prefetched according to the logical read instruction matched in the pre-decoding step. Receiving a second bit sequence of instructions having fewer than a predetermined number of instruction bits but more than the first bit sequence, the plurality of received second bit sequences being the most significant of the plurality of instructions Bit. The received second bit sequence is pre-decoded in a logic circuit of the memory device to determine whether the received second bit sequence matches a bit sequence of a corresponding logical read instruction. Decoding the remaining bits of the instruction in the pad output circuit to determine pre-decoding in the second sequence Whether the matching in the step correctly predicts the logical read instruction. The logical data prefetched in the prefetching step is output. In a variation, the first sequence and the second sequence of the most significant bits are 7 bits. In another variation, the first partial sequence of the most significant bits is 4 bits and the second partial sequence of the most significant bits is 7 bits.

Flash memory is widely used in digital electronic devices and systems. However, high performance devices and systems typically require flash memory to operate at higher frequencies. For example, in an operational situation of memory reading, although the use of a dummy clock after the instruction may allow for higher frequency operations, the speed of the logical read operation may still be bottlenecked. This problem is caused by excessive delays in the instruction decode and logic circuits, the data register circuits, and the interconnect internal signal lines.

For example, the signal JEDEC read command (9Fh), the first state register read command (signal RDSR1 05h), and the second state register read command (signal RDSR2 35h) are all examples of logical read instructions. A signal JEDEC read command outputs a manufacturer and device identity bit from the device to determine the identity of the device. The signals RDSR1 and RDSR2 read instructions respectively output the contents of the first state register and the second state register.

Figure 4 illustrates the operation of signals JEDEC, RDSR1, and RDSR2 in very high frequency operation, and assumes that there are no other bottlenecks in the flash memory device. The serial input SI includes 8 clocks to control 8 instruction bits on the rising edge, followed by multiple control edges at the falling edge. Additional timing of the material. The flash memory can be designed such that the 8th clock not only controls its Least Significant Bit (LSB) at the rising edge of the command, but also controls its first data bit at its falling edge. That is, the leftmost down arrow points to it. Therefore, the timing margin for completing instruction decoding and fetching and outputting data is only a relatively short half cycle.

Unfortunately, assuming that there are no other bottlenecks in the flash memory, the timing tolerance of the half cycle is insufficient when the frequency of operation is raised to a particular point, as depicted in FIG. When there are many delays, the more significant delays are indicated by arrows A1, B1, C1, D1 and E1. Arrow A1 indicates the delay caused by the buffering of the system clock SCK, which allows the internal clock signal CLK to be provided. Arrow B1 indicates that after the arrival of the eighth bit, the instruction is decoded to produce a delay of signal JEDEC, RDSR1 or RDSR2. The arrow C1 is indicated in logic 12, and the delay of selecting the appropriate logic data after the signal JEDEC, RDSR1 or RDSR2 is generated. The arrow D1 indicates the combination logic 24 and the multiplexer 26 in the data register 14 when the serial data output signal SDOUT/ is selected between the array data ARRAYDATA and the logic data LOGICDATA (shown in FIG. 2). The delay associated with the rising edge of the clock signal CLK. The arrow E1 indicates the delay along the rising edge of the RDLR signal path and the clock signal CLK in the D-type flip-flop 32, and the delay associated with the output enable signal OE, wherein the output enable signal OE enables the output driver 34. The arrow F1 indicates the overall delay, which in this example is nearly the entire period and far exceeds the timing tolerance of the half period.

The operating frequency of an ideal flash memory is generally higher. In a memory array read operation, when the improved timing eliminates bottlenecks, the timing delay in the logical read operation may exceed the timing tolerance of the half cycle and become the next bottleneck in higher frequency operation. Advantageously, the various embodiments herein can improve the timing of logical read operations in different ways.

The timing of the logic read operation can be improved by the pad serial output circuit, which receives the pre-decode command signal and the prefetch logic data before the last instruction clock, and the last of the command input sequence of the pad serial output circuit A clock instruction performs fast resolution to avoid serial logic delay, data register latency, and internal signal line delay. In an illustrative embodiment of an SPI, instruction pre-decoding is done in a seventh clock of the instruction input and is used to generate a pre-command signal, which may be pre-provisioned to the solder The pad serial output circuit can also be used to prefetch logic data, which can be provided in advance to the pad serial output circuit. In an illustrative embodiment of another SPI, instruction pre-decoding is performed in a fourth clock of the instruction input to generate a pre-command signal, which may be provided in advance to the pad serial output circuit And another instruction pre-decoding is completed in the seventh clock of the instruction input for prefetching logic data, which may be provided in advance to the pad serial output circuit. In an illustrative embodiment of a QPI, instruction pre-decoding is performed in a first clock of a 4-bit instruction input to generate a pre-command signal, which may be pre-provisioned to the four pads Each circuit of the serial output circuit, the pre-finger The signal is also pre-fetched with logic data that can be provided in advance to the various circuits of the four pad serial output circuits. The fast instruction parsing can be done in the second clock of the command input sequence of the various circuits of the four pad serial output circuits, each of the four pad serial output circuits receiving the four LSBs of the command. The techniques of instruction pre-decoding, logic data prefetching, and fast instruction parsing in pad array output circuits can be used alone or in any combination to improve the timing of logic reads.

6 is a block diagram showing the structure of a flash memory device, including logic read instruction pre-decoding, logic data prefetching, and fast instruction parsing in a pad array output circuit. The flash memory cell array 66 can be addressed for reading and writing due to different addressing, reading and writing circuits, including a column decoding circuit 64 and a row decoding circuit 68, wherein the row decoding circuit 68 includes 32 The sense amplifier block 68_1 and the 256-bit block page buffer 68_2, 32 sense amplifier block 68_1 are used to read the flash memory cell array 66, and the 256-bit block page buffer 68_2 is used to write the flash memory cell. Array 66. Write protection logic 64_1 is responsive to status register 42 to prevent writing to flash memory cell array 66 under certain circumstances. The instruction and control logic 50 controls the high voltage generator 56 and the page address latch and counter 58, wherein the high voltage generator 56 and the page address latch and counter 58 alternately control the column decode circuit 64. The instruction and control logic 50 also controls the byte address latch and counter 60, which in turn controls the row decode circuit 68. The instruction and control logic 50 includes four input/output signal lines IO0~IO3, a buffered clock input pin CLK1, and a chip select input pin CS. Supports SPI and QPI, including standard SPI instructions, dual SPI instructions, quad SPI Instructions and QPI instructions. QPI operation is supported when the device is switched from standard/dual/quaternary SPI mode to QPI mode using the Enable QPI (38h) command. Use the Disable QPI (FFh) command to switch the device back to standard/dual/quaternary SPI mode.

The implementation of the instruction pre-decoding can be illustrated by three instructions, namely signals RDSR1 (05h), RDSR2 (35h) and JEDEC (9Fh). It can add additional logic and logical read instructions, for example, a third state register, but the principles described herein are still applicable. Since the instruction bit is sensed at the rising edge of the clock, any instruction can be explicitly determined at the rising edge of the 8th clock. However, as shown in FIG. 7, the LSBs of the signals JEDEC, RDSR1, and RDSR2 are the same, that is, both are 1. Therefore, in these instructions, a clear judgment can be made on the rising edge of the seventh clock. Although the eight instruction bits are still unknown to the instruction decoder, the instructions may be obtained by parsing the instruction bits one clock cycle earlier, that is, based on only seven instruction bits. In addition, as shown in Figure 7, the four Most Significant Bits (MSBs) of these instructions are different. Therefore, in these instructions, an explicit decision can be made at the rising edge of the fourth clock to prefetch the data JEDEC, SR1, and SR2 from the state register 42. The decoding operation after the 4 instruction bits may not be as clear as other instructions, but such ambiguity may be based on pre-decoding of 7 bits and/or in the pad array output circuit 46 (painting This is solved by the instruction analysis executed in Figure 6).

8 is a letter with 4-bit instruction pre-decoding and data prefetching, 7-bit instruction pre-decoding, and instruction parsing in the pad serial output circuit Timing diagram for JEDEC, RDSR1, and RDSR2 instructions. FIG. 9 is a detailed block diagram showing the above operation in the flash memory circuit of FIG. 6. The details of logic 54 are shown in FIG. 10, and the details of pad array output circuit 46 are shown in FIG.

As shown in FIG. 9, the system clock SCK is applied to the pad serial output circuit 46 and simultaneously applied to the input pad circuit 48. The system clock SCK is buffered in the input pad circuit 48 and provided as the clock signal CLK. . The clock signal CLK is applied to logic 54 and data register 52, which is disposed in instruction and control logic 50 (shown in Figure 6). Logic 54 also receives logic data such as signal JEDEC and status data SR1 and SR2 from the status register. Logic 54 additionally receives the serial input SI.

As shown in FIG. 10, the logic 54 includes a 4-bit pre-decoder 100 that decodes 4 MSBs of the serial input SI, and if the 4 MSBs are respectively indicated as signals RDSR1, RDSR2 or JEDEC, 4-bit pre- The decoder 100 triggers signals PD4_RDSR1, PD4_RDSR2 or PD4_JEDEC. The signals PD4_RDSR1, PD4_RDSR2, and PD4_JEDEC are applied to the combinational logic 102, which generates a selection signal SELECT<1:0> for controlling the multiplexer 104. The manufacturer and partial identification signal JEDEC and the status data SR1 and SR2 from the status register are applied to the multiplexer 104 as data inputs, and the selection of these signals is based on the selection signal SELECT<1:0> and is prefetched. The identity of the data signal logic LOGICDATA is applied to the pad serial output circuit 46 (shown in Figure 9). Therefore, as shown in FIG. 8, at time point A2, the logic data LOGICDATA can be supplied to the solder after the rising edge of the fourth clock. The pad array output circuit 46.

10 illustrates that logic 54 includes a 7-bit predecoder 106 that decodes 7 MSBs of a serial input SI, and a 7-bit predecoder if the 7 MSBs are indicated as signals RDSR1, RDSR2, or JEDEC, respectively. 106 trigger signal PD7_RDSR1, PD7_RDSR2 or PD7_JEDEC. Signal lines PD7_RDSR1, PD7_RDSR2, and PD7_JEDEC are applied to combination logic 108, which generates pre-command signals PRECMD<1:0>. The pre-command signal PRECMD<1:0> may be supplied to the pad serial output circuit 46 at time point B2 (shown in FIG. 8), that is, the rising edge of the seventh clock of the buffer clock signal CLK. As shown in FIG. 8, the values of the pre-command signals PRECMD<1:0> are 0 and 1 as shown.

As shown in FIG. 11, the pad serial output circuit 46 includes combinational logic 110 that receives the pre-command signals PRECMD<1:0> and the serial input SI for performing fast in the last opcode cycle. Instruction parsing. The pre-command signals PRECMD<1:0> indicate whether the instructions are the expected signals RDSR1, RDSR2, JEDEC or instructions other than these instructions. The combinational logic 110 combines the pre-instruction signals PRECMD<1:0> with the LSB of the instruction to resolve whether the instruction is indeed the signal RDSR1, RDSR2 or JEDEC and applies this result to the input of the D-type flip-flop 112 The terminal D is used to generate an output to the input terminal SET1' at a time point C2 (shown in FIG. 8), that is, a rising edge after the 8th clock signal CLK. Thus, when the instruction is the expected signal RDSR1, RDSR2 or JEDEC and the LSB of the instruction is 1 (shown in Figure 7), the signal SET1 is triggered. Otherwise, the signal SET1 will not be triggered.

The pad serial output circuit 46 also includes another D-type flip-flop 114 that provides an output enable signal OE to the output driver 118 at the output Q. The D-type flip-flop 114 receives a signal OEIN at its input D, which is used to enable array reading. The D-type flip-flop 114 also includes an input SET1' and a SET that receive signals SET1 and RDLD, respectively. When both signals SET1 and RDLD are zero, the state of D-type flip-flop 114 and the enablement of output driver 118 are determined by the signal OEIN used to perform the array read. However, when the signal SET1 is 1, that is, it is confirmed that the logic reading should be performed, the output enable signal OE is generated at the time point D2 (shown in FIG. 8), that is, at the falling edge of the eighth instruction clock. The machine ensures that the data from the output driver 118 is available at the clock falling edge of the eighth command and can be expected to be used in the flash memory device for proper operation.

The serial data output signal SDOUT/ and the logic data LOGICDATA are applied to the input of the multiplexer 116, and one of the following methods is applied to the input of the output driver 118. The signal ARRAY_READ is associated with the reading of the flash memory cell array 66 and is not triggered until the array read command is decoded. Therefore, the signal ARRAY_READ is preset to be untriggered, which causes the multiplexer to be preset as the selection logic LOGICDATA.

In some instruction sets, an unambiguous determination of the instruction cannot be made based on the 7 MSBs of the instruction. For example, the signal JEDEC (9Fh or 10011111) cannot be separated from 9Eh (10011110) based on the 7 MSBs. Similarly, the signal RDSR1 (05h or 00000101) cannot be separated from 04h (00000100) based on the 7 MSBs. When an unambiguous determination cannot be made based on the 7 MSBs, two possible outcomes will occur.

The first case is the example of the instruction 9Eh. Currently 9Eh is an invalid instruction. Since the output signal JEDEC data does not affect the flash memory and may be ignored by the device or system, there may be no problem from the invalid 9Eh speculative signal JEDEC. In addition, a well-designed system or device should not issue such invalid instructions. Therefore, this problem can be ignored when ambiguity arises due to invalid instructions. Nonetheless, for the flash memory control system, it is desirable to avoid avoiding misinterpreting invalid instructions as valid instructions.

The second case is the command 04h. In some flash memory, currently 04h is a write disable command, which is issued to reset the write enable latch (WEL) bit in the status register from 1 to 1. 0. Therefore, from the point of view of the computer program, 04h can be a valid instruction. However, if such an instruction is misinterpreted by the flash memory control circuit as the signal RDSR1 05h, the computer program will malfunction. For flash memory that receives these valid instructions that cannot be explicitly determined based on its seven MSBs, it is desirable to have the flash memory control system be able to detect potentially erroneous instructions and properly process their decoding.

The combination logic 110 in the pad serial output circuit 46 performs fuzzy analysis on the 7-bit pre-decoding in the following method. Both the invalid instruction 9Eh and the LSB of the write enable latch instruction 04h include a zero. In this case, the output of the combinational logic 110 transmits 0 to the input D of the flip-flop 112, causes the D-type flip-flop 112 to store 0 and causes the output Q to transmit 0 to the input SET1' of the flip-flop 114. , which does not cover the logical value of input D. Therefore, any assertion of the output enable signal OE is made by input D Controlled.

The techniques described herein can be applied to SPI or QPI interfaces. The memory device structure shown in FIG. 6 can be modified as shown in FIG. 12 to support one-bit and multi-bit SPI as in the case of QPI.

In the one-bit and multi-bit SPI interfaces, 8-bit instructions are provided in a one-bit string, that is, one bit is provided in each of the eight clocks. This input is provided as a serial input SI. For a multi-bit SPI, the memory device structure shown in FIG. 6 can be modified to include a plurality of pad serial output circuit circuits equal in number to a plurality of output bit numbers controlled at a time point, and Fast instruction parsing can be performed in each pad serial output circuit. The pre-command signals PRECMD<1:0> may have a value of 0 and 1 to enable each pad serial output circuit for output.

In the QPI interface, 8-bit instructions are provided in 4-bit concatenation, that is, 4 bits are transmitted individually using two clocks. For the QPI interface, the memory structure shown in FIG. 6 can be modified as shown in FIG. The instruction and control logic block 120 includes a data register 122 and logic 124. The pad serial output circuits 130, 131, 132, and 133 can be used in conjunction with the input/output signal lines IO0, IO1, IO2, and IO3 respectively connected thereto. In addition, the bits <4, 0>, <5, 1>, <6, 2>, and <7, 3> of the logic data LOGICDATA may be transferred from the logic 124 to the pad serial output circuits 130, 131, 132, respectively. 133, and the pre-command signals PRECMD<1:0> may be transmitted by logic 124 to pad serial output circuits 130, 131, 132, and 133. Serial data output signal SDOUT/ bit The elements <4, 0>, <5, 1>, <6, 2>, and <7, 3> may be transmitted from the data register 122 to the pad serial output circuits 130, 131, 132, and 133, respectively. The system clock SCK can be transmitted to the pad serial output circuits 130, 131, 132, and 133. The fast instruction parsing for QPI can be performed by the following method. That is, when IO3 to IO0 of signals RDSR1, RDSR2, and JEDEC are 0101, 0101, and 1111, respectively (FIG. 7), the 0, 1 values of the pre-command signals PRECMD<1:0> can be used to enable the pad serial output. The outputs of circuits 130, 131, 132, and 133.

13 is a generalized flow diagram 140 showing logical data read operations using 4-bit and 7-bit instruction pre-decoding. The system clock SCK is buffered in the input pad circuit 48 to provide the buffered clock signal CLK to logic 54 and data register 52 (step 141). After the four clock signals CLK control the four MSBs entering the instruction, and the four MSBs are pre-decoded by the logic 54 (step 142), the logic reads in the logic 54 based on the pre-decoding in the four bits. The instruction fetch (e.g., signal JEDEC or status data SR1 or SR2 in the status register) prefetches the logic data (step 143). The prefetch logic is provided to the pad serial output circuit 46 prior to the eighth system clock SCK clock (step 144). After the seven clock signals CLK control the 7 MSBs of the incoming command and are pre-decoded in logic 54 to generate the pre-command signals (step 145), the pre-command signals are provided to the pad serial output circuit 46 (steps) 146). The pre-command signal is combined with the LSB (in the rising edge of the eighth system clock SCK) for fast instruction parsing in the pad serial output circuit 46 to account for the ambiguity of the pre-decode instruction (step 147) . If the instruction is not a logical read instruction (No in step 148), The memory operation is continued without logical data reading (step 150). If the instruction is a logical read instruction (YES in step 148), the prefetch logic is selected at the falling edge of the eighth system clock SCK, and the pad serial output controlled by the system clock SCK Circuit 46 outputs (step 149).

Advantageously, one of the logical data, the SR1 data, and the SR2 data can be prefetched at the 4th clock, so even if multiplex is performed in logic 54, the selected data has sufficient time to be processed as It is available to the multiplexer 116 in the pad serial output circuit 46. Advantageously, the logic data can be multiplexed in the multiplexer 116 in the pad serial output circuit 46 and provided directly by the multiplexer 116 to the output driver 118, thereby avoiding signal lines and other transmission and gate delays. Advantageously, the pad serial output circuit 46, including the multiplexer 116 and the output driver 118, can be controlled by the system clock SCK, thereby avoiding clock buffering delays. Advantageously, the decoding ambiguity can be resolved at the rising edge of the system clock SCK of the combinational logic 110 in the pad serial output circuit 46 such that any logical read is performed unless the instruction is parsed as a logical read instruction The prefetched data in the instruction fetch is not selected as the input to the output driver 118.

14 depicts a general flow diagram 160 of a logical data read operation using a 7-bit instruction pre-decode. The system clock SCK is buffered in input pad circuit 48 to provide buffered clock signal CLK to logic 54 and data register 52 (step 161). After the seven clock signals CLK control the 7 MSBs entering the command, and the 7 MSBs are pre-decoded by the logic 54 to generate the pre-command signals (step 162), the pre-command signals are provided to the pad serial output. Circuit 46 (step 163). In addition, logic data (such as signal JEDEC Or the status data SR1 or SR2 in the status register is prefetched in logic 54, based on which logical read instruction was pre-decoded in the 7 bits (step 164), and The logic data is provided to the pad serial output circuit 46 (step 165). The pre-command signal is combined with the LSB (in the rising edge of the eighth system clock SCK) for fast instruction parsing in the pad serial output circuit 46 to account for the ambiguity of the pre-decode instruction (step 166) . If the instruction is not a logical read instruction (NO in step 167), the memory operation is continued without performing the logic data reading (step 169). If the instruction is a logical read instruction (YES in step 167), the prefetch logic is selected at the falling edge of the eighth system clock SCK, and the pad serial output controlled by the system clock SCK Circuit 46 outputs (step 168).

The description of the present invention, including the advantages and the application thereof, are intended to be illustrative only, and the description is not intended to limit the invention, and the scope of the invention is defined by the scope of the claims. The embodiments disclosed herein may be changed and modified, and the actual replacement and equivalents of the various elements of the embodiments will be apparent to those skilled in the art. The specific numerical values given herein are for illustrative purposes only, and may vary as needed. Here, the various points in time proposed by the present invention are not exact time points unless otherwise explicitly defined, and will vary with circuit layout, signal line impedance, and other practical design factors well known in the art. Various values in a range that are referenced will include all values within the range. These and other variations and modifications of the embodiments disclosed herein may be made without departing from the scope of the invention.

2, 109‧‧‧ main array sense amplifier

4, 25, 107‧‧‧ register

10, 48, 134‧‧‧ Input pad circuit

12, 54, 124‧‧ ‧ Logic

14, 52, 122‧‧‧ data registers

16, 46, 130, 131, 132, 133‧‧‧ solder pad serial output circuit

24, 102, 108, 110‧‧‧ combinational logic

26, 104, 116‧‧‧ multiplexers

32, 112, 114‧‧‧D type flip-flops

34, 118‧‧‧ Output Driver

40‧‧‧Write Control Logic

42‧‧‧Status register

50, 120‧‧‧ instruction and control logic

56‧‧‧High voltage generator

58‧‧‧Page address latch and counter

60‧‧‧-byte address latches and counters

62‧‧‧secure register

64‧‧‧ column decoding circuit

64_1‧‧‧Write protection logic

66‧‧‧Flash memory cell array

68‧‧‧ line decoding circuit

68_1‧‧‧256 byte page buffer

68_2‧‧‧32 sense amplifier block

100‧‧‧4-ary predecoder

106‧‧7-bit predecoder

140, 160‧‧‧ Flowchart

141~150, 161~169‧‧‧ steps

ARRAYDATA‧‧‧Array data

A1, B1, C1, D1, E1, F1‧‧‧ arrows

A2, B2, C2, D2‧‧‧ points

CLK‧‧‧ clock signal

CLK1, CLK'‧‧‧ buffer clock input pin

CS‧‧‧chip selection input pin

D, SET, SET1'‧‧‧ input

IO0, IO1, IO2, IO3‧‧‧ input/output signal lines

JEDEC, RDSR1, RDSR2, RDLD, OEIN, PD4_RDSR1, PD4_RDSR2, PD4_JEDEC, PD7_RDSR1, PD7_RDSR2, PD7_JEDEC, SET1, ARRAY_READ‧‧‧ signals

JEDECID, SR1, SR2‧‧‧ data

LOGICDATA‧‧‧Logical Information

OE‧‧‧ output enable signal

PRECMD<1:0>‧‧‧ pre-command signal

Q‧‧‧output

SI‧‧‧serial input

SDOUT/‧‧‧Listed data output signal

SCK‧‧‧ system clock

SCK’‧‧‧ system clock input pin

SELECT<1:0>‧‧‧Selection signal

1 is a block diagram of a pad, logic, and data register circuit of a flash memory device in the prior art.

2 is a detailed block diagram of the logic circuit of FIG. 1.

3 is a detailed block diagram of the pad output circuit of FIG. 1.

4 is a timing diagram showing a failure condition of the flash memory device of FIG. 1.

FIG. 5 is a detailed timing chart showing a portion of the timing chart of FIG. 4. FIG.

6 is a circuit diagram of a flash memory architecture including instruction pre-decoding and data prefetching.

Figure 7 is a schematic diagram showing the digital representation of different logical read instructions.

FIG. 8 is a timing diagram showing different signals of the operation of the flash memory included in FIG. 6.

9 is a block diagram of the pad, logic, and data register circuit of the flash memory device of FIG. 6.

Figure 10 is a detailed block diagram of the logic circuit of Figure 9.

Figure 11 is a detailed block diagram of the pad output circuit of Figure 9.

12 is a partial circuit diagram of a flash memory architecture including instruction pre-decoding and data prefetching in QPI mode.

Figure 13 is a flow chart summarizing the logic data reading using instruction pre-decoding and logical data prefetching in the operation of the flash memory device of Figure 6.

Figure 14 is a flow chart outlining the operation of the flash memory device, using only 7-bit instruction pre-decoding and logical data prefetching for logical data reading.

140‧‧‧Flowchart

141~150‧‧‧Steps

Claims (12)

  1. A flash memory having the ability to output logic data in response to a set of logical read commands, comprising: an external signal input; an addressable flash memory cell array; a data register coupled to the addressable a flash memory cell array for receiving and storing array data from the addressable flash memory cell array; a plurality of registers for storing logic data; instruction and control logic circuits, including: prefetch logic (pre -fetch logic), coupled to the external signal input terminal, when the first signal sequence of the most significant bit of the instruction received by the external signal input terminal is a predicted specific logic data read instruction, and is read according to the logic One of the specific instructions, prefetching logic data from one of the logic data registers; and output control logic coupled to the external signal input terminal for receiving the most effective command when the external signal input terminal receives The second partial sequence of the bit is any one of the predicted plurality of logical data read instructions, and the predicted logical read command signal is generated; and the output a pad circuit coupled to the data register, the prefetch logic, the output control logic, and the external signal receiving end for reading the command signal and the first partial sequence and the second portion when the predicted logic When a part of the instructions other than the sequence parses any one of the received logical data read instructions, the logical data from the prefetch logic is selected and output.
  2. For example, the flash memory described in claim 1 of the patent scope, wherein: The external signal input end is disposed in a serial peripheral interface (SPI) and includes a serial input signal line; and the output pad circuit is disposed in the serial peripheral interface protocol, and includes a serial data output line .
  3. The flash memory according to claim 1, wherein the external signal input terminal is disposed in a quad-peripheral interface (QPI), and includes a first serial input/output signal line, a two-column input/output signal line, a third serial input/output signal line, and a fourth serial input/output signal line; and the output pad circuit is disposed in the quaternary peripheral interface protocol and includes the first bit The first pad input/output signal line and the second one-bit pad output circuit are coupled to the second serial input/output signal line and the third bit. And a fourth serial input/output signal line coupled to the fourth serial input/output signal line.
  4. The flash memory of claim 1, wherein the most significant bit of the first and second partial sequences is 7 bits.
  5. The flash memory as described in claim 4, wherein: the external signal input end is disposed in the serial peripheral interface protocol, and includes a serial input signal line; and the output pad circuit is disposed in the series periphery Interface protocol and includes serial data output lines.
  6. The flash memory of claim 1, wherein: the first partial sequence of the most significant bit is 4 bits; The second partial sequence of the most significant bits is 7 bits.
  7. The flash memory of claim 6, wherein the external signal input terminal is disposed in a quaternary peripheral interface protocol, and includes a first serial input/output signal line and a second serial input/output signal. a line, a third serial input/output signal line, and a fourth serial input/output signal line; and the output pad circuit is disposed in the quaternary peripheral interface protocol, and includes a first one-bit pad output circuit, The first serial input/output signal line and the second one-bit pad output circuit are coupled to the second serial input/output signal line and the third one-bit pad output circuit. The third serial input/output signal line and the fourth one-bit pad output circuit are coupled to the fourth serial input/output signal line.
  8. The flash memory of claim 1, further comprising: a system clock input signal line coupled to the output pad circuit; and an input pad circuit coupled to the system clock for A buffered clock signal is provided to the prefetch logic, the output control logic, and the data register.
  9. A method of operating a memory device, the memory device having a flash memory cell array responsive to a logical read instruction having a predetermined number of instruction bits to provide logic data to an application, the method comprising: receiving a bit a sequence of bits of instructions less than a predetermined number of instruction bits, the received sequence of bits being a plurality of most significant bits of the instruction; the sequence of received bits in the logic circuit of the memory device Pre-decoding to determine whether the received bit sequence matches the bit sequence of the corresponding logical read command; decoding the remaining bits of the instruction in the pad output circuit to determine the pre-decode Whether the matching in the step correctly predicts the logical read instruction; and outputs the logical data according to the logical read instruction.
  10. A method of operating a memory device, the memory device having a flash memory cell array responsive to a logical read instruction having a predetermined number of instruction bits to provide logic data to an application, the method comprising: receiving a bit a first bit sequence of instructions less than a predetermined number of instruction bits, the received first bit sequence being a plurality of most significant bits of the instruction; the received in the logic circuit of the memory device The first bit sequence is pre-decoded to determine whether the received first bit sequence matches the bit sequence of the corresponding logical read instruction; prefetching the logical data according to the logical read instruction matched in the pre-decoding step Receiving a second bit sequence of instructions having less than a predetermined number of instruction bits but more than the first bit sequence, the received second bit sequence being a plurality of most significant bits of the instruction; Pre-decoding the received second bit sequence in a logic circuit of the memory device to determine whether the received second bit sequence matches a bit sequence of a corresponding logical read command; Decoding the remaining bits of the complete command output circuit to Determining whether the matching in the step of precoding the second bit sequence correctly predicts the logical read instruction; and outputting the logical data prefetched in the prefetching step.
  11. The method of claim 10, wherein the first bit sequence and the second bit sequence are the 7 most significant bits of the instruction.
  12. The method of claim 10, wherein: the first bit sequence is the 4 most significant bits of the instruction; and the second bit sequence is the 7 most significant bits of the instruction.
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